1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
34 * All rights reserved.
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37 * modification, are permitted provided that the following conditions
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
75 #include "iwl-agn-hw.h"
78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
79 u32 reg, u32 mask, u32 value)
83 #ifdef CONFIG_IWLWIFI_DEBUG
84 WARN_ON_ONCE(value & ~mask);
87 v = iwl_read32(trans, reg);
90 iwl_write32(trans, reg, v);
93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
96 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
102 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
107 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
108 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
109 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
110 ~APMG_PS_CTRL_MSK_PWR_SRC);
112 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
113 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
114 ~APMG_PS_CTRL_MSK_PWR_SRC);
118 #define PCI_CFG_RETRY_TIMEOUT 0x041
120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
126 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
127 * Check if BIOS (or OS) enabled L1-ASPM on this device.
128 * If so (likely), disable L0S, so device moves directly L0->L1;
129 * costs negligible amount of power savings.
130 * If not (unlikely), enable L0S, so there is at least some
131 * power savings, even without L1.
133 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
134 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
135 /* L1-ASPM enabled; disable(!) L0S */
136 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
137 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
139 /* L1-ASPM disabled; enable(!) L0S */
140 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
141 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
143 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
147 * Start up NIC's basic functionality after it has been reset
148 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
149 * NOTE: This does not load uCode nor start the embedded processor
151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
153 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
155 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
158 * Use "set_bit" below rather than "write", to preserve any hardware
159 * bits already set by default after reset.
162 /* Disable L0S exit timer (platform NMI Work/Around) */
163 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
164 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
167 * Disable L0s without affecting L1;
168 * don't wait for ICH L0s (ICH bug W/A)
170 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
171 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
173 /* Set FH wait threshold to maximum (HW error during stress W/A) */
174 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
177 * Enable HAP INTA (interrupt from management bus) to
178 * wake device's PCI Express link L1a -> L0s
180 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
181 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
183 iwl_pcie_apm_config(trans);
185 /* Configure analog phase-lock-loop before activating to D0A */
186 if (trans->cfg->base_params->pll_cfg_val)
187 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
188 trans->cfg->base_params->pll_cfg_val);
191 * Set "initialization complete" bit to move adapter from
192 * D0U* --> D0A* (powered-up active) state.
194 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
197 * Wait for clock stabilization; once stabilized, access to
198 * device-internal resources is supported, e.g. iwl_write_prph()
199 * and accesses to uCode SRAM.
201 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
202 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
203 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
205 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
210 * Enable DMA clock and wait for it to stabilize.
212 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
213 * do not disable clocks. This preserves any hardware bits already
214 * set by default in "CLK_CTRL_REG" after reset.
216 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
219 /* Disable L1-Active */
220 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
221 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
223 /* Clear the interrupt in APMG if the NIC is in RFKILL */
224 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
226 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
232 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
236 /* stop device's busmaster DMA activity */
237 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
239 ret = iwl_poll_bit(trans, CSR_RESET,
240 CSR_RESET_REG_FLAG_MASTER_DISABLED,
241 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
243 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
245 IWL_DEBUG_INFO(trans, "stop master\n");
250 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
252 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
253 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
255 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
257 /* Stop device's DMA activity */
258 iwl_pcie_apm_stop_master(trans);
260 /* Reset the entire device */
261 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
266 * Clear "initialization complete" bit to move adapter from
267 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
269 iwl_clear_bit(trans, CSR_GP_CNTRL,
270 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
273 static int iwl_pcie_nic_init(struct iwl_trans *trans)
275 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
279 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
280 iwl_pcie_apm_init(trans);
282 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
284 iwl_pcie_set_pwr(trans, false);
286 iwl_op_mode_nic_config(trans->op_mode);
288 /* Allocate the RX queue, or reset if it is already allocated */
289 iwl_pcie_rx_init(trans);
291 /* Allocate or reset and init all Tx and Command queues */
292 if (iwl_pcie_tx_init(trans))
295 if (trans->cfg->base_params->shadow_reg_enable) {
296 /* enable shadow regs in HW */
297 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
298 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
304 #define HW_READY_TIMEOUT (50)
306 /* Note: returns poll_bit return value, which is >= 0 if success */
307 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
311 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
312 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
314 /* See if we got it */
315 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
316 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
317 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
320 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
324 /* Note: returns standard 0/-ERROR code */
325 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
330 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
332 ret = iwl_pcie_set_hw_ready(trans);
333 /* If the card is ready, exit 0 */
337 /* If HW is not ready, prepare the conditions to check again */
338 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
339 CSR_HW_IF_CONFIG_REG_PREPARE);
342 ret = iwl_pcie_set_hw_ready(trans);
346 usleep_range(200, 1000);
348 } while (t < 150000);
356 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
357 dma_addr_t phy_addr, u32 byte_cnt)
359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
362 trans_pcie->ucode_write_complete = false;
364 iwl_write_direct32(trans,
365 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
366 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
368 iwl_write_direct32(trans,
369 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
372 iwl_write_direct32(trans,
373 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
374 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
376 iwl_write_direct32(trans,
377 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
378 (iwl_get_dma_hi_addr(phy_addr)
379 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
381 iwl_write_direct32(trans,
382 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
383 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
384 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
385 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
387 iwl_write_direct32(trans,
388 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
389 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
390 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
391 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
393 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
394 trans_pcie->ucode_write_complete, 5 * HZ);
396 IWL_ERR(trans, "Failed to load firmware chunk!\n");
403 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
404 const struct fw_desc *section)
408 u32 offset, chunk_sz = section->len;
411 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
414 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
415 GFP_KERNEL | __GFP_NOWARN);
417 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
418 chunk_sz = PAGE_SIZE;
419 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
420 &p_addr, GFP_KERNEL);
425 for (offset = 0; offset < section->len; offset += chunk_sz) {
428 copy_size = min_t(u32, chunk_sz, section->len - offset);
430 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
431 ret = iwl_pcie_load_firmware_chunk(trans,
432 section->offset + offset,
436 "Could not load the [%d] uCode section\n",
442 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
446 static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
454 address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
457 address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
460 /* set CPU to started */
461 iwl_trans_set_bits_mask(trans,
462 CSR_UCODE_LOAD_STATUS_ADDR,
463 CSR_CPU_STATUS_LOADING_STARTED << shift_param,
466 /* set last complete descriptor number */
467 iwl_trans_set_bits_mask(trans,
468 CSR_UCODE_LOAD_STATUS_ADDR,
469 CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
473 /* set last loaded block */
474 iwl_trans_set_bits_mask(trans,
475 CSR_UCODE_LOAD_STATUS_ADDR,
476 CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
480 /* image loading complete */
481 iwl_trans_set_bits_mask(trans,
482 CSR_UCODE_LOAD_STATUS_ADDR,
483 CSR_CPU_STATUS_LOADING_COMPLETED
487 /* set FH_TCSR_0_REG */
488 iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);
490 /* verify image verification started */
491 ret = iwl_poll_bit(trans, address,
492 CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
493 CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
494 CSR_SECURE_TIME_OUT);
496 IWL_ERR(trans, "secure boot process didn't start\n");
500 /* wait for image verification to complete */
501 ret = iwl_poll_bit(trans, address,
502 CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
503 CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
504 CSR_SECURE_TIME_OUT);
507 IWL_ERR(trans, "Time out on secure boot process\n");
514 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
515 const struct fw_img *image)
520 "working with %s image\n",
521 image->is_secure ? "Secured" : "Non Secured");
523 "working with %s CPU\n",
524 image->is_dual_cpus ? "Dual" : "Single");
526 /* configure the ucode to be ready to get the secured image */
527 if (image->is_secure) {
528 /* set secure boot inspector addresses */
529 iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
530 iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);
532 /* release CPU1 reset if secure inspector image burned in OTP */
533 iwl_write32(trans, CSR_RESET, 0);
536 /* load to FW the binary sections of CPU1 */
537 IWL_DEBUG_INFO(trans, "Loading CPU1\n");
539 i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
541 if (!image->sec[i].data)
543 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
548 /* configure the ucode to start secure process on CPU1 */
549 if (image->is_secure) {
550 /* config CPU1 to start secure protocol */
551 ret = iwl_pcie_secure_set(trans, 1);
555 /* Remove all resets to allow NIC to operate */
556 iwl_write32(trans, CSR_RESET, 0);
559 if (image->is_dual_cpus) {
560 /* load to FW the binary sections of CPU2 */
561 IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
562 for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
563 i < IWL_UCODE_SECTION_MAX; i++) {
564 if (!image->sec[i].data)
566 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
571 if (image->is_secure) {
572 /* set CPU2 for secure protocol */
573 ret = iwl_pcie_secure_set(trans, 2);
582 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
583 const struct fw_img *fw, bool run_in_rfkill)
585 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
589 /* This may fail if AMT took ownership of the device */
590 if (iwl_pcie_prepare_card_hw(trans)) {
591 IWL_WARN(trans, "Exit HW not ready\n");
595 clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
597 iwl_enable_rfkill_int(trans);
599 /* If platform's RF_KILL switch is NOT set to KILL */
600 hw_rfkill = iwl_is_rfkill_set(trans);
602 set_bit(STATUS_RFKILL, &trans_pcie->status);
604 clear_bit(STATUS_RFKILL, &trans_pcie->status);
605 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
606 if (hw_rfkill && !run_in_rfkill)
609 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
611 ret = iwl_pcie_nic_init(trans);
613 IWL_ERR(trans, "Unable to init nic\n");
617 /* make sure rfkill handshake bits are cleared */
618 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
619 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
620 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
622 /* clear (again), then enable host interrupts */
623 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
624 iwl_enable_interrupts(trans);
626 /* really make sure rfkill handshake bits are cleared */
627 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
628 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
630 /* Load the given image to the HW */
631 return iwl_pcie_load_given_ucode(trans, fw);
634 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
636 iwl_pcie_reset_ict(trans);
637 iwl_pcie_tx_start(trans, scd_addr);
640 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
642 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
645 /* tell the device to stop sending interrupts */
646 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
647 iwl_disable_interrupts(trans);
648 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
650 /* device going down, Stop using ICT table */
651 iwl_pcie_disable_ict(trans);
654 * If a HW restart happens during firmware loading,
655 * then the firmware loading might call this function
656 * and later it might be called again due to the
657 * restart. So don't process again if the device is
660 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
661 iwl_pcie_tx_stop(trans);
662 iwl_pcie_rx_stop(trans);
664 /* Power-down device's busmaster DMA clocks */
665 iwl_write_prph(trans, APMG_CLK_DIS_REG,
666 APMG_CLK_VAL_DMA_CLK_RQT);
670 /* Make sure (redundant) we've released our request to stay awake */
671 iwl_clear_bit(trans, CSR_GP_CNTRL,
672 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
674 /* Stop the device, and put it in low power state */
675 iwl_pcie_apm_stop(trans);
677 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
678 * Clean again the interrupt here
680 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
681 iwl_disable_interrupts(trans);
682 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
684 iwl_enable_rfkill_int(trans);
686 /* stop and reset the on-board processor */
687 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
689 /* clear all status bits */
690 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
691 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
692 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
693 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
694 clear_bit(STATUS_RFKILL, &trans_pcie->status);
697 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
699 iwl_disable_interrupts(trans);
702 * in testing mode, the host stays awake and the
703 * hardware won't be reset (not even partially)
708 iwl_pcie_disable_ict(trans);
710 iwl_clear_bit(trans, CSR_GP_CNTRL,
711 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
712 iwl_clear_bit(trans, CSR_GP_CNTRL,
713 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
716 * reset TX queues -- some of their registers reset during S3
717 * so if we don't reset everything here the D3 image would try
718 * to execute some invalid memory upon resume
720 iwl_trans_pcie_tx_reset(trans);
722 iwl_pcie_set_pwr(trans, true);
725 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
726 enum iwl_d3_status *status,
733 iwl_enable_interrupts(trans);
734 *status = IWL_D3_STATUS_ALIVE;
738 iwl_pcie_set_pwr(trans, false);
740 val = iwl_read32(trans, CSR_RESET);
741 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
742 *status = IWL_D3_STATUS_RESET;
747 * Also enables interrupts - none will happen as the device doesn't
748 * know we're waking it up, only when the opmode actually tells it
751 iwl_pcie_reset_ict(trans);
753 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
754 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
756 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
757 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
758 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
761 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
765 iwl_trans_pcie_tx_reset(trans);
767 ret = iwl_pcie_rx_init(trans);
769 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
773 *status = IWL_D3_STATUS_ALIVE;
777 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
779 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
783 err = iwl_pcie_prepare_card_hw(trans);
785 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
789 /* Reset the entire device */
790 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
792 usleep_range(10, 15);
794 iwl_pcie_apm_init(trans);
796 /* From now on, the op_mode will be kept updated about RF kill state */
797 iwl_enable_rfkill_int(trans);
799 hw_rfkill = iwl_is_rfkill_set(trans);
801 set_bit(STATUS_RFKILL, &trans_pcie->status);
803 clear_bit(STATUS_RFKILL, &trans_pcie->status);
804 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
809 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
810 bool op_mode_leaving)
812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
816 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
817 iwl_disable_interrupts(trans);
818 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
820 iwl_pcie_apm_stop(trans);
822 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
823 iwl_disable_interrupts(trans);
824 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
826 iwl_pcie_disable_ict(trans);
828 if (!op_mode_leaving) {
830 * Even if we stop the HW, we still want the RF kill
833 iwl_enable_rfkill_int(trans);
836 * Check again since the RF kill state may have changed while
837 * all the interrupts were disabled, in this case we couldn't
838 * receive the RF kill interrupt and update the state in the
841 hw_rfkill = iwl_is_rfkill_set(trans);
843 set_bit(STATUS_RFKILL, &trans_pcie->status);
845 clear_bit(STATUS_RFKILL, &trans_pcie->status);
846 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
850 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
852 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
855 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
857 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
860 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
862 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
865 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
867 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
868 ((reg & 0x000FFFFF) | (3 << 24)));
869 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
872 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
875 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
876 ((addr & 0x000FFFFF) | (3 << 24)));
877 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
880 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
881 const struct iwl_trans_config *trans_cfg)
883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
885 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
886 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
887 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
888 trans_pcie->n_no_reclaim_cmds = 0;
890 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
891 if (trans_pcie->n_no_reclaim_cmds)
892 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
893 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
895 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
896 if (trans_pcie->rx_buf_size_8k)
897 trans_pcie->rx_page_order = get_order(8 * 1024);
899 trans_pcie->rx_page_order = get_order(4 * 1024);
901 trans_pcie->wd_timeout =
902 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
904 trans_pcie->command_names = trans_cfg->command_names;
905 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
908 void iwl_trans_pcie_free(struct iwl_trans *trans)
910 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
912 synchronize_irq(trans_pcie->pci_dev->irq);
914 iwl_pcie_tx_free(trans);
915 iwl_pcie_rx_free(trans);
917 free_irq(trans_pcie->pci_dev->irq, trans);
918 iwl_pcie_free_ict(trans);
920 pci_disable_msi(trans_pcie->pci_dev);
921 iounmap(trans_pcie->hw_base);
922 pci_release_regions(trans_pcie->pci_dev);
923 pci_disable_device(trans_pcie->pci_dev);
924 kmem_cache_destroy(trans->dev_cmd_pool);
929 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
931 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
934 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
936 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
939 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
940 unsigned long *flags)
943 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
945 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
947 /* this bit wakes up the NIC */
948 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
949 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
952 * These bits say the device is running, and should keep running for
953 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
954 * but they do not indicate that embedded SRAM is restored yet;
955 * 3945 and 4965 have volatile SRAM, and must save/restore contents
956 * to/from host DRAM when sleeping/waking for power-saving.
957 * Each direction takes approximately 1/4 millisecond; with this
958 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
959 * series of register accesses are expected (e.g. reading Event Log),
960 * to keep device from sleeping.
962 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
963 * SRAM is okay/restored. We don't check that here because this call
964 * is just for hardware register access; but GP1 MAC_SLEEP check is a
965 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
967 * 5000 series and later (including 1000 series) have non-volatile SRAM,
968 * and do not save/restore SRAM when power cycling.
970 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
971 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
972 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
973 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
974 if (unlikely(ret < 0)) {
975 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
977 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
979 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
981 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
987 * Fool sparse by faking we release the lock - sparse will
988 * track nic_access anyway.
990 __release(&trans_pcie->reg_lock);
994 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
995 unsigned long *flags)
997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
999 lockdep_assert_held(&trans_pcie->reg_lock);
1002 * Fool sparse by faking we acquiring the lock - sparse will
1003 * track nic_access anyway.
1005 __acquire(&trans_pcie->reg_lock);
1007 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1008 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1010 * Above we read the CSR_GP_CNTRL register, which will flush
1011 * any previous writes, but we need the write that clears the
1012 * MAC_ACCESS_REQ bit to be performed before any other writes
1013 * scheduled on different CPUs (after we drop reg_lock).
1016 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1019 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1020 void *buf, int dwords)
1022 unsigned long flags;
1026 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1027 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1028 for (offs = 0; offs < dwords; offs++)
1029 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1030 iwl_trans_release_nic_access(trans, &flags);
1037 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1038 const void *buf, int dwords)
1040 unsigned long flags;
1042 const u32 *vals = buf;
1044 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1045 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1046 for (offs = 0; offs < dwords; offs++)
1047 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1048 vals ? vals[offs] : 0);
1049 iwl_trans_release_nic_access(trans, &flags);
1056 #define IWL_FLUSH_WAIT_MS 2000
1058 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061 struct iwl_txq *txq;
1062 struct iwl_queue *q;
1064 unsigned long now = jiffies;
1069 /* waiting for all the tx frames complete might take a while */
1070 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1071 if (cnt == trans_pcie->cmd_queue)
1073 txq = &trans_pcie->txq[cnt];
1075 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1076 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1079 if (q->read_ptr != q->write_ptr) {
1081 "fail to flush all tx fifo queues Q %d\n", cnt);
1090 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1091 txq->q.read_ptr, txq->q.write_ptr);
1093 scd_sram_addr = trans_pcie->scd_base_addr +
1094 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1095 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1097 iwl_print_hex_error(trans, buf, sizeof(buf));
1099 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1100 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1101 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1103 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1104 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1105 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1106 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1108 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1109 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1112 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1114 tbl_dw = tbl_dw & 0x0000FFFF;
1117 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1118 cnt, active ? "" : "in", fifo, tbl_dw,
1119 iwl_read_prph(trans,
1120 SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1121 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1127 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1128 u32 mask, u32 value)
1130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1131 unsigned long flags;
1133 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1134 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1135 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1138 static const char *get_csr_string(int cmd)
1140 #define IWL_CMD(x) case x: return #x
1142 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1143 IWL_CMD(CSR_INT_COALESCING);
1145 IWL_CMD(CSR_INT_MASK);
1146 IWL_CMD(CSR_FH_INT_STATUS);
1147 IWL_CMD(CSR_GPIO_IN);
1149 IWL_CMD(CSR_GP_CNTRL);
1150 IWL_CMD(CSR_HW_REV);
1151 IWL_CMD(CSR_EEPROM_REG);
1152 IWL_CMD(CSR_EEPROM_GP);
1153 IWL_CMD(CSR_OTP_GP_REG);
1154 IWL_CMD(CSR_GIO_REG);
1155 IWL_CMD(CSR_GP_UCODE_REG);
1156 IWL_CMD(CSR_GP_DRIVER_REG);
1157 IWL_CMD(CSR_UCODE_DRV_GP1);
1158 IWL_CMD(CSR_UCODE_DRV_GP2);
1159 IWL_CMD(CSR_LED_REG);
1160 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1161 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1162 IWL_CMD(CSR_ANA_PLL_CFG);
1163 IWL_CMD(CSR_HW_REV_WA_REG);
1164 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1171 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1174 static const u32 csr_tbl[] = {
1175 CSR_HW_IF_CONFIG_REG,
1193 CSR_DRAM_INT_TBL_REG,
1194 CSR_GIO_CHICKEN_BITS,
1197 CSR_DBG_HPET_MEM_REG
1199 IWL_ERR(trans, "CSR values:\n");
1200 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1201 "CSR_INT_PERIODIC_REG)\n");
1202 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1203 IWL_ERR(trans, " %25s: 0X%08x\n",
1204 get_csr_string(csr_tbl[i]),
1205 iwl_read32(trans, csr_tbl[i]));
1209 #ifdef CONFIG_IWLWIFI_DEBUGFS
1210 /* create and remove of files */
1211 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1212 if (!debugfs_create_file(#name, mode, parent, trans, \
1213 &iwl_dbgfs_##name##_ops)) \
1217 /* file operation */
1218 #define DEBUGFS_READ_FILE_OPS(name) \
1219 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1220 .read = iwl_dbgfs_##name##_read, \
1221 .open = simple_open, \
1222 .llseek = generic_file_llseek, \
1225 #define DEBUGFS_WRITE_FILE_OPS(name) \
1226 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1227 .write = iwl_dbgfs_##name##_write, \
1228 .open = simple_open, \
1229 .llseek = generic_file_llseek, \
1232 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1233 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1234 .write = iwl_dbgfs_##name##_write, \
1235 .read = iwl_dbgfs_##name##_read, \
1236 .open = simple_open, \
1237 .llseek = generic_file_llseek, \
1240 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1241 char __user *user_buf,
1242 size_t count, loff_t *ppos)
1244 struct iwl_trans *trans = file->private_data;
1245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1246 struct iwl_txq *txq;
1247 struct iwl_queue *q;
1254 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1256 if (!trans_pcie->txq)
1259 buf = kzalloc(bufsz, GFP_KERNEL);
1263 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1264 txq = &trans_pcie->txq[cnt];
1266 pos += scnprintf(buf + pos, bufsz - pos,
1267 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1268 cnt, q->read_ptr, q->write_ptr,
1269 !!test_bit(cnt, trans_pcie->queue_used),
1270 !!test_bit(cnt, trans_pcie->queue_stopped));
1272 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1277 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1278 char __user *user_buf,
1279 size_t count, loff_t *ppos)
1281 struct iwl_trans *trans = file->private_data;
1282 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1283 struct iwl_rxq *rxq = &trans_pcie->rxq;
1286 const size_t bufsz = sizeof(buf);
1288 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1290 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1292 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1295 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1296 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1298 pos += scnprintf(buf + pos, bufsz - pos,
1299 "closed_rb_num: Not Allocated\n");
1301 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1304 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1305 char __user *user_buf,
1306 size_t count, loff_t *ppos)
1308 struct iwl_trans *trans = file->private_data;
1309 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1310 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1314 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1317 buf = kzalloc(bufsz, GFP_KERNEL);
1321 pos += scnprintf(buf + pos, bufsz - pos,
1322 "Interrupt Statistics Report:\n");
1324 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1326 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1328 if (isr_stats->sw || isr_stats->hw) {
1329 pos += scnprintf(buf + pos, bufsz - pos,
1330 "\tLast Restarting Code: 0x%X\n",
1331 isr_stats->err_code);
1333 #ifdef CONFIG_IWLWIFI_DEBUG
1334 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1336 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1339 pos += scnprintf(buf + pos, bufsz - pos,
1340 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1342 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1345 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1348 pos += scnprintf(buf + pos, bufsz - pos,
1349 "Rx command responses:\t\t %u\n", isr_stats->rx);
1351 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1354 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1355 isr_stats->unhandled);
1357 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1362 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1363 const char __user *user_buf,
1364 size_t count, loff_t *ppos)
1366 struct iwl_trans *trans = file->private_data;
1367 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1368 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1374 memset(buf, 0, sizeof(buf));
1375 buf_size = min(count, sizeof(buf) - 1);
1376 if (copy_from_user(buf, user_buf, buf_size))
1378 if (sscanf(buf, "%x", &reset_flag) != 1)
1380 if (reset_flag == 0)
1381 memset(isr_stats, 0, sizeof(*isr_stats));
1386 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1387 const char __user *user_buf,
1388 size_t count, loff_t *ppos)
1390 struct iwl_trans *trans = file->private_data;
1395 memset(buf, 0, sizeof(buf));
1396 buf_size = min(count, sizeof(buf) - 1);
1397 if (copy_from_user(buf, user_buf, buf_size))
1399 if (sscanf(buf, "%d", &csr) != 1)
1402 iwl_pcie_dump_csr(trans);
1407 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1408 char __user *user_buf,
1409 size_t count, loff_t *ppos)
1411 struct iwl_trans *trans = file->private_data;
1414 ssize_t ret = -EFAULT;
1416 ret = pos = iwl_dump_fh(trans, &buf);
1418 ret = simple_read_from_buffer(user_buf,
1419 count, ppos, buf, pos);
1426 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1427 DEBUGFS_READ_FILE_OPS(fh_reg);
1428 DEBUGFS_READ_FILE_OPS(rx_queue);
1429 DEBUGFS_READ_FILE_OPS(tx_queue);
1430 DEBUGFS_WRITE_FILE_OPS(csr);
1433 * Create the debugfs files and directories
1436 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1439 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1440 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1441 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1442 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1443 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1447 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1451 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1456 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1458 static const struct iwl_trans_ops trans_ops_pcie = {
1459 .start_hw = iwl_trans_pcie_start_hw,
1460 .stop_hw = iwl_trans_pcie_stop_hw,
1461 .fw_alive = iwl_trans_pcie_fw_alive,
1462 .start_fw = iwl_trans_pcie_start_fw,
1463 .stop_device = iwl_trans_pcie_stop_device,
1465 .d3_suspend = iwl_trans_pcie_d3_suspend,
1466 .d3_resume = iwl_trans_pcie_d3_resume,
1468 .send_cmd = iwl_trans_pcie_send_hcmd,
1470 .tx = iwl_trans_pcie_tx,
1471 .reclaim = iwl_trans_pcie_reclaim,
1473 .txq_disable = iwl_trans_pcie_txq_disable,
1474 .txq_enable = iwl_trans_pcie_txq_enable,
1476 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1478 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1480 .write8 = iwl_trans_pcie_write8,
1481 .write32 = iwl_trans_pcie_write32,
1482 .read32 = iwl_trans_pcie_read32,
1483 .read_prph = iwl_trans_pcie_read_prph,
1484 .write_prph = iwl_trans_pcie_write_prph,
1485 .read_mem = iwl_trans_pcie_read_mem,
1486 .write_mem = iwl_trans_pcie_write_mem,
1487 .configure = iwl_trans_pcie_configure,
1488 .set_pmi = iwl_trans_pcie_set_pmi,
1489 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1490 .release_nic_access = iwl_trans_pcie_release_nic_access,
1491 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1494 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1495 const struct pci_device_id *ent,
1496 const struct iwl_cfg *cfg)
1498 struct iwl_trans_pcie *trans_pcie;
1499 struct iwl_trans *trans;
1503 trans = kzalloc(sizeof(struct iwl_trans) +
1504 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1510 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1512 trans->ops = &trans_ops_pcie;
1514 trans_lockdep_init(trans);
1515 trans_pcie->trans = trans;
1516 spin_lock_init(&trans_pcie->irq_lock);
1517 spin_lock_init(&trans_pcie->reg_lock);
1518 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1520 err = pci_enable_device(pdev);
1524 if (!cfg->base_params->pcie_l1_allowed) {
1526 * W/A - seems to solve weird behavior. We need to remove this
1527 * if we don't want to stay in L1 all the time. This wastes a
1530 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1531 PCIE_LINK_STATE_L1 |
1532 PCIE_LINK_STATE_CLKPM);
1535 pci_set_master(pdev);
1537 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1539 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1541 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1543 err = pci_set_consistent_dma_mask(pdev,
1545 /* both attempts failed: */
1547 dev_err(&pdev->dev, "No suitable DMA available\n");
1548 goto out_pci_disable_device;
1552 err = pci_request_regions(pdev, DRV_NAME);
1554 dev_err(&pdev->dev, "pci_request_regions failed\n");
1555 goto out_pci_disable_device;
1558 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1559 if (!trans_pcie->hw_base) {
1560 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1562 goto out_pci_release_regions;
1565 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1566 * PCI Tx retries from interfering with C3 CPU state */
1567 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1569 err = pci_enable_msi(pdev);
1571 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1572 /* enable rfkill interrupt: hw bug w/a */
1573 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1574 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1575 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1576 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1580 trans->dev = &pdev->dev;
1581 trans_pcie->pci_dev = pdev;
1582 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1583 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1584 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1585 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1587 /* Initialize the wait queue for commands */
1588 init_waitqueue_head(&trans_pcie->wait_command_queue);
1590 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1591 "iwl_cmd_pool:%s", dev_name(trans->dev));
1593 trans->dev_cmd_headroom = 0;
1594 trans->dev_cmd_pool =
1595 kmem_cache_create(trans->dev_cmd_pool_name,
1596 sizeof(struct iwl_device_cmd)
1597 + trans->dev_cmd_headroom,
1602 if (!trans->dev_cmd_pool) {
1604 goto out_pci_disable_msi;
1607 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1609 if (iwl_pcie_alloc_ict(trans))
1610 goto out_free_cmd_pool;
1612 err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1613 iwl_pcie_irq_handler,
1614 IRQF_SHARED, DRV_NAME, trans);
1616 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1623 iwl_pcie_free_ict(trans);
1625 kmem_cache_destroy(trans->dev_cmd_pool);
1626 out_pci_disable_msi:
1627 pci_disable_msi(pdev);
1628 out_pci_release_regions:
1629 pci_release_regions(pdev);
1630 out_pci_disable_device:
1631 pci_disable_device(pdev);
1635 return ERR_PTR(err);