drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
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  22  * along with this program; if not, write to the Free Software
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  27  * in the file called COPYING.
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32  *
  33  * BSD LICENSE
  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  38  * All rights reserved.
  39  *
  40  * Redistribution and use in source and binary forms, with or without
  41  * modification, are permitted provided that the following conditions
  42  * are met:
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  45  *    notice, this list of conditions and the following disclaimer.
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  48  *    the documentation and/or other materials provided with the
  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  59  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  60  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "fw/error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  92 {
  93 #define PCI_DUMP_SIZE   64
  94 #define PREFIX_LEN      32
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         struct pci_dev *pdev = trans_pcie->pci_dev;
  97         u32 i, pos, alloc_size, *ptr, *buf;
  98         char *prefix;
  99
 100         if (trans_pcie->pcie_dbg_dumped_once)
 101                 return;
 102
 103         /* Should be a multiple of 4 */
 104         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 105         /* Alloc a max size buffer */
 106         if (PCI_ERR_ROOT_ERR_SRC +  4 > PCI_DUMP_SIZE)
 107                 alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 108         else
 109                 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
 110         buf = kmalloc(alloc_size, GFP_ATOMIC);
 111         if (!buf)
 112                 return;
 113         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 114
 115         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 116
 117         /* Print wifi device registers */
 118         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 119         IWL_ERR(trans, "iwlwifi device config registers:\n");
 120         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 121                 if (pci_read_config_dword(pdev, i, ptr))
 122                         goto err_read;
 123         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 124
 125         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 126         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 127                 *ptr = iwl_read32(trans, i);
 128         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 129
 130         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 131         if (pos) {
 132                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 133                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 134                         if (pci_read_config_dword(pdev, pos + i, ptr))
 135                                 goto err_read;
 136                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 137                                32, 4, buf, i, 0);
 138         }
 139
 140         /* Print parent device registers next */
 141         if (!pdev->bus->self)
 142                 goto out;
 143
 144         pdev = pdev->bus->self;
 145         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 146
 147         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 148                 pci_name(pdev));
 149         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 150                 if (pci_read_config_dword(pdev, i, ptr))
 151                         goto err_read;
 152         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 153
 154         /* Print root port AER registers */
 155         pos = 0;
 156         pdev = pcie_find_root_port(pdev);
 157         if (pdev)
 158                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 159         if (pos) {
 160                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 161                         pci_name(pdev));
 162                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 163                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 164                         if (pci_read_config_dword(pdev, pos + i, ptr))
 165                                 goto err_read;
 166                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 167                                4, buf, i, 0);
 168         }
 169         goto out;
 170
 171 err_read:
 172         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 173         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 174 out:
 175         trans_pcie->pcie_dbg_dumped_once = 1;
 176         kfree(buf);
 177 }
 178
 179 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 180 {
 181         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 182
 183         if (!trans_pcie->fw_mon_page)
 184                 return;
 185
 186         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
 187                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 188         __free_pages(trans_pcie->fw_mon_page,
 189                      get_order(trans_pcie->fw_mon_size));
 190         trans_pcie->fw_mon_page = NULL;
 191         trans_pcie->fw_mon_phys = 0;
 192         trans_pcie->fw_mon_size = 0;
 193 }
 194
 195 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 196 {
 197         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 198         struct page *page = NULL;
 199         dma_addr_t phys;
 200         u32 size = 0;
 201         u8 power;
 202
 203         if (!max_power) {
 204                 /* default max_power is maximum */
 205                 max_power = 26;
 206         } else {
 207                 max_power += 11;
 208         }
 209
 210         if (WARN(max_power > 26,
 211                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 212                  max_power))
 213                 return;
 214
 215         if (trans_pcie->fw_mon_page) {
 216                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 217                                            trans_pcie->fw_mon_size,
 218                                            DMA_FROM_DEVICE);
 219                 return;
 220         }
 221
 222         phys = 0;
 223         for (power = max_power; power >= 11; power--) {
 224                 int order;
 225
 226                 size = BIT(power);
 227                 order = get_order(size);
 228                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 229                                    order);
 230                 if (!page)
 231                         continue;
 232
 233                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 234                                     DMA_FROM_DEVICE);
 235                 if (dma_mapping_error(trans->dev, phys)) {
 236                         __free_pages(page, order);
 237                         page = NULL;
 238                         continue;
 239                 }
 240                 IWL_INFO(trans,
 241                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 242                          size, order);
 243                 break;
 244         }
 245
 246         if (WARN_ON_ONCE(!page))
 247                 return;
 248
 249         if (power != max_power)
 250                 IWL_ERR(trans,
 251                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 252                         (unsigned long)BIT(power - 10),
 253                         (unsigned long)BIT(max_power - 10));
 254
 255         trans_pcie->fw_mon_page = page;
 256         trans_pcie->fw_mon_phys = phys;
 257         trans_pcie->fw_mon_size = size;
 258 }
 259
 260 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 261 {
 262         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 263                     ((reg & 0x0000ffff) | (2 << 28)));
 264         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 265 }
 266
 267 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 268 {
 269         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 270         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 271                     ((reg & 0x0000ffff) | (3 << 28)));
 272 }
 273
 274 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 275 {
 276         if (trans->cfg->apmg_not_supported)
 277                 return;
 278
 279         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 280                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 281                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 282                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 283         else
 284                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 285                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 286                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 287 }
 288
 289 /* PCI registers */
 290 #define PCI_CFG_RETRY_TIMEOUT   0x041
 291
 292 void iwl_pcie_apm_config(struct iwl_trans *trans)
 293 {
 294         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 295         u16 lctl;
 296         u16 cap;
 297
 298         /*
 299          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 300          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 301          * If so (likely), disable L0S, so device moves directly L0->L1;
 302          *    costs negligible amount of power savings.
 303          * If not (unlikely), enable L0S, so there is at least some
 304          *    power savings, even without L1.
 305          */
 306         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 307         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 308                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 309         else
 310                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 311         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 312
 313         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 314         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 315         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 316                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 317                         trans->ltr_enabled ? "En" : "Dis");
 318 }
 319
 320 /*
 321  * Start up NIC's basic functionality after it has been reset
 322  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 323  * NOTE:  This does not load uCode nor start the embedded processor
 324  */
 325 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 326 {
 327         int ret;
 328
 329         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 330
 331         /*
 332          * Use "set_bit" below rather than "write", to preserve any hardware
 333          * bits already set by default after reset.
 334          */
 335
 336         /* Disable L0S exit timer (platform NMI Work/Around) */
 337         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 338                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 339                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 340
 341         /*
 342          * Disable L0s without affecting L1;
 343          *  don't wait for ICH L0s (ICH bug W/A)
 344          */
 345         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 346                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 347
 348         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 349         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 350
 351         /*
 352          * Enable HAP INTA (interrupt from management bus) to
 353          * wake device's PCI Express link L1a -> L0s
 354          */
 355         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 356                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 357
 358         iwl_pcie_apm_config(trans);
 359
 360         /* Configure analog phase-lock-loop before activating to D0A */
 361         if (trans->cfg->base_params->pll_cfg)
 362                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 363
 364         /*
 365          * Set "initialization complete" bit to move adapter from
 366          * D0U* --> D0A* (powered-up active) state.
 367          */
 368         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 369
 370         /*
 371          * Wait for clock stabilization; once stabilized, access to
 372          * device-internal resources is supported, e.g. iwl_write_prph()
 373          * and accesses to uCode SRAM.
 374          */
 375         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 378         if (ret < 0) {
 379                 IWL_ERR(trans, "Failed to init the card\n");
 380                 return ret;
 381         }
 382
 383         if (trans->cfg->host_interrupt_operation_mode) {
 384                 /*
 385                  * This is a bit of an abuse - This is needed for 7260 / 3160
 386                  * only check host_interrupt_operation_mode even if this is
 387                  * not related to host_interrupt_operation_mode.
 388                  *
 389                  * Enable the oscillator to count wake up time for L1 exit. This
 390                  * consumes slightly more power (100uA) - but allows to be sure
 391                  * that we wake up from L1 on time.
 392                  *
 393                  * This looks weird: read twice the same register, discard the
 394                  * value, set a bit, and yet again, read that same register
 395                  * just to discard the value. But that's the way the hardware
 396                  * seems to like it.
 397                  */
 398                 iwl_read_prph(trans, OSC_CLK);
 399                 iwl_read_prph(trans, OSC_CLK);
 400                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 401                 iwl_read_prph(trans, OSC_CLK);
 402                 iwl_read_prph(trans, OSC_CLK);
 403         }
 404
 405         /*
 406          * Enable DMA clock and wait for it to stabilize.
 407          *
 408          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 409          * bits do not disable clocks.  This preserves any hardware
 410          * bits already set by default in "CLK_CTRL_REG" after reset.
 411          */
 412         if (!trans->cfg->apmg_not_supported) {
 413                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 414                                APMG_CLK_VAL_DMA_CLK_RQT);
 415                 udelay(20);
 416
 417                 /* Disable L1-Active */
 418                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 419                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 420
 421                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 422                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 423                                APMG_RTC_INT_STT_RFKILL);
 424         }
 425
 426         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 427
 428         return 0;
 429 }
 430
 431 /*
 432  * Enable LP XTAL to avoid HW bug where device may consume much power if
 433  * FW is not loaded after device reset. LP XTAL is disabled by default
 434  * after device HW reset. Do it only if XTAL is fed by internal source.
 435  * Configure device's "persistence" mode to avoid resetting XTAL again when
 436  * SHRD_HW_RST occurs in S3.
 437  */
 438 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 439 {
 440         int ret;
 441         u32 apmg_gp1_reg;
 442         u32 apmg_xtal_cfg_reg;
 443         u32 dl_cfg_reg;
 444
 445         /* Force XTAL ON */
 446         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 447                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 448
 449         iwl_pcie_sw_reset(trans);
 450
 451         /*
 452          * Set "initialization complete" bit to move adapter from
 453          * D0U* --> D0A* (powered-up active) state.
 454          */
 455         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 456
 457         /*
 458          * Wait for clock stabilization; once stabilized, access to
 459          * device-internal resources is possible.
 460          */
 461         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 462                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 463                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 464                            25000);
 465         if (WARN_ON(ret < 0)) {
 466                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 467                 /* Release XTAL ON request */
 468                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 469                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 470                 return;
 471         }
 472
 473         /*
 474          * Clear "disable persistence" to avoid LP XTAL resetting when
 475          * SHRD_HW_RST is applied in S3.
 476          */
 477         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 478                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 479
 480         /*
 481          * Force APMG XTAL to be active to prevent its disabling by HW
 482          * caused by APMG idle state.
 483          */
 484         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 485                                                     SHR_APMG_XTAL_CFG_REG);
 486         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 487                                  apmg_xtal_cfg_reg |
 488                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 489
 490         iwl_pcie_sw_reset(trans);
 491
 492         /* Enable LP XTAL by indirect access through CSR */
 493         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 494         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 495                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 496                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 497
 498         /* Clear delay line clock power up */
 499         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 500         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 501                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 502
 503         /*
 504          * Enable persistence mode to avoid LP XTAL resetting when
 505          * SHRD_HW_RST is applied in S3.
 506          */
 507         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 508                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 509
 510         /*
 511          * Clear "initialization complete" bit to move adapter from
 512          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 513          */
 514         iwl_clear_bit(trans, CSR_GP_CNTRL,
 515                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 516
 517         /* Activates XTAL resources monitor */
 518         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 519                                  CSR_MONITOR_XTAL_RESOURCES);
 520
 521         /* Release XTAL ON request */
 522         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 523                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 524         udelay(10);
 525
 526         /* Release APMG XTAL */
 527         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 528                                  apmg_xtal_cfg_reg &
 529                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 530 }
 531
 532 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 533 {
 534         int ret;
 535
 536         /* stop device's busmaster DMA activity */
 537         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 538
 539         ret = iwl_poll_bit(trans, CSR_RESET,
 540                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 541                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 542         if (ret < 0)
 543                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 544
 545         IWL_DEBUG_INFO(trans, "stop master\n");
 546 }
 547
 548 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 549 {
 550         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 551
 552         if (op_mode_leave) {
 553                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 554                         iwl_pcie_apm_init(trans);
 555
 556                 /* inform ME that we are leaving */
 557                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 558                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 559                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 560                 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
 561                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 562                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 563                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 564                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 565                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 566                         mdelay(1);
 567                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 568                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 569                 }
 570                 mdelay(5);
 571         }
 572
 573         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 574
 575         /* Stop device's DMA activity */
 576         iwl_pcie_apm_stop_master(trans);
 577
 578         if (trans->cfg->lp_xtal_workaround) {
 579                 iwl_pcie_apm_lp_xtal_enable(trans);
 580                 return;
 581         }
 582
 583         iwl_pcie_sw_reset(trans);
 584
 585         /*
 586          * Clear "initialization complete" bit to move adapter from
 587          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 588          */
 589         iwl_clear_bit(trans, CSR_GP_CNTRL,
 590                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 591 }
 592
 593 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 594 {
 595         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 596         int ret;
 597
 598         /* nic_init */
 599         spin_lock(&trans_pcie->irq_lock);
 600         ret = iwl_pcie_apm_init(trans);
 601         spin_unlock(&trans_pcie->irq_lock);
 602
 603         if (ret)
 604                 return ret;
 605
 606         iwl_pcie_set_pwr(trans, false);
 607
 608         iwl_op_mode_nic_config(trans->op_mode);
 609
 610         /* Allocate the RX queue, or reset if it is already allocated */
 611         iwl_pcie_rx_init(trans);
 612
 613         /* Allocate or reset and init all Tx and Command queues */
 614         if (iwl_pcie_tx_init(trans))
 615                 return -ENOMEM;
 616
 617         if (trans->cfg->base_params->shadow_reg_enable) {
 618                 /* enable shadow regs in HW */
 619                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 620                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 621         }
 622
 623         return 0;
 624 }
 625
 626 #define HW_READY_TIMEOUT (50)
 627
 628 /* Note: returns poll_bit return value, which is >= 0 if success */
 629 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 630 {
 631         int ret;
 632
 633         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 634                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 635
 636         /* See if we got it */
 637         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 638                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 639                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 640                            HW_READY_TIMEOUT);
 641
 642         if (ret >= 0)
 643                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 644
 645         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 646         return ret;
 647 }
 648
 649 /* Note: returns standard 0/-ERROR code */
 650 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 651 {
 652         int ret;
 653         int t = 0;
 654         int iter;
 655
 656         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 657
 658         ret = iwl_pcie_set_hw_ready(trans);
 659         /* If the card is ready, exit 0 */
 660         if (ret >= 0)
 661                 return 0;
 662
 663         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 664                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 665         usleep_range(1000, 2000);
 666
 667         for (iter = 0; iter < 10; iter++) {
 668                 /* If HW is not ready, prepare the conditions to check again */
 669                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 670                             CSR_HW_IF_CONFIG_REG_PREPARE);
 671
 672                 do {
 673                         ret = iwl_pcie_set_hw_ready(trans);
 674                         if (ret >= 0)
 675                                 return 0;
 676
 677                         usleep_range(200, 1000);
 678                         t += 200;
 679                 } while (t < 150000);
 680                 msleep(25);
 681         }
 682
 683         IWL_ERR(trans, "Couldn't prepare the card\n");
 684
 685         return ret;
 686 }
 687
 688 /*
 689  * ucode
 690  */
 691 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 692                                             u32 dst_addr, dma_addr_t phy_addr,
 693                                             u32 byte_cnt)
 694 {
 695         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 696                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 697
 698         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 699                     dst_addr);
 700
 701         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 702                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 703
 704         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 705                     (iwl_get_dma_hi_addr(phy_addr)
 706                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 707
 708         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 709                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 710                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 711                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 712
 713         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 714                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 715                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 716                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 717 }
 718
 719 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 720                                         u32 dst_addr, dma_addr_t phy_addr,
 721                                         u32 byte_cnt)
 722 {
 723         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 724         unsigned long flags;
 725         int ret;
 726
 727         trans_pcie->ucode_write_complete = false;
 728
 729         if (!iwl_trans_grab_nic_access(trans, &flags))
 730                 return -EIO;
 731
 732         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 733                                         byte_cnt);
 734         iwl_trans_release_nic_access(trans, &flags);
 735
 736         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 737                                  trans_pcie->ucode_write_complete, 5 * HZ);
 738         if (!ret) {
 739                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 740                 iwl_trans_pcie_dump_regs(trans);
 741                 return -ETIMEDOUT;
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 748                             const struct fw_desc *section)
 749 {
 750         u8 *v_addr;
 751         dma_addr_t p_addr;
 752         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 753         int ret = 0;
 754
 755         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 756                      section_num);
 757
 758         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 759                                     GFP_KERNEL | __GFP_NOWARN);
 760         if (!v_addr) {
 761                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 762                 chunk_sz = PAGE_SIZE;
 763                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 764                                             &p_addr, GFP_KERNEL);
 765                 if (!v_addr)
 766                         return -ENOMEM;
 767         }
 768
 769         for (offset = 0; offset < section->len; offset += chunk_sz) {
 770                 u32 copy_size, dst_addr;
 771                 bool extended_addr = false;
 772
 773                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 774                 dst_addr = section->offset + offset;
 775
 776                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 777                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 778                         extended_addr = true;
 779
 780                 if (extended_addr)
 781                         iwl_set_bits_prph(trans, LMPM_CHICK,
 782                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 783
 784                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 785                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 786                                                    copy_size);
 787
 788                 if (extended_addr)
 789                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 790                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 791
 792                 if (ret) {
 793                         IWL_ERR(trans,
 794                                 "Could not load the [%d] uCode section\n",
 795                                 section_num);
 796                         break;
 797                 }
 798         }
 799
 800         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 801         return ret;
 802 }
 803
 804 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 805                                            const struct fw_img *image,
 806                                            int cpu,
 807                                            int *first_ucode_section)
 808 {
 809         int shift_param;
 810         int i, ret = 0, sec_num = 0x1;
 811         u32 val, last_read_idx = 0;
 812
 813         if (cpu == 1) {
 814                 shift_param = 0;
 815                 *first_ucode_section = 0;
 816         } else {
 817                 shift_param = 16;
 818                 (*first_ucode_section)++;
 819         }
 820
 821         for (i = *first_ucode_section; i < image->num_sec; i++) {
 822                 last_read_idx = i;
 823
 824                 /*
 825                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 826                  * CPU1 to CPU2.
 827                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 828                  * CPU2 non paged to CPU2 paging sec.
 829                  */
 830                 if (!image->sec[i].data ||
 831                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 832                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 833                         IWL_DEBUG_FW(trans,
 834                                      "Break since Data not valid or Empty section, sec = %d\n",
 835                                      i);
 836                         break;
 837                 }
 838
 839                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 840                 if (ret)
 841                         return ret;
 842
 843                 /* Notify ucode of loaded section number and status */
 844                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 845                 val = val | (sec_num << shift_param);
 846                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 847
 848                 sec_num = (sec_num << 1) | 0x1;
 849         }
 850
 851         *first_ucode_section = last_read_idx;
 852
 853         iwl_enable_interrupts(trans);
 854
 855         if (trans->cfg->use_tfh) {
 856                 if (cpu == 1)
 857                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 858                                        0xFFFF);
 859                 else
 860                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 861                                        0xFFFFFFFF);
 862         } else {
 863                 if (cpu == 1)
 864                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 865                                            0xFFFF);
 866                 else
 867                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 868                                            0xFFFFFFFF);
 869         }
 870
 871         return 0;
 872 }
 873
 874 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 875                                       const struct fw_img *image,
 876                                       int cpu,
 877                                       int *first_ucode_section)
 878 {
 879         int i, ret = 0;
 880         u32 last_read_idx = 0;
 881
 882         if (cpu == 1)
 883                 *first_ucode_section = 0;
 884         else
 885                 (*first_ucode_section)++;
 886
 887         for (i = *first_ucode_section; i < image->num_sec; i++) {
 888                 last_read_idx = i;
 889
 890                 /*
 891                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 892                  * CPU1 to CPU2.
 893                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 894                  * CPU2 non paged to CPU2 paging sec.
 895                  */
 896                 if (!image->sec[i].data ||
 897                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 898                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 899                         IWL_DEBUG_FW(trans,
 900                                      "Break since Data not valid or Empty section, sec = %d\n",
 901                                      i);
 902                         break;
 903                 }
 904
 905                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 906                 if (ret)
 907                         return ret;
 908         }
 909
 910         *first_ucode_section = last_read_idx;
 911
 912         return 0;
 913 }
 914
 915 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 916 {
 917         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 918         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 919         int i;
 920
 921         if (dest->version)
 922                 IWL_ERR(trans,
 923                         "DBG DEST version is %d - expect issues\n",
 924                         dest->version);
 925
 926         IWL_INFO(trans, "Applying debug destination %s\n",
 927                  get_fw_dbg_mode_string(dest->monitor_mode));
 928
 929         if (dest->monitor_mode == EXTERNAL_MODE)
 930                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 931         else
 932                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 933
 934         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 935                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 936                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 937
 938                 switch (dest->reg_ops[i].op) {
 939                 case CSR_ASSIGN:
 940                         iwl_write32(trans, addr, val);
 941                         break;
 942                 case CSR_SETBIT:
 943                         iwl_set_bit(trans, addr, BIT(val));
 944                         break;
 945                 case CSR_CLEARBIT:
 946                         iwl_clear_bit(trans, addr, BIT(val));
 947                         break;
 948                 case PRPH_ASSIGN:
 949                         iwl_write_prph(trans, addr, val);
 950                         break;
 951                 case PRPH_SETBIT:
 952                         iwl_set_bits_prph(trans, addr, BIT(val));
 953                         break;
 954                 case PRPH_CLEARBIT:
 955                         iwl_clear_bits_prph(trans, addr, BIT(val));
 956                         break;
 957                 case PRPH_BLOCKBIT:
 958                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 959                                 IWL_ERR(trans,
 960                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 961                                         val, addr);
 962                                 goto monitor;
 963                         }
 964                         break;
 965                 default:
 966                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 967                                 dest->reg_ops[i].op);
 968                         break;
 969                 }
 970         }
 971
 972 monitor:
 973         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 974                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 975                                trans_pcie->fw_mon_phys >> dest->base_shift);
 976                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 977                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 978                                        (trans_pcie->fw_mon_phys +
 979                                         trans_pcie->fw_mon_size - 256) >>
 980                                                 dest->end_shift);
 981                 else
 982                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 983                                        (trans_pcie->fw_mon_phys +
 984                                         trans_pcie->fw_mon_size) >>
 985                                                 dest->end_shift);
 986         }
 987 }
 988
 989 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 990                                 const struct fw_img *image)
 991 {
 992         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 993         int ret = 0;
 994         int first_ucode_section;
 995
 996         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 997                      image->is_dual_cpus ? "Dual" : "Single");
 998
 999         /* load to FW the binary non secured sections of CPU1 */
1000         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1001         if (ret)
1002                 return ret;
1003
1004         if (image->is_dual_cpus) {
1005                 /* set CPU2 header address */
1006                 iwl_write_prph(trans,
1007                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1008                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1009
1010                 /* load to FW the binary sections of CPU2 */
1011                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1012                                                  &first_ucode_section);
1013                 if (ret)
1014                         return ret;
1015         }
1016
1017         /* supported for 7000 only for the moment */
1018         if (iwlwifi_mod_params.fw_monitor &&
1019             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1020                 iwl_pcie_alloc_fw_monitor(trans, 0);
1021
1022                 if (trans_pcie->fw_mon_size) {
1023                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1024                                        trans_pcie->fw_mon_phys >> 4);
1025                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1026                                        (trans_pcie->fw_mon_phys +
1027                                         trans_pcie->fw_mon_size) >> 4);
1028                 }
1029         } else if (trans->dbg_dest_tlv) {
1030                 iwl_pcie_apply_destination(trans);
1031         }
1032
1033         iwl_enable_interrupts(trans);
1034
1035         /* release CPU reset */
1036         iwl_write32(trans, CSR_RESET, 0);
1037
1038         return 0;
1039 }
1040
1041 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1042                                           const struct fw_img *image)
1043 {
1044         int ret = 0;
1045         int first_ucode_section;
1046
1047         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1048                      image->is_dual_cpus ? "Dual" : "Single");
1049
1050         if (trans->dbg_dest_tlv)
1051                 iwl_pcie_apply_destination(trans);
1052
1053         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1054                         iwl_read_prph(trans, WFPM_GP2));
1055
1056         /*
1057          * Set default value. On resume reading the values that were
1058          * zeored can provide debug data on the resume flow.
1059          * This is for debugging only and has no functional impact.
1060          */
1061         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1062
1063         /* configure the ucode to be ready to get the secured image */
1064         /* release CPU reset */
1065         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1066
1067         /* load to FW the binary Secured sections of CPU1 */
1068         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1069                                               &first_ucode_section);
1070         if (ret)
1071                 return ret;
1072
1073         /* load to FW the binary sections of CPU2 */
1074         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1075                                                &first_ucode_section);
1076 }
1077
1078 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1079 {
1080         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1081         bool hw_rfkill = iwl_is_rfkill_set(trans);
1082         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083         bool report;
1084
1085         if (hw_rfkill) {
1086                 set_bit(STATUS_RFKILL_HW, &trans->status);
1087                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1088         } else {
1089                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1090                 if (trans_pcie->opmode_down)
1091                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1092         }
1093
1094         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1095
1096         if (prev != report)
1097                 iwl_trans_pcie_rf_kill(trans, report);
1098
1099         return hw_rfkill;
1100 }
1101
1102 struct iwl_causes_list {
1103         u32 cause_num;
1104         u32 mask_reg;
1105         u8 addr;
1106 };
1107
1108 static struct iwl_causes_list causes_list[] = {
1109         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1110         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1111         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1112         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1113         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1114         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1115         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1116         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1117         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1118         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1119         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1120         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1121         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1122         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1123 };
1124
1125 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1126 {
1127         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1128         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1129         int i;
1130
1131         /*
1132          * Access all non RX causes and map them to the default irq.
1133          * In case we are missing at least one interrupt vector,
1134          * the first interrupt vector will serve non-RX and FBQ causes.
1135          */
1136         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1137                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1138                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1139                               causes_list[i].cause_num);
1140         }
1141 }
1142
1143 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1144 {
1145         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1146         u32 offset =
1147                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1148         u32 val, idx;
1149
1150         /*
1151          * The first RX queue - fallback queue, which is designated for
1152          * management frame, command responses etc, is always mapped to the
1153          * first interrupt vector. The other RX queues are mapped to
1154          * the other (N - 2) interrupt vectors.
1155          */
1156         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1157         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1158                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1159                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1160                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1161         }
1162         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1163
1164         val = MSIX_FH_INT_CAUSES_Q(0);
1165         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1166                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1167         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1168
1169         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1170                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1171 }
1172
1173 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1174 {
1175         struct iwl_trans *trans = trans_pcie->trans;
1176
1177         if (!trans_pcie->msix_enabled) {
1178                 if (trans->cfg->mq_rx_supported &&
1179                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1180                         iwl_write_prph(trans, UREG_CHICK,
1181                                        UREG_CHICK_MSI_ENABLE);
1182                 return;
1183         }
1184         /*
1185          * The IVAR table needs to be configured again after reset,
1186          * but if the device is disabled, we can't write to
1187          * prph.
1188          */
1189         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1190                 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1191
1192         /*
1193          * Each cause from the causes list above and the RX causes is
1194          * represented as a byte in the IVAR table. The first nibble
1195          * represents the bound interrupt vector of the cause, the second
1196          * represents no auto clear for this cause. This will be set if its
1197          * interrupt vector is bound to serve other causes.
1198          */
1199         iwl_pcie_map_rx_causes(trans);
1200
1201         iwl_pcie_map_non_rx_causes(trans);
1202 }
1203
1204 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1205 {
1206         struct iwl_trans *trans = trans_pcie->trans;
1207
1208         iwl_pcie_conf_msix_hw(trans_pcie);
1209
1210         if (!trans_pcie->msix_enabled)
1211                 return;
1212
1213         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1214         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1215         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1216         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1217 }
1218
1219 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1220 {
1221         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1222
1223         lockdep_assert_held(&trans_pcie->mutex);
1224
1225         if (trans_pcie->is_down)
1226                 return;
1227
1228         trans_pcie->is_down = true;
1229
1230         /* tell the device to stop sending interrupts */
1231         iwl_disable_interrupts(trans);
1232
1233         /* device going down, Stop using ICT table */
1234         iwl_pcie_disable_ict(trans);
1235
1236         /*
1237          * If a HW restart happens during firmware loading,
1238          * then the firmware loading might call this function
1239          * and later it might be called again due to the
1240          * restart. So don't process again if the device is
1241          * already dead.
1242          */
1243         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1244                 IWL_DEBUG_INFO(trans,
1245                                "DEVICE_ENABLED bit was set and is now cleared\n");
1246                 iwl_pcie_tx_stop(trans);
1247                 iwl_pcie_rx_stop(trans);
1248
1249                 /* Power-down device's busmaster DMA clocks */
1250                 if (!trans->cfg->apmg_not_supported) {
1251                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1252                                        APMG_CLK_VAL_DMA_CLK_RQT);
1253                         udelay(5);
1254                 }
1255         }
1256
1257         /* Make sure (redundant) we've released our request to stay awake */
1258         iwl_clear_bit(trans, CSR_GP_CNTRL,
1259                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1260
1261         /* Stop the device, and put it in low power state */
1262         iwl_pcie_apm_stop(trans, false);
1263
1264         iwl_pcie_sw_reset(trans);
1265
1266         /*
1267          * Upon stop, the IVAR table gets erased, so msi-x won't
1268          * work. This causes a bug in RF-KILL flows, since the interrupt
1269          * that enables radio won't fire on the correct irq, and the
1270          * driver won't be able to handle the interrupt.
1271          * Configure the IVAR table again after reset.
1272          */
1273         iwl_pcie_conf_msix_hw(trans_pcie);
1274
1275         /*
1276          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1277          * This is a bug in certain verions of the hardware.
1278          * Certain devices also keep sending HW RF kill interrupt all
1279          * the time, unless the interrupt is ACKed even if the interrupt
1280          * should be masked. Re-ACK all the interrupts here.
1281          */
1282         iwl_disable_interrupts(trans);
1283
1284         /* clear all status bits */
1285         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1286         clear_bit(STATUS_INT_ENABLED, &trans->status);
1287         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1288
1289         /*
1290          * Even if we stop the HW, we still want the RF kill
1291          * interrupt
1292          */
1293         iwl_enable_rfkill_int(trans);
1294
1295         /* re-take ownership to prevent other users from stealing the device */
1296         iwl_pcie_prepare_card_hw(trans);
1297 }
1298
1299 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1300 {
1301         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1302
1303         if (trans_pcie->msix_enabled) {
1304                 int i;
1305
1306                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1307                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1308         } else {
1309                 synchronize_irq(trans_pcie->pci_dev->irq);
1310         }
1311 }
1312
1313 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1314                                    const struct fw_img *fw, bool run_in_rfkill)
1315 {
1316         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1317         bool hw_rfkill;
1318         int ret;
1319
1320         /* This may fail if AMT took ownership of the device */
1321         if (iwl_pcie_prepare_card_hw(trans)) {
1322                 IWL_WARN(trans, "Exit HW not ready\n");
1323                 ret = -EIO;
1324                 goto out;
1325         }
1326
1327         iwl_enable_rfkill_int(trans);
1328
1329         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1330
1331         /*
1332          * We enabled the RF-Kill interrupt and the handler may very
1333          * well be running. Disable the interrupts to make sure no other
1334          * interrupt can be fired.
1335          */
1336         iwl_disable_interrupts(trans);
1337
1338         /* Make sure it finished running */
1339         iwl_pcie_synchronize_irqs(trans);
1340
1341         mutex_lock(&trans_pcie->mutex);
1342
1343         /* If platform's RF_KILL switch is NOT set to KILL */
1344         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1345         if (hw_rfkill && !run_in_rfkill) {
1346                 ret = -ERFKILL;
1347                 goto out;
1348         }
1349
1350         /* Someone called stop_device, don't try to start_fw */
1351         if (trans_pcie->is_down) {
1352                 IWL_WARN(trans,
1353                          "Can't start_fw since the HW hasn't been started\n");
1354                 ret = -EIO;
1355                 goto out;
1356         }
1357
1358         /* make sure rfkill handshake bits are cleared */
1359         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1360         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1361                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1362
1363         /* clear (again), then enable host interrupts */
1364         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1365
1366         ret = iwl_pcie_nic_init(trans);
1367         if (ret) {
1368                 IWL_ERR(trans, "Unable to init nic\n");
1369                 goto out;
1370         }
1371
1372         /*
1373          * Now, we load the firmware and don't want to be interrupted, even
1374          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1375          * FH_TX interrupt which is needed to load the firmware). If the
1376          * RF-Kill switch is toggled, we will find out after having loaded
1377          * the firmware and return the proper value to the caller.
1378          */
1379         iwl_enable_fw_load_int(trans);
1380
1381         /* really make sure rfkill handshake bits are cleared */
1382         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1383         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1384
1385         /* Load the given image to the HW */
1386         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1387                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1388         else
1389                 ret = iwl_pcie_load_given_ucode(trans, fw);
1390
1391         /* re-check RF-Kill state since we may have missed the interrupt */
1392         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1393         if (hw_rfkill && !run_in_rfkill)
1394                 ret = -ERFKILL;
1395
1396 out:
1397         mutex_unlock(&trans_pcie->mutex);
1398         return ret;
1399 }
1400
1401 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1402 {
1403         iwl_pcie_reset_ict(trans);
1404         iwl_pcie_tx_start(trans, scd_addr);
1405 }
1406
1407 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1408                                        bool was_in_rfkill)
1409 {
1410         bool hw_rfkill;
1411
1412         /*
1413          * Check again since the RF kill state may have changed while
1414          * all the interrupts were disabled, in this case we couldn't
1415          * receive the RF kill interrupt and update the state in the
1416          * op_mode.
1417          * Don't call the op_mode if the rkfill state hasn't changed.
1418          * This allows the op_mode to call stop_device from the rfkill
1419          * notification without endless recursion. Under very rare
1420          * circumstances, we might have a small recursion if the rfkill
1421          * state changed exactly now while we were called from stop_device.
1422          * This is very unlikely but can happen and is supported.
1423          */
1424         hw_rfkill = iwl_is_rfkill_set(trans);
1425         if (hw_rfkill) {
1426                 set_bit(STATUS_RFKILL_HW, &trans->status);
1427                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1428         } else {
1429                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1430                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1431         }
1432         if (hw_rfkill != was_in_rfkill)
1433                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1434 }
1435
1436 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1437 {
1438         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1439         bool was_in_rfkill;
1440
1441         mutex_lock(&trans_pcie->mutex);
1442         trans_pcie->opmode_down = true;
1443         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1444         _iwl_trans_pcie_stop_device(trans, low_power);
1445         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1446         mutex_unlock(&trans_pcie->mutex);
1447 }
1448
1449 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1450 {
1451         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1452                 IWL_TRANS_GET_PCIE_TRANS(trans);
1453
1454         lockdep_assert_held(&trans_pcie->mutex);
1455
1456         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1457                  state ? "disabled" : "enabled");
1458         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1459                 if (trans->cfg->gen2)
1460                         _iwl_trans_pcie_gen2_stop_device(trans, true);
1461                 else
1462                         _iwl_trans_pcie_stop_device(trans, true);
1463         }
1464 }
1465
1466 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1467                                       bool reset)
1468 {
1469         if (!reset) {
1470                 /* Enable persistence mode to avoid reset */
1471                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1472                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1473         }
1474
1475         iwl_disable_interrupts(trans);
1476
1477         /*
1478          * in testing mode, the host stays awake and the
1479          * hardware won't be reset (not even partially)
1480          */
1481         if (test)
1482                 return;
1483
1484         iwl_pcie_disable_ict(trans);
1485
1486         iwl_pcie_synchronize_irqs(trans);
1487
1488         iwl_clear_bit(trans, CSR_GP_CNTRL,
1489                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1490         iwl_clear_bit(trans, CSR_GP_CNTRL,
1491                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1492
1493         iwl_pcie_enable_rx_wake(trans, false);
1494
1495         if (reset) {
1496                 /*
1497                  * reset TX queues -- some of their registers reset during S3
1498                  * so if we don't reset everything here the D3 image would try
1499                  * to execute some invalid memory upon resume
1500                  */
1501                 iwl_trans_pcie_tx_reset(trans);
1502         }
1503
1504         iwl_pcie_set_pwr(trans, true);
1505 }
1506
1507 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1508                                     enum iwl_d3_status *status,
1509                                     bool test,  bool reset)
1510 {
1511         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1512         u32 val;
1513         int ret;
1514
1515         if (test) {
1516                 iwl_enable_interrupts(trans);
1517                 *status = IWL_D3_STATUS_ALIVE;
1518                 return 0;
1519         }
1520
1521         iwl_pcie_enable_rx_wake(trans, true);
1522
1523         /*
1524          * Reconfigure IVAR table in case of MSIX or reset ict table in
1525          * MSI mode since HW reset erased it.
1526          * Also enables interrupts - none will happen as
1527          * the device doesn't know we're waking it up, only when
1528          * the opmode actually tells it after this call.
1529          */
1530         iwl_pcie_conf_msix_hw(trans_pcie);
1531         if (!trans_pcie->msix_enabled)
1532                 iwl_pcie_reset_ict(trans);
1533         iwl_enable_interrupts(trans);
1534
1535         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1536         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1537
1538         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1539                 udelay(2);
1540
1541         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1542                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1543                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1544                            25000);
1545         if (ret < 0) {
1546                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1547                 return ret;
1548         }
1549
1550         iwl_pcie_set_pwr(trans, false);
1551
1552         if (!reset) {
1553                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1554                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1555         } else {
1556                 iwl_trans_pcie_tx_reset(trans);
1557
1558                 ret = iwl_pcie_rx_init(trans);
1559                 if (ret) {
1560                         IWL_ERR(trans,
1561                                 "Failed to resume the device (RX reset)\n");
1562                         return ret;
1563                 }
1564         }
1565
1566         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1567                         iwl_read_prph(trans, WFPM_GP2));
1568
1569         val = iwl_read32(trans, CSR_RESET);
1570         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1571                 *status = IWL_D3_STATUS_RESET;
1572         else
1573                 *status = IWL_D3_STATUS_ALIVE;
1574
1575         return 0;
1576 }
1577
1578 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1579                                         struct iwl_trans *trans)
1580 {
1581         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1582         int max_irqs, num_irqs, i, ret, nr_online_cpus;
1583         u16 pci_cmd;
1584
1585         if (!trans->cfg->mq_rx_supported)
1586                 goto enable_msi;
1587
1588         nr_online_cpus = num_online_cpus();
1589         max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
1590         for (i = 0; i < max_irqs; i++)
1591                 trans_pcie->msix_entries[i].entry = i;
1592
1593         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1594                                          MSIX_MIN_INTERRUPT_VECTORS,
1595                                          max_irqs);
1596         if (num_irqs < 0) {
1597                 IWL_DEBUG_INFO(trans,
1598                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1599                                num_irqs);
1600                 goto enable_msi;
1601         }
1602         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1603
1604         IWL_DEBUG_INFO(trans,
1605                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1606                        num_irqs);
1607
1608         /*
1609          * In case the OS provides fewer interrupts than requested, different
1610          * causes will share the same interrupt vector as follows:
1611          * One interrupt less: non rx causes shared with FBQ.
1612          * Two interrupts less: non rx causes shared with FBQ and RSS.
1613          * More than two interrupts: we will use fewer RSS queues.
1614          */
1615         if (num_irqs <= nr_online_cpus) {
1616                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1617                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1618                         IWL_SHARED_IRQ_FIRST_RSS;
1619         } else if (num_irqs == nr_online_cpus + 1) {
1620                 trans_pcie->trans->num_rx_queues = num_irqs;
1621                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1622         } else {
1623                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1624         }
1625
1626         trans_pcie->alloc_vecs = num_irqs;
1627         trans_pcie->msix_enabled = true;
1628         return;
1629
1630 enable_msi:
1631         ret = pci_enable_msi(pdev);
1632         if (ret) {
1633                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1634                 /* enable rfkill interrupt: hw bug w/a */
1635                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1636                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1637                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1638                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1639                 }
1640         }
1641 }
1642
1643 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1644 {
1645         int iter_rx_q, i, ret, cpu, offset;
1646         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1647
1648         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1649         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1650         offset = 1 + i;
1651         for (; i < iter_rx_q ; i++) {
1652                 /*
1653                  * Get the cpu prior to the place to search
1654                  * (i.e. return will be > i - 1).
1655                  */
1656                 cpu = cpumask_next(i - offset, cpu_online_mask);
1657                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1658                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1659                                             &trans_pcie->affinity_mask[i]);
1660                 if (ret)
1661                         IWL_ERR(trans_pcie->trans,
1662                                 "Failed to set affinity mask for IRQ %d\n",
1663                                 i);
1664         }
1665 }
1666
1667 static const char *queue_name(struct device *dev,
1668                               struct iwl_trans_pcie *trans_p, int i)
1669 {
1670         if (trans_p->shared_vec_mask) {
1671                 int vec = trans_p->shared_vec_mask &
1672                           IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1673
1674                 if (i == 0)
1675                         return DRV_NAME ": shared IRQ";
1676
1677                 return devm_kasprintf(dev, GFP_KERNEL,
1678                                       DRV_NAME ": queue %d", i + vec);
1679         }
1680         if (i == 0)
1681                 return DRV_NAME ": default queue";
1682
1683         if (i == trans_p->alloc_vecs - 1)
1684                 return DRV_NAME ": exception";
1685
1686         return devm_kasprintf(dev, GFP_KERNEL,
1687                               DRV_NAME  ": queue %d", i);
1688 }
1689
1690 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1691                                       struct iwl_trans_pcie *trans_pcie)
1692 {
1693         int i;
1694
1695         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1696                 int ret;
1697                 struct msix_entry *msix_entry;
1698                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1699
1700                 if (!qname)
1701                         return -ENOMEM;
1702
1703                 msix_entry = &trans_pcie->msix_entries[i];
1704                 ret = devm_request_threaded_irq(&pdev->dev,
1705                                                 msix_entry->vector,
1706                                                 iwl_pcie_msix_isr,
1707                                                 (i == trans_pcie->def_irq) ?
1708                                                 iwl_pcie_irq_msix_handler :
1709                                                 iwl_pcie_irq_rx_msix_handler,
1710                                                 IRQF_SHARED,
1711                                                 qname,
1712                                                 msix_entry);
1713                 if (ret) {
1714                         IWL_ERR(trans_pcie->trans,
1715                                 "Error allocating IRQ %d\n", i);
1716
1717                         return ret;
1718                 }
1719         }
1720         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1721
1722         return 0;
1723 }
1724
1725 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1726 {
1727         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1728         int err;
1729
1730         lockdep_assert_held(&trans_pcie->mutex);
1731
1732         err = iwl_pcie_prepare_card_hw(trans);
1733         if (err) {
1734                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1735                 return err;
1736         }
1737
1738         iwl_pcie_sw_reset(trans);
1739
1740         err = iwl_pcie_apm_init(trans);
1741         if (err)
1742                 return err;
1743
1744         iwl_pcie_init_msix(trans_pcie);
1745
1746         /* From now on, the op_mode will be kept updated about RF kill state */
1747         iwl_enable_rfkill_int(trans);
1748
1749         trans_pcie->opmode_down = false;
1750
1751         /* Set is_down to false here so that...*/
1752         trans_pcie->is_down = false;
1753
1754         /* ...rfkill can call stop_device and set it false if needed */
1755         iwl_pcie_check_hw_rf_kill(trans);
1756
1757         /* Make sure we sync here, because we'll need full access later */
1758         if (low_power)
1759                 pm_runtime_resume(trans->dev);
1760
1761         return 0;
1762 }
1763
1764 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1765 {
1766         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1767         int ret;
1768
1769         mutex_lock(&trans_pcie->mutex);
1770         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1771         mutex_unlock(&trans_pcie->mutex);
1772
1773         return ret;
1774 }
1775
1776 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1777 {
1778         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1779
1780         mutex_lock(&trans_pcie->mutex);
1781
1782         /* disable interrupts - don't enable HW RF kill interrupt */
1783         iwl_disable_interrupts(trans);
1784
1785         iwl_pcie_apm_stop(trans, true);
1786
1787         iwl_disable_interrupts(trans);
1788
1789         iwl_pcie_disable_ict(trans);
1790
1791         mutex_unlock(&trans_pcie->mutex);
1792
1793         iwl_pcie_synchronize_irqs(trans);
1794 }
1795
1796 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1797 {
1798         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1799 }
1800
1801 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1802 {
1803         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1804 }
1805
1806 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1807 {
1808         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1809 }
1810
1811 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1812 {
1813         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1814                                ((reg & 0x000FFFFF) | (3 << 24)));
1815         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1816 }
1817
1818 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1819                                       u32 val)
1820 {
1821         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1822                                ((addr & 0x000FFFFF) | (3 << 24)));
1823         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1824 }
1825
1826 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1827                                      const struct iwl_trans_config *trans_cfg)
1828 {
1829         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1830
1831         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1832         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1833         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1834         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1835                 trans_pcie->n_no_reclaim_cmds = 0;
1836         else
1837                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1838         if (trans_pcie->n_no_reclaim_cmds)
1839                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1840                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1841
1842         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1843         trans_pcie->rx_page_order =
1844                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1845
1846         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1847         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1848         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1849
1850         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1851         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1852
1853         trans->command_groups = trans_cfg->command_groups;
1854         trans->command_groups_size = trans_cfg->command_groups_size;
1855
1856         /* Initialize NAPI here - it should be before registering to mac80211
1857          * in the opmode but after the HW struct is allocated.
1858          * As this function may be called again in some corner cases don't
1859          * do anything if NAPI was already initialized.
1860          */
1861         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1862                 init_dummy_netdev(&trans_pcie->napi_dev);
1863 }
1864
1865 void iwl_trans_pcie_free(struct iwl_trans *trans)
1866 {
1867         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1868         int i;
1869
1870         iwl_pcie_synchronize_irqs(trans);
1871
1872         if (trans->cfg->gen2)
1873                 iwl_pcie_gen2_tx_free(trans);
1874         else
1875                 iwl_pcie_tx_free(trans);
1876         iwl_pcie_rx_free(trans);
1877
1878         if (trans_pcie->rba.alloc_wq) {
1879                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1880                 trans_pcie->rba.alloc_wq = NULL;
1881         }
1882
1883         if (trans_pcie->msix_enabled) {
1884                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1885                         irq_set_affinity_hint(
1886                                 trans_pcie->msix_entries[i].vector,
1887                                 NULL);
1888                 }
1889
1890                 trans_pcie->msix_enabled = false;
1891         } else {
1892                 iwl_pcie_free_ict(trans);
1893         }
1894
1895         iwl_pcie_free_fw_monitor(trans);
1896
1897         for_each_possible_cpu(i) {
1898                 struct iwl_tso_hdr_page *p =
1899                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1900
1901                 if (p->page)
1902                         __free_page(p->page);
1903         }
1904
1905         free_percpu(trans_pcie->tso_hdr_page);
1906         mutex_destroy(&trans_pcie->mutex);
1907         iwl_trans_free(trans);
1908 }
1909
1910 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1911 {
1912         if (state)
1913                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1914         else
1915                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1916 }
1917
1918 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1919                                            unsigned long *flags)
1920 {
1921         int ret;
1922         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1923
1924         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1925
1926         if (trans_pcie->cmd_hold_nic_awake)
1927                 goto out;
1928
1929         /* this bit wakes up the NIC */
1930         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1931                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1932         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1933                 udelay(2);
1934
1935         /*
1936          * These bits say the device is running, and should keep running for
1937          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1938          * but they do not indicate that embedded SRAM is restored yet;
1939          * HW with volatile SRAM must save/restore contents to/from
1940          * host DRAM when sleeping/waking for power-saving.
1941          * Each direction takes approximately 1/4 millisecond; with this
1942          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1943          * series of register accesses are expected (e.g. reading Event Log),
1944          * to keep device from sleeping.
1945          *
1946          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1947          * SRAM is okay/restored.  We don't check that here because this call
1948          * is just for hardware register access; but GP1 MAC_SLEEP
1949          * check is a good idea before accessing the SRAM of HW with
1950          * volatile SRAM (e.g. reading Event Log).
1951          *
1952          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1953          * and do not save/restore SRAM when power cycling.
1954          */
1955         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1956                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1957                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1958                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1959         if (unlikely(ret < 0)) {
1960                 iwl_trans_pcie_dump_regs(trans);
1961                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1962                 WARN_ONCE(1,
1963                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1964                           iwl_read32(trans, CSR_GP_CNTRL));
1965                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1966                 return false;
1967         }
1968
1969 out:
1970         /*
1971          * Fool sparse by faking we release the lock - sparse will
1972          * track nic_access anyway.
1973          */
1974         __release(&trans_pcie->reg_lock);
1975         return true;
1976 }
1977
1978 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1979                                               unsigned long *flags)
1980 {
1981         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1982
1983         lockdep_assert_held(&trans_pcie->reg_lock);
1984
1985         /*
1986          * Fool sparse by faking we acquiring the lock - sparse will
1987          * track nic_access anyway.
1988          */
1989         __acquire(&trans_pcie->reg_lock);
1990
1991         if (trans_pcie->cmd_hold_nic_awake)
1992                 goto out;
1993
1994         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1995                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1996         /*
1997          * Above we read the CSR_GP_CNTRL register, which will flush
1998          * any previous writes, but we need the write that clears the
1999          * MAC_ACCESS_REQ bit to be performed before any other writes
2000          * scheduled on different CPUs (after we drop reg_lock).
2001          */
2002         mmiowb();
2003 out:
2004         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2005 }
2006
2007 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2008                                    void *buf, int dwords)
2009 {
2010         unsigned long flags;
2011         int offs, ret = 0;
2012         u32 *vals = buf;
2013
2014         if (iwl_trans_grab_nic_access(trans, &flags)) {
2015                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2016                 for (offs = 0; offs < dwords; offs++)
2017                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2018                 iwl_trans_release_nic_access(trans, &flags);
2019         } else {
2020                 ret = -EBUSY;
2021         }
2022         return ret;
2023 }
2024
2025 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2026                                     const void *buf, int dwords)
2027 {
2028         unsigned long flags;
2029         int offs, ret = 0;
2030         const u32 *vals = buf;
2031
2032         if (iwl_trans_grab_nic_access(trans, &flags)) {
2033                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2034                 for (offs = 0; offs < dwords; offs++)
2035                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2036                                     vals ? vals[offs] : 0);
2037                 iwl_trans_release_nic_access(trans, &flags);
2038         } else {
2039                 ret = -EBUSY;
2040         }
2041         return ret;
2042 }
2043
2044 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2045                                             unsigned long txqs,
2046                                             bool freeze)
2047 {
2048         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2049         int queue;
2050
2051         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2052                 struct iwl_txq *txq = trans_pcie->txq[queue];
2053                 unsigned long now;
2054
2055                 spin_lock_bh(&txq->lock);
2056
2057                 now = jiffies;
2058
2059                 if (txq->frozen == freeze)
2060                         goto next_queue;
2061
2062                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2063                                     freeze ? "Freezing" : "Waking", queue);
2064
2065                 txq->frozen = freeze;
2066
2067                 if (txq->read_ptr == txq->write_ptr)
2068                         goto next_queue;
2069
2070                 if (freeze) {
2071                         if (unlikely(time_after(now,
2072                                                 txq->stuck_timer.expires))) {
2073                                 /*
2074                                  * The timer should have fired, maybe it is
2075                                  * spinning right now on the lock.
2076                                  */
2077                                 goto next_queue;
2078                         }
2079                         /* remember how long until the timer fires */
2080                         txq->frozen_expiry_remainder =
2081                                 txq->stuck_timer.expires - now;
2082                         del_timer(&txq->stuck_timer);
2083                         goto next_queue;
2084                 }
2085
2086                 /*
2087                  * Wake a non-empty queue -> arm timer with the
2088                  * remainder before it froze
2089                  */
2090                 mod_timer(&txq->stuck_timer,
2091                           now + txq->frozen_expiry_remainder);
2092
2093 next_queue:
2094                 spin_unlock_bh(&txq->lock);
2095         }
2096 }
2097
2098 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2099 {
2100         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2101         int i;
2102
2103         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2104                 struct iwl_txq *txq = trans_pcie->txq[i];
2105
2106                 if (i == trans_pcie->cmd_queue)
2107                         continue;
2108
2109                 spin_lock_bh(&txq->lock);
2110
2111                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2112                         txq->block--;
2113                         if (!txq->block) {
2114                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2115                                             txq->write_ptr | (i << 8));
2116                         }
2117                 } else if (block) {
2118                         txq->block++;
2119                 }
2120
2121                 spin_unlock_bh(&txq->lock);
2122         }
2123 }
2124
2125 #define IWL_FLUSH_WAIT_MS       2000
2126
2127 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2128 {
2129         u32 txq_id = txq->id;
2130         u32 status;
2131         bool active;
2132         u8 fifo;
2133
2134         if (trans->cfg->use_tfh) {
2135                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2136                         txq->read_ptr, txq->write_ptr);
2137                 /* TODO: access new SCD registers and dump them */
2138                 return;
2139         }
2140
2141         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2142         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2143         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2144
2145         IWL_ERR(trans,
2146                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2147                 txq_id, active ? "" : "in", fifo,
2148                 jiffies_to_msecs(txq->wd_timeout),
2149                 txq->read_ptr, txq->write_ptr,
2150                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2151                         (TFD_QUEUE_SIZE_MAX - 1),
2152                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2153                         (TFD_QUEUE_SIZE_MAX - 1),
2154                 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2155 }
2156
2157 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2158 {
2159         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2160         struct iwl_txq *txq;
2161         unsigned long now = jiffies;
2162         u8 wr_ptr;
2163
2164         if (!test_bit(txq_idx, trans_pcie->queue_used))
2165                 return -EINVAL;
2166
2167         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2168         txq = trans_pcie->txq[txq_idx];
2169         wr_ptr = READ_ONCE(txq->write_ptr);
2170
2171         while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
2172                !time_after(jiffies,
2173                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2174                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2175
2176                 if (WARN_ONCE(wr_ptr != write_ptr,
2177                               "WR pointer moved while flushing %d -> %d\n",
2178                               wr_ptr, write_ptr))
2179                         return -ETIMEDOUT;
2180                 usleep_range(1000, 2000);
2181         }
2182
2183         if (txq->read_ptr != txq->write_ptr) {
2184                 IWL_ERR(trans,
2185                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2186                 iwl_trans_pcie_log_scd_error(trans, txq);
2187                 return -ETIMEDOUT;
2188         }
2189
2190         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2191
2192         return 0;
2193 }
2194
2195 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2196 {
2197         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2198         int cnt;
2199         int ret = 0;
2200
2201         /* waiting for all the tx frames complete might take a while */
2202         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2203
2204                 if (cnt == trans_pcie->cmd_queue)
2205                         continue;
2206                 if (!test_bit(cnt, trans_pcie->queue_used))
2207                         continue;
2208                 if (!(BIT(cnt) & txq_bm))
2209                         continue;
2210
2211                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2212                 if (ret)
2213                         break;
2214         }
2215
2216         return ret;
2217 }
2218
2219 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2220                                          u32 mask, u32 value)
2221 {
2222         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2223         unsigned long flags;
2224
2225         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2226         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2227         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2228 }
2229
2230 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2231 {
2232         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2233
2234         if (iwlwifi_mod_params.d0i3_disable)
2235                 return;
2236
2237         pm_runtime_get(&trans_pcie->pci_dev->dev);
2238
2239 #ifdef CONFIG_PM
2240         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2241                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2242 #endif /* CONFIG_PM */
2243 }
2244
2245 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2246 {
2247         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2248
2249         if (iwlwifi_mod_params.d0i3_disable)
2250                 return;
2251
2252         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2253         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2254
2255 #ifdef CONFIG_PM
2256         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2257                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2258 #endif /* CONFIG_PM */
2259 }
2260
2261 static const char *get_csr_string(int cmd)
2262 {
2263 #define IWL_CMD(x) case x: return #x
2264         switch (cmd) {
2265         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2266         IWL_CMD(CSR_INT_COALESCING);
2267         IWL_CMD(CSR_INT);
2268         IWL_CMD(CSR_INT_MASK);
2269         IWL_CMD(CSR_FH_INT_STATUS);
2270         IWL_CMD(CSR_GPIO_IN);
2271         IWL_CMD(CSR_RESET);
2272         IWL_CMD(CSR_GP_CNTRL);
2273         IWL_CMD(CSR_HW_REV);
2274         IWL_CMD(CSR_EEPROM_REG);
2275         IWL_CMD(CSR_EEPROM_GP);
2276         IWL_CMD(CSR_OTP_GP_REG);
2277         IWL_CMD(CSR_GIO_REG);
2278         IWL_CMD(CSR_GP_UCODE_REG);
2279         IWL_CMD(CSR_GP_DRIVER_REG);
2280         IWL_CMD(CSR_UCODE_DRV_GP1);
2281         IWL_CMD(CSR_UCODE_DRV_GP2);
2282         IWL_CMD(CSR_LED_REG);
2283         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2284         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2285         IWL_CMD(CSR_ANA_PLL_CFG);
2286         IWL_CMD(CSR_HW_REV_WA_REG);
2287         IWL_CMD(CSR_MONITOR_STATUS_REG);
2288         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2289         default:
2290                 return "UNKNOWN";
2291         }
2292 #undef IWL_CMD
2293 }
2294
2295 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2296 {
2297         int i;
2298         static const u32 csr_tbl[] = {
2299                 CSR_HW_IF_CONFIG_REG,
2300                 CSR_INT_COALESCING,
2301                 CSR_INT,
2302                 CSR_INT_MASK,
2303                 CSR_FH_INT_STATUS,
2304                 CSR_GPIO_IN,
2305                 CSR_RESET,
2306                 CSR_GP_CNTRL,
2307                 CSR_HW_REV,
2308                 CSR_EEPROM_REG,
2309                 CSR_EEPROM_GP,
2310                 CSR_OTP_GP_REG,
2311                 CSR_GIO_REG,
2312                 CSR_GP_UCODE_REG,
2313                 CSR_GP_DRIVER_REG,
2314                 CSR_UCODE_DRV_GP1,
2315                 CSR_UCODE_DRV_GP2,
2316                 CSR_LED_REG,
2317                 CSR_DRAM_INT_TBL_REG,
2318                 CSR_GIO_CHICKEN_BITS,
2319                 CSR_ANA_PLL_CFG,
2320                 CSR_MONITOR_STATUS_REG,
2321                 CSR_HW_REV_WA_REG,
2322                 CSR_DBG_HPET_MEM_REG
2323         };
2324         IWL_ERR(trans, "CSR values:\n");
2325         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2326                 "CSR_INT_PERIODIC_REG)\n");
2327         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2328                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2329                         get_csr_string(csr_tbl[i]),
2330                         iwl_read32(trans, csr_tbl[i]));
2331         }
2332 }
2333
2334 #ifdef CONFIG_IWLWIFI_DEBUGFS
2335 /* create and remove of files */
2336 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2337         if (!debugfs_create_file(#name, mode, parent, trans,            \
2338                                  &iwl_dbgfs_##name##_ops))              \
2339                 goto err;                                               \
2340 } while (0)
2341
2342 /* file operation */
2343 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2344 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2345         .read = iwl_dbgfs_##name##_read,                                \
2346         .open = simple_open,                                            \
2347         .llseek = generic_file_llseek,                                  \
2348 };
2349
2350 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2351 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2352         .write = iwl_dbgfs_##name##_write,                              \
2353         .open = simple_open,                                            \
2354         .llseek = generic_file_llseek,                                  \
2355 };
2356
2357 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2358 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2359         .write = iwl_dbgfs_##name##_write,                              \
2360         .read = iwl_dbgfs_##name##_read,                                \
2361         .open = simple_open,                                            \
2362         .llseek = generic_file_llseek,                                  \
2363 };
2364
2365 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2366                                        char __user *user_buf,
2367                                        size_t count, loff_t *ppos)
2368 {
2369         struct iwl_trans *trans = file->private_data;
2370         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2371         struct iwl_txq *txq;
2372         char *buf;
2373         int pos = 0;
2374         int cnt;
2375         int ret;
2376         size_t bufsz;
2377
2378         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2379
2380         if (!trans_pcie->txq_memory)
2381                 return -EAGAIN;
2382
2383         buf = kzalloc(bufsz, GFP_KERNEL);
2384         if (!buf)
2385                 return -ENOMEM;
2386
2387         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2388                 txq = trans_pcie->txq[cnt];
2389                 pos += scnprintf(buf + pos, bufsz - pos,
2390                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2391                                 cnt, txq->read_ptr, txq->write_ptr,
2392                                 !!test_bit(cnt, trans_pcie->queue_used),
2393                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2394                                  txq->need_update, txq->frozen,
2395                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2396         }
2397         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2398         kfree(buf);
2399         return ret;
2400 }
2401
2402 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2403                                        char __user *user_buf,
2404                                        size_t count, loff_t *ppos)
2405 {
2406         struct iwl_trans *trans = file->private_data;
2407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2408         char *buf;
2409         int pos = 0, i, ret;
2410         size_t bufsz = sizeof(buf);
2411
2412         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2413
2414         if (!trans_pcie->rxq)
2415                 return -EAGAIN;
2416
2417         buf = kzalloc(bufsz, GFP_KERNEL);
2418         if (!buf)
2419                 return -ENOMEM;
2420
2421         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2422                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2423
2424                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2425                                  i);
2426                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2427                                  rxq->read);
2428                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2429                                  rxq->write);
2430                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2431                                  rxq->write_actual);
2432                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2433                                  rxq->need_update);
2434                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2435                                  rxq->free_count);
2436                 if (rxq->rb_stts) {
2437                         pos += scnprintf(buf + pos, bufsz - pos,
2438                                          "\tclosed_rb_num: %u\n",
2439                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2440                                          0x0FFF);
2441                 } else {
2442                         pos += scnprintf(buf + pos, bufsz - pos,
2443                                          "\tclosed_rb_num: Not Allocated\n");
2444                 }
2445         }
2446         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2447         kfree(buf);
2448
2449         return ret;
2450 }
2451
2452 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2453                                         char __user *user_buf,
2454                                         size_t count, loff_t *ppos)
2455 {
2456         struct iwl_trans *trans = file->private_data;
2457         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2458         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2459
2460         int pos = 0;
2461         char *buf;
2462         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2463         ssize_t ret;
2464
2465         buf = kzalloc(bufsz, GFP_KERNEL);
2466         if (!buf)
2467                 return -ENOMEM;
2468
2469         pos += scnprintf(buf + pos, bufsz - pos,
2470                         "Interrupt Statistics Report:\n");
2471
2472         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2473                 isr_stats->hw);
2474         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2475                 isr_stats->sw);
2476         if (isr_stats->sw || isr_stats->hw) {
2477                 pos += scnprintf(buf + pos, bufsz - pos,
2478                         "\tLast Restarting Code:  0x%X\n",
2479                         isr_stats->err_code);
2480         }
2481 #ifdef CONFIG_IWLWIFI_DEBUG
2482         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2483                 isr_stats->sch);
2484         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2485                 isr_stats->alive);
2486 #endif
2487         pos += scnprintf(buf + pos, bufsz - pos,
2488                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2489
2490         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2491                 isr_stats->ctkill);
2492
2493         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2494                 isr_stats->wakeup);
2495
2496         pos += scnprintf(buf + pos, bufsz - pos,
2497                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2498
2499         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2500                 isr_stats->tx);
2501
2502         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2503                 isr_stats->unhandled);
2504
2505         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2506         kfree(buf);
2507         return ret;
2508 }
2509
2510 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2511                                          const char __user *user_buf,
2512                                          size_t count, loff_t *ppos)
2513 {
2514         struct iwl_trans *trans = file->private_data;
2515         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2516         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2517         u32 reset_flag;
2518         int ret;
2519
2520         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2521         if (ret)
2522                 return ret;
2523         if (reset_flag == 0)
2524                 memset(isr_stats, 0, sizeof(*isr_stats));
2525
2526         return count;
2527 }
2528
2529 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2530                                    const char __user *user_buf,
2531                                    size_t count, loff_t *ppos)
2532 {
2533         struct iwl_trans *trans = file->private_data;
2534
2535         iwl_pcie_dump_csr(trans);
2536
2537         return count;
2538 }
2539
2540 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2541                                      char __user *user_buf,
2542                                      size_t count, loff_t *ppos)
2543 {
2544         struct iwl_trans *trans = file->private_data;
2545         char *buf = NULL;
2546         ssize_t ret;
2547
2548         ret = iwl_dump_fh(trans, &buf);
2549         if (ret < 0)
2550                 return ret;
2551         if (!buf)
2552                 return -EINVAL;
2553         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2554         kfree(buf);
2555         return ret;
2556 }
2557
2558 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2559                                      char __user *user_buf,
2560                                      size_t count, loff_t *ppos)
2561 {
2562         struct iwl_trans *trans = file->private_data;
2563         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2564         char buf[100];
2565         int pos;
2566
2567         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2568                         trans_pcie->debug_rfkill,
2569                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2570                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2571
2572         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2573 }
2574
2575 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2576                                       const char __user *user_buf,
2577                                       size_t count, loff_t *ppos)
2578 {
2579         struct iwl_trans *trans = file->private_data;
2580         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2581         bool old = trans_pcie->debug_rfkill;
2582         int ret;
2583
2584         ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2585         if (ret)
2586                 return ret;
2587         if (old == trans_pcie->debug_rfkill)
2588                 return count;
2589         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2590                  old, trans_pcie->debug_rfkill);
2591         iwl_pcie_handle_rfkill_irq(trans);
2592
2593         return count;
2594 }
2595
2596 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2597 DEBUGFS_READ_FILE_OPS(fh_reg);
2598 DEBUGFS_READ_FILE_OPS(rx_queue);
2599 DEBUGFS_READ_FILE_OPS(tx_queue);
2600 DEBUGFS_WRITE_FILE_OPS(csr);
2601 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2602
2603 /* Create the debugfs files and directories */
2604 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2605 {
2606         struct dentry *dir = trans->dbgfs_dir;
2607
2608         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2609         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2610         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2611         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2612         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2613         DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
2614         return 0;
2615
2616 err:
2617         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2618         return -ENOMEM;
2619 }
2620 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2621
2622 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2623 {
2624         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2625         u32 cmdlen = 0;
2626         int i;
2627
2628         for (i = 0; i < trans_pcie->max_tbs; i++)
2629                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2630
2631         return cmdlen;
2632 }
2633
2634 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2635                                    struct iwl_fw_error_dump_data **data,
2636                                    int allocated_rb_nums)
2637 {
2638         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2639         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2640         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2641         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2642         u32 i, r, j, rb_len = 0;
2643
2644         spin_lock(&rxq->lock);
2645
2646         r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2647
2648         for (i = rxq->read, j = 0;
2649              i != r && j < allocated_rb_nums;
2650              i = (i + 1) & RX_QUEUE_MASK, j++) {
2651                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2652                 struct iwl_fw_error_dump_rb *rb;
2653
2654                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2655                                DMA_FROM_DEVICE);
2656
2657                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2658
2659                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2660                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2661                 rb = (void *)(*data)->data;
2662                 rb->index = cpu_to_le32(i);
2663                 memcpy(rb->data, page_address(rxb->page), max_len);
2664                 /* remap the page for the free benefit */
2665                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2666                                                      max_len,
2667                                                      DMA_FROM_DEVICE);
2668
2669                 *data = iwl_fw_error_next_data(*data);
2670         }
2671
2672         spin_unlock(&rxq->lock);
2673
2674         return rb_len;
2675 }
2676 #define IWL_CSR_TO_DUMP (0x250)
2677
2678 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2679                                    struct iwl_fw_error_dump_data **data)
2680 {
2681         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2682         __le32 *val;
2683         int i;
2684
2685         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2686         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2687         val = (void *)(*data)->data;
2688
2689         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2690                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2691
2692         *data = iwl_fw_error_next_data(*data);
2693
2694         return csr_len;
2695 }
2696
2697 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2698                                        struct iwl_fw_error_dump_data **data)
2699 {
2700         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2701         unsigned long flags;
2702         __le32 *val;
2703         int i;
2704
2705         if (!iwl_trans_grab_nic_access(trans, &flags))
2706                 return 0;
2707
2708         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2709         (*data)->len = cpu_to_le32(fh_regs_len);
2710         val = (void *)(*data)->data;
2711
2712         if (!trans->cfg->gen2)
2713                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2714                      i += sizeof(u32))
2715                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2716         else
2717                 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2718                      i += sizeof(u32))
2719                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2720                                                                       i));
2721
2722         iwl_trans_release_nic_access(trans, &flags);
2723
2724         *data = iwl_fw_error_next_data(*data);
2725
2726         return sizeof(**data) + fh_regs_len;
2727 }
2728
2729 static u32
2730 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2731                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2732                                  u32 monitor_len)
2733 {
2734         u32 buf_size_in_dwords = (monitor_len >> 2);
2735         u32 *buffer = (u32 *)fw_mon_data->data;
2736         unsigned long flags;
2737         u32 i;
2738
2739         if (!iwl_trans_grab_nic_access(trans, &flags))
2740                 return 0;
2741
2742         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2743         for (i = 0; i < buf_size_in_dwords; i++)
2744                 buffer[i] = iwl_read_prph_no_grab(trans,
2745                                 MON_DMARB_RD_DATA_ADDR);
2746         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2747
2748         iwl_trans_release_nic_access(trans, &flags);
2749
2750         return monitor_len;
2751 }
2752
2753 static u32
2754 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2755                             struct iwl_fw_error_dump_data **data,
2756                             u32 monitor_len)
2757 {
2758         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2759         u32 len = 0;
2760
2761         if ((trans_pcie->fw_mon_page &&
2762              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2763             trans->dbg_dest_tlv) {
2764                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2765                 u32 base, write_ptr, wrap_cnt;
2766
2767                 /* If there was a dest TLV - use the values from there */
2768                 if (trans->dbg_dest_tlv) {
2769                         write_ptr =
2770                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2771                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2772                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2773                 } else {
2774                         base = MON_BUFF_BASE_ADDR;
2775                         write_ptr = MON_BUFF_WRPTR;
2776                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2777                 }
2778
2779                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2780                 fw_mon_data = (void *)(*data)->data;
2781                 fw_mon_data->fw_mon_wr_ptr =
2782                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2783                 fw_mon_data->fw_mon_cycle_cnt =
2784                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2785                 fw_mon_data->fw_mon_base_ptr =
2786                         cpu_to_le32(iwl_read_prph(trans, base));
2787
2788                 len += sizeof(**data) + sizeof(*fw_mon_data);
2789                 if (trans_pcie->fw_mon_page) {
2790                         /*
2791                          * The firmware is now asserted, it won't write anything
2792                          * to the buffer. CPU can take ownership to fetch the
2793                          * data. The buffer will be handed back to the device
2794                          * before the firmware will be restarted.
2795                          */
2796                         dma_sync_single_for_cpu(trans->dev,
2797                                                 trans_pcie->fw_mon_phys,
2798                                                 trans_pcie->fw_mon_size,
2799                                                 DMA_FROM_DEVICE);
2800                         memcpy(fw_mon_data->data,
2801                                page_address(trans_pcie->fw_mon_page),
2802                                trans_pcie->fw_mon_size);
2803
2804                         monitor_len = trans_pcie->fw_mon_size;
2805                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2806                         /*
2807                          * Update pointers to reflect actual values after
2808                          * shifting
2809                          */
2810                         base = iwl_read_prph(trans, base) <<
2811                                trans->dbg_dest_tlv->base_shift;
2812                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2813                                            monitor_len / sizeof(u32));
2814                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2815                         monitor_len =
2816                                 iwl_trans_pci_dump_marbh_monitor(trans,
2817                                                                  fw_mon_data,
2818                                                                  monitor_len);
2819                 } else {
2820                         /* Didn't match anything - output no monitor data */
2821                         monitor_len = 0;
2822                 }
2823
2824                 len += monitor_len;
2825                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2826         }
2827
2828         return len;
2829 }
2830
2831 static struct iwl_trans_dump_data
2832 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2833                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2834 {
2835         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2836         struct iwl_fw_error_dump_data *data;
2837         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2838         struct iwl_fw_error_dump_txcmd *txcmd;
2839         struct iwl_trans_dump_data *dump_data;
2840         u32 len, num_rbs;
2841         u32 monitor_len;
2842         int i, ptr;
2843         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2844                         !trans->cfg->mq_rx_supported;
2845
2846         /* transport dump header */
2847         len = sizeof(*dump_data);
2848
2849         /* host commands */
2850         len += sizeof(*data) +
2851                 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2852
2853         /* FW monitor */
2854         if (trans_pcie->fw_mon_page) {
2855                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2856                        trans_pcie->fw_mon_size;
2857                 monitor_len = trans_pcie->fw_mon_size;
2858         } else if (trans->dbg_dest_tlv) {
2859                 u32 base, end;
2860
2861                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2862                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2863
2864                 base = iwl_read_prph(trans, base) <<
2865                        trans->dbg_dest_tlv->base_shift;
2866                 end = iwl_read_prph(trans, end) <<
2867                       trans->dbg_dest_tlv->end_shift;
2868
2869                 /* Make "end" point to the actual end */
2870                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 ||
2871                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2872                         end += (1 << trans->dbg_dest_tlv->end_shift);
2873                 monitor_len = end - base;
2874                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2875                        monitor_len;
2876         } else {
2877                 monitor_len = 0;
2878         }
2879
2880         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2881                 dump_data = vzalloc(len);
2882                 if (!dump_data)
2883                         return NULL;
2884
2885                 data = (void *)dump_data->data;
2886                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2887                 dump_data->len = len;
2888
2889                 return dump_data;
2890         }
2891
2892         /* CSR registers */
2893         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2894
2895         /* FH registers */
2896         if (trans->cfg->gen2)
2897                 len += sizeof(*data) +
2898                        (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2899         else
2900                 len += sizeof(*data) +
2901                        (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2902
2903         if (dump_rbs) {
2904                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2905                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2906                 /* RBs */
2907                 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num))
2908                                       & 0x0FFF;
2909                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2910                 len += num_rbs * (sizeof(*data) +
2911                                   sizeof(struct iwl_fw_error_dump_rb) +
2912                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2913         }
2914
2915         /* Paged memory for gen2 HW */
2916         if (trans->cfg->gen2)
2917                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2918                         len += sizeof(*data) +
2919                                sizeof(struct iwl_fw_error_dump_paging) +
2920                                trans_pcie->init_dram.paging[i].size;
2921
2922         dump_data = vzalloc(len);
2923         if (!dump_data)
2924                 return NULL;
2925
2926         len = 0;
2927         data = (void *)dump_data->data;
2928         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2929         txcmd = (void *)data->data;
2930         spin_lock_bh(&cmdq->lock);
2931         ptr = cmdq->write_ptr;
2932         for (i = 0; i < cmdq->n_window; i++) {
2933                 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
2934                 u32 caplen, cmdlen;
2935
2936                 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2937                                                    trans_pcie->tfd_size * ptr);
2938                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2939
2940                 if (cmdlen) {
2941                         len += sizeof(*txcmd) + caplen;
2942                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2943                         txcmd->caplen = cpu_to_le32(caplen);
2944                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2945                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2946                 }
2947
2948                 ptr = iwl_queue_dec_wrap(ptr);
2949         }
2950         spin_unlock_bh(&cmdq->lock);
2951
2952         data->len = cpu_to_le32(len);
2953         len += sizeof(*data);
2954         data = iwl_fw_error_next_data(data);
2955
2956         len += iwl_trans_pcie_dump_csr(trans, &data);
2957         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2958         if (dump_rbs)
2959                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2960
2961         /* Paged memory for gen2 HW */
2962         if (trans->cfg->gen2) {
2963                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2964                         struct iwl_fw_error_dump_paging *paging;
2965                         dma_addr_t addr =
2966                                 trans_pcie->init_dram.paging[i].physical;
2967                         u32 page_len = trans_pcie->init_dram.paging[i].size;
2968
2969                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2970                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
2971                         paging = (void *)data->data;
2972                         paging->index = cpu_to_le32(i);
2973                         dma_sync_single_for_cpu(trans->dev, addr, page_len,
2974                                                 DMA_BIDIRECTIONAL);
2975                         memcpy(paging->data,
2976                                trans_pcie->init_dram.paging[i].block, page_len);
2977                         data = iwl_fw_error_next_data(data);
2978
2979                         len += sizeof(*data) + sizeof(*paging) + page_len;
2980                 }
2981         }
2982
2983         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2984
2985         dump_data->len = len;
2986
2987         return dump_data;
2988 }
2989
2990 #ifdef CONFIG_PM_SLEEP
2991 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2992 {
2993         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2994             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2995                 return iwl_pci_fw_enter_d0i3(trans);
2996
2997         return 0;
2998 }
2999
3000 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3001 {
3002         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3003             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3004                 iwl_pci_fw_exit_d0i3(trans);
3005 }
3006 #endif /* CONFIG_PM_SLEEP */
3007
3008 #define IWL_TRANS_COMMON_OPS                                            \
3009         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3010         .write8 = iwl_trans_pcie_write8,                                \
3011         .write32 = iwl_trans_pcie_write32,                              \
3012         .read32 = iwl_trans_pcie_read32,                                \
3013         .read_prph = iwl_trans_pcie_read_prph,                          \
3014         .write_prph = iwl_trans_pcie_write_prph,                        \
3015         .read_mem = iwl_trans_pcie_read_mem,                            \
3016         .write_mem = iwl_trans_pcie_write_mem,                          \
3017         .configure = iwl_trans_pcie_configure,                          \
3018         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3019         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3020         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3021         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3022         .ref = iwl_trans_pcie_ref,                                      \
3023         .unref = iwl_trans_pcie_unref,                                  \
3024         .dump_data = iwl_trans_pcie_dump_data,                          \
3025         .dump_regs = iwl_trans_pcie_dump_regs,                          \
3026         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3027         .d3_resume = iwl_trans_pcie_d3_resume
3028
3029 #ifdef CONFIG_PM_SLEEP
3030 #define IWL_TRANS_PM_OPS                                                \
3031         .suspend = iwl_trans_pcie_suspend,                              \
3032         .resume = iwl_trans_pcie_resume,
3033 #else
3034 #define IWL_TRANS_PM_OPS
3035 #endif /* CONFIG_PM_SLEEP */
3036
3037 static const struct iwl_trans_ops trans_ops_pcie = {
3038         IWL_TRANS_COMMON_OPS,
3039         IWL_TRANS_PM_OPS
3040         .start_hw = iwl_trans_pcie_start_hw,
3041         .fw_alive = iwl_trans_pcie_fw_alive,
3042         .start_fw = iwl_trans_pcie_start_fw,
3043         .stop_device = iwl_trans_pcie_stop_device,
3044
3045         .send_cmd = iwl_trans_pcie_send_hcmd,
3046
3047         .tx = iwl_trans_pcie_tx,
3048         .reclaim = iwl_trans_pcie_reclaim,
3049
3050         .txq_disable = iwl_trans_pcie_txq_disable,
3051         .txq_enable = iwl_trans_pcie_txq_enable,
3052
3053         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3054
3055         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3056
3057         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3058         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3059 };
3060
3061 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3062         IWL_TRANS_COMMON_OPS,
3063         IWL_TRANS_PM_OPS
3064         .start_hw = iwl_trans_pcie_start_hw,
3065         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3066         .start_fw = iwl_trans_pcie_gen2_start_fw,
3067         .stop_device = iwl_trans_pcie_gen2_stop_device,
3068
3069         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3070
3071         .tx = iwl_trans_pcie_gen2_tx,
3072         .reclaim = iwl_trans_pcie_reclaim,
3073
3074         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3075         .txq_free = iwl_trans_pcie_dyn_txq_free,
3076         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3077 };
3078
3079 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3080                                        const struct pci_device_id *ent,
3081                                        const struct iwl_cfg *cfg)
3082 {
3083         struct iwl_trans_pcie *trans_pcie;
3084         struct iwl_trans *trans;
3085         int ret, addr_size;
3086
3087         ret = pcim_enable_device(pdev);
3088         if (ret)
3089                 return ERR_PTR(ret);
3090
3091         if (cfg->gen2)
3092                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3093                                         &pdev->dev, cfg, &trans_ops_pcie_gen2);
3094         else
3095                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3096                                         &pdev->dev, cfg, &trans_ops_pcie);
3097         if (!trans)
3098                 return ERR_PTR(-ENOMEM);
3099
3100         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3101
3102         trans_pcie->trans = trans;
3103         trans_pcie->opmode_down = true;
3104         spin_lock_init(&trans_pcie->irq_lock);
3105         spin_lock_init(&trans_pcie->reg_lock);
3106         mutex_init(&trans_pcie->mutex);
3107         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3108         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3109         if (!trans_pcie->tso_hdr_page) {
3110                 ret = -ENOMEM;
3111                 goto out_no_pci;
3112         }
3113
3114
3115         if (!cfg->base_params->pcie_l1_allowed) {
3116                 /*
3117                  * W/A - seems to solve weird behavior. We need to remove this
3118                  * if we don't want to stay in L1 all the time. This wastes a
3119                  * lot of power.
3120                  */
3121                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3122                                        PCIE_LINK_STATE_L1 |
3123                                        PCIE_LINK_STATE_CLKPM);
3124         }
3125
3126         if (cfg->use_tfh) {
3127                 addr_size = 64;
3128                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3129                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3130         } else {
3131                 addr_size = 36;
3132                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3133                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3134         }
3135         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3136
3137         pci_set_master(pdev);
3138
3139         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3140         if (!ret)
3141                 ret = pci_set_consistent_dma_mask(pdev,
3142                                                   DMA_BIT_MASK(addr_size));
3143         if (ret) {
3144                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3145                 if (!ret)
3146                         ret = pci_set_consistent_dma_mask(pdev,
3147                                                           DMA_BIT_MASK(32));
3148                 /* both attempts failed: */
3149                 if (ret) {
3150                         dev_err(&pdev->dev, "No suitable DMA available\n");
3151                         goto out_no_pci;
3152                 }
3153         }
3154
3155         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3156         if (ret) {
3157                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3158                 goto out_no_pci;
3159         }
3160
3161         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3162         if (!trans_pcie->hw_base) {
3163                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3164                 ret = -ENODEV;
3165                 goto out_no_pci;
3166         }
3167
3168         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3169          * PCI Tx retries from interfering with C3 CPU state */
3170         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3171
3172         trans_pcie->pci_dev = pdev;
3173         iwl_disable_interrupts(trans);
3174
3175         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3176         /*
3177          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3178          * changed, and now the revision step also includes bit 0-1 (no more
3179          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3180          * in the old format.
3181          */
3182         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3183                 unsigned long flags;
3184
3185                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3186                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3187
3188                 ret = iwl_pcie_prepare_card_hw(trans);
3189                 if (ret) {
3190                         IWL_WARN(trans, "Exit HW not ready\n");
3191                         goto out_no_pci;
3192                 }
3193
3194                 /*
3195                  * in-order to recognize C step driver should read chip version
3196                  * id located at the AUX bus MISC address space.
3197                  */
3198                 iwl_set_bit(trans, CSR_GP_CNTRL,
3199                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3200                 udelay(2);
3201
3202                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3203                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3204                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3205                                    25000);
3206                 if (ret < 0) {
3207                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3208                         goto out_no_pci;
3209                 }
3210
3211                 if (iwl_trans_grab_nic_access(trans, &flags)) {
3212                         u32 hw_step;
3213
3214                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3215                         hw_step |= ENABLE_WFPM;
3216                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3217                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3218                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3219                         if (hw_step == 0x3)
3220                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3221                                                 (SILICON_C_STEP << 2);
3222                         iwl_trans_release_nic_access(trans, &flags);
3223                 }
3224         }
3225
3226         /*
3227          * 9000-series integrated A-step has a problem with suspend/resume
3228          * and sometimes even causes the whole platform to get stuck. This
3229          * workaround makes the hardware not go into the problematic state.
3230          */
3231         if (trans->cfg->integrated &&
3232             trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3233             CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3234                 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3235                             CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3236
3237 #if IS_ENABLED(CONFIG_IWLMVM)
3238         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3239         if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3240                 u32 hw_status;
3241
3242                 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3243                 if (hw_status & UMAG_GEN_HW_IS_FPGA)
3244                         trans->cfg = &iwla000_2ax_cfg_qnj_hr_f0;
3245                 else
3246                         trans->cfg = &iwla000_2ac_cfg_hr;
3247         }
3248 #endif
3249
3250         iwl_pcie_set_interrupt_capa(pdev, trans);
3251         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3252         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3253                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3254
3255         /* Initialize the wait queue for commands */
3256         init_waitqueue_head(&trans_pcie->wait_command_queue);
3257
3258         init_waitqueue_head(&trans_pcie->d0i3_waitq);
3259
3260         if (trans_pcie->msix_enabled) {
3261                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3262                 if (ret)
3263                         goto out_no_pci;
3264          } else {
3265                 ret = iwl_pcie_alloc_ict(trans);
3266                 if (ret)
3267                         goto out_no_pci;
3268
3269                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3270                                                 iwl_pcie_isr,
3271                                                 iwl_pcie_irq_handler,
3272                                                 IRQF_SHARED, DRV_NAME, trans);
3273                 if (ret) {
3274                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3275                         goto out_free_ict;
3276                 }
3277                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3278          }
3279
3280         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3281                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3282         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3283
3284 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3285         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3286 #else
3287         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3288 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3289
3290         return trans;
3291
3292 out_free_ict:
3293         iwl_pcie_free_ict(trans);
3294 out_no_pci:
3295         free_percpu(trans_pcie->tso_hdr_page);
3296         iwl_trans_free(trans);
3297         return ERR_PTR(ret);
3298 }