drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2007-2015, 2018-2023 Intel Corporation
   4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
   5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
   6  */
   7 #include <linux/pci.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/sched.h>
  11 #include <linux/bitops.h>
  12 #include <linux/gfp.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/module.h>
  15 #include <linux/wait.h>
  16 #include <linux/seq_file.h>
  17
  18 #include "iwl-drv.h"
  19 #include "iwl-trans.h"
  20 #include "iwl-csr.h"
  21 #include "iwl-prph.h"
  22 #include "iwl-scd.h"
  23 #include "iwl-agn-hw.h"
  24 #include "fw/error-dump.h"
  25 #include "fw/dbg.h"
  26 #include "fw/api/tx.h"
  27 #include "mei/iwl-mei.h"
  28 #include "internal.h"
  29 #include "iwl-fh.h"
  30 #include "iwl-context-info-gen3.h"
  31
  32 /* extended range in FW SRAM */
  33 #define IWL_FW_MEM_EXTENDED_START       0x40000
  34 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  35
  36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  37 {
  38 #define PCI_DUMP_SIZE           352
  39 #define PCI_MEM_DUMP_SIZE       64
  40 #define PCI_PARENT_DUMP_SIZE    524
  41 #define PREFIX_LEN              32
  42         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  43         struct pci_dev *pdev = trans_pcie->pci_dev;
  44         u32 i, pos, alloc_size, *ptr, *buf;
  45         char *prefix;
  46
  47         if (trans_pcie->pcie_dbg_dumped_once)
  48                 return;
  49
  50         /* Should be a multiple of 4 */
  51         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
  52         BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
  53         BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
  54
  55         /* Alloc a max size buffer */
  56         alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
  57         alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
  58         alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
  59         alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
  60
  61         buf = kmalloc(alloc_size, GFP_ATOMIC);
  62         if (!buf)
  63                 return;
  64         prefix = (char *)buf + alloc_size - PREFIX_LEN;
  65
  66         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
  67
  68         /* Print wifi device registers */
  69         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
  70         IWL_ERR(trans, "iwlwifi device config registers:\n");
  71         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
  72                 if (pci_read_config_dword(pdev, i, ptr))
  73                         goto err_read;
  74         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
  75
  76         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
  77         for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
  78                 *ptr = iwl_read32(trans, i);
  79         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
  80
  81         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  82         if (pos) {
  83                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
  84                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
  85                         if (pci_read_config_dword(pdev, pos + i, ptr))
  86                                 goto err_read;
  87                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
  88                                32, 4, buf, i, 0);
  89         }
  90
  91         /* Print parent device registers next */
  92         if (!pdev->bus->self)
  93                 goto out;
  94
  95         pdev = pdev->bus->self;
  96         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
  97
  98         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
  99                 pci_name(pdev));
 100         for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
 101                 if (pci_read_config_dword(pdev, i, ptr))
 102                         goto err_read;
 103         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 104
 105         /* Print root port AER registers */
 106         pos = 0;
 107         pdev = pcie_find_root_port(pdev);
 108         if (pdev)
 109                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 110         if (pos) {
 111                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 112                         pci_name(pdev));
 113                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 114                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 115                         if (pci_read_config_dword(pdev, pos + i, ptr))
 116                                 goto err_read;
 117                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 118                                4, buf, i, 0);
 119         }
 120         goto out;
 121
 122 err_read:
 123         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 124         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 125 out:
 126         trans_pcie->pcie_dbg_dumped_once = 1;
 127         kfree(buf);
 128 }
 129
 130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
 131                                    bool retake_ownership)
 132 {
 133         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 134         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
 135                 iwl_set_bit(trans, CSR_GP_CNTRL,
 136                             CSR_GP_CNTRL_REG_FLAG_SW_RESET);
 137                 usleep_range(10000, 20000);
 138         } else {
 139                 iwl_set_bit(trans, CSR_RESET,
 140                             CSR_RESET_REG_FLAG_SW_RESET);
 141                 usleep_range(5000, 6000);
 142         }
 143
 144         if (retake_ownership)
 145                 return iwl_pcie_prepare_card_hw(trans);
 146
 147         return 0;
 148 }
 149
 150 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 151 {
 152         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 153
 154         if (!fw_mon->size)
 155                 return;
 156
 157         dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
 158                           fw_mon->physical);
 159
 160         fw_mon->block = NULL;
 161         fw_mon->physical = 0;
 162         fw_mon->size = 0;
 163 }
 164
 165 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
 166                                             u8 max_power)
 167 {
 168         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 169         void *block = NULL;
 170         dma_addr_t physical = 0;
 171         u32 size = 0;
 172         u8 power;
 173
 174         if (fw_mon->size) {
 175                 memset(fw_mon->block, 0, fw_mon->size);
 176                 return;
 177         }
 178
 179         /* need at least 2 KiB, so stop at 11 */
 180         for (power = max_power; power >= 11; power--) {
 181                 size = BIT(power);
 182                 block = dma_alloc_coherent(trans->dev, size, &physical,
 183                                            GFP_KERNEL | __GFP_NOWARN);
 184                 if (!block)
 185                         continue;
 186
 187                 IWL_INFO(trans,
 188                          "Allocated 0x%08x bytes for firmware monitor.\n",
 189                          size);
 190                 break;
 191         }
 192
 193         if (WARN_ON_ONCE(!block))
 194                 return;
 195
 196         if (power != max_power)
 197                 IWL_ERR(trans,
 198                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 199                         (unsigned long)BIT(power - 10),
 200                         (unsigned long)BIT(max_power - 10));
 201
 202         fw_mon->block = block;
 203         fw_mon->physical = physical;
 204         fw_mon->size = size;
 205 }
 206
 207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 208 {
 209         if (!max_power) {
 210                 /* default max_power is maximum */
 211                 max_power = 26;
 212         } else {
 213                 max_power += 11;
 214         }
 215
 216         if (WARN(max_power > 26,
 217                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 218                  max_power))
 219                 return;
 220
 221         iwl_pcie_alloc_fw_monitor_block(trans, max_power);
 222 }
 223
 224 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 225 {
 226         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 227                     ((reg & 0x0000ffff) | (2 << 28)));
 228         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 229 }
 230
 231 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 232 {
 233         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 234         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 235                     ((reg & 0x0000ffff) | (3 << 28)));
 236 }
 237
 238 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 239 {
 240         if (trans->cfg->apmg_not_supported)
 241                 return;
 242
 243         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 244                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 245                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 246                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 247         else
 248                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 249                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 250                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 251 }
 252
 253 /* PCI registers */
 254 #define PCI_CFG_RETRY_TIMEOUT   0x041
 255
 256 void iwl_pcie_apm_config(struct iwl_trans *trans)
 257 {
 258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 259         u16 lctl;
 260         u16 cap;
 261
 262         /*
 263          * L0S states have been found to be unstable with our devices
 264          * and in newer hardware they are not officially supported at
 265          * all, so we must always set the L0S_DISABLED bit.
 266          */
 267         iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
 268
 269         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 270         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 271
 272         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 273         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 274         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 275                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 276                         trans->ltr_enabled ? "En" : "Dis");
 277 }
 278
 279 /*
 280  * Start up NIC's basic functionality after it has been reset
 281  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 282  * NOTE:  This does not load uCode nor start the embedded processor
 283  */
 284 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 285 {
 286         int ret;
 287
 288         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 289
 290         /*
 291          * Use "set_bit" below rather than "write", to preserve any hardware
 292          * bits already set by default after reset.
 293          */
 294
 295         /* Disable L0S exit timer (platform NMI Work/Around) */
 296         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
 297                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 298                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 299
 300         /*
 301          * Disable L0s without affecting L1;
 302          *  don't wait for ICH L0s (ICH bug W/A)
 303          */
 304         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 305                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 306
 307         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 308         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 309
 310         /*
 311          * Enable HAP INTA (interrupt from management bus) to
 312          * wake device's PCI Express link L1a -> L0s
 313          */
 314         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 315                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 316
 317         iwl_pcie_apm_config(trans);
 318
 319         /* Configure analog phase-lock-loop before activating to D0A */
 320         if (trans->trans_cfg->base_params->pll_cfg)
 321                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 322
 323         ret = iwl_finish_nic_init(trans);
 324         if (ret)
 325                 return ret;
 326
 327         if (trans->cfg->host_interrupt_operation_mode) {
 328                 /*
 329                  * This is a bit of an abuse - This is needed for 7260 / 3160
 330                  * only check host_interrupt_operation_mode even if this is
 331                  * not related to host_interrupt_operation_mode.
 332                  *
 333                  * Enable the oscillator to count wake up time for L1 exit. This
 334                  * consumes slightly more power (100uA) - but allows to be sure
 335                  * that we wake up from L1 on time.
 336                  *
 337                  * This looks weird: read twice the same register, discard the
 338                  * value, set a bit, and yet again, read that same register
 339                  * just to discard the value. But that's the way the hardware
 340                  * seems to like it.
 341                  */
 342                 iwl_read_prph(trans, OSC_CLK);
 343                 iwl_read_prph(trans, OSC_CLK);
 344                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 345                 iwl_read_prph(trans, OSC_CLK);
 346                 iwl_read_prph(trans, OSC_CLK);
 347         }
 348
 349         /*
 350          * Enable DMA clock and wait for it to stabilize.
 351          *
 352          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 353          * bits do not disable clocks.  This preserves any hardware
 354          * bits already set by default in "CLK_CTRL_REG" after reset.
 355          */
 356         if (!trans->cfg->apmg_not_supported) {
 357                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 358                                APMG_CLK_VAL_DMA_CLK_RQT);
 359                 udelay(20);
 360
 361                 /* Disable L1-Active */
 362                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 363                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 364
 365                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 366                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 367                                APMG_RTC_INT_STT_RFKILL);
 368         }
 369
 370         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 371
 372         return 0;
 373 }
 374
 375 /*
 376  * Enable LP XTAL to avoid HW bug where device may consume much power if
 377  * FW is not loaded after device reset. LP XTAL is disabled by default
 378  * after device HW reset. Do it only if XTAL is fed by internal source.
 379  * Configure device's "persistence" mode to avoid resetting XTAL again when
 380  * SHRD_HW_RST occurs in S3.
 381  */
 382 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 383 {
 384         int ret;
 385         u32 apmg_gp1_reg;
 386         u32 apmg_xtal_cfg_reg;
 387         u32 dl_cfg_reg;
 388
 389         /* Force XTAL ON */
 390         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 391                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 392
 393         ret = iwl_trans_pcie_sw_reset(trans, true);
 394
 395         if (!ret)
 396                 ret = iwl_finish_nic_init(trans);
 397
 398         if (WARN_ON(ret)) {
 399                 /* Release XTAL ON request */
 400                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 401                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 402                 return;
 403         }
 404
 405         /*
 406          * Clear "disable persistence" to avoid LP XTAL resetting when
 407          * SHRD_HW_RST is applied in S3.
 408          */
 409         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 410                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 411
 412         /*
 413          * Force APMG XTAL to be active to prevent its disabling by HW
 414          * caused by APMG idle state.
 415          */
 416         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 417                                                     SHR_APMG_XTAL_CFG_REG);
 418         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 419                                  apmg_xtal_cfg_reg |
 420                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 421
 422         ret = iwl_trans_pcie_sw_reset(trans, true);
 423         if (ret)
 424                 IWL_ERR(trans,
 425                         "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n");
 426
 427         /* Enable LP XTAL by indirect access through CSR */
 428         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 429         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 430                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 431                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 432
 433         /* Clear delay line clock power up */
 434         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 435         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 436                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 437
 438         /*
 439          * Enable persistence mode to avoid LP XTAL resetting when
 440          * SHRD_HW_RST is applied in S3.
 441          */
 442         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 443                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 444
 445         /*
 446          * Clear "initialization complete" bit to move adapter from
 447          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 448          */
 449         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 450
 451         /* Activates XTAL resources monitor */
 452         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 453                                  CSR_MONITOR_XTAL_RESOURCES);
 454
 455         /* Release XTAL ON request */
 456         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 457                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 458         udelay(10);
 459
 460         /* Release APMG XTAL */
 461         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 462                                  apmg_xtal_cfg_reg &
 463                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 464 }
 465
 466 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 467 {
 468         int ret;
 469
 470         /* stop device's busmaster DMA activity */
 471
 472         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
 473                 iwl_set_bit(trans, CSR_GP_CNTRL,
 474                             CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
 475
 476                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 477                                    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
 478                                    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
 479                                    100);
 480                 usleep_range(10000, 20000);
 481         } else {
 482                 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 483
 484                 ret = iwl_poll_bit(trans, CSR_RESET,
 485                                    CSR_RESET_REG_FLAG_MASTER_DISABLED,
 486                                    CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 487         }
 488
 489         if (ret < 0)
 490                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 491
 492         IWL_DEBUG_INFO(trans, "stop master\n");
 493 }
 494
 495 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 496 {
 497         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 498
 499         if (op_mode_leave) {
 500                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 501                         iwl_pcie_apm_init(trans);
 502
 503                 /* inform ME that we are leaving */
 504                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
 505                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 506                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 507                 else if (trans->trans_cfg->device_family >=
 508                          IWL_DEVICE_FAMILY_8000) {
 509                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 510                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 511                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 512                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 513                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 514                         mdelay(1);
 515                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 516                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 517                 }
 518                 mdelay(5);
 519         }
 520
 521         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 522
 523         /* Stop device's DMA activity */
 524         iwl_pcie_apm_stop_master(trans);
 525
 526         if (trans->cfg->lp_xtal_workaround) {
 527                 iwl_pcie_apm_lp_xtal_enable(trans);
 528                 return;
 529         }
 530
 531         iwl_trans_pcie_sw_reset(trans, false);
 532
 533         /*
 534          * Clear "initialization complete" bit to move adapter from
 535          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 536          */
 537         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 538 }
 539
 540 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 541 {
 542         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 543         int ret;
 544
 545         /* nic_init */
 546         spin_lock_bh(&trans_pcie->irq_lock);
 547         ret = iwl_pcie_apm_init(trans);
 548         spin_unlock_bh(&trans_pcie->irq_lock);
 549
 550         if (ret)
 551                 return ret;
 552
 553         iwl_pcie_set_pwr(trans, false);
 554
 555         iwl_op_mode_nic_config(trans->op_mode);
 556
 557         /* Allocate the RX queue, or reset if it is already allocated */
 558         ret = iwl_pcie_rx_init(trans);
 559         if (ret)
 560                 return ret;
 561
 562         /* Allocate or reset and init all Tx and Command queues */
 563         if (iwl_pcie_tx_init(trans)) {
 564                 iwl_pcie_rx_free(trans);
 565                 return -ENOMEM;
 566         }
 567
 568         if (trans->trans_cfg->base_params->shadow_reg_enable) {
 569                 /* enable shadow regs in HW */
 570                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 571                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 572         }
 573
 574         return 0;
 575 }
 576
 577 #define HW_READY_TIMEOUT (50)
 578
 579 /* Note: returns poll_bit return value, which is >= 0 if success */
 580 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 581 {
 582         int ret;
 583
 584         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 585                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 586
 587         /* See if we got it */
 588         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 589                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 590                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 591                            HW_READY_TIMEOUT);
 592
 593         if (ret >= 0)
 594                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 595
 596         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 597         return ret;
 598 }
 599
 600 /* Note: returns standard 0/-ERROR code */
 601 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 602 {
 603         int ret;
 604         int iter;
 605
 606         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 607
 608         ret = iwl_pcie_set_hw_ready(trans);
 609         /* If the card is ready, exit 0 */
 610         if (ret >= 0) {
 611                 trans->csme_own = false;
 612                 return 0;
 613         }
 614
 615         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 616                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 617         usleep_range(1000, 2000);
 618
 619         for (iter = 0; iter < 10; iter++) {
 620                 int t = 0;
 621
 622                 /* If HW is not ready, prepare the conditions to check again */
 623                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 624                             CSR_HW_IF_CONFIG_REG_PREPARE);
 625
 626                 do {
 627                         ret = iwl_pcie_set_hw_ready(trans);
 628                         if (ret >= 0) {
 629                                 trans->csme_own = false;
 630                                 return 0;
 631                         }
 632
 633                         if (iwl_mei_is_connected()) {
 634                                 IWL_DEBUG_INFO(trans,
 635                                                "Couldn't prepare the card but SAP is connected\n");
 636                                 trans->csme_own = true;
 637                                 if (trans->trans_cfg->device_family !=
 638                                     IWL_DEVICE_FAMILY_9000)
 639                                         IWL_ERR(trans,
 640                                                 "SAP not supported for this NIC family\n");
 641
 642                                 return -EBUSY;
 643                         }
 644
 645                         usleep_range(200, 1000);
 646                         t += 200;
 647                 } while (t < 150000);
 648                 msleep(25);
 649         }
 650
 651         IWL_ERR(trans, "Couldn't prepare the card\n");
 652
 653         return ret;
 654 }
 655
 656 /*
 657  * ucode
 658  */
 659 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 660                                             u32 dst_addr, dma_addr_t phy_addr,
 661                                             u32 byte_cnt)
 662 {
 663         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 664                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 665
 666         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 667                     dst_addr);
 668
 669         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 670                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 671
 672         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 673                     (iwl_get_dma_hi_addr(phy_addr)
 674                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 675
 676         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 677                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 678                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 679                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 680
 681         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 682                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 683                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 684                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 685 }
 686
 687 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 688                                         u32 dst_addr, dma_addr_t phy_addr,
 689                                         u32 byte_cnt)
 690 {
 691         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 692         int ret;
 693
 694         trans_pcie->ucode_write_complete = false;
 695
 696         if (!iwl_trans_grab_nic_access(trans))
 697                 return -EIO;
 698
 699         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 700                                         byte_cnt);
 701         iwl_trans_release_nic_access(trans);
 702
 703         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 704                                  trans_pcie->ucode_write_complete, 5 * HZ);
 705         if (!ret) {
 706                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 707                 iwl_trans_pcie_dump_regs(trans);
 708                 return -ETIMEDOUT;
 709         }
 710
 711         return 0;
 712 }
 713
 714 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 715                             const struct fw_desc *section)
 716 {
 717         u8 *v_addr;
 718         dma_addr_t p_addr;
 719         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 720         int ret = 0;
 721
 722         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 723                      section_num);
 724
 725         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 726                                     GFP_KERNEL | __GFP_NOWARN);
 727         if (!v_addr) {
 728                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 729                 chunk_sz = PAGE_SIZE;
 730                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 731                                             &p_addr, GFP_KERNEL);
 732                 if (!v_addr)
 733                         return -ENOMEM;
 734         }
 735
 736         for (offset = 0; offset < section->len; offset += chunk_sz) {
 737                 u32 copy_size, dst_addr;
 738                 bool extended_addr = false;
 739
 740                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 741                 dst_addr = section->offset + offset;
 742
 743                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 744                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 745                         extended_addr = true;
 746
 747                 if (extended_addr)
 748                         iwl_set_bits_prph(trans, LMPM_CHICK,
 749                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 750
 751                 memcpy(v_addr, (const u8 *)section->data + offset, copy_size);
 752                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 753                                                    copy_size);
 754
 755                 if (extended_addr)
 756                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 757                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 758
 759                 if (ret) {
 760                         IWL_ERR(trans,
 761                                 "Could not load the [%d] uCode section\n",
 762                                 section_num);
 763                         break;
 764                 }
 765         }
 766
 767         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 768         return ret;
 769 }
 770
 771 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 772                                            const struct fw_img *image,
 773                                            int cpu,
 774                                            int *first_ucode_section)
 775 {
 776         int shift_param;
 777         int i, ret = 0, sec_num = 0x1;
 778         u32 val, last_read_idx = 0;
 779
 780         if (cpu == 1) {
 781                 shift_param = 0;
 782                 *first_ucode_section = 0;
 783         } else {
 784                 shift_param = 16;
 785                 (*first_ucode_section)++;
 786         }
 787
 788         for (i = *first_ucode_section; i < image->num_sec; i++) {
 789                 last_read_idx = i;
 790
 791                 /*
 792                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 793                  * CPU1 to CPU2.
 794                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 795                  * CPU2 non paged to CPU2 paging sec.
 796                  */
 797                 if (!image->sec[i].data ||
 798                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 799                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 800                         IWL_DEBUG_FW(trans,
 801                                      "Break since Data not valid or Empty section, sec = %d\n",
 802                                      i);
 803                         break;
 804                 }
 805
 806                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 807                 if (ret)
 808                         return ret;
 809
 810                 /* Notify ucode of loaded section number and status */
 811                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 812                 val = val | (sec_num << shift_param);
 813                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 814
 815                 sec_num = (sec_num << 1) | 0x1;
 816         }
 817
 818         *first_ucode_section = last_read_idx;
 819
 820         iwl_enable_interrupts(trans);
 821
 822         if (trans->trans_cfg->gen2) {
 823                 if (cpu == 1)
 824                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 825                                        0xFFFF);
 826                 else
 827                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 828                                        0xFFFFFFFF);
 829         } else {
 830                 if (cpu == 1)
 831                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 832                                            0xFFFF);
 833                 else
 834                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 835                                            0xFFFFFFFF);
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 842                                       const struct fw_img *image,
 843                                       int cpu,
 844                                       int *first_ucode_section)
 845 {
 846         int i, ret = 0;
 847         u32 last_read_idx = 0;
 848
 849         if (cpu == 1)
 850                 *first_ucode_section = 0;
 851         else
 852                 (*first_ucode_section)++;
 853
 854         for (i = *first_ucode_section; i < image->num_sec; i++) {
 855                 last_read_idx = i;
 856
 857                 /*
 858                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 859                  * CPU1 to CPU2.
 860                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 861                  * CPU2 non paged to CPU2 paging sec.
 862                  */
 863                 if (!image->sec[i].data ||
 864                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 865                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 866                         IWL_DEBUG_FW(trans,
 867                                      "Break since Data not valid or Empty section, sec = %d\n",
 868                                      i);
 869                         break;
 870                 }
 871
 872                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 873                 if (ret)
 874                         return ret;
 875         }
 876
 877         *first_ucode_section = last_read_idx;
 878
 879         return 0;
 880 }
 881
 882 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
 883 {
 884         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
 885         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
 886                 &trans->dbg.fw_mon_cfg[alloc_id];
 887         struct iwl_dram_data *frag;
 888
 889         if (!iwl_trans_dbg_ini_valid(trans))
 890                 return;
 891
 892         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
 893             IWL_FW_INI_LOCATION_SRAM_PATH) {
 894                 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
 895                 /* set sram monitor by enabling bit 7 */
 896                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 897                             CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
 898
 899                 return;
 900         }
 901
 902         if (le32_to_cpu(fw_mon_cfg->buf_location) !=
 903             IWL_FW_INI_LOCATION_DRAM_PATH ||
 904             !trans->dbg.fw_mon_ini[alloc_id].num_frags)
 905                 return;
 906
 907         frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
 908
 909         IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
 910                      alloc_id);
 911
 912         iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
 913                             frag->physical >> MON_BUFF_SHIFT_VER2);
 914         iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
 915                             (frag->physical + frag->size - 256) >>
 916                             MON_BUFF_SHIFT_VER2);
 917 }
 918
 919 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 920 {
 921         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
 922         const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 923         int i;
 924
 925         if (iwl_trans_dbg_ini_valid(trans)) {
 926                 iwl_pcie_apply_destination_ini(trans);
 927                 return;
 928         }
 929
 930         IWL_INFO(trans, "Applying debug destination %s\n",
 931                  get_fw_dbg_mode_string(dest->monitor_mode));
 932
 933         if (dest->monitor_mode == EXTERNAL_MODE)
 934                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 935         else
 936                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 937
 938         for (i = 0; i < trans->dbg.n_dest_reg; i++) {
 939                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 940                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 941
 942                 switch (dest->reg_ops[i].op) {
 943                 case CSR_ASSIGN:
 944                         iwl_write32(trans, addr, val);
 945                         break;
 946                 case CSR_SETBIT:
 947                         iwl_set_bit(trans, addr, BIT(val));
 948                         break;
 949                 case CSR_CLEARBIT:
 950                         iwl_clear_bit(trans, addr, BIT(val));
 951                         break;
 952                 case PRPH_ASSIGN:
 953                         iwl_write_prph(trans, addr, val);
 954                         break;
 955                 case PRPH_SETBIT:
 956                         iwl_set_bits_prph(trans, addr, BIT(val));
 957                         break;
 958                 case PRPH_CLEARBIT:
 959                         iwl_clear_bits_prph(trans, addr, BIT(val));
 960                         break;
 961                 case PRPH_BLOCKBIT:
 962                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 963                                 IWL_ERR(trans,
 964                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 965                                         val, addr);
 966                                 goto monitor;
 967                         }
 968                         break;
 969                 default:
 970                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 971                                 dest->reg_ops[i].op);
 972                         break;
 973                 }
 974         }
 975
 976 monitor:
 977         if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
 978                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 979                                fw_mon->physical >> dest->base_shift);
 980                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 981                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 982                                        (fw_mon->physical + fw_mon->size -
 983                                         256) >> dest->end_shift);
 984                 else
 985                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 986                                        (fw_mon->physical + fw_mon->size) >>
 987                                        dest->end_shift);
 988         }
 989 }
 990
 991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 992                                 const struct fw_img *image)
 993 {
 994         int ret = 0;
 995         int first_ucode_section;
 996
 997         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 998                      image->is_dual_cpus ? "Dual" : "Single");
 999
1000         /* load to FW the binary non secured sections of CPU1 */
1001         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1002         if (ret)
1003                 return ret;
1004
1005         if (image->is_dual_cpus) {
1006                 /* set CPU2 header address */
1007                 iwl_write_prph(trans,
1008                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1009                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1010
1011                 /* load to FW the binary sections of CPU2 */
1012                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1013                                                  &first_ucode_section);
1014                 if (ret)
1015                         return ret;
1016         }
1017
1018         if (iwl_pcie_dbg_on(trans))
1019                 iwl_pcie_apply_destination(trans);
1020
1021         iwl_enable_interrupts(trans);
1022
1023         /* release CPU reset */
1024         iwl_write32(trans, CSR_RESET, 0);
1025
1026         return 0;
1027 }
1028
1029 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1030                                           const struct fw_img *image)
1031 {
1032         int ret = 0;
1033         int first_ucode_section;
1034
1035         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1036                      image->is_dual_cpus ? "Dual" : "Single");
1037
1038         if (iwl_pcie_dbg_on(trans))
1039                 iwl_pcie_apply_destination(trans);
1040
1041         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1042                         iwl_read_prph(trans, WFPM_GP2));
1043
1044         /*
1045          * Set default value. On resume reading the values that were
1046          * zeored can provide debug data on the resume flow.
1047          * This is for debugging only and has no functional impact.
1048          */
1049         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1050
1051         /* configure the ucode to be ready to get the secured image */
1052         /* release CPU reset */
1053         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1054
1055         /* load to FW the binary Secured sections of CPU1 */
1056         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1057                                               &first_ucode_section);
1058         if (ret)
1059                 return ret;
1060
1061         /* load to FW the binary sections of CPU2 */
1062         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1063                                                &first_ucode_section);
1064 }
1065
1066 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1067 {
1068         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1069         bool hw_rfkill = iwl_is_rfkill_set(trans);
1070         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1071         bool report;
1072
1073         if (hw_rfkill) {
1074                 set_bit(STATUS_RFKILL_HW, &trans->status);
1075                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1076         } else {
1077                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1078                 if (trans_pcie->opmode_down)
1079                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1080         }
1081
1082         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083
1084         if (prev != report)
1085                 iwl_trans_pcie_rf_kill(trans, report);
1086
1087         return hw_rfkill;
1088 }
1089
1090 struct iwl_causes_list {
1091         u16 mask_reg;
1092         u8 bit;
1093         u8 addr;
1094 };
1095
1096 #define IWL_CAUSE(reg, mask)                                            \
1097         {                                                               \
1098                 .mask_reg = reg,                                        \
1099                 .bit = ilog2(mask),                                     \
1100                 .addr = ilog2(mask) +                                   \
1101                         ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 :       \
1102                          (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 :        \
1103                          0xffff),       /* causes overflow warning */   \
1104         }
1105
1106 static const struct iwl_causes_list causes_list_common[] = {
1107         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM),
1108         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM),
1109         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D),
1110         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR),
1111         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE),
1112         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP),
1113         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE),
1114         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR),
1115         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL),
1116         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL),
1117         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC),
1118         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD),
1119         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX),
1120         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR),
1121         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP),
1122 };
1123
1124 static const struct iwl_causes_list causes_list_pre_bz[] = {
1125         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR),
1126 };
1127
1128 static const struct iwl_causes_list causes_list_bz[] = {
1129         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ),
1130 };
1131
1132 static void iwl_pcie_map_list(struct iwl_trans *trans,
1133                               const struct iwl_causes_list *causes,
1134                               int arr_size, int val)
1135 {
1136         int i;
1137
1138         for (i = 0; i < arr_size; i++) {
1139                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1140                 iwl_clear_bit(trans, causes[i].mask_reg,
1141                               BIT(causes[i].bit));
1142         }
1143 }
1144
1145 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1146 {
1147         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1148         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1149         /*
1150          * Access all non RX causes and map them to the default irq.
1151          * In case we are missing at least one interrupt vector,
1152          * the first interrupt vector will serve non-RX and FBQ causes.
1153          */
1154         iwl_pcie_map_list(trans, causes_list_common,
1155                           ARRAY_SIZE(causes_list_common), val);
1156         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1157                 iwl_pcie_map_list(trans, causes_list_bz,
1158                                   ARRAY_SIZE(causes_list_bz), val);
1159         else
1160                 iwl_pcie_map_list(trans, causes_list_pre_bz,
1161                                   ARRAY_SIZE(causes_list_pre_bz), val);
1162 }
1163
1164 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1165 {
1166         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1167         u32 offset =
1168                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1169         u32 val, idx;
1170
1171         /*
1172          * The first RX queue - fallback queue, which is designated for
1173          * management frame, command responses etc, is always mapped to the
1174          * first interrupt vector. The other RX queues are mapped to
1175          * the other (N - 2) interrupt vectors.
1176          */
1177         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1178         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1179                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1180                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1181                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1182         }
1183         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1184
1185         val = MSIX_FH_INT_CAUSES_Q(0);
1186         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1187                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1188         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1189
1190         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1191                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1192 }
1193
1194 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1195 {
1196         struct iwl_trans *trans = trans_pcie->trans;
1197
1198         if (!trans_pcie->msix_enabled) {
1199                 if (trans->trans_cfg->mq_rx_supported &&
1200                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1201                         iwl_write_umac_prph(trans, UREG_CHICK,
1202                                             UREG_CHICK_MSI_ENABLE);
1203                 return;
1204         }
1205         /*
1206          * The IVAR table needs to be configured again after reset,
1207          * but if the device is disabled, we can't write to
1208          * prph.
1209          */
1210         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1211                 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1212
1213         /*
1214          * Each cause from the causes list above and the RX causes is
1215          * represented as a byte in the IVAR table. The first nibble
1216          * represents the bound interrupt vector of the cause, the second
1217          * represents no auto clear for this cause. This will be set if its
1218          * interrupt vector is bound to serve other causes.
1219          */
1220         iwl_pcie_map_rx_causes(trans);
1221
1222         iwl_pcie_map_non_rx_causes(trans);
1223 }
1224
1225 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1226 {
1227         struct iwl_trans *trans = trans_pcie->trans;
1228
1229         iwl_pcie_conf_msix_hw(trans_pcie);
1230
1231         if (!trans_pcie->msix_enabled)
1232                 return;
1233
1234         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1235         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1236         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1237         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1238 }
1239
1240 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1241 {
1242         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243
1244         lockdep_assert_held(&trans_pcie->mutex);
1245
1246         if (trans_pcie->is_down)
1247                 return;
1248
1249         trans_pcie->is_down = true;
1250
1251         /* tell the device to stop sending interrupts */
1252         iwl_disable_interrupts(trans);
1253
1254         /* device going down, Stop using ICT table */
1255         iwl_pcie_disable_ict(trans);
1256
1257         /*
1258          * If a HW restart happens during firmware loading,
1259          * then the firmware loading might call this function
1260          * and later it might be called again due to the
1261          * restart. So don't process again if the device is
1262          * already dead.
1263          */
1264         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1265                 IWL_DEBUG_INFO(trans,
1266                                "DEVICE_ENABLED bit was set and is now cleared\n");
1267                 iwl_pcie_synchronize_irqs(trans);
1268                 iwl_pcie_rx_napi_sync(trans);
1269                 iwl_pcie_tx_stop(trans);
1270                 iwl_pcie_rx_stop(trans);
1271
1272                 /* Power-down device's busmaster DMA clocks */
1273                 if (!trans->cfg->apmg_not_supported) {
1274                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1275                                        APMG_CLK_VAL_DMA_CLK_RQT);
1276                         udelay(5);
1277                 }
1278         }
1279
1280         /* Make sure (redundant) we've released our request to stay awake */
1281         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1282                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1283                               CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1284         else
1285                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1286                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1287
1288         /* Stop the device, and put it in low power state */
1289         iwl_pcie_apm_stop(trans, false);
1290
1291         /* re-take ownership to prevent other users from stealing the device */
1292         iwl_trans_pcie_sw_reset(trans, true);
1293
1294         /*
1295          * Upon stop, the IVAR table gets erased, so msi-x won't
1296          * work. This causes a bug in RF-KILL flows, since the interrupt
1297          * that enables radio won't fire on the correct irq, and the
1298          * driver won't be able to handle the interrupt.
1299          * Configure the IVAR table again after reset.
1300          */
1301         iwl_pcie_conf_msix_hw(trans_pcie);
1302
1303         /*
1304          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1305          * This is a bug in certain verions of the hardware.
1306          * Certain devices also keep sending HW RF kill interrupt all
1307          * the time, unless the interrupt is ACKed even if the interrupt
1308          * should be masked. Re-ACK all the interrupts here.
1309          */
1310         iwl_disable_interrupts(trans);
1311
1312         /* clear all status bits */
1313         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1314         clear_bit(STATUS_INT_ENABLED, &trans->status);
1315         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1316
1317         /*
1318          * Even if we stop the HW, we still want the RF kill
1319          * interrupt
1320          */
1321         iwl_enable_rfkill_int(trans);
1322 }
1323
1324 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1325 {
1326         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1327
1328         if (trans_pcie->msix_enabled) {
1329                 int i;
1330
1331                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1332                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1333         } else {
1334                 synchronize_irq(trans_pcie->pci_dev->irq);
1335         }
1336 }
1337
1338 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1339                                    const struct fw_img *fw, bool run_in_rfkill)
1340 {
1341         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1342         bool hw_rfkill;
1343         int ret;
1344
1345         /* This may fail if AMT took ownership of the device */
1346         if (iwl_pcie_prepare_card_hw(trans)) {
1347                 IWL_WARN(trans, "Exit HW not ready\n");
1348                 return -EIO;
1349         }
1350
1351         iwl_enable_rfkill_int(trans);
1352
1353         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1354
1355         /*
1356          * We enabled the RF-Kill interrupt and the handler may very
1357          * well be running. Disable the interrupts to make sure no other
1358          * interrupt can be fired.
1359          */
1360         iwl_disable_interrupts(trans);
1361
1362         /* Make sure it finished running */
1363         iwl_pcie_synchronize_irqs(trans);
1364
1365         mutex_lock(&trans_pcie->mutex);
1366
1367         /* If platform's RF_KILL switch is NOT set to KILL */
1368         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1369         if (hw_rfkill && !run_in_rfkill) {
1370                 ret = -ERFKILL;
1371                 goto out;
1372         }
1373
1374         /* Someone called stop_device, don't try to start_fw */
1375         if (trans_pcie->is_down) {
1376                 IWL_WARN(trans,
1377                          "Can't start_fw since the HW hasn't been started\n");
1378                 ret = -EIO;
1379                 goto out;
1380         }
1381
1382         /* make sure rfkill handshake bits are cleared */
1383         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1384         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1385                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1386
1387         /* clear (again), then enable host interrupts */
1388         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1389
1390         ret = iwl_pcie_nic_init(trans);
1391         if (ret) {
1392                 IWL_ERR(trans, "Unable to init nic\n");
1393                 goto out;
1394         }
1395
1396         /*
1397          * Now, we load the firmware and don't want to be interrupted, even
1398          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1399          * FH_TX interrupt which is needed to load the firmware). If the
1400          * RF-Kill switch is toggled, we will find out after having loaded
1401          * the firmware and return the proper value to the caller.
1402          */
1403         iwl_enable_fw_load_int(trans);
1404
1405         /* really make sure rfkill handshake bits are cleared */
1406         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1407         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1408
1409         /* Load the given image to the HW */
1410         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1411                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1412         else
1413                 ret = iwl_pcie_load_given_ucode(trans, fw);
1414
1415         /* re-check RF-Kill state since we may have missed the interrupt */
1416         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1417         if (hw_rfkill && !run_in_rfkill)
1418                 ret = -ERFKILL;
1419
1420 out:
1421         mutex_unlock(&trans_pcie->mutex);
1422         return ret;
1423 }
1424
1425 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1426 {
1427         iwl_pcie_reset_ict(trans);
1428         iwl_pcie_tx_start(trans, scd_addr);
1429 }
1430
1431 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1432                                        bool was_in_rfkill)
1433 {
1434         bool hw_rfkill;
1435
1436         /*
1437          * Check again since the RF kill state may have changed while
1438          * all the interrupts were disabled, in this case we couldn't
1439          * receive the RF kill interrupt and update the state in the
1440          * op_mode.
1441          * Don't call the op_mode if the rkfill state hasn't changed.
1442          * This allows the op_mode to call stop_device from the rfkill
1443          * notification without endless recursion. Under very rare
1444          * circumstances, we might have a small recursion if the rfkill
1445          * state changed exactly now while we were called from stop_device.
1446          * This is very unlikely but can happen and is supported.
1447          */
1448         hw_rfkill = iwl_is_rfkill_set(trans);
1449         if (hw_rfkill) {
1450                 set_bit(STATUS_RFKILL_HW, &trans->status);
1451                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1452         } else {
1453                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1454                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1455         }
1456         if (hw_rfkill != was_in_rfkill)
1457                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1458 }
1459
1460 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1461 {
1462         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1463         bool was_in_rfkill;
1464
1465         iwl_op_mode_time_point(trans->op_mode,
1466                                IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1467                                NULL);
1468
1469         mutex_lock(&trans_pcie->mutex);
1470         trans_pcie->opmode_down = true;
1471         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1472         _iwl_trans_pcie_stop_device(trans);
1473         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1474         mutex_unlock(&trans_pcie->mutex);
1475 }
1476
1477 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1478 {
1479         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1480                 IWL_TRANS_GET_PCIE_TRANS(trans);
1481
1482         lockdep_assert_held(&trans_pcie->mutex);
1483
1484         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1485                  state ? "disabled" : "enabled");
1486         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1487                 if (trans->trans_cfg->gen2)
1488                         _iwl_trans_pcie_gen2_stop_device(trans);
1489                 else
1490                         _iwl_trans_pcie_stop_device(trans);
1491         }
1492 }
1493
1494 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1495                                   bool test, bool reset)
1496 {
1497         iwl_disable_interrupts(trans);
1498
1499         /*
1500          * in testing mode, the host stays awake and the
1501          * hardware won't be reset (not even partially)
1502          */
1503         if (test)
1504                 return;
1505
1506         iwl_pcie_disable_ict(trans);
1507
1508         iwl_pcie_synchronize_irqs(trans);
1509
1510         iwl_clear_bit(trans, CSR_GP_CNTRL,
1511                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1512         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1513
1514         if (reset) {
1515                 /*
1516                  * reset TX queues -- some of their registers reset during S3
1517                  * so if we don't reset everything here the D3 image would try
1518                  * to execute some invalid memory upon resume
1519                  */
1520                 iwl_trans_pcie_tx_reset(trans);
1521         }
1522
1523         iwl_pcie_set_pwr(trans, true);
1524 }
1525
1526 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
1527 {
1528         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1529         int ret;
1530
1531         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
1532                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1533                                     suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
1534                                               UREG_DOORBELL_TO_ISR6_RESUME);
1535         else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1536                 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
1537                             suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
1538                                       CSR_IPC_SLEEP_CONTROL_RESUME);
1539         else
1540                 return 0;
1541
1542         ret = wait_event_timeout(trans_pcie->sx_waitq,
1543                                  trans_pcie->sx_complete, 2 * HZ);
1544
1545         /* Invalidate it toward next suspend or resume */
1546         trans_pcie->sx_complete = false;
1547
1548         if (!ret) {
1549                 IWL_ERR(trans, "Timeout %s D3\n",
1550                         suspend ? "entering" : "exiting");
1551                 return -ETIMEDOUT;
1552         }
1553
1554         return 0;
1555 }
1556
1557 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1558                                      bool reset)
1559 {
1560         int ret;
1561
1562         if (!reset)
1563                 /* Enable persistence mode to avoid reset */
1564                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1565                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1566
1567         ret = iwl_pcie_d3_handshake(trans, true);
1568         if (ret)
1569                 return ret;
1570
1571         iwl_pcie_d3_complete_suspend(trans, test, reset);
1572
1573         return 0;
1574 }
1575
1576 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1577                                     enum iwl_d3_status *status,
1578                                     bool test,  bool reset)
1579 {
1580         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1581         u32 val;
1582         int ret;
1583
1584         if (test) {
1585                 iwl_enable_interrupts(trans);
1586                 *status = IWL_D3_STATUS_ALIVE;
1587                 ret = 0;
1588                 goto out;
1589         }
1590
1591         iwl_set_bit(trans, CSR_GP_CNTRL,
1592                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1593
1594         ret = iwl_finish_nic_init(trans);
1595         if (ret)
1596                 return ret;
1597
1598         /*
1599          * Reconfigure IVAR table in case of MSIX or reset ict table in
1600          * MSI mode since HW reset erased it.
1601          * Also enables interrupts - none will happen as
1602          * the device doesn't know we're waking it up, only when
1603          * the opmode actually tells it after this call.
1604          */
1605         iwl_pcie_conf_msix_hw(trans_pcie);
1606         if (!trans_pcie->msix_enabled)
1607                 iwl_pcie_reset_ict(trans);
1608         iwl_enable_interrupts(trans);
1609
1610         iwl_pcie_set_pwr(trans, false);
1611
1612         if (!reset) {
1613                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1614                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1615         } else {
1616                 iwl_trans_pcie_tx_reset(trans);
1617
1618                 ret = iwl_pcie_rx_init(trans);
1619                 if (ret) {
1620                         IWL_ERR(trans,
1621                                 "Failed to resume the device (RX reset)\n");
1622                         return ret;
1623                 }
1624         }
1625
1626         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1627                         iwl_read_umac_prph(trans, WFPM_GP2));
1628
1629         val = iwl_read32(trans, CSR_RESET);
1630         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1631                 *status = IWL_D3_STATUS_RESET;
1632         else
1633                 *status = IWL_D3_STATUS_ALIVE;
1634
1635 out:
1636         if (*status == IWL_D3_STATUS_ALIVE)
1637                 ret = iwl_pcie_d3_handshake(trans, false);
1638
1639         return ret;
1640 }
1641
1642 static void
1643 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1644                             struct iwl_trans *trans,
1645                             const struct iwl_cfg_trans_params *cfg_trans)
1646 {
1647         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1648         int max_irqs, num_irqs, i, ret;
1649         u16 pci_cmd;
1650         u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1651
1652         if (!cfg_trans->mq_rx_supported)
1653                 goto enable_msi;
1654
1655         if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1656                 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1657
1658         max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1659         for (i = 0; i < max_irqs; i++)
1660                 trans_pcie->msix_entries[i].entry = i;
1661
1662         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1663                                          MSIX_MIN_INTERRUPT_VECTORS,
1664                                          max_irqs);
1665         if (num_irqs < 0) {
1666                 IWL_DEBUG_INFO(trans,
1667                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1668                                num_irqs);
1669                 goto enable_msi;
1670         }
1671         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1672
1673         IWL_DEBUG_INFO(trans,
1674                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1675                        num_irqs);
1676
1677         /*
1678          * In case the OS provides fewer interrupts than requested, different
1679          * causes will share the same interrupt vector as follows:
1680          * One interrupt less: non rx causes shared with FBQ.
1681          * Two interrupts less: non rx causes shared with FBQ and RSS.
1682          * More than two interrupts: we will use fewer RSS queues.
1683          */
1684         if (num_irqs <= max_irqs - 2) {
1685                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1686                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1687                         IWL_SHARED_IRQ_FIRST_RSS;
1688         } else if (num_irqs == max_irqs - 1) {
1689                 trans_pcie->trans->num_rx_queues = num_irqs;
1690                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1691         } else {
1692                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1693         }
1694
1695         IWL_DEBUG_INFO(trans,
1696                        "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1697                        trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1698
1699         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1700
1701         trans_pcie->alloc_vecs = num_irqs;
1702         trans_pcie->msix_enabled = true;
1703         return;
1704
1705 enable_msi:
1706         ret = pci_enable_msi(pdev);
1707         if (ret) {
1708                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1709                 /* enable rfkill interrupt: hw bug w/a */
1710                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1711                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1712                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1713                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1714                 }
1715         }
1716 }
1717
1718 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1719 {
1720         int iter_rx_q, i, ret, cpu, offset;
1721         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1722
1723         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1724         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1725         offset = 1 + i;
1726         for (; i < iter_rx_q ; i++) {
1727                 /*
1728                  * Get the cpu prior to the place to search
1729                  * (i.e. return will be > i - 1).
1730                  */
1731                 cpu = cpumask_next(i - offset, cpu_online_mask);
1732                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1733                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1734                                             &trans_pcie->affinity_mask[i]);
1735                 if (ret)
1736                         IWL_ERR(trans_pcie->trans,
1737                                 "Failed to set affinity mask for IRQ %d\n",
1738                                 trans_pcie->msix_entries[i].vector);
1739         }
1740 }
1741
1742 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1743                                       struct iwl_trans_pcie *trans_pcie)
1744 {
1745         int i;
1746
1747         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1748                 int ret;
1749                 struct msix_entry *msix_entry;
1750                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1751
1752                 if (!qname)
1753                         return -ENOMEM;
1754
1755                 msix_entry = &trans_pcie->msix_entries[i];
1756                 ret = devm_request_threaded_irq(&pdev->dev,
1757                                                 msix_entry->vector,
1758                                                 iwl_pcie_msix_isr,
1759                                                 (i == trans_pcie->def_irq) ?
1760                                                 iwl_pcie_irq_msix_handler :
1761                                                 iwl_pcie_irq_rx_msix_handler,
1762                                                 IRQF_SHARED,
1763                                                 qname,
1764                                                 msix_entry);
1765                 if (ret) {
1766                         IWL_ERR(trans_pcie->trans,
1767                                 "Error allocating IRQ %d\n", i);
1768
1769                         return ret;
1770                 }
1771         }
1772         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1773
1774         return 0;
1775 }
1776
1777 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1778 {
1779         u32 hpm, wprot;
1780
1781         switch (trans->trans_cfg->device_family) {
1782         case IWL_DEVICE_FAMILY_9000:
1783                 wprot = PREG_PRPH_WPROT_9000;
1784                 break;
1785         case IWL_DEVICE_FAMILY_22000:
1786                 wprot = PREG_PRPH_WPROT_22000;
1787                 break;
1788         default:
1789                 return 0;
1790         }
1791
1792         hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1793         if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
1794                 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1795
1796                 if (wprot_val & PREG_WFPM_ACCESS) {
1797                         IWL_ERR(trans,
1798                                 "Error, can not clear persistence bit\n");
1799                         return -EPERM;
1800                 }
1801                 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1802                                             hpm & ~PERSISTENCE_BIT);
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1809 {
1810         int ret;
1811
1812         ret = iwl_finish_nic_init(trans);
1813         if (ret < 0)
1814                 return ret;
1815
1816         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1817                           HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1818         udelay(20);
1819         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1820                           HPM_HIPM_GEN_CFG_CR_PG_EN |
1821                           HPM_HIPM_GEN_CFG_CR_SLP_EN);
1822         udelay(20);
1823         iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1824                             HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1825
1826         return iwl_trans_pcie_sw_reset(trans, true);
1827 }
1828
1829 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1830 {
1831         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1832         int err;
1833
1834         lockdep_assert_held(&trans_pcie->mutex);
1835
1836         err = iwl_pcie_prepare_card_hw(trans);
1837         if (err) {
1838                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1839                 return err;
1840         }
1841
1842         err = iwl_trans_pcie_clear_persistence_bit(trans);
1843         if (err)
1844                 return err;
1845
1846         err = iwl_trans_pcie_sw_reset(trans, true);
1847         if (err)
1848                 return err;
1849
1850         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1851             trans->trans_cfg->integrated) {
1852                 err = iwl_pcie_gen2_force_power_gating(trans);
1853                 if (err)
1854                         return err;
1855         }
1856
1857         err = iwl_pcie_apm_init(trans);
1858         if (err)
1859                 return err;
1860
1861         iwl_pcie_init_msix(trans_pcie);
1862
1863         /* From now on, the op_mode will be kept updated about RF kill state */
1864         iwl_enable_rfkill_int(trans);
1865
1866         trans_pcie->opmode_down = false;
1867
1868         /* Set is_down to false here so that...*/
1869         trans_pcie->is_down = false;
1870
1871         /* ...rfkill can call stop_device and set it false if needed */
1872         iwl_pcie_check_hw_rf_kill(trans);
1873
1874         return 0;
1875 }
1876
1877 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1878 {
1879         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1880         int ret;
1881
1882         mutex_lock(&trans_pcie->mutex);
1883         ret = _iwl_trans_pcie_start_hw(trans);
1884         mutex_unlock(&trans_pcie->mutex);
1885
1886         return ret;
1887 }
1888
1889 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1890 {
1891         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892
1893         mutex_lock(&trans_pcie->mutex);
1894
1895         /* disable interrupts - don't enable HW RF kill interrupt */
1896         iwl_disable_interrupts(trans);
1897
1898         iwl_pcie_apm_stop(trans, true);
1899
1900         iwl_disable_interrupts(trans);
1901
1902         iwl_pcie_disable_ict(trans);
1903
1904         mutex_unlock(&trans_pcie->mutex);
1905
1906         iwl_pcie_synchronize_irqs(trans);
1907 }
1908
1909 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1910 {
1911         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1912 }
1913
1914 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1915 {
1916         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1917 }
1918
1919 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1920 {
1921         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1922 }
1923
1924 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1925 {
1926         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1927                 return 0x00FFFFFF;
1928         else
1929                 return 0x000FFFFF;
1930 }
1931
1932 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1933 {
1934         u32 mask = iwl_trans_pcie_prph_msk(trans);
1935
1936         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1937                                ((reg & mask) | (3 << 24)));
1938         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1939 }
1940
1941 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1942                                       u32 val)
1943 {
1944         u32 mask = iwl_trans_pcie_prph_msk(trans);
1945
1946         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1947                                ((addr & mask) | (3 << 24)));
1948         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1949 }
1950
1951 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1952                                      const struct iwl_trans_config *trans_cfg)
1953 {
1954         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1955
1956         /* free all first - we might be reconfigured for a different size */
1957         iwl_pcie_free_rbs_pool(trans);
1958
1959         trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1960         trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1961         trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1962         trans->txqs.page_offs = trans_cfg->cb_data_offs;
1963         trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1964         trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver;
1965
1966         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1967                 trans_pcie->n_no_reclaim_cmds = 0;
1968         else
1969                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1970         if (trans_pcie->n_no_reclaim_cmds)
1971                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1972                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1973
1974         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1975         trans_pcie->rx_page_order =
1976                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1977         trans_pcie->rx_buf_bytes =
1978                 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1979         trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1980         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1981                 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1982
1983         trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1984         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1985
1986         trans->command_groups = trans_cfg->command_groups;
1987         trans->command_groups_size = trans_cfg->command_groups_size;
1988
1989         /* Initialize NAPI here - it should be before registering to mac80211
1990          * in the opmode but after the HW struct is allocated.
1991          * As this function may be called again in some corner cases don't
1992          * do anything if NAPI was already initialized.
1993          */
1994         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1995                 init_dummy_netdev(&trans_pcie->napi_dev);
1996
1997         trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1998 }
1999
2000 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
2001                                            struct device *dev)
2002 {
2003         u8 i;
2004         struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
2005
2006         /* free DRAM payloads */
2007         for (i = 0; i < dram_regions->n_regions; i++) {
2008                 dma_free_coherent(dev, dram_regions->drams[i].size,
2009                                   dram_regions->drams[i].block,
2010                                   dram_regions->drams[i].physical);
2011         }
2012         dram_regions->n_regions = 0;
2013
2014         /* free DRAM addresses array */
2015         if (desc_dram->block) {
2016                 dma_free_coherent(dev, desc_dram->size,
2017                                   desc_dram->block,
2018                                   desc_dram->physical);
2019         }
2020         memset(desc_dram, 0, sizeof(*desc_dram));
2021 }
2022
2023 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans)
2024 {
2025         iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd);
2026 }
2027
2028 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans)
2029 {
2030         struct iwl_cmd_header_wide bad_cmd = {
2031                 .cmd = INVALID_WR_PTR_CMD,
2032                 .group_id = DEBUG_GROUP,
2033                 .sequence = cpu_to_le16(0xffff),
2034                 .length = cpu_to_le16(0),
2035                 .version = 0,
2036         };
2037         int ret;
2038
2039         ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd,
2040                                      sizeof(bad_cmd));
2041         if (ret)
2042                 return ret;
2043         memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd));
2044         return 0;
2045 }
2046
2047 void iwl_trans_pcie_free(struct iwl_trans *trans)
2048 {
2049         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2050         int i;
2051
2052         iwl_pcie_synchronize_irqs(trans);
2053
2054         if (trans->trans_cfg->gen2)
2055                 iwl_txq_gen2_tx_free(trans);
2056         else
2057                 iwl_pcie_tx_free(trans);
2058         iwl_pcie_rx_free(trans);
2059
2060         if (trans_pcie->rba.alloc_wq) {
2061                 destroy_workqueue(trans_pcie->rba.alloc_wq);
2062                 trans_pcie->rba.alloc_wq = NULL;
2063         }
2064
2065         if (trans_pcie->msix_enabled) {
2066                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2067                         irq_set_affinity_hint(
2068                                 trans_pcie->msix_entries[i].vector,
2069                                 NULL);
2070                 }
2071
2072                 trans_pcie->msix_enabled = false;
2073         } else {
2074                 iwl_pcie_free_ict(trans);
2075         }
2076
2077         iwl_pcie_free_invalid_tx_cmd(trans);
2078
2079         iwl_pcie_free_fw_monitor(trans);
2080
2081         iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,
2082                                               trans->dev);
2083         iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,
2084                                               trans->dev);
2085
2086         mutex_destroy(&trans_pcie->mutex);
2087         iwl_trans_free(trans);
2088 }
2089
2090 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2091 {
2092         if (state)
2093                 set_bit(STATUS_TPOWER_PMI, &trans->status);
2094         else
2095                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
2096 }
2097
2098 struct iwl_trans_pcie_removal {
2099         struct pci_dev *pdev;
2100         struct work_struct work;
2101         bool rescan;
2102 };
2103
2104 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2105 {
2106         struct iwl_trans_pcie_removal *removal =
2107                 container_of(wk, struct iwl_trans_pcie_removal, work);
2108         struct pci_dev *pdev = removal->pdev;
2109         static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2110         struct pci_bus *bus = pdev->bus;
2111
2112         dev_err(&pdev->dev, "Device gone - attempting removal\n");
2113         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2114         pci_lock_rescan_remove();
2115         pci_dev_put(pdev);
2116         pci_stop_and_remove_bus_device(pdev);
2117         if (removal->rescan && bus) {
2118                 if (bus->parent)
2119                         bus = bus->parent;
2120                 pci_rescan_bus(bus);
2121         }
2122         pci_unlock_rescan_remove();
2123
2124         kfree(removal);
2125         module_put(THIS_MODULE);
2126 }
2127
2128 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan)
2129 {
2130         struct iwl_trans_pcie_removal *removal;
2131
2132         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2133                 return;
2134
2135         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2136
2137         /*
2138          * get a module reference to avoid doing this
2139          * while unloading anyway and to avoid
2140          * scheduling a work with code that's being
2141          * removed.
2142          */
2143         if (!try_module_get(THIS_MODULE)) {
2144                 IWL_ERR(trans,
2145                         "Module is being unloaded - abort\n");
2146                 return;
2147         }
2148
2149         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2150         if (!removal) {
2151                 module_put(THIS_MODULE);
2152                 return;
2153         }
2154         /*
2155          * we don't need to clear this flag, because
2156          * the trans will be freed and reallocated.
2157          */
2158         set_bit(STATUS_TRANS_DEAD, &trans->status);
2159
2160         removal->pdev = to_pci_dev(trans->dev);
2161         removal->rescan = rescan;
2162         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2163         pci_dev_get(removal->pdev);
2164         schedule_work(&removal->work);
2165 }
2166 EXPORT_SYMBOL(iwl_trans_pcie_remove);
2167
2168 /*
2169  * This version doesn't disable BHs but rather assumes they're
2170  * already disabled.
2171  */
2172 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2173 {
2174         int ret;
2175         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2176         u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2177         u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2178                    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2179         u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
2180
2181         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2182                 return false;
2183
2184         spin_lock(&trans_pcie->reg_lock);
2185
2186         if (trans_pcie->cmd_hold_nic_awake)
2187                 goto out;
2188
2189         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2190                 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2191                 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2192                 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2193         }
2194
2195         /* this bit wakes up the NIC */
2196         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
2197         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2198                 udelay(2);
2199
2200         /*
2201          * These bits say the device is running, and should keep running for
2202          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2203          * but they do not indicate that embedded SRAM is restored yet;
2204          * HW with volatile SRAM must save/restore contents to/from
2205          * host DRAM when sleeping/waking for power-saving.
2206          * Each direction takes approximately 1/4 millisecond; with this
2207          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2208          * series of register accesses are expected (e.g. reading Event Log),
2209          * to keep device from sleeping.
2210          *
2211          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2212          * SRAM is okay/restored.  We don't check that here because this call
2213          * is just for hardware register access; but GP1 MAC_SLEEP
2214          * check is a good idea before accessing the SRAM of HW with
2215          * volatile SRAM (e.g. reading Event Log).
2216          *
2217          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2218          * and do not save/restore SRAM when power cycling.
2219          */
2220         ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
2221         if (unlikely(ret < 0)) {
2222                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2223
2224                 WARN_ONCE(1,
2225                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2226                           cntrl);
2227
2228                 iwl_trans_pcie_dump_regs(trans);
2229
2230                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U)
2231                         iwl_trans_pcie_remove(trans, false);
2232                 else
2233                         iwl_write32(trans, CSR_RESET,
2234                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2235
2236                 spin_unlock(&trans_pcie->reg_lock);
2237                 return false;
2238         }
2239
2240 out:
2241         /*
2242          * Fool sparse by faking we release the lock - sparse will
2243          * track nic_access anyway.
2244          */
2245         __release(&trans_pcie->reg_lock);
2246         return true;
2247 }
2248
2249 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2250 {
2251         bool ret;
2252
2253         local_bh_disable();
2254         ret = __iwl_trans_pcie_grab_nic_access(trans);
2255         if (ret) {
2256                 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2257                 return ret;
2258         }
2259         local_bh_enable();
2260         return false;
2261 }
2262
2263 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2264 {
2265         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2266
2267         lockdep_assert_held(&trans_pcie->reg_lock);
2268
2269         /*
2270          * Fool sparse by faking we acquiring the lock - sparse will
2271          * track nic_access anyway.
2272          */
2273         __acquire(&trans_pcie->reg_lock);
2274
2275         if (trans_pcie->cmd_hold_nic_awake)
2276                 goto out;
2277         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2278                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2279                                            CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
2280         else
2281                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2282                                            CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2283         /*
2284          * Above we read the CSR_GP_CNTRL register, which will flush
2285          * any previous writes, but we need the write that clears the
2286          * MAC_ACCESS_REQ bit to be performed before any other writes
2287          * scheduled on different CPUs (after we drop reg_lock).
2288          */
2289 out:
2290         spin_unlock_bh(&trans_pcie->reg_lock);
2291 }
2292
2293 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2294                                    void *buf, int dwords)
2295 {
2296 #define IWL_MAX_HW_ERRS 5
2297         unsigned int num_consec_hw_errors = 0;
2298         int offs = 0;
2299         u32 *vals = buf;
2300
2301         while (offs < dwords) {
2302                 /* limit the time we spin here under lock to 1/2s */
2303                 unsigned long end = jiffies + HZ / 2;
2304                 bool resched = false;
2305
2306                 if (iwl_trans_grab_nic_access(trans)) {
2307                         iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2308                                     addr + 4 * offs);
2309
2310                         while (offs < dwords) {
2311                                 vals[offs] = iwl_read32(trans,
2312                                                         HBUS_TARG_MEM_RDAT);
2313
2314                                 if (iwl_trans_is_hw_error_value(vals[offs]))
2315                                         num_consec_hw_errors++;
2316                                 else
2317                                         num_consec_hw_errors = 0;
2318
2319                                 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) {
2320                                         iwl_trans_release_nic_access(trans);
2321                                         return -EIO;
2322                                 }
2323
2324                                 offs++;
2325
2326                                 if (time_after(jiffies, end)) {
2327                                         resched = true;
2328                                         break;
2329                                 }
2330                         }
2331                         iwl_trans_release_nic_access(trans);
2332
2333                         if (resched)
2334                                 cond_resched();
2335                 } else {
2336                         return -EBUSY;
2337                 }
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2344                                     const void *buf, int dwords)
2345 {
2346         int offs, ret = 0;
2347         const u32 *vals = buf;
2348
2349         if (iwl_trans_grab_nic_access(trans)) {
2350                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2351                 for (offs = 0; offs < dwords; offs++)
2352                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2353                                     vals ? vals[offs] : 0);
2354                 iwl_trans_release_nic_access(trans);
2355         } else {
2356                 ret = -EBUSY;
2357         }
2358         return ret;
2359 }
2360
2361 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2362                                         u32 *val)
2363 {
2364         return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2365                                      ofs, val);
2366 }
2367
2368 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2369 {
2370         int i;
2371
2372         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2373                 struct iwl_txq *txq = trans->txqs.txq[i];
2374
2375                 if (i == trans->txqs.cmd.q_id)
2376                         continue;
2377
2378                 spin_lock_bh(&txq->lock);
2379
2380                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2381                         txq->block--;
2382                         if (!txq->block) {
2383                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2384                                             txq->write_ptr | (i << 8));
2385                         }
2386                 } else if (block) {
2387                         txq->block++;
2388                 }
2389
2390                 spin_unlock_bh(&txq->lock);
2391         }
2392 }
2393
2394 #define IWL_FLUSH_WAIT_MS       2000
2395
2396 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2397                                        struct iwl_trans_rxq_dma_data *data)
2398 {
2399         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2400
2401         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2402                 return -EINVAL;
2403
2404         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2405         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2406         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2407         data->fr_bd_wid = 0;
2408
2409         return 0;
2410 }
2411
2412 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2413 {
2414         struct iwl_txq *txq;
2415         unsigned long now = jiffies;
2416         bool overflow_tx;
2417         u8 wr_ptr;
2418
2419         /* Make sure the NIC is still alive in the bus */
2420         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2421                 return -ENODEV;
2422
2423         if (!test_bit(txq_idx, trans->txqs.queue_used))
2424                 return -EINVAL;
2425
2426         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2427         txq = trans->txqs.txq[txq_idx];
2428
2429         spin_lock_bh(&txq->lock);
2430         overflow_tx = txq->overflow_tx ||
2431                       !skb_queue_empty(&txq->overflow_q);
2432         spin_unlock_bh(&txq->lock);
2433
2434         wr_ptr = READ_ONCE(txq->write_ptr);
2435
2436         while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2437                 overflow_tx) &&
2438                !time_after(jiffies,
2439                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2440                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2441
2442                 /*
2443                  * If write pointer moved during the wait, warn only
2444                  * if the TX came from op mode. In case TX came from
2445                  * trans layer (overflow TX) don't warn.
2446                  */
2447                 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2448                               "WR pointer moved while flushing %d -> %d\n",
2449                               wr_ptr, write_ptr))
2450                         return -ETIMEDOUT;
2451                 wr_ptr = write_ptr;
2452
2453                 usleep_range(1000, 2000);
2454
2455                 spin_lock_bh(&txq->lock);
2456                 overflow_tx = txq->overflow_tx ||
2457                               !skb_queue_empty(&txq->overflow_q);
2458                 spin_unlock_bh(&txq->lock);
2459         }
2460
2461         if (txq->read_ptr != txq->write_ptr) {
2462                 IWL_ERR(trans,
2463                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2464                 iwl_txq_log_scd_error(trans, txq);
2465                 return -ETIMEDOUT;
2466         }
2467
2468         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2469
2470         return 0;
2471 }
2472
2473 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2474 {
2475         int cnt;
2476         int ret = 0;
2477
2478         /* waiting for all the tx frames complete might take a while */
2479         for (cnt = 0;
2480              cnt < trans->trans_cfg->base_params->num_of_queues;
2481              cnt++) {
2482
2483                 if (cnt == trans->txqs.cmd.q_id)
2484                         continue;
2485                 if (!test_bit(cnt, trans->txqs.queue_used))
2486                         continue;
2487                 if (!(BIT(cnt) & txq_bm))
2488                         continue;
2489
2490                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2491                 if (ret)
2492                         break;
2493         }
2494
2495         return ret;
2496 }
2497
2498 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2499                                          u32 mask, u32 value)
2500 {
2501         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2502
2503         spin_lock_bh(&trans_pcie->reg_lock);
2504         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2505         spin_unlock_bh(&trans_pcie->reg_lock);
2506 }
2507
2508 static const char *get_csr_string(int cmd)
2509 {
2510 #define IWL_CMD(x) case x: return #x
2511         switch (cmd) {
2512         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2513         IWL_CMD(CSR_INT_COALESCING);
2514         IWL_CMD(CSR_INT);
2515         IWL_CMD(CSR_INT_MASK);
2516         IWL_CMD(CSR_FH_INT_STATUS);
2517         IWL_CMD(CSR_GPIO_IN);
2518         IWL_CMD(CSR_RESET);
2519         IWL_CMD(CSR_GP_CNTRL);
2520         IWL_CMD(CSR_HW_REV);
2521         IWL_CMD(CSR_EEPROM_REG);
2522         IWL_CMD(CSR_EEPROM_GP);
2523         IWL_CMD(CSR_OTP_GP_REG);
2524         IWL_CMD(CSR_GIO_REG);
2525         IWL_CMD(CSR_GP_UCODE_REG);
2526         IWL_CMD(CSR_GP_DRIVER_REG);
2527         IWL_CMD(CSR_UCODE_DRV_GP1);
2528         IWL_CMD(CSR_UCODE_DRV_GP2);
2529         IWL_CMD(CSR_LED_REG);
2530         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2531         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2532         IWL_CMD(CSR_ANA_PLL_CFG);
2533         IWL_CMD(CSR_HW_REV_WA_REG);
2534         IWL_CMD(CSR_MONITOR_STATUS_REG);
2535         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2536         default:
2537                 return "UNKNOWN";
2538         }
2539 #undef IWL_CMD
2540 }
2541
2542 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2543 {
2544         int i;
2545         static const u32 csr_tbl[] = {
2546                 CSR_HW_IF_CONFIG_REG,
2547                 CSR_INT_COALESCING,
2548                 CSR_INT,
2549                 CSR_INT_MASK,
2550                 CSR_FH_INT_STATUS,
2551                 CSR_GPIO_IN,
2552                 CSR_RESET,
2553                 CSR_GP_CNTRL,
2554                 CSR_HW_REV,
2555                 CSR_EEPROM_REG,
2556                 CSR_EEPROM_GP,
2557                 CSR_OTP_GP_REG,
2558                 CSR_GIO_REG,
2559                 CSR_GP_UCODE_REG,
2560                 CSR_GP_DRIVER_REG,
2561                 CSR_UCODE_DRV_GP1,
2562                 CSR_UCODE_DRV_GP2,
2563                 CSR_LED_REG,
2564                 CSR_DRAM_INT_TBL_REG,
2565                 CSR_GIO_CHICKEN_BITS,
2566                 CSR_ANA_PLL_CFG,
2567                 CSR_MONITOR_STATUS_REG,
2568                 CSR_HW_REV_WA_REG,
2569                 CSR_DBG_HPET_MEM_REG
2570         };
2571         IWL_ERR(trans, "CSR values:\n");
2572         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2573                 "CSR_INT_PERIODIC_REG)\n");
2574         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2575                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2576                         get_csr_string(csr_tbl[i]),
2577                         iwl_read32(trans, csr_tbl[i]));
2578         }
2579 }
2580
2581 #ifdef CONFIG_IWLWIFI_DEBUGFS
2582 /* create and remove of files */
2583 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2584         debugfs_create_file(#name, mode, parent, trans,                 \
2585                             &iwl_dbgfs_##name##_ops);                   \
2586 } while (0)
2587
2588 /* file operation */
2589 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2590 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2591         .read = iwl_dbgfs_##name##_read,                                \
2592         .open = simple_open,                                            \
2593         .llseek = generic_file_llseek,                                  \
2594 };
2595
2596 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2597 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2598         .write = iwl_dbgfs_##name##_write,                              \
2599         .open = simple_open,                                            \
2600         .llseek = generic_file_llseek,                                  \
2601 };
2602
2603 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2604 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2605         .write = iwl_dbgfs_##name##_write,                              \
2606         .read = iwl_dbgfs_##name##_read,                                \
2607         .open = simple_open,                                            \
2608         .llseek = generic_file_llseek,                                  \
2609 };
2610
2611 struct iwl_dbgfs_tx_queue_priv {
2612         struct iwl_trans *trans;
2613 };
2614
2615 struct iwl_dbgfs_tx_queue_state {
2616         loff_t pos;
2617 };
2618
2619 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2620 {
2621         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2622         struct iwl_dbgfs_tx_queue_state *state;
2623
2624         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2625                 return NULL;
2626
2627         state = kmalloc(sizeof(*state), GFP_KERNEL);
2628         if (!state)
2629                 return NULL;
2630         state->pos = *pos;
2631         return state;
2632 }
2633
2634 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2635                                          void *v, loff_t *pos)
2636 {
2637         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2638         struct iwl_dbgfs_tx_queue_state *state = v;
2639
2640         *pos = ++state->pos;
2641
2642         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2643                 return NULL;
2644
2645         return state;
2646 }
2647
2648 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2649 {
2650         kfree(v);
2651 }
2652
2653 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2654 {
2655         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2656         struct iwl_dbgfs_tx_queue_state *state = v;
2657         struct iwl_trans *trans = priv->trans;
2658         struct iwl_txq *txq = trans->txqs.txq[state->pos];
2659
2660         seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2661                    (unsigned int)state->pos,
2662                    !!test_bit(state->pos, trans->txqs.queue_used),
2663                    !!test_bit(state->pos, trans->txqs.queue_stopped));
2664         if (txq)
2665                 seq_printf(seq,
2666                            "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2667                            txq->read_ptr, txq->write_ptr,
2668                            txq->need_update, txq->frozen,
2669                            txq->n_window, txq->ampdu);
2670         else
2671                 seq_puts(seq, "(unallocated)");
2672
2673         if (state->pos == trans->txqs.cmd.q_id)
2674                 seq_puts(seq, " (HCMD)");
2675         seq_puts(seq, "\n");
2676
2677         return 0;
2678 }
2679
2680 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2681         .start = iwl_dbgfs_tx_queue_seq_start,
2682         .next = iwl_dbgfs_tx_queue_seq_next,
2683         .stop = iwl_dbgfs_tx_queue_seq_stop,
2684         .show = iwl_dbgfs_tx_queue_seq_show,
2685 };
2686
2687 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2688 {
2689         struct iwl_dbgfs_tx_queue_priv *priv;
2690
2691         priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2692                                   sizeof(*priv));
2693
2694         if (!priv)
2695                 return -ENOMEM;
2696
2697         priv->trans = inode->i_private;
2698         return 0;
2699 }
2700
2701 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2702                                        char __user *user_buf,
2703                                        size_t count, loff_t *ppos)
2704 {
2705         struct iwl_trans *trans = file->private_data;
2706         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2707         char *buf;
2708         int pos = 0, i, ret;
2709         size_t bufsz;
2710
2711         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2712
2713         if (!trans_pcie->rxq)
2714                 return -EAGAIN;
2715
2716         buf = kzalloc(bufsz, GFP_KERNEL);
2717         if (!buf)
2718                 return -ENOMEM;
2719
2720         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2721                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2722
2723                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2724                                  i);
2725                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2726                                  rxq->read);
2727                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2728                                  rxq->write);
2729                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2730                                  rxq->write_actual);
2731                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2732                                  rxq->need_update);
2733                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2734                                  rxq->free_count);
2735                 if (rxq->rb_stts) {
2736                         u32 r = iwl_get_closed_rb_stts(trans, rxq);
2737                         pos += scnprintf(buf + pos, bufsz - pos,
2738                                          "\tclosed_rb_num: %u\n", r);
2739                 } else {
2740                         pos += scnprintf(buf + pos, bufsz - pos,
2741                                          "\tclosed_rb_num: Not Allocated\n");
2742                 }
2743         }
2744         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2745         kfree(buf);
2746
2747         return ret;
2748 }
2749
2750 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2751                                         char __user *user_buf,
2752                                         size_t count, loff_t *ppos)
2753 {
2754         struct iwl_trans *trans = file->private_data;
2755         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2756         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2757
2758         int pos = 0;
2759         char *buf;
2760         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2761         ssize_t ret;
2762
2763         buf = kzalloc(bufsz, GFP_KERNEL);
2764         if (!buf)
2765                 return -ENOMEM;
2766
2767         pos += scnprintf(buf + pos, bufsz - pos,
2768                         "Interrupt Statistics Report:\n");
2769
2770         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2771                 isr_stats->hw);
2772         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2773                 isr_stats->sw);
2774         if (isr_stats->sw || isr_stats->hw) {
2775                 pos += scnprintf(buf + pos, bufsz - pos,
2776                         "\tLast Restarting Code:  0x%X\n",
2777                         isr_stats->err_code);
2778         }
2779 #ifdef CONFIG_IWLWIFI_DEBUG
2780         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2781                 isr_stats->sch);
2782         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2783                 isr_stats->alive);
2784 #endif
2785         pos += scnprintf(buf + pos, bufsz - pos,
2786                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2787
2788         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2789                 isr_stats->ctkill);
2790
2791         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2792                 isr_stats->wakeup);
2793
2794         pos += scnprintf(buf + pos, bufsz - pos,
2795                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2796
2797         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2798                 isr_stats->tx);
2799
2800         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2801                 isr_stats->unhandled);
2802
2803         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2804         kfree(buf);
2805         return ret;
2806 }
2807
2808 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2809                                          const char __user *user_buf,
2810                                          size_t count, loff_t *ppos)
2811 {
2812         struct iwl_trans *trans = file->private_data;
2813         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2814         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2815         u32 reset_flag;
2816         int ret;
2817
2818         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2819         if (ret)
2820                 return ret;
2821         if (reset_flag == 0)
2822                 memset(isr_stats, 0, sizeof(*isr_stats));
2823
2824         return count;
2825 }
2826
2827 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2828                                    const char __user *user_buf,
2829                                    size_t count, loff_t *ppos)
2830 {
2831         struct iwl_trans *trans = file->private_data;
2832
2833         iwl_pcie_dump_csr(trans);
2834
2835         return count;
2836 }
2837
2838 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2839                                      char __user *user_buf,
2840                                      size_t count, loff_t *ppos)
2841 {
2842         struct iwl_trans *trans = file->private_data;
2843         char *buf = NULL;
2844         ssize_t ret;
2845
2846         ret = iwl_dump_fh(trans, &buf);
2847         if (ret < 0)
2848                 return ret;
2849         if (!buf)
2850                 return -EINVAL;
2851         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2852         kfree(buf);
2853         return ret;
2854 }
2855
2856 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2857                                      char __user *user_buf,
2858                                      size_t count, loff_t *ppos)
2859 {
2860         struct iwl_trans *trans = file->private_data;
2861         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2862         char buf[100];
2863         int pos;
2864
2865         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2866                         trans_pcie->debug_rfkill,
2867                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2868                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2869
2870         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2871 }
2872
2873 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2874                                       const char __user *user_buf,
2875                                       size_t count, loff_t *ppos)
2876 {
2877         struct iwl_trans *trans = file->private_data;
2878         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2879         bool new_value;
2880         int ret;
2881
2882         ret = kstrtobool_from_user(user_buf, count, &new_value);
2883         if (ret)
2884                 return ret;
2885         if (new_value == trans_pcie->debug_rfkill)
2886                 return count;
2887         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2888                  trans_pcie->debug_rfkill, new_value);
2889         trans_pcie->debug_rfkill = new_value;
2890         iwl_pcie_handle_rfkill_irq(trans);
2891
2892         return count;
2893 }
2894
2895 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2896                                        struct file *file)
2897 {
2898         struct iwl_trans *trans = inode->i_private;
2899         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2900
2901         if (!trans->dbg.dest_tlv ||
2902             trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2903                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2904                 return -ENOENT;
2905         }
2906
2907         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2908                 return -EBUSY;
2909
2910         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2911         return simple_open(inode, file);
2912 }
2913
2914 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2915                                           struct file *file)
2916 {
2917         struct iwl_trans_pcie *trans_pcie =
2918                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2919
2920         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2921                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2922         return 0;
2923 }
2924
2925 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2926                                   void *buf, ssize_t *size,
2927                                   ssize_t *bytes_copied)
2928 {
2929         ssize_t buf_size_left = count - *bytes_copied;
2930
2931         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2932         if (*size > buf_size_left)
2933                 *size = buf_size_left;
2934
2935         *size -= copy_to_user(user_buf, buf, *size);
2936         *bytes_copied += *size;
2937
2938         if (buf_size_left == *size)
2939                 return true;
2940         return false;
2941 }
2942
2943 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2944                                            char __user *user_buf,
2945                                            size_t count, loff_t *ppos)
2946 {
2947         struct iwl_trans *trans = file->private_data;
2948         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2949         u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2950         struct cont_rec *data = &trans_pcie->fw_mon_data;
2951         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2952         ssize_t size, bytes_copied = 0;
2953         bool b_full;
2954
2955         if (trans->dbg.dest_tlv) {
2956                 write_ptr_addr =
2957                         le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2958                 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2959         } else {
2960                 write_ptr_addr = MON_BUFF_WRPTR;
2961                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2962         }
2963
2964         if (unlikely(!trans->dbg.rec_on))
2965                 return 0;
2966
2967         mutex_lock(&data->mutex);
2968         if (data->state ==
2969             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2970                 mutex_unlock(&data->mutex);
2971                 return 0;
2972         }
2973
2974         /* write_ptr position in bytes rather then DW */
2975         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2976         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2977
2978         if (data->prev_wrap_cnt == wrap_cnt) {
2979                 size = write_ptr - data->prev_wr_ptr;
2980                 curr_buf = cpu_addr + data->prev_wr_ptr;
2981                 b_full = iwl_write_to_user_buf(user_buf, count,
2982                                                curr_buf, &size,
2983                                                &bytes_copied);
2984                 data->prev_wr_ptr += size;
2985
2986         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2987                    write_ptr < data->prev_wr_ptr) {
2988                 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2989                 curr_buf = cpu_addr + data->prev_wr_ptr;
2990                 b_full = iwl_write_to_user_buf(user_buf, count,
2991                                                curr_buf, &size,
2992                                                &bytes_copied);
2993                 data->prev_wr_ptr += size;
2994
2995                 if (!b_full) {
2996                         size = write_ptr;
2997                         b_full = iwl_write_to_user_buf(user_buf, count,
2998                                                        cpu_addr, &size,
2999                                                        &bytes_copied);
3000                         data->prev_wr_ptr = size;
3001                         data->prev_wrap_cnt++;
3002                 }
3003         } else {
3004                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
3005                     write_ptr > data->prev_wr_ptr)
3006                         IWL_WARN(trans,
3007                                  "write pointer passed previous write pointer, start copying from the beginning\n");
3008                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
3009                                    data->prev_wr_ptr == 0))
3010                         IWL_WARN(trans,
3011                                  "monitor data is out of sync, start copying from the beginning\n");
3012
3013                 size = write_ptr;
3014                 b_full = iwl_write_to_user_buf(user_buf, count,
3015                                                cpu_addr, &size,
3016                                                &bytes_copied);
3017                 data->prev_wr_ptr = size;
3018                 data->prev_wrap_cnt = wrap_cnt;
3019         }
3020
3021         mutex_unlock(&data->mutex);
3022
3023         return bytes_copied;
3024 }
3025
3026 static ssize_t iwl_dbgfs_rf_read(struct file *file,
3027                                  char __user *user_buf,
3028                                  size_t count, loff_t *ppos)
3029 {
3030         struct iwl_trans *trans = file->private_data;
3031         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3032
3033         if (!trans_pcie->rf_name[0])
3034                 return -ENODEV;
3035
3036         return simple_read_from_buffer(user_buf, count, ppos,
3037                                        trans_pcie->rf_name,
3038                                        strlen(trans_pcie->rf_name));
3039 }
3040
3041 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
3042 DEBUGFS_READ_FILE_OPS(fh_reg);
3043 DEBUGFS_READ_FILE_OPS(rx_queue);
3044 DEBUGFS_WRITE_FILE_OPS(csr);
3045 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
3046 DEBUGFS_READ_FILE_OPS(rf);
3047
3048 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
3049         .owner = THIS_MODULE,
3050         .open = iwl_dbgfs_tx_queue_open,
3051         .read = seq_read,
3052         .llseek = seq_lseek,
3053         .release = seq_release_private,
3054 };
3055
3056 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
3057         .read = iwl_dbgfs_monitor_data_read,
3058         .open = iwl_dbgfs_monitor_data_open,
3059         .release = iwl_dbgfs_monitor_data_release,
3060 };
3061
3062 /* Create the debugfs files and directories */
3063 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
3064 {
3065         struct dentry *dir = trans->dbgfs_dir;
3066
3067         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
3068         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
3069         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
3070         DEBUGFS_ADD_FILE(csr, dir, 0200);
3071         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
3072         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
3073         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
3074         DEBUGFS_ADD_FILE(rf, dir, 0400);
3075 }
3076
3077 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
3078 {
3079         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3080         struct cont_rec *data = &trans_pcie->fw_mon_data;
3081
3082         mutex_lock(&data->mutex);
3083         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
3084         mutex_unlock(&data->mutex);
3085 }
3086 #endif /*CONFIG_IWLWIFI_DEBUGFS */
3087
3088 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
3089 {
3090         u32 cmdlen = 0;
3091         int i;
3092
3093         for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
3094                 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
3095
3096         return cmdlen;
3097 }
3098
3099 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3100                                    struct iwl_fw_error_dump_data **data,
3101                                    int allocated_rb_nums)
3102 {
3103         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3104         int max_len = trans_pcie->rx_buf_bytes;
3105         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3106         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3107         u32 i, r, j, rb_len = 0;
3108
3109         spin_lock_bh(&rxq->lock);
3110
3111         r = iwl_get_closed_rb_stts(trans, rxq);
3112
3113         for (i = rxq->read, j = 0;
3114              i != r && j < allocated_rb_nums;
3115              i = (i + 1) & RX_QUEUE_MASK, j++) {
3116                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3117                 struct iwl_fw_error_dump_rb *rb;
3118
3119                 dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3120                                         max_len, DMA_FROM_DEVICE);
3121
3122                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3123
3124                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3125                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3126                 rb = (void *)(*data)->data;
3127                 rb->index = cpu_to_le32(i);
3128                 memcpy(rb->data, page_address(rxb->page), max_len);
3129
3130                 *data = iwl_fw_error_next_data(*data);
3131         }
3132
3133         spin_unlock_bh(&rxq->lock);
3134
3135         return rb_len;
3136 }
3137 #define IWL_CSR_TO_DUMP (0x250)
3138
3139 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3140                                    struct iwl_fw_error_dump_data **data)
3141 {
3142         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3143         __le32 *val;
3144         int i;
3145
3146         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3147         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3148         val = (void *)(*data)->data;
3149
3150         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3151                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3152
3153         *data = iwl_fw_error_next_data(*data);
3154
3155         return csr_len;
3156 }
3157
3158 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3159                                        struct iwl_fw_error_dump_data **data)
3160 {
3161         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3162         __le32 *val;
3163         int i;
3164
3165         if (!iwl_trans_grab_nic_access(trans))
3166                 return 0;
3167
3168         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3169         (*data)->len = cpu_to_le32(fh_regs_len);
3170         val = (void *)(*data)->data;
3171
3172         if (!trans->trans_cfg->gen2)
3173                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3174                      i += sizeof(u32))
3175                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3176         else
3177                 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3178                      i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3179                      i += sizeof(u32))
3180                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3181                                                                       i));
3182
3183         iwl_trans_release_nic_access(trans);
3184
3185         *data = iwl_fw_error_next_data(*data);
3186
3187         return sizeof(**data) + fh_regs_len;
3188 }
3189
3190 static u32
3191 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3192                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3193                                  u32 monitor_len)
3194 {
3195         u32 buf_size_in_dwords = (monitor_len >> 2);
3196         u32 *buffer = (u32 *)fw_mon_data->data;
3197         u32 i;
3198
3199         if (!iwl_trans_grab_nic_access(trans))
3200                 return 0;
3201
3202         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3203         for (i = 0; i < buf_size_in_dwords; i++)
3204                 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3205                                                        MON_DMARB_RD_DATA_ADDR);
3206         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3207
3208         iwl_trans_release_nic_access(trans);
3209
3210         return monitor_len;
3211 }
3212
3213 static void
3214 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3215                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3216 {
3217         u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3218
3219         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3220                 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3221                 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3222                 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3223                 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3224         } else if (trans->dbg.dest_tlv) {
3225                 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3226                 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3227                 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3228         } else {
3229                 base = MON_BUFF_BASE_ADDR;
3230                 write_ptr = MON_BUFF_WRPTR;
3231                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3232         }
3233
3234         write_ptr_val = iwl_read_prph(trans, write_ptr);
3235         fw_mon_data->fw_mon_cycle_cnt =
3236                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3237         fw_mon_data->fw_mon_base_ptr =
3238                 cpu_to_le32(iwl_read_prph(trans, base));
3239         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3240                 fw_mon_data->fw_mon_base_high_ptr =
3241                         cpu_to_le32(iwl_read_prph(trans, base_high));
3242                 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3243                 /* convert wrtPtr to DWs, to align with all HWs */
3244                 write_ptr_val >>= 2;
3245         }
3246         fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3247 }
3248
3249 static u32
3250 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3251                             struct iwl_fw_error_dump_data **data,
3252                             u32 monitor_len)
3253 {
3254         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3255         u32 len = 0;
3256
3257         if (trans->dbg.dest_tlv ||
3258             (fw_mon->size &&
3259              (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3260               trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3261                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3262
3263                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3264                 fw_mon_data = (void *)(*data)->data;
3265
3266                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3267
3268                 len += sizeof(**data) + sizeof(*fw_mon_data);
3269                 if (fw_mon->size) {
3270                         memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3271                         monitor_len = fw_mon->size;
3272                 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3273                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3274                         /*
3275                          * Update pointers to reflect actual values after
3276                          * shifting
3277                          */
3278                         if (trans->dbg.dest_tlv->version) {
3279                                 base = (iwl_read_prph(trans, base) &
3280                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3281                                        trans->dbg.dest_tlv->base_shift;
3282                                 base *= IWL_M2S_UNIT_SIZE;
3283                                 base += trans->cfg->smem_offset;
3284                         } else {
3285                                 base = iwl_read_prph(trans, base) <<
3286                                        trans->dbg.dest_tlv->base_shift;
3287                         }
3288
3289                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3290                                            monitor_len / sizeof(u32));
3291                 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3292                         monitor_len =
3293                                 iwl_trans_pci_dump_marbh_monitor(trans,
3294                                                                  fw_mon_data,
3295                                                                  monitor_len);
3296                 } else {
3297                         /* Didn't match anything - output no monitor data */
3298                         monitor_len = 0;
3299                 }
3300
3301                 len += monitor_len;
3302                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3303         }
3304
3305         return len;
3306 }
3307
3308 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3309 {
3310         if (trans->dbg.fw_mon.size) {
3311                 *len += sizeof(struct iwl_fw_error_dump_data) +
3312                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3313                         trans->dbg.fw_mon.size;
3314                 return trans->dbg.fw_mon.size;
3315         } else if (trans->dbg.dest_tlv) {
3316                 u32 base, end, cfg_reg, monitor_len;
3317
3318                 if (trans->dbg.dest_tlv->version == 1) {
3319                         cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3320                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3321                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3322                                 trans->dbg.dest_tlv->base_shift;
3323                         base *= IWL_M2S_UNIT_SIZE;
3324                         base += trans->cfg->smem_offset;
3325
3326                         monitor_len =
3327                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3328                                 trans->dbg.dest_tlv->end_shift;
3329                         monitor_len *= IWL_M2S_UNIT_SIZE;
3330                 } else {
3331                         base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3332                         end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3333
3334                         base = iwl_read_prph(trans, base) <<
3335                                trans->dbg.dest_tlv->base_shift;
3336                         end = iwl_read_prph(trans, end) <<
3337                               trans->dbg.dest_tlv->end_shift;
3338
3339                         /* Make "end" point to the actual end */
3340                         if (trans->trans_cfg->device_family >=
3341                             IWL_DEVICE_FAMILY_8000 ||
3342                             trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3343                                 end += (1 << trans->dbg.dest_tlv->end_shift);
3344                         monitor_len = end - base;
3345                 }
3346                 *len += sizeof(struct iwl_fw_error_dump_data) +
3347                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3348                         monitor_len;
3349                 return monitor_len;
3350         }
3351         return 0;
3352 }
3353
3354 static struct iwl_trans_dump_data *
3355 iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3356                          u32 dump_mask,
3357                          const struct iwl_dump_sanitize_ops *sanitize_ops,
3358                          void *sanitize_ctx)
3359 {
3360         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3361         struct iwl_fw_error_dump_data *data;
3362         struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
3363         struct iwl_fw_error_dump_txcmd *txcmd;
3364         struct iwl_trans_dump_data *dump_data;
3365         u32 len, num_rbs = 0, monitor_len = 0;
3366         int i, ptr;
3367         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3368                         !trans->trans_cfg->mq_rx_supported &&
3369                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3370
3371         if (!dump_mask)
3372                 return NULL;
3373
3374         /* transport dump header */
3375         len = sizeof(*dump_data);
3376
3377         /* host commands */
3378         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3379                 len += sizeof(*data) +
3380                         cmdq->n_window * (sizeof(*txcmd) +
3381                                           TFD_MAX_PAYLOAD_SIZE);
3382
3383         /* FW monitor */
3384         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3385                 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3386
3387         /* CSR registers */
3388         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3389                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3390
3391         /* FH registers */
3392         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3393                 if (trans->trans_cfg->gen2)
3394                         len += sizeof(*data) +
3395                                (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3396                                 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3397                 else
3398                         len += sizeof(*data) +
3399                                (FH_MEM_UPPER_BOUND -
3400                                 FH_MEM_LOWER_BOUND);
3401         }
3402
3403         if (dump_rbs) {
3404                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3405                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3406                 /* RBs */
3407                 num_rbs = iwl_get_closed_rb_stts(trans, rxq);
3408                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3409                 len += num_rbs * (sizeof(*data) +
3410                                   sizeof(struct iwl_fw_error_dump_rb) +
3411                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3412         }
3413
3414         /* Paged memory for gen2 HW */
3415         if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3416                 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3417                         len += sizeof(*data) +
3418                                sizeof(struct iwl_fw_error_dump_paging) +
3419                                trans->init_dram.paging[i].size;
3420
3421         dump_data = vzalloc(len);
3422         if (!dump_data)
3423                 return NULL;
3424
3425         len = 0;
3426         data = (void *)dump_data->data;
3427
3428         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3429                 u16 tfd_size = trans->txqs.tfd.size;
3430
3431                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3432                 txcmd = (void *)data->data;
3433                 spin_lock_bh(&cmdq->lock);
3434                 ptr = cmdq->write_ptr;
3435                 for (i = 0; i < cmdq->n_window; i++) {
3436                         u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3437                         u8 tfdidx;
3438                         u32 caplen, cmdlen;
3439
3440                         if (trans->trans_cfg->gen2)
3441                                 tfdidx = idx;
3442                         else
3443                                 tfdidx = ptr;
3444
3445                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3446                                                            (u8 *)cmdq->tfds +
3447                                                            tfd_size * tfdidx);
3448                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3449
3450                         if (cmdlen) {
3451                                 len += sizeof(*txcmd) + caplen;
3452                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3453                                 txcmd->caplen = cpu_to_le32(caplen);
3454                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3455                                        caplen);
3456                                 if (sanitize_ops && sanitize_ops->frob_hcmd)
3457                                         sanitize_ops->frob_hcmd(sanitize_ctx,
3458                                                                 txcmd->data,
3459                                                                 caplen);
3460                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3461                         }
3462
3463                         ptr = iwl_txq_dec_wrap(trans, ptr);
3464                 }
3465                 spin_unlock_bh(&cmdq->lock);
3466
3467                 data->len = cpu_to_le32(len);
3468                 len += sizeof(*data);
3469                 data = iwl_fw_error_next_data(data);
3470         }
3471
3472         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3473                 len += iwl_trans_pcie_dump_csr(trans, &data);
3474         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3475                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3476         if (dump_rbs)
3477                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3478
3479         /* Paged memory for gen2 HW */
3480         if (trans->trans_cfg->gen2 &&
3481             dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3482                 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3483                         struct iwl_fw_error_dump_paging *paging;
3484                         u32 page_len = trans->init_dram.paging[i].size;
3485
3486                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3487                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3488                         paging = (void *)data->data;
3489                         paging->index = cpu_to_le32(i);
3490                         memcpy(paging->data,
3491                                trans->init_dram.paging[i].block, page_len);
3492                         data = iwl_fw_error_next_data(data);
3493
3494                         len += sizeof(*data) + sizeof(*paging) + page_len;
3495                 }
3496         }
3497         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3498                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3499
3500         dump_data->len = len;
3501
3502         return dump_data;
3503 }
3504
3505 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3506 {
3507         if (enable)
3508                 iwl_enable_interrupts(trans);
3509         else
3510                 iwl_disable_interrupts(trans);
3511 }
3512
3513 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3514 {
3515         u32 inta_addr, sw_err_bit;
3516         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3517
3518         if (trans_pcie->msix_enabled) {
3519                 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3520                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3521                         sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
3522                 else
3523                         sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3524         } else {
3525                 inta_addr = CSR_INT;
3526                 sw_err_bit = CSR_INT_BIT_SW_ERR;
3527         }
3528
3529         iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3530 }
3531
3532 #define IWL_TRANS_COMMON_OPS                                            \
3533         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3534         .write8 = iwl_trans_pcie_write8,                                \
3535         .write32 = iwl_trans_pcie_write32,                              \
3536         .read32 = iwl_trans_pcie_read32,                                \
3537         .read_prph = iwl_trans_pcie_read_prph,                          \
3538         .write_prph = iwl_trans_pcie_write_prph,                        \
3539         .read_mem = iwl_trans_pcie_read_mem,                            \
3540         .write_mem = iwl_trans_pcie_write_mem,                          \
3541         .read_config32 = iwl_trans_pcie_read_config32,                  \
3542         .configure = iwl_trans_pcie_configure,                          \
3543         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3544         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3545         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3546         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3547         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3548         .dump_data = iwl_trans_pcie_dump_data,                          \
3549         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3550         .d3_resume = iwl_trans_pcie_d3_resume,                          \
3551         .interrupts = iwl_trans_pci_interrupts,                         \
3552         .sync_nmi = iwl_trans_pcie_sync_nmi,                            \
3553         .imr_dma_data = iwl_trans_pcie_copy_imr                         \
3554
3555 static const struct iwl_trans_ops trans_ops_pcie = {
3556         IWL_TRANS_COMMON_OPS,
3557         .start_hw = iwl_trans_pcie_start_hw,
3558         .fw_alive = iwl_trans_pcie_fw_alive,
3559         .start_fw = iwl_trans_pcie_start_fw,
3560         .stop_device = iwl_trans_pcie_stop_device,
3561
3562         .send_cmd = iwl_pcie_enqueue_hcmd,
3563
3564         .tx = iwl_trans_pcie_tx,
3565         .reclaim = iwl_txq_reclaim,
3566
3567         .txq_disable = iwl_trans_pcie_txq_disable,
3568         .txq_enable = iwl_trans_pcie_txq_enable,
3569
3570         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3571
3572         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3573
3574         .freeze_txq_timer = iwl_trans_txq_freeze_timer,
3575         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3576 #ifdef CONFIG_IWLWIFI_DEBUGFS
3577         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3578 #endif
3579 };
3580
3581 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3582         IWL_TRANS_COMMON_OPS,
3583         .start_hw = iwl_trans_pcie_start_hw,
3584         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3585         .start_fw = iwl_trans_pcie_gen2_start_fw,
3586         .stop_device = iwl_trans_pcie_gen2_stop_device,
3587
3588         .send_cmd = iwl_pcie_gen2_enqueue_hcmd,
3589
3590         .tx = iwl_txq_gen2_tx,
3591         .reclaim = iwl_txq_reclaim,
3592
3593         .set_q_ptrs = iwl_txq_set_q_ptrs,
3594
3595         .txq_alloc = iwl_txq_dyn_alloc,
3596         .txq_free = iwl_txq_dyn_free,
3597         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3598         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3599         .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm,
3600         .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3601         .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power,
3602         .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3603 #ifdef CONFIG_IWLWIFI_DEBUGFS
3604         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3605 #endif
3606 };
3607
3608 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3609                                const struct pci_device_id *ent,
3610                                const struct iwl_cfg_trans_params *cfg_trans)
3611 {
3612         struct iwl_trans_pcie *trans_pcie;
3613         struct iwl_trans *trans;
3614         int ret, addr_size;
3615         const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3616         void __iomem * const *table;
3617         u32 bar0;
3618
3619         if (!cfg_trans->gen2)
3620                 ops = &trans_ops_pcie;
3621
3622         /* reassign our BAR 0 if invalid due to possible runtime PM races */
3623         pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);
3624         if (bar0 == PCI_BASE_ADDRESS_MEM_TYPE_64) {
3625                 ret = pci_assign_resource(pdev, 0);
3626                 if (ret)
3627                         return ERR_PTR(ret);
3628         }
3629
3630         ret = pcim_enable_device(pdev);
3631         if (ret)
3632                 return ERR_PTR(ret);
3633
3634         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3635                                 cfg_trans);
3636         if (!trans)
3637                 return ERR_PTR(-ENOMEM);
3638
3639         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3640
3641         trans_pcie->trans = trans;
3642         trans_pcie->opmode_down = true;
3643         spin_lock_init(&trans_pcie->irq_lock);
3644         spin_lock_init(&trans_pcie->reg_lock);
3645         spin_lock_init(&trans_pcie->alloc_page_lock);
3646         mutex_init(&trans_pcie->mutex);
3647         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3648         init_waitqueue_head(&trans_pcie->fw_reset_waitq);
3649         init_waitqueue_head(&trans_pcie->imr_waitq);
3650
3651         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3652                                                    WQ_HIGHPRI | WQ_UNBOUND, 0);
3653         if (!trans_pcie->rba.alloc_wq) {
3654                 ret = -ENOMEM;
3655                 goto out_free_trans;
3656         }
3657         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3658
3659         trans_pcie->debug_rfkill = -1;
3660
3661         if (!cfg_trans->base_params->pcie_l1_allowed) {
3662                 /*
3663                  * W/A - seems to solve weird behavior. We need to remove this
3664                  * if we don't want to stay in L1 all the time. This wastes a
3665                  * lot of power.
3666                  */
3667                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3668                                        PCIE_LINK_STATE_L1 |
3669                                        PCIE_LINK_STATE_CLKPM);
3670         }
3671
3672         pci_set_master(pdev);
3673
3674         addr_size = trans->txqs.tfd.addr_size;
3675         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
3676         if (ret) {
3677                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3678                 /* both attempts failed: */
3679                 if (ret) {
3680                         dev_err(&pdev->dev, "No suitable DMA available\n");
3681                         goto out_no_pci;
3682                 }
3683         }
3684
3685         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3686         if (ret) {
3687                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3688                 goto out_no_pci;
3689         }
3690
3691         table = pcim_iomap_table(pdev);
3692         if (!table) {
3693                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3694                 ret = -ENOMEM;
3695                 goto out_no_pci;
3696         }
3697
3698         trans_pcie->hw_base = table[0];
3699         if (!trans_pcie->hw_base) {
3700                 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
3701                 ret = -ENODEV;
3702                 goto out_no_pci;
3703         }
3704
3705         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3706          * PCI Tx retries from interfering with C3 CPU state */
3707         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3708
3709         trans_pcie->pci_dev = pdev;
3710         iwl_disable_interrupts(trans);
3711
3712         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3713         if (trans->hw_rev == 0xffffffff) {
3714                 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3715                 ret = -EIO;
3716                 goto out_no_pci;
3717         }
3718
3719         /*
3720          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3721          * changed, and now the revision step also includes bit 0-1 (no more
3722          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3723          * in the old format.
3724          */
3725         if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
3726                 trans->hw_rev_step = trans->hw_rev & 0xF;
3727         else
3728                 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2;
3729
3730         IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3731
3732         iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3733         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3734         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3735                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3736
3737         init_waitqueue_head(&trans_pcie->sx_waitq);
3738
3739         ret = iwl_pcie_alloc_invalid_tx_cmd(trans);
3740         if (ret)
3741                 goto out_no_pci;
3742
3743         if (trans_pcie->msix_enabled) {
3744                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3745                 if (ret)
3746                         goto out_no_pci;
3747          } else {
3748                 ret = iwl_pcie_alloc_ict(trans);
3749                 if (ret)
3750                         goto out_no_pci;
3751
3752                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3753                                                 iwl_pcie_isr,
3754                                                 iwl_pcie_irq_handler,
3755                                                 IRQF_SHARED, DRV_NAME, trans);
3756                 if (ret) {
3757                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3758                         goto out_free_ict;
3759                 }
3760          }
3761
3762 #ifdef CONFIG_IWLWIFI_DEBUGFS
3763         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3764         mutex_init(&trans_pcie->fw_mon_data.mutex);
3765 #endif
3766
3767         iwl_dbg_tlv_init(trans);
3768
3769         return trans;
3770
3771 out_free_ict:
3772         iwl_pcie_free_ict(trans);
3773 out_no_pci:
3774         destroy_workqueue(trans_pcie->rba.alloc_wq);
3775 out_free_trans:
3776         iwl_trans_free(trans);
3777         return ERR_PTR(ret);
3778 }
3779
3780 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
3781                                 u32 dst_addr, u64 src_addr, u32 byte_cnt)
3782 {
3783         iwl_write_prph(trans, IMR_UREG_CHICK,
3784                        iwl_read_prph(trans, IMR_UREG_CHICK) |
3785                        IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
3786         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
3787         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
3788                        (u32)(src_addr & 0xFFFFFFFF));
3789         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
3790                        iwl_get_dma_hi_addr(src_addr));
3791         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
3792         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
3793                        IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
3794                        IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
3795                        IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
3796 }
3797
3798 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
3799                             u32 dst_addr, u64 src_addr, u32 byte_cnt)
3800 {
3801         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3802         int ret = -1;
3803
3804         trans_pcie->imr_status = IMR_D2S_REQUESTED;
3805         iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);
3806         ret = wait_event_timeout(trans_pcie->imr_waitq,
3807                                  trans_pcie->imr_status !=
3808                                  IMR_D2S_REQUESTED, 5 * HZ);
3809         if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) {
3810                 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");
3811                 iwl_trans_pcie_dump_regs(trans);
3812                 return -ETIMEDOUT;
3813         }
3814         trans_pcie->imr_status = IMR_D2S_IDLE;
3815         return 0;
3816 }