1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
38 * All rights reserved.
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
78 #include "iwl-trans.h"
82 #include "iwl-agn-hw.h"
83 #include "fw/error-dump.h"
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
91 static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
93 #define PCI_DUMP_SIZE 64
95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
96 struct pci_dev *pdev = trans_pcie->pci_dev;
97 u32 i, pos, alloc_size, *ptr, *buf;
100 if (trans_pcie->pcie_dbg_dumped_once)
103 /* Should be a multiple of 4 */
104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
105 /* Alloc a max size buffer */
106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE)
107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;
109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
110 buf = kmalloc(alloc_size, GFP_ATOMIC);
113 prefix = (char *)buf + alloc_size - PREFIX_LEN;
115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
117 /* Print wifi device registers */
118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
119 IWL_ERR(trans, "iwlwifi device config registers:\n");
120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
121 if (pci_read_config_dword(pdev, i, ptr))
123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
127 *ptr = iwl_read32(trans, i);
128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
134 if (pci_read_config_dword(pdev, pos + i, ptr))
136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
140 /* Print parent device registers next */
141 if (!pdev->bus->self)
144 pdev = pdev->bus->self;
145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
150 if (pci_read_config_dword(pdev, i, ptr))
152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
154 /* Print root port AER registers */
156 pdev = pcie_find_root_port(pdev);
158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
164 if (pci_read_config_dword(pdev, pos + i, ptr))
166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
171 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
172 IWL_ERR(trans, "Read failed at 0x%X\n", i);
174 trans_pcie->pcie_dbg_dumped_once = 1;
178 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
180 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
182 if (!trans_pcie->fw_mon_page)
185 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
186 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
187 __free_pages(trans_pcie->fw_mon_page,
188 get_order(trans_pcie->fw_mon_size));
189 trans_pcie->fw_mon_page = NULL;
190 trans_pcie->fw_mon_phys = 0;
191 trans_pcie->fw_mon_size = 0;
194 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
196 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
197 struct page *page = NULL;
203 /* default max_power is maximum */
209 if (WARN(max_power > 26,
210 "External buffer size for monitor is too big %d, check the FW TLV\n",
214 if (trans_pcie->fw_mon_page) {
215 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
216 trans_pcie->fw_mon_size,
222 for (power = max_power; power >= 11; power--) {
226 order = get_order(size);
227 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
232 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
234 if (dma_mapping_error(trans->dev, phys)) {
235 __free_pages(page, order);
240 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
245 if (WARN_ON_ONCE(!page))
248 if (power != max_power)
250 "Sorry - debug buffer is only %luK while you requested %luK\n",
251 (unsigned long)BIT(power - 10),
252 (unsigned long)BIT(max_power - 10));
254 trans_pcie->fw_mon_page = page;
255 trans_pcie->fw_mon_phys = phys;
256 trans_pcie->fw_mon_size = size;
259 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
261 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
262 ((reg & 0x0000ffff) | (2 << 28)));
263 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
266 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
268 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
269 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
270 ((reg & 0x0000ffff) | (3 << 28)));
273 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
275 if (trans->cfg->apmg_not_supported)
278 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
279 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
280 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
281 ~APMG_PS_CTRL_MSK_PWR_SRC);
283 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
284 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
285 ~APMG_PS_CTRL_MSK_PWR_SRC);
289 #define PCI_CFG_RETRY_TIMEOUT 0x041
291 void iwl_pcie_apm_config(struct iwl_trans *trans)
293 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
298 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
299 * Check if BIOS (or OS) enabled L1-ASPM on this device.
300 * If so (likely), disable L0S, so device moves directly L0->L1;
301 * costs negligible amount of power savings.
302 * If not (unlikely), enable L0S, so there is at least some
303 * power savings, even without L1.
305 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
306 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
307 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
309 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
310 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
312 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
313 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
314 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
315 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
316 trans->ltr_enabled ? "En" : "Dis");
320 * Start up NIC's basic functionality after it has been reset
321 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
322 * NOTE: This does not load uCode nor start the embedded processor
324 static int iwl_pcie_apm_init(struct iwl_trans *trans)
328 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
331 * Use "set_bit" below rather than "write", to preserve any hardware
332 * bits already set by default after reset.
335 /* Disable L0S exit timer (platform NMI Work/Around) */
336 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
337 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
338 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
341 * Disable L0s without affecting L1;
342 * don't wait for ICH L0s (ICH bug W/A)
344 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
345 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
347 /* Set FH wait threshold to maximum (HW error during stress W/A) */
348 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
351 * Enable HAP INTA (interrupt from management bus) to
352 * wake device's PCI Express link L1a -> L0s
354 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
355 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
357 iwl_pcie_apm_config(trans);
359 /* Configure analog phase-lock-loop before activating to D0A */
360 if (trans->cfg->base_params->pll_cfg)
361 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
364 * Set "initialization complete" bit to move adapter from
365 * D0U* --> D0A* (powered-up active) state.
367 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370 * Wait for clock stabilization; once stabilized, access to
371 * device-internal resources is supported, e.g. iwl_write_prph()
372 * and accesses to uCode SRAM.
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
378 IWL_ERR(trans, "Failed to init the card\n");
382 if (trans->cfg->host_interrupt_operation_mode) {
384 * This is a bit of an abuse - This is needed for 7260 / 3160
385 * only check host_interrupt_operation_mode even if this is
386 * not related to host_interrupt_operation_mode.
388 * Enable the oscillator to count wake up time for L1 exit. This
389 * consumes slightly more power (100uA) - but allows to be sure
390 * that we wake up from L1 on time.
392 * This looks weird: read twice the same register, discard the
393 * value, set a bit, and yet again, read that same register
394 * just to discard the value. But that's the way the hardware
397 iwl_read_prph(trans, OSC_CLK);
398 iwl_read_prph(trans, OSC_CLK);
399 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
400 iwl_read_prph(trans, OSC_CLK);
401 iwl_read_prph(trans, OSC_CLK);
405 * Enable DMA clock and wait for it to stabilize.
407 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
408 * bits do not disable clocks. This preserves any hardware
409 * bits already set by default in "CLK_CTRL_REG" after reset.
411 if (!trans->cfg->apmg_not_supported) {
412 iwl_write_prph(trans, APMG_CLK_EN_REG,
413 APMG_CLK_VAL_DMA_CLK_RQT);
416 /* Disable L1-Active */
417 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
418 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
420 /* Clear the interrupt in APMG if the NIC is in RFKILL */
421 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
422 APMG_RTC_INT_STT_RFKILL);
425 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
431 * Enable LP XTAL to avoid HW bug where device may consume much power if
432 * FW is not loaded after device reset. LP XTAL is disabled by default
433 * after device HW reset. Do it only if XTAL is fed by internal source.
434 * Configure device's "persistence" mode to avoid resetting XTAL again when
435 * SHRD_HW_RST occurs in S3.
437 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
441 u32 apmg_xtal_cfg_reg;
445 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
446 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
448 iwl_pcie_sw_reset(trans);
451 * Set "initialization complete" bit to move adapter from
452 * D0U* --> D0A* (powered-up active) state.
454 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
457 * Wait for clock stabilization; once stabilized, access to
458 * device-internal resources is possible.
460 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
461 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
462 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
464 if (WARN_ON(ret < 0)) {
465 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
466 /* Release XTAL ON request */
467 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
468 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
473 * Clear "disable persistence" to avoid LP XTAL resetting when
474 * SHRD_HW_RST is applied in S3.
476 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
477 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
480 * Force APMG XTAL to be active to prevent its disabling by HW
481 * caused by APMG idle state.
483 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
484 SHR_APMG_XTAL_CFG_REG);
485 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
487 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
489 iwl_pcie_sw_reset(trans);
491 /* Enable LP XTAL by indirect access through CSR */
492 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
493 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
494 SHR_APMG_GP1_WF_XTAL_LP_EN |
495 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
497 /* Clear delay line clock power up */
498 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
499 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
500 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
503 * Enable persistence mode to avoid LP XTAL resetting when
504 * SHRD_HW_RST is applied in S3.
506 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
507 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
510 * Clear "initialization complete" bit to move adapter from
511 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
513 iwl_clear_bit(trans, CSR_GP_CNTRL,
514 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
516 /* Activates XTAL resources monitor */
517 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
518 CSR_MONITOR_XTAL_RESOURCES);
520 /* Release XTAL ON request */
521 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
522 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
525 /* Release APMG XTAL */
526 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
528 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
531 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
535 /* stop device's busmaster DMA activity */
536 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
538 ret = iwl_poll_bit(trans, CSR_RESET,
539 CSR_RESET_REG_FLAG_MASTER_DISABLED,
540 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
542 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
544 IWL_DEBUG_INFO(trans, "stop master\n");
547 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
549 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
552 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
553 iwl_pcie_apm_init(trans);
555 /* inform ME that we are leaving */
556 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
557 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
558 APMG_PCIDEV_STT_VAL_WAKE_ME);
559 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
560 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
561 CSR_RESET_LINK_PWR_MGMT_DISABLED);
562 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
563 CSR_HW_IF_CONFIG_REG_PREPARE |
564 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
566 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
567 CSR_RESET_LINK_PWR_MGMT_DISABLED);
572 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
574 /* Stop device's DMA activity */
575 iwl_pcie_apm_stop_master(trans);
577 if (trans->cfg->lp_xtal_workaround) {
578 iwl_pcie_apm_lp_xtal_enable(trans);
582 iwl_pcie_sw_reset(trans);
585 * Clear "initialization complete" bit to move adapter from
586 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
588 iwl_clear_bit(trans, CSR_GP_CNTRL,
589 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
592 static int iwl_pcie_nic_init(struct iwl_trans *trans)
594 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
598 spin_lock(&trans_pcie->irq_lock);
599 ret = iwl_pcie_apm_init(trans);
600 spin_unlock(&trans_pcie->irq_lock);
605 iwl_pcie_set_pwr(trans, false);
607 iwl_op_mode_nic_config(trans->op_mode);
609 /* Allocate the RX queue, or reset if it is already allocated */
610 iwl_pcie_rx_init(trans);
612 /* Allocate or reset and init all Tx and Command queues */
613 if (iwl_pcie_tx_init(trans))
616 if (trans->cfg->base_params->shadow_reg_enable) {
617 /* enable shadow regs in HW */
618 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
619 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
625 #define HW_READY_TIMEOUT (50)
627 /* Note: returns poll_bit return value, which is >= 0 if success */
628 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
632 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
633 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
635 /* See if we got it */
636 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
637 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
638 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
642 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
644 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
648 /* Note: returns standard 0/-ERROR code */
649 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
655 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
657 ret = iwl_pcie_set_hw_ready(trans);
658 /* If the card is ready, exit 0 */
662 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
663 CSR_RESET_LINK_PWR_MGMT_DISABLED);
664 usleep_range(1000, 2000);
666 for (iter = 0; iter < 10; iter++) {
667 /* If HW is not ready, prepare the conditions to check again */
668 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
669 CSR_HW_IF_CONFIG_REG_PREPARE);
672 ret = iwl_pcie_set_hw_ready(trans);
676 usleep_range(200, 1000);
678 } while (t < 150000);
682 IWL_ERR(trans, "Couldn't prepare the card\n");
690 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
691 u32 dst_addr, dma_addr_t phy_addr,
694 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
695 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
697 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
700 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
701 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
703 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
704 (iwl_get_dma_hi_addr(phy_addr)
705 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
707 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
708 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
709 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
710 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
712 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
713 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
714 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
715 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
718 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
719 u32 dst_addr, dma_addr_t phy_addr,
722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
726 trans_pcie->ucode_write_complete = false;
728 if (!iwl_trans_grab_nic_access(trans, &flags))
731 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
733 iwl_trans_release_nic_access(trans, &flags);
735 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
736 trans_pcie->ucode_write_complete, 5 * HZ);
738 IWL_ERR(trans, "Failed to load firmware chunk!\n");
739 iwl_trans_pcie_dump_regs(trans);
746 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
747 const struct fw_desc *section)
751 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
754 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
757 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
758 GFP_KERNEL | __GFP_NOWARN);
760 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
761 chunk_sz = PAGE_SIZE;
762 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
763 &p_addr, GFP_KERNEL);
768 for (offset = 0; offset < section->len; offset += chunk_sz) {
769 u32 copy_size, dst_addr;
770 bool extended_addr = false;
772 copy_size = min_t(u32, chunk_sz, section->len - offset);
773 dst_addr = section->offset + offset;
775 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
776 dst_addr <= IWL_FW_MEM_EXTENDED_END)
777 extended_addr = true;
780 iwl_set_bits_prph(trans, LMPM_CHICK,
781 LMPM_CHICK_EXTENDED_ADDR_SPACE);
783 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
784 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
788 iwl_clear_bits_prph(trans, LMPM_CHICK,
789 LMPM_CHICK_EXTENDED_ADDR_SPACE);
793 "Could not load the [%d] uCode section\n",
799 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
803 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
804 const struct fw_img *image,
806 int *first_ucode_section)
809 int i, ret = 0, sec_num = 0x1;
810 u32 val, last_read_idx = 0;
814 *first_ucode_section = 0;
817 (*first_ucode_section)++;
820 for (i = *first_ucode_section; i < image->num_sec; i++) {
824 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
826 * PAGING_SEPARATOR_SECTION delimiter - separate between
827 * CPU2 non paged to CPU2 paging sec.
829 if (!image->sec[i].data ||
830 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
831 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
833 "Break since Data not valid or Empty section, sec = %d\n",
838 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
842 /* Notify ucode of loaded section number and status */
843 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
844 val = val | (sec_num << shift_param);
845 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
847 sec_num = (sec_num << 1) | 0x1;
850 *first_ucode_section = last_read_idx;
852 iwl_enable_interrupts(trans);
854 if (trans->cfg->use_tfh) {
856 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
859 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
863 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
866 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
873 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
874 const struct fw_img *image,
876 int *first_ucode_section)
879 u32 last_read_idx = 0;
882 *first_ucode_section = 0;
884 (*first_ucode_section)++;
886 for (i = *first_ucode_section; i < image->num_sec; i++) {
890 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
892 * PAGING_SEPARATOR_SECTION delimiter - separate between
893 * CPU2 non paged to CPU2 paging sec.
895 if (!image->sec[i].data ||
896 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
897 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
899 "Break since Data not valid or Empty section, sec = %d\n",
904 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
909 *first_ucode_section = last_read_idx;
914 void iwl_pcie_apply_destination(struct iwl_trans *trans)
916 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
917 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
922 "DBG DEST version is %d - expect issues\n",
925 IWL_INFO(trans, "Applying debug destination %s\n",
926 get_fw_dbg_mode_string(dest->monitor_mode));
928 if (dest->monitor_mode == EXTERNAL_MODE)
929 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
931 IWL_WARN(trans, "PCI should have external buffer debug\n");
933 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
934 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
935 u32 val = le32_to_cpu(dest->reg_ops[i].val);
937 switch (dest->reg_ops[i].op) {
939 iwl_write32(trans, addr, val);
942 iwl_set_bit(trans, addr, BIT(val));
945 iwl_clear_bit(trans, addr, BIT(val));
948 iwl_write_prph(trans, addr, val);
951 iwl_set_bits_prph(trans, addr, BIT(val));
954 iwl_clear_bits_prph(trans, addr, BIT(val));
957 if (iwl_read_prph(trans, addr) & BIT(val)) {
959 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
965 IWL_ERR(trans, "FW debug - unknown OP %d\n",
966 dest->reg_ops[i].op);
972 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
973 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
974 trans_pcie->fw_mon_phys >> dest->base_shift);
975 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
976 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
977 (trans_pcie->fw_mon_phys +
978 trans_pcie->fw_mon_size - 256) >>
981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
982 (trans_pcie->fw_mon_phys +
983 trans_pcie->fw_mon_size) >>
988 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
989 const struct fw_img *image)
991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
993 int first_ucode_section;
995 IWL_DEBUG_FW(trans, "working with %s CPU\n",
996 image->is_dual_cpus ? "Dual" : "Single");
998 /* load to FW the binary non secured sections of CPU1 */
999 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1003 if (image->is_dual_cpus) {
1004 /* set CPU2 header address */
1005 iwl_write_prph(trans,
1006 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1007 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1009 /* load to FW the binary sections of CPU2 */
1010 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1011 &first_ucode_section);
1016 /* supported for 7000 only for the moment */
1017 if (iwlwifi_mod_params.fw_monitor &&
1018 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1019 iwl_pcie_alloc_fw_monitor(trans, 0);
1021 if (trans_pcie->fw_mon_size) {
1022 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1023 trans_pcie->fw_mon_phys >> 4);
1024 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1025 (trans_pcie->fw_mon_phys +
1026 trans_pcie->fw_mon_size) >> 4);
1028 } else if (trans->dbg_dest_tlv) {
1029 iwl_pcie_apply_destination(trans);
1032 iwl_enable_interrupts(trans);
1034 /* release CPU reset */
1035 iwl_write32(trans, CSR_RESET, 0);
1040 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1041 const struct fw_img *image)
1044 int first_ucode_section;
1046 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1047 image->is_dual_cpus ? "Dual" : "Single");
1049 if (trans->dbg_dest_tlv)
1050 iwl_pcie_apply_destination(trans);
1052 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1053 iwl_read_prph(trans, WFPM_GP2));
1056 * Set default value. On resume reading the values that were
1057 * zeored can provide debug data on the resume flow.
1058 * This is for debugging only and has no functional impact.
1060 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1062 /* configure the ucode to be ready to get the secured image */
1063 /* release CPU reset */
1064 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1066 /* load to FW the binary Secured sections of CPU1 */
1067 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1068 &first_ucode_section);
1072 /* load to FW the binary sections of CPU2 */
1073 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1074 &first_ucode_section);
1077 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1079 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1080 bool hw_rfkill = iwl_is_rfkill_set(trans);
1081 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1085 set_bit(STATUS_RFKILL_HW, &trans->status);
1086 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1088 clear_bit(STATUS_RFKILL_HW, &trans->status);
1089 if (trans_pcie->opmode_down)
1090 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1093 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1096 iwl_trans_pcie_rf_kill(trans, report);
1101 struct iwl_causes_list {
1107 static struct iwl_causes_list causes_list[] = {
1108 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1109 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1110 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1111 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1112 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1113 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1114 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1115 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1116 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1117 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1118 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1119 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1120 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1121 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1124 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1126 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1127 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1131 * Access all non RX causes and map them to the default irq.
1132 * In case we are missing at least one interrupt vector,
1133 * the first interrupt vector will serve non-RX and FBQ causes.
1135 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1136 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1137 iwl_clear_bit(trans, causes_list[i].mask_reg,
1138 causes_list[i].cause_num);
1142 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1146 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1150 * The first RX queue - fallback queue, which is designated for
1151 * management frame, command responses etc, is always mapped to the
1152 * first interrupt vector. The other RX queues are mapped to
1153 * the other (N - 2) interrupt vectors.
1155 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1156 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1157 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1158 MSIX_FH_INT_CAUSES_Q(idx - offset));
1159 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1161 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1163 val = MSIX_FH_INT_CAUSES_Q(0);
1164 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1165 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1166 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1168 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1169 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1172 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1174 struct iwl_trans *trans = trans_pcie->trans;
1176 if (!trans_pcie->msix_enabled) {
1177 if (trans->cfg->mq_rx_supported &&
1178 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1179 iwl_write_prph(trans, UREG_CHICK,
1180 UREG_CHICK_MSI_ENABLE);
1184 * The IVAR table needs to be configured again after reset,
1185 * but if the device is disabled, we can't write to
1188 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1189 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1192 * Each cause from the causes list above and the RX causes is
1193 * represented as a byte in the IVAR table. The first nibble
1194 * represents the bound interrupt vector of the cause, the second
1195 * represents no auto clear for this cause. This will be set if its
1196 * interrupt vector is bound to serve other causes.
1198 iwl_pcie_map_rx_causes(trans);
1200 iwl_pcie_map_non_rx_causes(trans);
1203 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1205 struct iwl_trans *trans = trans_pcie->trans;
1207 iwl_pcie_conf_msix_hw(trans_pcie);
1209 if (!trans_pcie->msix_enabled)
1212 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1213 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1214 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1215 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1218 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1222 lockdep_assert_held(&trans_pcie->mutex);
1224 if (trans_pcie->is_down)
1227 trans_pcie->is_down = true;
1229 /* tell the device to stop sending interrupts */
1230 iwl_disable_interrupts(trans);
1232 /* device going down, Stop using ICT table */
1233 iwl_pcie_disable_ict(trans);
1236 * If a HW restart happens during firmware loading,
1237 * then the firmware loading might call this function
1238 * and later it might be called again due to the
1239 * restart. So don't process again if the device is
1242 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1243 IWL_DEBUG_INFO(trans,
1244 "DEVICE_ENABLED bit was set and is now cleared\n");
1245 iwl_pcie_tx_stop(trans);
1246 iwl_pcie_rx_stop(trans);
1248 /* Power-down device's busmaster DMA clocks */
1249 if (!trans->cfg->apmg_not_supported) {
1250 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1251 APMG_CLK_VAL_DMA_CLK_RQT);
1256 /* Make sure (redundant) we've released our request to stay awake */
1257 iwl_clear_bit(trans, CSR_GP_CNTRL,
1258 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1260 /* Stop the device, and put it in low power state */
1261 iwl_pcie_apm_stop(trans, false);
1263 iwl_pcie_sw_reset(trans);
1266 * Upon stop, the IVAR table gets erased, so msi-x won't
1267 * work. This causes a bug in RF-KILL flows, since the interrupt
1268 * that enables radio won't fire on the correct irq, and the
1269 * driver won't be able to handle the interrupt.
1270 * Configure the IVAR table again after reset.
1272 iwl_pcie_conf_msix_hw(trans_pcie);
1275 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1276 * This is a bug in certain verions of the hardware.
1277 * Certain devices also keep sending HW RF kill interrupt all
1278 * the time, unless the interrupt is ACKed even if the interrupt
1279 * should be masked. Re-ACK all the interrupts here.
1281 iwl_disable_interrupts(trans);
1283 /* clear all status bits */
1284 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1285 clear_bit(STATUS_INT_ENABLED, &trans->status);
1286 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1289 * Even if we stop the HW, we still want the RF kill
1292 iwl_enable_rfkill_int(trans);
1294 /* re-take ownership to prevent other users from stealing the device */
1295 iwl_pcie_prepare_card_hw(trans);
1298 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1302 if (trans_pcie->msix_enabled) {
1305 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1306 synchronize_irq(trans_pcie->msix_entries[i].vector);
1308 synchronize_irq(trans_pcie->pci_dev->irq);
1312 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1313 const struct fw_img *fw, bool run_in_rfkill)
1315 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1319 /* This may fail if AMT took ownership of the device */
1320 if (iwl_pcie_prepare_card_hw(trans)) {
1321 IWL_WARN(trans, "Exit HW not ready\n");
1326 iwl_enable_rfkill_int(trans);
1328 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1331 * We enabled the RF-Kill interrupt and the handler may very
1332 * well be running. Disable the interrupts to make sure no other
1333 * interrupt can be fired.
1335 iwl_disable_interrupts(trans);
1337 /* Make sure it finished running */
1338 iwl_pcie_synchronize_irqs(trans);
1340 mutex_lock(&trans_pcie->mutex);
1342 /* If platform's RF_KILL switch is NOT set to KILL */
1343 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1344 if (hw_rfkill && !run_in_rfkill) {
1349 /* Someone called stop_device, don't try to start_fw */
1350 if (trans_pcie->is_down) {
1352 "Can't start_fw since the HW hasn't been started\n");
1357 /* make sure rfkill handshake bits are cleared */
1358 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1359 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1360 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1362 /* clear (again), then enable host interrupts */
1363 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1365 ret = iwl_pcie_nic_init(trans);
1367 IWL_ERR(trans, "Unable to init nic\n");
1372 * Now, we load the firmware and don't want to be interrupted, even
1373 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1374 * FH_TX interrupt which is needed to load the firmware). If the
1375 * RF-Kill switch is toggled, we will find out after having loaded
1376 * the firmware and return the proper value to the caller.
1378 iwl_enable_fw_load_int(trans);
1380 /* really make sure rfkill handshake bits are cleared */
1381 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1382 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1384 /* Load the given image to the HW */
1385 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1386 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1388 ret = iwl_pcie_load_given_ucode(trans, fw);
1390 /* re-check RF-Kill state since we may have missed the interrupt */
1391 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1392 if (hw_rfkill && !run_in_rfkill)
1396 mutex_unlock(&trans_pcie->mutex);
1400 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1402 iwl_pcie_reset_ict(trans);
1403 iwl_pcie_tx_start(trans, scd_addr);
1406 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1412 * Check again since the RF kill state may have changed while
1413 * all the interrupts were disabled, in this case we couldn't
1414 * receive the RF kill interrupt and update the state in the
1416 * Don't call the op_mode if the rkfill state hasn't changed.
1417 * This allows the op_mode to call stop_device from the rfkill
1418 * notification without endless recursion. Under very rare
1419 * circumstances, we might have a small recursion if the rfkill
1420 * state changed exactly now while we were called from stop_device.
1421 * This is very unlikely but can happen and is supported.
1423 hw_rfkill = iwl_is_rfkill_set(trans);
1425 set_bit(STATUS_RFKILL_HW, &trans->status);
1426 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1428 clear_bit(STATUS_RFKILL_HW, &trans->status);
1429 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1431 if (hw_rfkill != was_in_rfkill)
1432 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1435 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1437 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1440 mutex_lock(&trans_pcie->mutex);
1441 trans_pcie->opmode_down = true;
1442 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1443 _iwl_trans_pcie_stop_device(trans, low_power);
1444 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1445 mutex_unlock(&trans_pcie->mutex);
1448 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1450 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1451 IWL_TRANS_GET_PCIE_TRANS(trans);
1453 lockdep_assert_held(&trans_pcie->mutex);
1455 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1456 state ? "disabled" : "enabled");
1457 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1458 if (trans->cfg->gen2)
1459 _iwl_trans_pcie_gen2_stop_device(trans, true);
1461 _iwl_trans_pcie_stop_device(trans, true);
1465 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1469 /* Enable persistence mode to avoid reset */
1470 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1471 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1474 iwl_disable_interrupts(trans);
1477 * in testing mode, the host stays awake and the
1478 * hardware won't be reset (not even partially)
1483 iwl_pcie_disable_ict(trans);
1485 iwl_pcie_synchronize_irqs(trans);
1487 iwl_clear_bit(trans, CSR_GP_CNTRL,
1488 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1489 iwl_clear_bit(trans, CSR_GP_CNTRL,
1490 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1492 iwl_pcie_enable_rx_wake(trans, false);
1496 * reset TX queues -- some of their registers reset during S3
1497 * so if we don't reset everything here the D3 image would try
1498 * to execute some invalid memory upon resume
1500 iwl_trans_pcie_tx_reset(trans);
1503 iwl_pcie_set_pwr(trans, true);
1506 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1507 enum iwl_d3_status *status,
1508 bool test, bool reset)
1510 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1515 iwl_enable_interrupts(trans);
1516 *status = IWL_D3_STATUS_ALIVE;
1520 iwl_pcie_enable_rx_wake(trans, true);
1523 * Reconfigure IVAR table in case of MSIX or reset ict table in
1524 * MSI mode since HW reset erased it.
1525 * Also enables interrupts - none will happen as
1526 * the device doesn't know we're waking it up, only when
1527 * the opmode actually tells it after this call.
1529 iwl_pcie_conf_msix_hw(trans_pcie);
1530 if (!trans_pcie->msix_enabled)
1531 iwl_pcie_reset_ict(trans);
1532 iwl_enable_interrupts(trans);
1534 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1535 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1537 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1540 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1541 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1542 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1545 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1549 iwl_pcie_set_pwr(trans, false);
1552 iwl_clear_bit(trans, CSR_GP_CNTRL,
1553 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1555 iwl_trans_pcie_tx_reset(trans);
1557 ret = iwl_pcie_rx_init(trans);
1560 "Failed to resume the device (RX reset)\n");
1565 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1566 iwl_read_prph(trans, WFPM_GP2));
1568 val = iwl_read32(trans, CSR_RESET);
1569 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1570 *status = IWL_D3_STATUS_RESET;
1572 *status = IWL_D3_STATUS_ALIVE;
1577 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1578 struct iwl_trans *trans)
1580 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1581 int max_irqs, num_irqs, i, ret, nr_online_cpus;
1584 if (!trans->cfg->mq_rx_supported)
1587 nr_online_cpus = num_online_cpus();
1588 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
1589 for (i = 0; i < max_irqs; i++)
1590 trans_pcie->msix_entries[i].entry = i;
1592 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1593 MSIX_MIN_INTERRUPT_VECTORS,
1596 IWL_DEBUG_INFO(trans,
1597 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1601 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1603 IWL_DEBUG_INFO(trans,
1604 "MSI-X enabled. %d interrupt vectors were allocated\n",
1608 * In case the OS provides fewer interrupts than requested, different
1609 * causes will share the same interrupt vector as follows:
1610 * One interrupt less: non rx causes shared with FBQ.
1611 * Two interrupts less: non rx causes shared with FBQ and RSS.
1612 * More than two interrupts: we will use fewer RSS queues.
1614 if (num_irqs <= nr_online_cpus) {
1615 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1616 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1617 IWL_SHARED_IRQ_FIRST_RSS;
1618 } else if (num_irqs == nr_online_cpus + 1) {
1619 trans_pcie->trans->num_rx_queues = num_irqs;
1620 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1622 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1625 trans_pcie->alloc_vecs = num_irqs;
1626 trans_pcie->msix_enabled = true;
1630 ret = pci_enable_msi(pdev);
1632 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1633 /* enable rfkill interrupt: hw bug w/a */
1634 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1635 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1636 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1637 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1642 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1644 int iter_rx_q, i, ret, cpu, offset;
1645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1647 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1648 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1650 for (; i < iter_rx_q ; i++) {
1652 * Get the cpu prior to the place to search
1653 * (i.e. return will be > i - 1).
1655 cpu = cpumask_next(i - offset, cpu_online_mask);
1656 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1657 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1658 &trans_pcie->affinity_mask[i]);
1660 IWL_ERR(trans_pcie->trans,
1661 "Failed to set affinity mask for IRQ %d\n",
1666 static const char *queue_name(struct device *dev,
1667 struct iwl_trans_pcie *trans_p, int i)
1669 if (trans_p->shared_vec_mask) {
1670 int vec = trans_p->shared_vec_mask &
1671 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1674 return DRV_NAME ": shared IRQ";
1676 return devm_kasprintf(dev, GFP_KERNEL,
1677 DRV_NAME ": queue %d", i + vec);
1680 return DRV_NAME ": default queue";
1682 if (i == trans_p->alloc_vecs - 1)
1683 return DRV_NAME ": exception";
1685 return devm_kasprintf(dev, GFP_KERNEL,
1686 DRV_NAME ": queue %d", i);
1689 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1690 struct iwl_trans_pcie *trans_pcie)
1694 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1696 struct msix_entry *msix_entry;
1697 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1702 msix_entry = &trans_pcie->msix_entries[i];
1703 ret = devm_request_threaded_irq(&pdev->dev,
1706 (i == trans_pcie->def_irq) ?
1707 iwl_pcie_irq_msix_handler :
1708 iwl_pcie_irq_rx_msix_handler,
1713 IWL_ERR(trans_pcie->trans,
1714 "Error allocating IRQ %d\n", i);
1719 iwl_pcie_irq_set_affinity(trans_pcie->trans);
1724 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1729 lockdep_assert_held(&trans_pcie->mutex);
1731 err = iwl_pcie_prepare_card_hw(trans);
1733 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1737 iwl_pcie_sw_reset(trans);
1739 err = iwl_pcie_apm_init(trans);
1743 iwl_pcie_init_msix(trans_pcie);
1745 /* From now on, the op_mode will be kept updated about RF kill state */
1746 iwl_enable_rfkill_int(trans);
1748 trans_pcie->opmode_down = false;
1750 /* Set is_down to false here so that...*/
1751 trans_pcie->is_down = false;
1753 /* ...rfkill can call stop_device and set it false if needed */
1754 iwl_pcie_check_hw_rf_kill(trans);
1756 /* Make sure we sync here, because we'll need full access later */
1758 pm_runtime_resume(trans->dev);
1763 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1765 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1768 mutex_lock(&trans_pcie->mutex);
1769 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1770 mutex_unlock(&trans_pcie->mutex);
1775 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1777 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1779 mutex_lock(&trans_pcie->mutex);
1781 /* disable interrupts - don't enable HW RF kill interrupt */
1782 iwl_disable_interrupts(trans);
1784 iwl_pcie_apm_stop(trans, true);
1786 iwl_disable_interrupts(trans);
1788 iwl_pcie_disable_ict(trans);
1790 mutex_unlock(&trans_pcie->mutex);
1792 iwl_pcie_synchronize_irqs(trans);
1795 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1797 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1800 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1802 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1805 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1807 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1810 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1812 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1813 ((reg & 0x000FFFFF) | (3 << 24)));
1814 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1817 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1820 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1821 ((addr & 0x000FFFFF) | (3 << 24)));
1822 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1825 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1826 const struct iwl_trans_config *trans_cfg)
1828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1830 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1831 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1832 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1833 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1834 trans_pcie->n_no_reclaim_cmds = 0;
1836 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1837 if (trans_pcie->n_no_reclaim_cmds)
1838 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1839 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1841 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1842 trans_pcie->rx_page_order =
1843 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1845 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1846 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1847 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1849 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1850 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1852 trans->command_groups = trans_cfg->command_groups;
1853 trans->command_groups_size = trans_cfg->command_groups_size;
1855 /* Initialize NAPI here - it should be before registering to mac80211
1856 * in the opmode but after the HW struct is allocated.
1857 * As this function may be called again in some corner cases don't
1858 * do anything if NAPI was already initialized.
1860 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1861 init_dummy_netdev(&trans_pcie->napi_dev);
1864 void iwl_trans_pcie_free(struct iwl_trans *trans)
1866 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1869 iwl_pcie_synchronize_irqs(trans);
1871 if (trans->cfg->gen2)
1872 iwl_pcie_gen2_tx_free(trans);
1874 iwl_pcie_tx_free(trans);
1875 iwl_pcie_rx_free(trans);
1877 if (trans_pcie->rba.alloc_wq) {
1878 destroy_workqueue(trans_pcie->rba.alloc_wq);
1879 trans_pcie->rba.alloc_wq = NULL;
1882 if (trans_pcie->msix_enabled) {
1883 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1884 irq_set_affinity_hint(
1885 trans_pcie->msix_entries[i].vector,
1889 trans_pcie->msix_enabled = false;
1891 iwl_pcie_free_ict(trans);
1894 iwl_pcie_free_fw_monitor(trans);
1896 for_each_possible_cpu(i) {
1897 struct iwl_tso_hdr_page *p =
1898 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1901 __free_page(p->page);
1904 free_percpu(trans_pcie->tso_hdr_page);
1905 mutex_destroy(&trans_pcie->mutex);
1906 iwl_trans_free(trans);
1909 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1912 set_bit(STATUS_TPOWER_PMI, &trans->status);
1914 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1917 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1918 unsigned long *flags)
1921 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1923 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1925 if (trans_pcie->cmd_hold_nic_awake)
1928 /* this bit wakes up the NIC */
1929 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1930 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1931 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1935 * These bits say the device is running, and should keep running for
1936 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1937 * but they do not indicate that embedded SRAM is restored yet;
1938 * HW with volatile SRAM must save/restore contents to/from
1939 * host DRAM when sleeping/waking for power-saving.
1940 * Each direction takes approximately 1/4 millisecond; with this
1941 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1942 * series of register accesses are expected (e.g. reading Event Log),
1943 * to keep device from sleeping.
1945 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1946 * SRAM is okay/restored. We don't check that here because this call
1947 * is just for hardware register access; but GP1 MAC_SLEEP
1948 * check is a good idea before accessing the SRAM of HW with
1949 * volatile SRAM (e.g. reading Event Log).
1951 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1952 * and do not save/restore SRAM when power cycling.
1954 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1955 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1956 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1957 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1958 if (unlikely(ret < 0)) {
1959 iwl_trans_pcie_dump_regs(trans);
1960 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1962 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1963 iwl_read32(trans, CSR_GP_CNTRL));
1964 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1970 * Fool sparse by faking we release the lock - sparse will
1971 * track nic_access anyway.
1973 __release(&trans_pcie->reg_lock);
1977 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1978 unsigned long *flags)
1980 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1982 lockdep_assert_held(&trans_pcie->reg_lock);
1985 * Fool sparse by faking we acquiring the lock - sparse will
1986 * track nic_access anyway.
1988 __acquire(&trans_pcie->reg_lock);
1990 if (trans_pcie->cmd_hold_nic_awake)
1993 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1994 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1996 * Above we read the CSR_GP_CNTRL register, which will flush
1997 * any previous writes, but we need the write that clears the
1998 * MAC_ACCESS_REQ bit to be performed before any other writes
1999 * scheduled on different CPUs (after we drop reg_lock).
2003 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2006 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2007 void *buf, int dwords)
2009 unsigned long flags;
2013 if (iwl_trans_grab_nic_access(trans, &flags)) {
2014 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2015 for (offs = 0; offs < dwords; offs++)
2016 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2017 iwl_trans_release_nic_access(trans, &flags);
2024 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2025 const void *buf, int dwords)
2027 unsigned long flags;
2029 const u32 *vals = buf;
2031 if (iwl_trans_grab_nic_access(trans, &flags)) {
2032 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2033 for (offs = 0; offs < dwords; offs++)
2034 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2035 vals ? vals[offs] : 0);
2036 iwl_trans_release_nic_access(trans, &flags);
2043 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2047 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2050 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2051 struct iwl_txq *txq = trans_pcie->txq[queue];
2054 spin_lock_bh(&txq->lock);
2058 if (txq->frozen == freeze)
2061 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2062 freeze ? "Freezing" : "Waking", queue);
2064 txq->frozen = freeze;
2066 if (txq->read_ptr == txq->write_ptr)
2070 if (unlikely(time_after(now,
2071 txq->stuck_timer.expires))) {
2073 * The timer should have fired, maybe it is
2074 * spinning right now on the lock.
2078 /* remember how long until the timer fires */
2079 txq->frozen_expiry_remainder =
2080 txq->stuck_timer.expires - now;
2081 del_timer(&txq->stuck_timer);
2086 * Wake a non-empty queue -> arm timer with the
2087 * remainder before it froze
2089 mod_timer(&txq->stuck_timer,
2090 now + txq->frozen_expiry_remainder);
2093 spin_unlock_bh(&txq->lock);
2097 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2099 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2102 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2103 struct iwl_txq *txq = trans_pcie->txq[i];
2105 if (i == trans_pcie->cmd_queue)
2108 spin_lock_bh(&txq->lock);
2110 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2113 iwl_write32(trans, HBUS_TARG_WRPTR,
2114 txq->write_ptr | (i << 8));
2120 spin_unlock_bh(&txq->lock);
2124 #define IWL_FLUSH_WAIT_MS 2000
2126 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2128 u32 txq_id = txq->id;
2133 if (trans->cfg->use_tfh) {
2134 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2135 txq->read_ptr, txq->write_ptr);
2136 /* TODO: access new SCD registers and dump them */
2140 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2141 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2142 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2145 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2146 txq_id, active ? "" : "in", fifo,
2147 jiffies_to_msecs(txq->wd_timeout),
2148 txq->read_ptr, txq->write_ptr,
2149 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2150 (TFD_QUEUE_SIZE_MAX - 1),
2151 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2152 (TFD_QUEUE_SIZE_MAX - 1),
2153 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2156 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2158 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2159 struct iwl_txq *txq;
2160 unsigned long now = jiffies;
2163 if (!test_bit(txq_idx, trans_pcie->queue_used))
2166 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2167 txq = trans_pcie->txq[txq_idx];
2168 wr_ptr = READ_ONCE(txq->write_ptr);
2170 while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
2171 !time_after(jiffies,
2172 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2173 u8 write_ptr = READ_ONCE(txq->write_ptr);
2175 if (WARN_ONCE(wr_ptr != write_ptr,
2176 "WR pointer moved while flushing %d -> %d\n",
2179 usleep_range(1000, 2000);
2182 if (txq->read_ptr != txq->write_ptr) {
2184 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2185 iwl_trans_pcie_log_scd_error(trans, txq);
2189 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2194 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2196 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2200 /* waiting for all the tx frames complete might take a while */
2201 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2203 if (cnt == trans_pcie->cmd_queue)
2205 if (!test_bit(cnt, trans_pcie->queue_used))
2207 if (!(BIT(cnt) & txq_bm))
2210 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2218 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2219 u32 mask, u32 value)
2221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2222 unsigned long flags;
2224 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2225 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2226 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2229 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2231 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2233 if (iwlwifi_mod_params.d0i3_disable)
2236 pm_runtime_get(&trans_pcie->pci_dev->dev);
2239 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2240 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2241 #endif /* CONFIG_PM */
2244 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2246 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2248 if (iwlwifi_mod_params.d0i3_disable)
2251 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2252 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2255 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2256 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2257 #endif /* CONFIG_PM */
2260 static const char *get_csr_string(int cmd)
2262 #define IWL_CMD(x) case x: return #x
2264 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2265 IWL_CMD(CSR_INT_COALESCING);
2267 IWL_CMD(CSR_INT_MASK);
2268 IWL_CMD(CSR_FH_INT_STATUS);
2269 IWL_CMD(CSR_GPIO_IN);
2271 IWL_CMD(CSR_GP_CNTRL);
2272 IWL_CMD(CSR_HW_REV);
2273 IWL_CMD(CSR_EEPROM_REG);
2274 IWL_CMD(CSR_EEPROM_GP);
2275 IWL_CMD(CSR_OTP_GP_REG);
2276 IWL_CMD(CSR_GIO_REG);
2277 IWL_CMD(CSR_GP_UCODE_REG);
2278 IWL_CMD(CSR_GP_DRIVER_REG);
2279 IWL_CMD(CSR_UCODE_DRV_GP1);
2280 IWL_CMD(CSR_UCODE_DRV_GP2);
2281 IWL_CMD(CSR_LED_REG);
2282 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2283 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2284 IWL_CMD(CSR_ANA_PLL_CFG);
2285 IWL_CMD(CSR_HW_REV_WA_REG);
2286 IWL_CMD(CSR_MONITOR_STATUS_REG);
2287 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2294 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2297 static const u32 csr_tbl[] = {
2298 CSR_HW_IF_CONFIG_REG,
2316 CSR_DRAM_INT_TBL_REG,
2317 CSR_GIO_CHICKEN_BITS,
2319 CSR_MONITOR_STATUS_REG,
2321 CSR_DBG_HPET_MEM_REG
2323 IWL_ERR(trans, "CSR values:\n");
2324 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2325 "CSR_INT_PERIODIC_REG)\n");
2326 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2327 IWL_ERR(trans, " %25s: 0X%08x\n",
2328 get_csr_string(csr_tbl[i]),
2329 iwl_read32(trans, csr_tbl[i]));
2333 #ifdef CONFIG_IWLWIFI_DEBUGFS
2334 /* create and remove of files */
2335 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2336 if (!debugfs_create_file(#name, mode, parent, trans, \
2337 &iwl_dbgfs_##name##_ops)) \
2341 /* file operation */
2342 #define DEBUGFS_READ_FILE_OPS(name) \
2343 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2344 .read = iwl_dbgfs_##name##_read, \
2345 .open = simple_open, \
2346 .llseek = generic_file_llseek, \
2349 #define DEBUGFS_WRITE_FILE_OPS(name) \
2350 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2351 .write = iwl_dbgfs_##name##_write, \
2352 .open = simple_open, \
2353 .llseek = generic_file_llseek, \
2356 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2357 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2358 .write = iwl_dbgfs_##name##_write, \
2359 .read = iwl_dbgfs_##name##_read, \
2360 .open = simple_open, \
2361 .llseek = generic_file_llseek, \
2364 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2365 char __user *user_buf,
2366 size_t count, loff_t *ppos)
2368 struct iwl_trans *trans = file->private_data;
2369 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2370 struct iwl_txq *txq;
2377 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2379 if (!trans_pcie->txq_memory)
2382 buf = kzalloc(bufsz, GFP_KERNEL);
2386 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2387 txq = trans_pcie->txq[cnt];
2388 pos += scnprintf(buf + pos, bufsz - pos,
2389 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2390 cnt, txq->read_ptr, txq->write_ptr,
2391 !!test_bit(cnt, trans_pcie->queue_used),
2392 !!test_bit(cnt, trans_pcie->queue_stopped),
2393 txq->need_update, txq->frozen,
2394 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2396 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2401 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2402 char __user *user_buf,
2403 size_t count, loff_t *ppos)
2405 struct iwl_trans *trans = file->private_data;
2406 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2408 int pos = 0, i, ret;
2409 size_t bufsz = sizeof(buf);
2411 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2413 if (!trans_pcie->rxq)
2416 buf = kzalloc(bufsz, GFP_KERNEL);
2420 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2421 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2423 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2425 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2427 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2429 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2431 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2433 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2436 pos += scnprintf(buf + pos, bufsz - pos,
2437 "\tclosed_rb_num: %u\n",
2438 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2441 pos += scnprintf(buf + pos, bufsz - pos,
2442 "\tclosed_rb_num: Not Allocated\n");
2445 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2451 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2452 char __user *user_buf,
2453 size_t count, loff_t *ppos)
2455 struct iwl_trans *trans = file->private_data;
2456 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2457 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2461 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2464 buf = kzalloc(bufsz, GFP_KERNEL);
2468 pos += scnprintf(buf + pos, bufsz - pos,
2469 "Interrupt Statistics Report:\n");
2471 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2473 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2475 if (isr_stats->sw || isr_stats->hw) {
2476 pos += scnprintf(buf + pos, bufsz - pos,
2477 "\tLast Restarting Code: 0x%X\n",
2478 isr_stats->err_code);
2480 #ifdef CONFIG_IWLWIFI_DEBUG
2481 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2483 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2486 pos += scnprintf(buf + pos, bufsz - pos,
2487 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2489 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2492 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2495 pos += scnprintf(buf + pos, bufsz - pos,
2496 "Rx command responses:\t\t %u\n", isr_stats->rx);
2498 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2501 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2502 isr_stats->unhandled);
2504 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2509 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2510 const char __user *user_buf,
2511 size_t count, loff_t *ppos)
2513 struct iwl_trans *trans = file->private_data;
2514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2515 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2519 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2522 if (reset_flag == 0)
2523 memset(isr_stats, 0, sizeof(*isr_stats));
2528 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2529 const char __user *user_buf,
2530 size_t count, loff_t *ppos)
2532 struct iwl_trans *trans = file->private_data;
2534 iwl_pcie_dump_csr(trans);
2539 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2540 char __user *user_buf,
2541 size_t count, loff_t *ppos)
2543 struct iwl_trans *trans = file->private_data;
2547 ret = iwl_dump_fh(trans, &buf);
2552 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2557 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2558 char __user *user_buf,
2559 size_t count, loff_t *ppos)
2561 struct iwl_trans *trans = file->private_data;
2562 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2566 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2567 trans_pcie->debug_rfkill,
2568 !(iwl_read32(trans, CSR_GP_CNTRL) &
2569 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2571 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2574 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2575 const char __user *user_buf,
2576 size_t count, loff_t *ppos)
2578 struct iwl_trans *trans = file->private_data;
2579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2580 bool old = trans_pcie->debug_rfkill;
2583 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2586 if (old == trans_pcie->debug_rfkill)
2588 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2589 old, trans_pcie->debug_rfkill);
2590 iwl_pcie_handle_rfkill_irq(trans);
2595 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2596 DEBUGFS_READ_FILE_OPS(fh_reg);
2597 DEBUGFS_READ_FILE_OPS(rx_queue);
2598 DEBUGFS_READ_FILE_OPS(tx_queue);
2599 DEBUGFS_WRITE_FILE_OPS(csr);
2600 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2602 /* Create the debugfs files and directories */
2603 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2605 struct dentry *dir = trans->dbgfs_dir;
2607 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2608 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2609 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2610 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2611 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2612 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
2616 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2619 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2621 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2623 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2627 for (i = 0; i < trans_pcie->max_tbs; i++)
2628 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2633 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2634 struct iwl_fw_error_dump_data **data,
2635 int allocated_rb_nums)
2637 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2638 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2639 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2640 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2641 u32 i, r, j, rb_len = 0;
2643 spin_lock(&rxq->lock);
2645 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2647 for (i = rxq->read, j = 0;
2648 i != r && j < allocated_rb_nums;
2649 i = (i + 1) & RX_QUEUE_MASK, j++) {
2650 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2651 struct iwl_fw_error_dump_rb *rb;
2653 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2656 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2658 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2659 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2660 rb = (void *)(*data)->data;
2661 rb->index = cpu_to_le32(i);
2662 memcpy(rb->data, page_address(rxb->page), max_len);
2663 /* remap the page for the free benefit */
2664 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2668 *data = iwl_fw_error_next_data(*data);
2671 spin_unlock(&rxq->lock);
2675 #define IWL_CSR_TO_DUMP (0x250)
2677 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2678 struct iwl_fw_error_dump_data **data)
2680 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2684 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2685 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2686 val = (void *)(*data)->data;
2688 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2689 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2691 *data = iwl_fw_error_next_data(*data);
2696 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2697 struct iwl_fw_error_dump_data **data)
2699 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2700 unsigned long flags;
2704 if (!iwl_trans_grab_nic_access(trans, &flags))
2707 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2708 (*data)->len = cpu_to_le32(fh_regs_len);
2709 val = (void *)(*data)->data;
2711 if (!trans->cfg->gen2)
2712 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2714 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2716 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2718 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2721 iwl_trans_release_nic_access(trans, &flags);
2723 *data = iwl_fw_error_next_data(*data);
2725 return sizeof(**data) + fh_regs_len;
2729 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2730 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2733 u32 buf_size_in_dwords = (monitor_len >> 2);
2734 u32 *buffer = (u32 *)fw_mon_data->data;
2735 unsigned long flags;
2738 if (!iwl_trans_grab_nic_access(trans, &flags))
2741 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2742 for (i = 0; i < buf_size_in_dwords; i++)
2743 buffer[i] = iwl_read_prph_no_grab(trans,
2744 MON_DMARB_RD_DATA_ADDR);
2745 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2747 iwl_trans_release_nic_access(trans, &flags);
2753 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2754 struct iwl_fw_error_dump_data **data,
2757 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2760 if ((trans_pcie->fw_mon_page &&
2761 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2762 trans->dbg_dest_tlv) {
2763 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2764 u32 base, write_ptr, wrap_cnt;
2766 /* If there was a dest TLV - use the values from there */
2767 if (trans->dbg_dest_tlv) {
2769 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2770 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2771 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2773 base = MON_BUFF_BASE_ADDR;
2774 write_ptr = MON_BUFF_WRPTR;
2775 wrap_cnt = MON_BUFF_CYCLE_CNT;
2778 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2779 fw_mon_data = (void *)(*data)->data;
2780 fw_mon_data->fw_mon_wr_ptr =
2781 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2782 fw_mon_data->fw_mon_cycle_cnt =
2783 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2784 fw_mon_data->fw_mon_base_ptr =
2785 cpu_to_le32(iwl_read_prph(trans, base));
2787 len += sizeof(**data) + sizeof(*fw_mon_data);
2788 if (trans_pcie->fw_mon_page) {
2790 * The firmware is now asserted, it won't write anything
2791 * to the buffer. CPU can take ownership to fetch the
2792 * data. The buffer will be handed back to the device
2793 * before the firmware will be restarted.
2795 dma_sync_single_for_cpu(trans->dev,
2796 trans_pcie->fw_mon_phys,
2797 trans_pcie->fw_mon_size,
2799 memcpy(fw_mon_data->data,
2800 page_address(trans_pcie->fw_mon_page),
2801 trans_pcie->fw_mon_size);
2803 monitor_len = trans_pcie->fw_mon_size;
2804 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2806 * Update pointers to reflect actual values after
2809 base = iwl_read_prph(trans, base) <<
2810 trans->dbg_dest_tlv->base_shift;
2811 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2812 monitor_len / sizeof(u32));
2813 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2815 iwl_trans_pci_dump_marbh_monitor(trans,
2819 /* Didn't match anything - output no monitor data */
2824 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2830 static struct iwl_trans_dump_data
2831 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2832 const struct iwl_fw_dbg_trigger_tlv *trigger)
2834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2835 struct iwl_fw_error_dump_data *data;
2836 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2837 struct iwl_fw_error_dump_txcmd *txcmd;
2838 struct iwl_trans_dump_data *dump_data;
2842 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2843 !trans->cfg->mq_rx_supported;
2845 /* transport dump header */
2846 len = sizeof(*dump_data);
2849 len += sizeof(*data) +
2850 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2853 if (trans_pcie->fw_mon_page) {
2854 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2855 trans_pcie->fw_mon_size;
2856 monitor_len = trans_pcie->fw_mon_size;
2857 } else if (trans->dbg_dest_tlv) {
2860 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2861 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2863 base = iwl_read_prph(trans, base) <<
2864 trans->dbg_dest_tlv->base_shift;
2865 end = iwl_read_prph(trans, end) <<
2866 trans->dbg_dest_tlv->end_shift;
2868 /* Make "end" point to the actual end */
2869 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 ||
2870 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2871 end += (1 << trans->dbg_dest_tlv->end_shift);
2872 monitor_len = end - base;
2873 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2879 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2880 dump_data = vzalloc(len);
2884 data = (void *)dump_data->data;
2885 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2886 dump_data->len = len;
2892 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2895 if (trans->cfg->gen2)
2896 len += sizeof(*data) +
2897 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2899 len += sizeof(*data) +
2900 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2903 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2904 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2906 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num))
2908 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2909 len += num_rbs * (sizeof(*data) +
2910 sizeof(struct iwl_fw_error_dump_rb) +
2911 (PAGE_SIZE << trans_pcie->rx_page_order));
2914 /* Paged memory for gen2 HW */
2915 if (trans->cfg->gen2)
2916 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2917 len += sizeof(*data) +
2918 sizeof(struct iwl_fw_error_dump_paging) +
2919 trans_pcie->init_dram.paging[i].size;
2921 dump_data = vzalloc(len);
2926 data = (void *)dump_data->data;
2927 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2928 txcmd = (void *)data->data;
2929 spin_lock_bh(&cmdq->lock);
2930 ptr = cmdq->write_ptr;
2931 for (i = 0; i < cmdq->n_window; i++) {
2932 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
2935 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2936 trans_pcie->tfd_size * ptr);
2937 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2940 len += sizeof(*txcmd) + caplen;
2941 txcmd->cmdlen = cpu_to_le32(cmdlen);
2942 txcmd->caplen = cpu_to_le32(caplen);
2943 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2944 txcmd = (void *)((u8 *)txcmd->data + caplen);
2947 ptr = iwl_queue_dec_wrap(ptr);
2949 spin_unlock_bh(&cmdq->lock);
2951 data->len = cpu_to_le32(len);
2952 len += sizeof(*data);
2953 data = iwl_fw_error_next_data(data);
2955 len += iwl_trans_pcie_dump_csr(trans, &data);
2956 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2958 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2960 /* Paged memory for gen2 HW */
2961 if (trans->cfg->gen2) {
2962 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2963 struct iwl_fw_error_dump_paging *paging;
2965 trans_pcie->init_dram.paging[i].physical;
2966 u32 page_len = trans_pcie->init_dram.paging[i].size;
2968 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2969 data->len = cpu_to_le32(sizeof(*paging) + page_len);
2970 paging = (void *)data->data;
2971 paging->index = cpu_to_le32(i);
2972 dma_sync_single_for_cpu(trans->dev, addr, page_len,
2974 memcpy(paging->data,
2975 trans_pcie->init_dram.paging[i].block, page_len);
2976 data = iwl_fw_error_next_data(data);
2978 len += sizeof(*data) + sizeof(*paging) + page_len;
2982 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2984 dump_data->len = len;
2989 #ifdef CONFIG_PM_SLEEP
2990 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2992 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2993 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2994 return iwl_pci_fw_enter_d0i3(trans);
2999 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3001 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3002 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3003 iwl_pci_fw_exit_d0i3(trans);
3005 #endif /* CONFIG_PM_SLEEP */
3007 #define IWL_TRANS_COMMON_OPS \
3008 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3009 .write8 = iwl_trans_pcie_write8, \
3010 .write32 = iwl_trans_pcie_write32, \
3011 .read32 = iwl_trans_pcie_read32, \
3012 .read_prph = iwl_trans_pcie_read_prph, \
3013 .write_prph = iwl_trans_pcie_write_prph, \
3014 .read_mem = iwl_trans_pcie_read_mem, \
3015 .write_mem = iwl_trans_pcie_write_mem, \
3016 .configure = iwl_trans_pcie_configure, \
3017 .set_pmi = iwl_trans_pcie_set_pmi, \
3018 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3019 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3020 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3021 .ref = iwl_trans_pcie_ref, \
3022 .unref = iwl_trans_pcie_unref, \
3023 .dump_data = iwl_trans_pcie_dump_data, \
3024 .dump_regs = iwl_trans_pcie_dump_regs, \
3025 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3026 .d3_resume = iwl_trans_pcie_d3_resume
3028 #ifdef CONFIG_PM_SLEEP
3029 #define IWL_TRANS_PM_OPS \
3030 .suspend = iwl_trans_pcie_suspend, \
3031 .resume = iwl_trans_pcie_resume,
3033 #define IWL_TRANS_PM_OPS
3034 #endif /* CONFIG_PM_SLEEP */
3036 static const struct iwl_trans_ops trans_ops_pcie = {
3037 IWL_TRANS_COMMON_OPS,
3039 .start_hw = iwl_trans_pcie_start_hw,
3040 .fw_alive = iwl_trans_pcie_fw_alive,
3041 .start_fw = iwl_trans_pcie_start_fw,
3042 .stop_device = iwl_trans_pcie_stop_device,
3044 .send_cmd = iwl_trans_pcie_send_hcmd,
3046 .tx = iwl_trans_pcie_tx,
3047 .reclaim = iwl_trans_pcie_reclaim,
3049 .txq_disable = iwl_trans_pcie_txq_disable,
3050 .txq_enable = iwl_trans_pcie_txq_enable,
3052 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3054 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3056 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3057 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3060 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3061 IWL_TRANS_COMMON_OPS,
3063 .start_hw = iwl_trans_pcie_start_hw,
3064 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3065 .start_fw = iwl_trans_pcie_gen2_start_fw,
3066 .stop_device = iwl_trans_pcie_gen2_stop_device,
3068 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3070 .tx = iwl_trans_pcie_gen2_tx,
3071 .reclaim = iwl_trans_pcie_reclaim,
3073 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3074 .txq_free = iwl_trans_pcie_dyn_txq_free,
3075 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3078 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3079 const struct pci_device_id *ent,
3080 const struct iwl_cfg *cfg)
3082 struct iwl_trans_pcie *trans_pcie;
3083 struct iwl_trans *trans;
3086 ret = pcim_enable_device(pdev);
3088 return ERR_PTR(ret);
3091 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3092 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3094 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3095 &pdev->dev, cfg, &trans_ops_pcie);
3097 return ERR_PTR(-ENOMEM);
3099 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3101 trans_pcie->trans = trans;
3102 trans_pcie->opmode_down = true;
3103 spin_lock_init(&trans_pcie->irq_lock);
3104 spin_lock_init(&trans_pcie->reg_lock);
3105 mutex_init(&trans_pcie->mutex);
3106 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3107 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3108 if (!trans_pcie->tso_hdr_page) {
3114 if (!cfg->base_params->pcie_l1_allowed) {
3116 * W/A - seems to solve weird behavior. We need to remove this
3117 * if we don't want to stay in L1 all the time. This wastes a
3120 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3121 PCIE_LINK_STATE_L1 |
3122 PCIE_LINK_STATE_CLKPM);
3127 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3128 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3131 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3132 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3134 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3136 pci_set_master(pdev);
3138 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3140 ret = pci_set_consistent_dma_mask(pdev,
3141 DMA_BIT_MASK(addr_size));
3143 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3145 ret = pci_set_consistent_dma_mask(pdev,
3147 /* both attempts failed: */
3149 dev_err(&pdev->dev, "No suitable DMA available\n");
3154 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3156 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3160 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3161 if (!trans_pcie->hw_base) {
3162 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3167 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3168 * PCI Tx retries from interfering with C3 CPU state */
3169 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3171 trans_pcie->pci_dev = pdev;
3172 iwl_disable_interrupts(trans);
3174 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3176 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3177 * changed, and now the revision step also includes bit 0-1 (no more
3178 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3179 * in the old format.
3181 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3182 unsigned long flags;
3184 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3185 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3187 ret = iwl_pcie_prepare_card_hw(trans);
3189 IWL_WARN(trans, "Exit HW not ready\n");
3194 * in-order to recognize C step driver should read chip version
3195 * id located at the AUX bus MISC address space.
3197 iwl_set_bit(trans, CSR_GP_CNTRL,
3198 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3201 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3202 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3203 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3206 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3210 if (iwl_trans_grab_nic_access(trans, &flags)) {
3213 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3214 hw_step |= ENABLE_WFPM;
3215 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3216 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3217 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3219 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3220 (SILICON_C_STEP << 2);
3221 iwl_trans_release_nic_access(trans, &flags);
3226 * 9000-series integrated A-step has a problem with suspend/resume
3227 * and sometimes even causes the whole platform to get stuck. This
3228 * workaround makes the hardware not go into the problematic state.
3230 if (trans->cfg->integrated &&
3231 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3232 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3233 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3234 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3236 #if IS_ENABLED(CONFIG_IWLMVM)
3237 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3238 if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3241 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3242 if (hw_status & UMAG_GEN_HW_IS_FPGA)
3243 trans->cfg = &iwla000_2ax_cfg_qnj_hr_f0;
3245 trans->cfg = &iwla000_2ac_cfg_hr;
3249 iwl_pcie_set_interrupt_capa(pdev, trans);
3250 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3251 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3252 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3254 /* Initialize the wait queue for commands */
3255 init_waitqueue_head(&trans_pcie->wait_command_queue);
3257 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3259 if (trans_pcie->msix_enabled) {
3260 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3264 ret = iwl_pcie_alloc_ict(trans);
3268 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3270 iwl_pcie_irq_handler,
3271 IRQF_SHARED, DRV_NAME, trans);
3273 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3276 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3279 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3280 WQ_HIGHPRI | WQ_UNBOUND, 1);
3281 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3283 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3284 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3286 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3287 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3292 iwl_pcie_free_ict(trans);
3294 free_percpu(trans_pcie->tso_hdr_page);
3295 iwl_trans_free(trans);
3296 return ERR_PTR(ret);