drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   9  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  10  * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
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  21  * The full GNU General Public License is included in this distribution
  22  * in the file called COPYING.
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  29  *
  30  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  31  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  32  * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
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  40  *    notice, this list of conditions and the following disclaimer.
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  42  *    notice, this list of conditions and the following disclaimer in
  43  *    the documentation and/or other materials provided with the
  44  *    distribution.
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  46  *    contributors may be used to endorse or promote products derived
  47  *    from this software without specific prior written permission.
  48  *
  49  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  50  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  51  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  52  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  53  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  54  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  55  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  58  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  59  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  60  *
  61  *****************************************************************************/
  62 #include <linux/pci.h>
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/sched.h>
  66 #include <linux/bitops.h>
  67 #include <linux/gfp.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/module.h>
  70 #include <linux/wait.h>
  71 #include <linux/seq_file.h>
  72
  73 #include "iwl-drv.h"
  74 #include "iwl-trans.h"
  75 #include "iwl-csr.h"
  76 #include "iwl-prph.h"
  77 #include "iwl-scd.h"
  78 #include "iwl-agn-hw.h"
  79 #include "fw/error-dump.h"
  80 #include "fw/dbg.h"
  81 #include "fw/api/tx.h"
  82 #include "internal.h"
  83 #include "iwl-fh.h"
  84 #include "iwl-context-info-gen3.h"
  85
  86 /* extended range in FW SRAM */
  87 #define IWL_FW_MEM_EXTENDED_START       0x40000
  88 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  89
  90 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  91 {
  92 #define PCI_DUMP_SIZE           352
  93 #define PCI_MEM_DUMP_SIZE       64
  94 #define PCI_PARENT_DUMP_SIZE    524
  95 #define PREFIX_LEN              32
  96         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  97         struct pci_dev *pdev = trans_pcie->pci_dev;
  98         u32 i, pos, alloc_size, *ptr, *buf;
  99         char *prefix;
 100
 101         if (trans_pcie->pcie_dbg_dumped_once)
 102                 return;
 103
 104         /* Should be a multiple of 4 */
 105         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 106         BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
 107         BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
 108
 109         /* Alloc a max size buffer */
 110         alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 111         alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
 112         alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
 113         alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
 114
 115         buf = kmalloc(alloc_size, GFP_ATOMIC);
 116         if (!buf)
 117                 return;
 118         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 119
 120         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 121
 122         /* Print wifi device registers */
 123         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 124         IWL_ERR(trans, "iwlwifi device config registers:\n");
 125         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 126                 if (pci_read_config_dword(pdev, i, ptr))
 127                         goto err_read;
 128         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 129
 130         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 131         for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
 132                 *ptr = iwl_read32(trans, i);
 133         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 134
 135         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 136         if (pos) {
 137                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 138                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 139                         if (pci_read_config_dword(pdev, pos + i, ptr))
 140                                 goto err_read;
 141                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 142                                32, 4, buf, i, 0);
 143         }
 144
 145         /* Print parent device registers next */
 146         if (!pdev->bus->self)
 147                 goto out;
 148
 149         pdev = pdev->bus->self;
 150         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 151
 152         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 153                 pci_name(pdev));
 154         for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
 155                 if (pci_read_config_dword(pdev, i, ptr))
 156                         goto err_read;
 157         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 158
 159         /* Print root port AER registers */
 160         pos = 0;
 161         pdev = pcie_find_root_port(pdev);
 162         if (pdev)
 163                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 164         if (pos) {
 165                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 166                         pci_name(pdev));
 167                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 168                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 169                         if (pci_read_config_dword(pdev, pos + i, ptr))
 170                                 goto err_read;
 171                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 172                                4, buf, i, 0);
 173         }
 174         goto out;
 175
 176 err_read:
 177         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 178         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 179 out:
 180         trans_pcie->pcie_dbg_dumped_once = 1;
 181         kfree(buf);
 182 }
 183
 184 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
 185 {
 186         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 187         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 188         usleep_range(5000, 6000);
 189 }
 190
 191 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 192 {
 193         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 194
 195         if (!fw_mon->size)
 196                 return;
 197
 198         dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
 199                           fw_mon->physical);
 200
 201         fw_mon->block = NULL;
 202         fw_mon->physical = 0;
 203         fw_mon->size = 0;
 204 }
 205
 206 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
 207                                             u8 max_power, u8 min_power)
 208 {
 209         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 210         void *block = NULL;
 211         dma_addr_t physical = 0;
 212         u32 size = 0;
 213         u8 power;
 214
 215         if (fw_mon->size)
 216                 return;
 217
 218         for (power = max_power; power >= min_power; power--) {
 219                 size = BIT(power);
 220                 block = dma_alloc_coherent(trans->dev, size, &physical,
 221                                            GFP_KERNEL | __GFP_NOWARN);
 222                 if (!block)
 223                         continue;
 224
 225                 IWL_INFO(trans,
 226                          "Allocated 0x%08x bytes for firmware monitor.\n",
 227                          size);
 228                 break;
 229         }
 230
 231         if (WARN_ON_ONCE(!block))
 232                 return;
 233
 234         if (power != max_power)
 235                 IWL_ERR(trans,
 236                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 237                         (unsigned long)BIT(power - 10),
 238                         (unsigned long)BIT(max_power - 10));
 239
 240         fw_mon->block = block;
 241         fw_mon->physical = physical;
 242         fw_mon->size = size;
 243 }
 244
 245 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 246 {
 247         if (!max_power) {
 248                 /* default max_power is maximum */
 249                 max_power = 26;
 250         } else {
 251                 max_power += 11;
 252         }
 253
 254         if (WARN(max_power > 26,
 255                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 256                  max_power))
 257                 return;
 258
 259         if (trans->dbg.fw_mon.size)
 260                 return;
 261
 262         iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
 263 }
 264
 265 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 266 {
 267         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 268                     ((reg & 0x0000ffff) | (2 << 28)));
 269         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 270 }
 271
 272 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 273 {
 274         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 275         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 276                     ((reg & 0x0000ffff) | (3 << 28)));
 277 }
 278
 279 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 280 {
 281         if (trans->cfg->apmg_not_supported)
 282                 return;
 283
 284         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 285                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 286                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 287                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 288         else
 289                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 290                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 291                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 292 }
 293
 294 /* PCI registers */
 295 #define PCI_CFG_RETRY_TIMEOUT   0x041
 296
 297 void iwl_pcie_apm_config(struct iwl_trans *trans)
 298 {
 299         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 300         u16 lctl;
 301         u16 cap;
 302
 303         /*
 304          * L0S states have been found to be unstable with our devices
 305          * and in newer hardware they are not officially supported at
 306          * all, so we must always set the L0S_DISABLED bit.
 307          */
 308         iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
 309
 310         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 311         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 312
 313         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 314         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 315         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 316                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 317                         trans->ltr_enabled ? "En" : "Dis");
 318 }
 319
 320 /*
 321  * Start up NIC's basic functionality after it has been reset
 322  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 323  * NOTE:  This does not load uCode nor start the embedded processor
 324  */
 325 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 326 {
 327         int ret;
 328
 329         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 330
 331         /*
 332          * Use "set_bit" below rather than "write", to preserve any hardware
 333          * bits already set by default after reset.
 334          */
 335
 336         /* Disable L0S exit timer (platform NMI Work/Around) */
 337         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
 338                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 339                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 340
 341         /*
 342          * Disable L0s without affecting L1;
 343          *  don't wait for ICH L0s (ICH bug W/A)
 344          */
 345         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 346                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 347
 348         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 349         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 350
 351         /*
 352          * Enable HAP INTA (interrupt from management bus) to
 353          * wake device's PCI Express link L1a -> L0s
 354          */
 355         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 356                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 357
 358         iwl_pcie_apm_config(trans);
 359
 360         /* Configure analog phase-lock-loop before activating to D0A */
 361         if (trans->trans_cfg->base_params->pll_cfg)
 362                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 363
 364         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
 365         if (ret)
 366                 return ret;
 367
 368         if (trans->cfg->host_interrupt_operation_mode) {
 369                 /*
 370                  * This is a bit of an abuse - This is needed for 7260 / 3160
 371                  * only check host_interrupt_operation_mode even if this is
 372                  * not related to host_interrupt_operation_mode.
 373                  *
 374                  * Enable the oscillator to count wake up time for L1 exit. This
 375                  * consumes slightly more power (100uA) - but allows to be sure
 376                  * that we wake up from L1 on time.
 377                  *
 378                  * This looks weird: read twice the same register, discard the
 379                  * value, set a bit, and yet again, read that same register
 380                  * just to discard the value. But that's the way the hardware
 381                  * seems to like it.
 382                  */
 383                 iwl_read_prph(trans, OSC_CLK);
 384                 iwl_read_prph(trans, OSC_CLK);
 385                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 386                 iwl_read_prph(trans, OSC_CLK);
 387                 iwl_read_prph(trans, OSC_CLK);
 388         }
 389
 390         /*
 391          * Enable DMA clock and wait for it to stabilize.
 392          *
 393          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 394          * bits do not disable clocks.  This preserves any hardware
 395          * bits already set by default in "CLK_CTRL_REG" after reset.
 396          */
 397         if (!trans->cfg->apmg_not_supported) {
 398                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 399                                APMG_CLK_VAL_DMA_CLK_RQT);
 400                 udelay(20);
 401
 402                 /* Disable L1-Active */
 403                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 404                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 405
 406                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 407                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 408                                APMG_RTC_INT_STT_RFKILL);
 409         }
 410
 411         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 412
 413         return 0;
 414 }
 415
 416 /*
 417  * Enable LP XTAL to avoid HW bug where device may consume much power if
 418  * FW is not loaded after device reset. LP XTAL is disabled by default
 419  * after device HW reset. Do it only if XTAL is fed by internal source.
 420  * Configure device's "persistence" mode to avoid resetting XTAL again when
 421  * SHRD_HW_RST occurs in S3.
 422  */
 423 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 424 {
 425         int ret;
 426         u32 apmg_gp1_reg;
 427         u32 apmg_xtal_cfg_reg;
 428         u32 dl_cfg_reg;
 429
 430         /* Force XTAL ON */
 431         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 432                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 433
 434         iwl_trans_pcie_sw_reset(trans);
 435
 436         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
 437         if (WARN_ON(ret)) {
 438                 /* Release XTAL ON request */
 439                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 440                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 441                 return;
 442         }
 443
 444         /*
 445          * Clear "disable persistence" to avoid LP XTAL resetting when
 446          * SHRD_HW_RST is applied in S3.
 447          */
 448         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 449                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 450
 451         /*
 452          * Force APMG XTAL to be active to prevent its disabling by HW
 453          * caused by APMG idle state.
 454          */
 455         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 456                                                     SHR_APMG_XTAL_CFG_REG);
 457         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 458                                  apmg_xtal_cfg_reg |
 459                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 460
 461         iwl_trans_pcie_sw_reset(trans);
 462
 463         /* Enable LP XTAL by indirect access through CSR */
 464         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 465         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 466                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 467                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 468
 469         /* Clear delay line clock power up */
 470         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 471         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 472                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 473
 474         /*
 475          * Enable persistence mode to avoid LP XTAL resetting when
 476          * SHRD_HW_RST is applied in S3.
 477          */
 478         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 479                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 480
 481         /*
 482          * Clear "initialization complete" bit to move adapter from
 483          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 484          */
 485         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 486
 487         /* Activates XTAL resources monitor */
 488         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 489                                  CSR_MONITOR_XTAL_RESOURCES);
 490
 491         /* Release XTAL ON request */
 492         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 493                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 494         udelay(10);
 495
 496         /* Release APMG XTAL */
 497         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 498                                  apmg_xtal_cfg_reg &
 499                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 500 }
 501
 502 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 503 {
 504         int ret;
 505
 506         /* stop device's busmaster DMA activity */
 507         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 508
 509         ret = iwl_poll_bit(trans, CSR_RESET,
 510                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 511                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 512         if (ret < 0)
 513                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 514
 515         IWL_DEBUG_INFO(trans, "stop master\n");
 516 }
 517
 518 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 519 {
 520         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 521
 522         if (op_mode_leave) {
 523                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 524                         iwl_pcie_apm_init(trans);
 525
 526                 /* inform ME that we are leaving */
 527                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
 528                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 529                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 530                 else if (trans->trans_cfg->device_family >=
 531                          IWL_DEVICE_FAMILY_8000) {
 532                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 533                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 534                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 535                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 536                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 537                         mdelay(1);
 538                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 539                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 540                 }
 541                 mdelay(5);
 542         }
 543
 544         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 545
 546         /* Stop device's DMA activity */
 547         iwl_pcie_apm_stop_master(trans);
 548
 549         if (trans->cfg->lp_xtal_workaround) {
 550                 iwl_pcie_apm_lp_xtal_enable(trans);
 551                 return;
 552         }
 553
 554         iwl_trans_pcie_sw_reset(trans);
 555
 556         /*
 557          * Clear "initialization complete" bit to move adapter from
 558          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 559          */
 560         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 561 }
 562
 563 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 564 {
 565         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 566         int ret;
 567
 568         /* nic_init */
 569         spin_lock(&trans_pcie->irq_lock);
 570         ret = iwl_pcie_apm_init(trans);
 571         spin_unlock(&trans_pcie->irq_lock);
 572
 573         if (ret)
 574                 return ret;
 575
 576         iwl_pcie_set_pwr(trans, false);
 577
 578         iwl_op_mode_nic_config(trans->op_mode);
 579
 580         /* Allocate the RX queue, or reset if it is already allocated */
 581         iwl_pcie_rx_init(trans);
 582
 583         /* Allocate or reset and init all Tx and Command queues */
 584         if (iwl_pcie_tx_init(trans))
 585                 return -ENOMEM;
 586
 587         if (trans->trans_cfg->base_params->shadow_reg_enable) {
 588                 /* enable shadow regs in HW */
 589                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 590                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 591         }
 592
 593         return 0;
 594 }
 595
 596 #define HW_READY_TIMEOUT (50)
 597
 598 /* Note: returns poll_bit return value, which is >= 0 if success */
 599 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 600 {
 601         int ret;
 602
 603         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 604                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 605
 606         /* See if we got it */
 607         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 608                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 609                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 610                            HW_READY_TIMEOUT);
 611
 612         if (ret >= 0)
 613                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 614
 615         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 616         return ret;
 617 }
 618
 619 /* Note: returns standard 0/-ERROR code */
 620 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 621 {
 622         int ret;
 623         int t = 0;
 624         int iter;
 625
 626         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 627
 628         ret = iwl_pcie_set_hw_ready(trans);
 629         /* If the card is ready, exit 0 */
 630         if (ret >= 0)
 631                 return 0;
 632
 633         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 634                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 635         usleep_range(1000, 2000);
 636
 637         for (iter = 0; iter < 10; iter++) {
 638                 /* If HW is not ready, prepare the conditions to check again */
 639                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 640                             CSR_HW_IF_CONFIG_REG_PREPARE);
 641
 642                 do {
 643                         ret = iwl_pcie_set_hw_ready(trans);
 644                         if (ret >= 0)
 645                                 return 0;
 646
 647                         usleep_range(200, 1000);
 648                         t += 200;
 649                 } while (t < 150000);
 650                 msleep(25);
 651         }
 652
 653         IWL_ERR(trans, "Couldn't prepare the card\n");
 654
 655         return ret;
 656 }
 657
 658 /*
 659  * ucode
 660  */
 661 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 662                                             u32 dst_addr, dma_addr_t phy_addr,
 663                                             u32 byte_cnt)
 664 {
 665         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 666                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 667
 668         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 669                     dst_addr);
 670
 671         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 672                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 673
 674         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 675                     (iwl_get_dma_hi_addr(phy_addr)
 676                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 677
 678         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 679                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 680                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 681                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 682
 683         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 684                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 685                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 686                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 687 }
 688
 689 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 690                                         u32 dst_addr, dma_addr_t phy_addr,
 691                                         u32 byte_cnt)
 692 {
 693         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 694         unsigned long flags;
 695         int ret;
 696
 697         trans_pcie->ucode_write_complete = false;
 698
 699         if (!iwl_trans_grab_nic_access(trans, &flags))
 700                 return -EIO;
 701
 702         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 703                                         byte_cnt);
 704         iwl_trans_release_nic_access(trans, &flags);
 705
 706         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 707                                  trans_pcie->ucode_write_complete, 5 * HZ);
 708         if (!ret) {
 709                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 710                 iwl_trans_pcie_dump_regs(trans);
 711                 return -ETIMEDOUT;
 712         }
 713
 714         return 0;
 715 }
 716
 717 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 718                             const struct fw_desc *section)
 719 {
 720         u8 *v_addr;
 721         dma_addr_t p_addr;
 722         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 723         int ret = 0;
 724
 725         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 726                      section_num);
 727
 728         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 729                                     GFP_KERNEL | __GFP_NOWARN);
 730         if (!v_addr) {
 731                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 732                 chunk_sz = PAGE_SIZE;
 733                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 734                                             &p_addr, GFP_KERNEL);
 735                 if (!v_addr)
 736                         return -ENOMEM;
 737         }
 738
 739         for (offset = 0; offset < section->len; offset += chunk_sz) {
 740                 u32 copy_size, dst_addr;
 741                 bool extended_addr = false;
 742
 743                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 744                 dst_addr = section->offset + offset;
 745
 746                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 747                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 748                         extended_addr = true;
 749
 750                 if (extended_addr)
 751                         iwl_set_bits_prph(trans, LMPM_CHICK,
 752                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 753
 754                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 755                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 756                                                    copy_size);
 757
 758                 if (extended_addr)
 759                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 760                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 761
 762                 if (ret) {
 763                         IWL_ERR(trans,
 764                                 "Could not load the [%d] uCode section\n",
 765                                 section_num);
 766                         break;
 767                 }
 768         }
 769
 770         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 771         return ret;
 772 }
 773
 774 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 775                                            const struct fw_img *image,
 776                                            int cpu,
 777                                            int *first_ucode_section)
 778 {
 779         int shift_param;
 780         int i, ret = 0, sec_num = 0x1;
 781         u32 val, last_read_idx = 0;
 782
 783         if (cpu == 1) {
 784                 shift_param = 0;
 785                 *first_ucode_section = 0;
 786         } else {
 787                 shift_param = 16;
 788                 (*first_ucode_section)++;
 789         }
 790
 791         for (i = *first_ucode_section; i < image->num_sec; i++) {
 792                 last_read_idx = i;
 793
 794                 /*
 795                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 796                  * CPU1 to CPU2.
 797                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 798                  * CPU2 non paged to CPU2 paging sec.
 799                  */
 800                 if (!image->sec[i].data ||
 801                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 802                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 803                         IWL_DEBUG_FW(trans,
 804                                      "Break since Data not valid or Empty section, sec = %d\n",
 805                                      i);
 806                         break;
 807                 }
 808
 809                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 810                 if (ret)
 811                         return ret;
 812
 813                 /* Notify ucode of loaded section number and status */
 814                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 815                 val = val | (sec_num << shift_param);
 816                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 817
 818                 sec_num = (sec_num << 1) | 0x1;
 819         }
 820
 821         *first_ucode_section = last_read_idx;
 822
 823         iwl_enable_interrupts(trans);
 824
 825         if (trans->trans_cfg->use_tfh) {
 826                 if (cpu == 1)
 827                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 828                                        0xFFFF);
 829                 else
 830                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 831                                        0xFFFFFFFF);
 832         } else {
 833                 if (cpu == 1)
 834                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 835                                            0xFFFF);
 836                 else
 837                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 838                                            0xFFFFFFFF);
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 845                                       const struct fw_img *image,
 846                                       int cpu,
 847                                       int *first_ucode_section)
 848 {
 849         int i, ret = 0;
 850         u32 last_read_idx = 0;
 851
 852         if (cpu == 1)
 853                 *first_ucode_section = 0;
 854         else
 855                 (*first_ucode_section)++;
 856
 857         for (i = *first_ucode_section; i < image->num_sec; i++) {
 858                 last_read_idx = i;
 859
 860                 /*
 861                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 862                  * CPU1 to CPU2.
 863                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 864                  * CPU2 non paged to CPU2 paging sec.
 865                  */
 866                 if (!image->sec[i].data ||
 867                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 868                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 869                         IWL_DEBUG_FW(trans,
 870                                      "Break since Data not valid or Empty section, sec = %d\n",
 871                                      i);
 872                         break;
 873                 }
 874
 875                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 876                 if (ret)
 877                         return ret;
 878         }
 879
 880         *first_ucode_section = last_read_idx;
 881
 882         return 0;
 883 }
 884
 885 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
 886 {
 887         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
 888         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
 889                 &trans->dbg.fw_mon_cfg[alloc_id];
 890         struct iwl_dram_data *frag;
 891
 892         if (!iwl_trans_dbg_ini_valid(trans))
 893                 return;
 894
 895         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
 896             IWL_FW_INI_LOCATION_SRAM_PATH) {
 897                 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
 898                 /* set sram monitor by enabling bit 7 */
 899                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 900                             CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
 901
 902                 return;
 903         }
 904
 905         if (le32_to_cpu(fw_mon_cfg->buf_location) !=
 906             IWL_FW_INI_LOCATION_DRAM_PATH ||
 907             !trans->dbg.fw_mon_ini[alloc_id].num_frags)
 908                 return;
 909
 910         frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
 911
 912         IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
 913                      alloc_id);
 914
 915         iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
 916                             frag->physical >> MON_BUFF_SHIFT_VER2);
 917         iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
 918                             (frag->physical + frag->size - 256) >>
 919                             MON_BUFF_SHIFT_VER2);
 920 }
 921
 922 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 923 {
 924         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
 925         const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 926         int i;
 927
 928         if (iwl_trans_dbg_ini_valid(trans)) {
 929                 iwl_pcie_apply_destination_ini(trans);
 930                 return;
 931         }
 932
 933         IWL_INFO(trans, "Applying debug destination %s\n",
 934                  get_fw_dbg_mode_string(dest->monitor_mode));
 935
 936         if (dest->monitor_mode == EXTERNAL_MODE)
 937                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 938         else
 939                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 940
 941         for (i = 0; i < trans->dbg.n_dest_reg; i++) {
 942                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 943                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 944
 945                 switch (dest->reg_ops[i].op) {
 946                 case CSR_ASSIGN:
 947                         iwl_write32(trans, addr, val);
 948                         break;
 949                 case CSR_SETBIT:
 950                         iwl_set_bit(trans, addr, BIT(val));
 951                         break;
 952                 case CSR_CLEARBIT:
 953                         iwl_clear_bit(trans, addr, BIT(val));
 954                         break;
 955                 case PRPH_ASSIGN:
 956                         iwl_write_prph(trans, addr, val);
 957                         break;
 958                 case PRPH_SETBIT:
 959                         iwl_set_bits_prph(trans, addr, BIT(val));
 960                         break;
 961                 case PRPH_CLEARBIT:
 962                         iwl_clear_bits_prph(trans, addr, BIT(val));
 963                         break;
 964                 case PRPH_BLOCKBIT:
 965                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 966                                 IWL_ERR(trans,
 967                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 968                                         val, addr);
 969                                 goto monitor;
 970                         }
 971                         break;
 972                 default:
 973                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 974                                 dest->reg_ops[i].op);
 975                         break;
 976                 }
 977         }
 978
 979 monitor:
 980         if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
 981                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 982                                fw_mon->physical >> dest->base_shift);
 983                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 984                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 985                                        (fw_mon->physical + fw_mon->size -
 986                                         256) >> dest->end_shift);
 987                 else
 988                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 989                                        (fw_mon->physical + fw_mon->size) >>
 990                                        dest->end_shift);
 991         }
 992 }
 993
 994 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 995                                 const struct fw_img *image)
 996 {
 997         int ret = 0;
 998         int first_ucode_section;
 999
1000         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1001                      image->is_dual_cpus ? "Dual" : "Single");
1002
1003         /* load to FW the binary non secured sections of CPU1 */
1004         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1005         if (ret)
1006                 return ret;
1007
1008         if (image->is_dual_cpus) {
1009                 /* set CPU2 header address */
1010                 iwl_write_prph(trans,
1011                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1012                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1013
1014                 /* load to FW the binary sections of CPU2 */
1015                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1016                                                  &first_ucode_section);
1017                 if (ret)
1018                         return ret;
1019         }
1020
1021         if (iwl_pcie_dbg_on(trans))
1022                 iwl_pcie_apply_destination(trans);
1023
1024         iwl_enable_interrupts(trans);
1025
1026         /* release CPU reset */
1027         iwl_write32(trans, CSR_RESET, 0);
1028
1029         return 0;
1030 }
1031
1032 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1033                                           const struct fw_img *image)
1034 {
1035         int ret = 0;
1036         int first_ucode_section;
1037
1038         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1039                      image->is_dual_cpus ? "Dual" : "Single");
1040
1041         if (iwl_pcie_dbg_on(trans))
1042                 iwl_pcie_apply_destination(trans);
1043
1044         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1045                         iwl_read_prph(trans, WFPM_GP2));
1046
1047         /*
1048          * Set default value. On resume reading the values that were
1049          * zeored can provide debug data on the resume flow.
1050          * This is for debugging only and has no functional impact.
1051          */
1052         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1053
1054         /* configure the ucode to be ready to get the secured image */
1055         /* release CPU reset */
1056         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1057
1058         /* load to FW the binary Secured sections of CPU1 */
1059         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1060                                               &first_ucode_section);
1061         if (ret)
1062                 return ret;
1063
1064         /* load to FW the binary sections of CPU2 */
1065         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1066                                                &first_ucode_section);
1067 }
1068
1069 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1070 {
1071         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1072         bool hw_rfkill = iwl_is_rfkill_set(trans);
1073         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1074         bool report;
1075
1076         if (hw_rfkill) {
1077                 set_bit(STATUS_RFKILL_HW, &trans->status);
1078                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1079         } else {
1080                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1081                 if (trans_pcie->opmode_down)
1082                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083         }
1084
1085         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1086
1087         if (prev != report)
1088                 iwl_trans_pcie_rf_kill(trans, report);
1089
1090         return hw_rfkill;
1091 }
1092
1093 struct iwl_causes_list {
1094         u32 cause_num;
1095         u32 mask_reg;
1096         u8 addr;
1097 };
1098
1099 static struct iwl_causes_list causes_list[] = {
1100         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1101         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1102         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1103         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1104         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1105         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1106         {MSIX_HW_INT_CAUSES_REG_IML,            CSR_MSIX_HW_INT_MASK_AD, 0x12},
1107         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1108         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1109         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1110         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1111         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1112         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1113         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1114         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1115 };
1116
1117 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1118 {
1119         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1120         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1121         int i, arr_size = ARRAY_SIZE(causes_list);
1122         struct iwl_causes_list *causes = causes_list;
1123
1124         /*
1125          * Access all non RX causes and map them to the default irq.
1126          * In case we are missing at least one interrupt vector,
1127          * the first interrupt vector will serve non-RX and FBQ causes.
1128          */
1129         for (i = 0; i < arr_size; i++) {
1130                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1131                 iwl_clear_bit(trans, causes[i].mask_reg,
1132                               causes[i].cause_num);
1133         }
1134 }
1135
1136 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1137 {
1138         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1139         u32 offset =
1140                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1141         u32 val, idx;
1142
1143         /*
1144          * The first RX queue - fallback queue, which is designated for
1145          * management frame, command responses etc, is always mapped to the
1146          * first interrupt vector. The other RX queues are mapped to
1147          * the other (N - 2) interrupt vectors.
1148          */
1149         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1150         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1151                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1152                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1153                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1154         }
1155         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1156
1157         val = MSIX_FH_INT_CAUSES_Q(0);
1158         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1159                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1160         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1161
1162         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1163                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1164 }
1165
1166 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1167 {
1168         struct iwl_trans *trans = trans_pcie->trans;
1169
1170         if (!trans_pcie->msix_enabled) {
1171                 if (trans->trans_cfg->mq_rx_supported &&
1172                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1173                         iwl_write_umac_prph(trans, UREG_CHICK,
1174                                             UREG_CHICK_MSI_ENABLE);
1175                 return;
1176         }
1177         /*
1178          * The IVAR table needs to be configured again after reset,
1179          * but if the device is disabled, we can't write to
1180          * prph.
1181          */
1182         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1183                 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1184
1185         /*
1186          * Each cause from the causes list above and the RX causes is
1187          * represented as a byte in the IVAR table. The first nibble
1188          * represents the bound interrupt vector of the cause, the second
1189          * represents no auto clear for this cause. This will be set if its
1190          * interrupt vector is bound to serve other causes.
1191          */
1192         iwl_pcie_map_rx_causes(trans);
1193
1194         iwl_pcie_map_non_rx_causes(trans);
1195 }
1196
1197 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1198 {
1199         struct iwl_trans *trans = trans_pcie->trans;
1200
1201         iwl_pcie_conf_msix_hw(trans_pcie);
1202
1203         if (!trans_pcie->msix_enabled)
1204                 return;
1205
1206         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1207         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1208         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1209         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1210 }
1211
1212 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1213 {
1214         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1215
1216         lockdep_assert_held(&trans_pcie->mutex);
1217
1218         if (trans_pcie->is_down)
1219                 return;
1220
1221         trans_pcie->is_down = true;
1222
1223         /* tell the device to stop sending interrupts */
1224         iwl_disable_interrupts(trans);
1225
1226         /* device going down, Stop using ICT table */
1227         iwl_pcie_disable_ict(trans);
1228
1229         /*
1230          * If a HW restart happens during firmware loading,
1231          * then the firmware loading might call this function
1232          * and later it might be called again due to the
1233          * restart. So don't process again if the device is
1234          * already dead.
1235          */
1236         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1237                 IWL_DEBUG_INFO(trans,
1238                                "DEVICE_ENABLED bit was set and is now cleared\n");
1239                 iwl_pcie_tx_stop(trans);
1240                 iwl_pcie_rx_stop(trans);
1241
1242                 /* Power-down device's busmaster DMA clocks */
1243                 if (!trans->cfg->apmg_not_supported) {
1244                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1245                                        APMG_CLK_VAL_DMA_CLK_RQT);
1246                         udelay(5);
1247                 }
1248         }
1249
1250         /* Make sure (redundant) we've released our request to stay awake */
1251         iwl_clear_bit(trans, CSR_GP_CNTRL,
1252                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1253
1254         /* Stop the device, and put it in low power state */
1255         iwl_pcie_apm_stop(trans, false);
1256
1257         iwl_trans_pcie_sw_reset(trans);
1258
1259         /*
1260          * Upon stop, the IVAR table gets erased, so msi-x won't
1261          * work. This causes a bug in RF-KILL flows, since the interrupt
1262          * that enables radio won't fire on the correct irq, and the
1263          * driver won't be able to handle the interrupt.
1264          * Configure the IVAR table again after reset.
1265          */
1266         iwl_pcie_conf_msix_hw(trans_pcie);
1267
1268         /*
1269          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1270          * This is a bug in certain verions of the hardware.
1271          * Certain devices also keep sending HW RF kill interrupt all
1272          * the time, unless the interrupt is ACKed even if the interrupt
1273          * should be masked. Re-ACK all the interrupts here.
1274          */
1275         iwl_disable_interrupts(trans);
1276
1277         /* clear all status bits */
1278         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1279         clear_bit(STATUS_INT_ENABLED, &trans->status);
1280         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1281
1282         /*
1283          * Even if we stop the HW, we still want the RF kill
1284          * interrupt
1285          */
1286         iwl_enable_rfkill_int(trans);
1287
1288         /* re-take ownership to prevent other users from stealing the device */
1289         iwl_pcie_prepare_card_hw(trans);
1290 }
1291
1292 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1293 {
1294         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1295
1296         if (trans_pcie->msix_enabled) {
1297                 int i;
1298
1299                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1300                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1301         } else {
1302                 synchronize_irq(trans_pcie->pci_dev->irq);
1303         }
1304 }
1305
1306 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1307                                    const struct fw_img *fw, bool run_in_rfkill)
1308 {
1309         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1310         bool hw_rfkill;
1311         int ret;
1312
1313         /* This may fail if AMT took ownership of the device */
1314         if (iwl_pcie_prepare_card_hw(trans)) {
1315                 IWL_WARN(trans, "Exit HW not ready\n");
1316                 ret = -EIO;
1317                 goto out;
1318         }
1319
1320         iwl_enable_rfkill_int(trans);
1321
1322         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1323
1324         /*
1325          * We enabled the RF-Kill interrupt and the handler may very
1326          * well be running. Disable the interrupts to make sure no other
1327          * interrupt can be fired.
1328          */
1329         iwl_disable_interrupts(trans);
1330
1331         /* Make sure it finished running */
1332         iwl_pcie_synchronize_irqs(trans);
1333
1334         mutex_lock(&trans_pcie->mutex);
1335
1336         /* If platform's RF_KILL switch is NOT set to KILL */
1337         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1338         if (hw_rfkill && !run_in_rfkill) {
1339                 ret = -ERFKILL;
1340                 goto out;
1341         }
1342
1343         /* Someone called stop_device, don't try to start_fw */
1344         if (trans_pcie->is_down) {
1345                 IWL_WARN(trans,
1346                          "Can't start_fw since the HW hasn't been started\n");
1347                 ret = -EIO;
1348                 goto out;
1349         }
1350
1351         /* make sure rfkill handshake bits are cleared */
1352         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1353         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1354                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1355
1356         /* clear (again), then enable host interrupts */
1357         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1358
1359         ret = iwl_pcie_nic_init(trans);
1360         if (ret) {
1361                 IWL_ERR(trans, "Unable to init nic\n");
1362                 goto out;
1363         }
1364
1365         /*
1366          * Now, we load the firmware and don't want to be interrupted, even
1367          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1368          * FH_TX interrupt which is needed to load the firmware). If the
1369          * RF-Kill switch is toggled, we will find out after having loaded
1370          * the firmware and return the proper value to the caller.
1371          */
1372         iwl_enable_fw_load_int(trans);
1373
1374         /* really make sure rfkill handshake bits are cleared */
1375         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1376         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1377
1378         /* Load the given image to the HW */
1379         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1380                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1381         else
1382                 ret = iwl_pcie_load_given_ucode(trans, fw);
1383
1384         /* re-check RF-Kill state since we may have missed the interrupt */
1385         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1386         if (hw_rfkill && !run_in_rfkill)
1387                 ret = -ERFKILL;
1388
1389 out:
1390         mutex_unlock(&trans_pcie->mutex);
1391         return ret;
1392 }
1393
1394 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1395 {
1396         iwl_pcie_reset_ict(trans);
1397         iwl_pcie_tx_start(trans, scd_addr);
1398 }
1399
1400 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1401                                        bool was_in_rfkill)
1402 {
1403         bool hw_rfkill;
1404
1405         /*
1406          * Check again since the RF kill state may have changed while
1407          * all the interrupts were disabled, in this case we couldn't
1408          * receive the RF kill interrupt and update the state in the
1409          * op_mode.
1410          * Don't call the op_mode if the rkfill state hasn't changed.
1411          * This allows the op_mode to call stop_device from the rfkill
1412          * notification without endless recursion. Under very rare
1413          * circumstances, we might have a small recursion if the rfkill
1414          * state changed exactly now while we were called from stop_device.
1415          * This is very unlikely but can happen and is supported.
1416          */
1417         hw_rfkill = iwl_is_rfkill_set(trans);
1418         if (hw_rfkill) {
1419                 set_bit(STATUS_RFKILL_HW, &trans->status);
1420                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1421         } else {
1422                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1423                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1424         }
1425         if (hw_rfkill != was_in_rfkill)
1426                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1427 }
1428
1429 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1430 {
1431         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432         bool was_in_rfkill;
1433
1434         mutex_lock(&trans_pcie->mutex);
1435         trans_pcie->opmode_down = true;
1436         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1437         _iwl_trans_pcie_stop_device(trans);
1438         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1439         mutex_unlock(&trans_pcie->mutex);
1440 }
1441
1442 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1443 {
1444         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1445                 IWL_TRANS_GET_PCIE_TRANS(trans);
1446
1447         lockdep_assert_held(&trans_pcie->mutex);
1448
1449         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1450                  state ? "disabled" : "enabled");
1451         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1452                 if (trans->trans_cfg->gen2)
1453                         _iwl_trans_pcie_gen2_stop_device(trans);
1454                 else
1455                         _iwl_trans_pcie_stop_device(trans);
1456         }
1457 }
1458
1459 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1460                                   bool test, bool reset)
1461 {
1462         iwl_disable_interrupts(trans);
1463
1464         /*
1465          * in testing mode, the host stays awake and the
1466          * hardware won't be reset (not even partially)
1467          */
1468         if (test)
1469                 return;
1470
1471         iwl_pcie_disable_ict(trans);
1472
1473         iwl_pcie_synchronize_irqs(trans);
1474
1475         iwl_clear_bit(trans, CSR_GP_CNTRL,
1476                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1477         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1478
1479         if (reset) {
1480                 /*
1481                  * reset TX queues -- some of their registers reset during S3
1482                  * so if we don't reset everything here the D3 image would try
1483                  * to execute some invalid memory upon resume
1484                  */
1485                 iwl_trans_pcie_tx_reset(trans);
1486         }
1487
1488         iwl_pcie_set_pwr(trans, true);
1489 }
1490
1491 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1492                                      bool reset)
1493 {
1494         int ret;
1495         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1496
1497         if (!reset)
1498                 /* Enable persistence mode to avoid reset */
1499                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1500                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1501
1502         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1503                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1504                                     UREG_DOORBELL_TO_ISR6_SUSPEND);
1505
1506                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1507                                          trans_pcie->sx_complete, 2 * HZ);
1508                 /*
1509                  * Invalidate it toward resume.
1510                  */
1511                 trans_pcie->sx_complete = false;
1512
1513                 if (!ret) {
1514                         IWL_ERR(trans, "Timeout entering D3\n");
1515                         return -ETIMEDOUT;
1516                 }
1517         }
1518         iwl_pcie_d3_complete_suspend(trans, test, reset);
1519
1520         return 0;
1521 }
1522
1523 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1524                                     enum iwl_d3_status *status,
1525                                     bool test,  bool reset)
1526 {
1527         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1528         u32 val;
1529         int ret;
1530
1531         if (test) {
1532                 iwl_enable_interrupts(trans);
1533                 *status = IWL_D3_STATUS_ALIVE;
1534                 goto out;
1535         }
1536
1537         iwl_set_bit(trans, CSR_GP_CNTRL,
1538                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1539
1540         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1541         if (ret)
1542                 return ret;
1543
1544         /*
1545          * Reconfigure IVAR table in case of MSIX or reset ict table in
1546          * MSI mode since HW reset erased it.
1547          * Also enables interrupts - none will happen as
1548          * the device doesn't know we're waking it up, only when
1549          * the opmode actually tells it after this call.
1550          */
1551         iwl_pcie_conf_msix_hw(trans_pcie);
1552         if (!trans_pcie->msix_enabled)
1553                 iwl_pcie_reset_ict(trans);
1554         iwl_enable_interrupts(trans);
1555
1556         iwl_pcie_set_pwr(trans, false);
1557
1558         if (!reset) {
1559                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1560                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1561         } else {
1562                 iwl_trans_pcie_tx_reset(trans);
1563
1564                 ret = iwl_pcie_rx_init(trans);
1565                 if (ret) {
1566                         IWL_ERR(trans,
1567                                 "Failed to resume the device (RX reset)\n");
1568                         return ret;
1569                 }
1570         }
1571
1572         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1573                         iwl_read_umac_prph(trans, WFPM_GP2));
1574
1575         val = iwl_read32(trans, CSR_RESET);
1576         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1577                 *status = IWL_D3_STATUS_RESET;
1578         else
1579                 *status = IWL_D3_STATUS_ALIVE;
1580
1581 out:
1582         if (*status == IWL_D3_STATUS_ALIVE &&
1583             trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1584                 trans_pcie->sx_complete = false;
1585                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1586                                     UREG_DOORBELL_TO_ISR6_RESUME);
1587
1588                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1589                                          trans_pcie->sx_complete, 2 * HZ);
1590                 /*
1591                  * Invalidate it toward next suspend.
1592                  */
1593                 trans_pcie->sx_complete = false;
1594
1595                 if (!ret) {
1596                         IWL_ERR(trans, "Timeout exiting D3\n");
1597                         return -ETIMEDOUT;
1598                 }
1599         }
1600         return 0;
1601 }
1602
1603 static void
1604 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1605                             struct iwl_trans *trans,
1606                             const struct iwl_cfg_trans_params *cfg_trans)
1607 {
1608         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1609         int max_irqs, num_irqs, i, ret;
1610         u16 pci_cmd;
1611         u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1612
1613         if (!cfg_trans->mq_rx_supported)
1614                 goto enable_msi;
1615
1616         if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1617                 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1618
1619         max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1620         for (i = 0; i < max_irqs; i++)
1621                 trans_pcie->msix_entries[i].entry = i;
1622
1623         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1624                                          MSIX_MIN_INTERRUPT_VECTORS,
1625                                          max_irqs);
1626         if (num_irqs < 0) {
1627                 IWL_DEBUG_INFO(trans,
1628                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1629                                num_irqs);
1630                 goto enable_msi;
1631         }
1632         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1633
1634         IWL_DEBUG_INFO(trans,
1635                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1636                        num_irqs);
1637
1638         /*
1639          * In case the OS provides fewer interrupts than requested, different
1640          * causes will share the same interrupt vector as follows:
1641          * One interrupt less: non rx causes shared with FBQ.
1642          * Two interrupts less: non rx causes shared with FBQ and RSS.
1643          * More than two interrupts: we will use fewer RSS queues.
1644          */
1645         if (num_irqs <= max_irqs - 2) {
1646                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1647                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1648                         IWL_SHARED_IRQ_FIRST_RSS;
1649         } else if (num_irqs == max_irqs - 1) {
1650                 trans_pcie->trans->num_rx_queues = num_irqs;
1651                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1652         } else {
1653                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1654         }
1655         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1656
1657         trans_pcie->alloc_vecs = num_irqs;
1658         trans_pcie->msix_enabled = true;
1659         return;
1660
1661 enable_msi:
1662         ret = pci_enable_msi(pdev);
1663         if (ret) {
1664                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1665                 /* enable rfkill interrupt: hw bug w/a */
1666                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1667                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1668                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1669                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1670                 }
1671         }
1672 }
1673
1674 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1675 {
1676         int iter_rx_q, i, ret, cpu, offset;
1677         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1678
1679         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1680         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1681         offset = 1 + i;
1682         for (; i < iter_rx_q ; i++) {
1683                 /*
1684                  * Get the cpu prior to the place to search
1685                  * (i.e. return will be > i - 1).
1686                  */
1687                 cpu = cpumask_next(i - offset, cpu_online_mask);
1688                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1689                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1690                                             &trans_pcie->affinity_mask[i]);
1691                 if (ret)
1692                         IWL_ERR(trans_pcie->trans,
1693                                 "Failed to set affinity mask for IRQ %d\n",
1694                                 i);
1695         }
1696 }
1697
1698 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1699                                       struct iwl_trans_pcie *trans_pcie)
1700 {
1701         int i;
1702
1703         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1704                 int ret;
1705                 struct msix_entry *msix_entry;
1706                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1707
1708                 if (!qname)
1709                         return -ENOMEM;
1710
1711                 msix_entry = &trans_pcie->msix_entries[i];
1712                 ret = devm_request_threaded_irq(&pdev->dev,
1713                                                 msix_entry->vector,
1714                                                 iwl_pcie_msix_isr,
1715                                                 (i == trans_pcie->def_irq) ?
1716                                                 iwl_pcie_irq_msix_handler :
1717                                                 iwl_pcie_irq_rx_msix_handler,
1718                                                 IRQF_SHARED,
1719                                                 qname,
1720                                                 msix_entry);
1721                 if (ret) {
1722                         IWL_ERR(trans_pcie->trans,
1723                                 "Error allocating IRQ %d\n", i);
1724
1725                         return ret;
1726                 }
1727         }
1728         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1729
1730         return 0;
1731 }
1732
1733 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1734 {
1735         u32 hpm, wprot;
1736
1737         switch (trans->trans_cfg->device_family) {
1738         case IWL_DEVICE_FAMILY_9000:
1739                 wprot = PREG_PRPH_WPROT_9000;
1740                 break;
1741         case IWL_DEVICE_FAMILY_22000:
1742                 wprot = PREG_PRPH_WPROT_22000;
1743                 break;
1744         default:
1745                 return 0;
1746         }
1747
1748         hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1749         if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1750                 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1751
1752                 if (wprot_val & PREG_WFPM_ACCESS) {
1753                         IWL_ERR(trans,
1754                                 "Error, can not clear persistence bit\n");
1755                         return -EPERM;
1756                 }
1757                 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1758                                             hpm & ~PERSISTENCE_BIT);
1759         }
1760
1761         return 0;
1762 }
1763
1764 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1765 {
1766         int ret;
1767
1768         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1769         if (ret < 0)
1770                 return ret;
1771
1772         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1773                           HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1774         udelay(20);
1775         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1776                           HPM_HIPM_GEN_CFG_CR_PG_EN |
1777                           HPM_HIPM_GEN_CFG_CR_SLP_EN);
1778         udelay(20);
1779         iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1780                             HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1781
1782         iwl_trans_pcie_sw_reset(trans);
1783
1784         return 0;
1785 }
1786
1787 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1788 {
1789         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1790         int err;
1791
1792         lockdep_assert_held(&trans_pcie->mutex);
1793
1794         err = iwl_pcie_prepare_card_hw(trans);
1795         if (err) {
1796                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1797                 return err;
1798         }
1799
1800         err = iwl_trans_pcie_clear_persistence_bit(trans);
1801         if (err)
1802                 return err;
1803
1804         iwl_trans_pcie_sw_reset(trans);
1805
1806         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1807             trans->trans_cfg->integrated) {
1808                 err = iwl_pcie_gen2_force_power_gating(trans);
1809                 if (err)
1810                         return err;
1811         }
1812
1813         err = iwl_pcie_apm_init(trans);
1814         if (err)
1815                 return err;
1816
1817         iwl_pcie_init_msix(trans_pcie);
1818
1819         /* From now on, the op_mode will be kept updated about RF kill state */
1820         iwl_enable_rfkill_int(trans);
1821
1822         trans_pcie->opmode_down = false;
1823
1824         /* Set is_down to false here so that...*/
1825         trans_pcie->is_down = false;
1826
1827         /* ...rfkill can call stop_device and set it false if needed */
1828         iwl_pcie_check_hw_rf_kill(trans);
1829
1830         return 0;
1831 }
1832
1833 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1834 {
1835         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1836         int ret;
1837
1838         mutex_lock(&trans_pcie->mutex);
1839         ret = _iwl_trans_pcie_start_hw(trans);
1840         mutex_unlock(&trans_pcie->mutex);
1841
1842         return ret;
1843 }
1844
1845 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1846 {
1847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1848
1849         mutex_lock(&trans_pcie->mutex);
1850
1851         /* disable interrupts - don't enable HW RF kill interrupt */
1852         iwl_disable_interrupts(trans);
1853
1854         iwl_pcie_apm_stop(trans, true);
1855
1856         iwl_disable_interrupts(trans);
1857
1858         iwl_pcie_disable_ict(trans);
1859
1860         mutex_unlock(&trans_pcie->mutex);
1861
1862         iwl_pcie_synchronize_irqs(trans);
1863 }
1864
1865 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1866 {
1867         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1868 }
1869
1870 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1871 {
1872         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1873 }
1874
1875 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1876 {
1877         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1878 }
1879
1880 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1881 {
1882         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1883                 return 0x00FFFFFF;
1884         else
1885                 return 0x000FFFFF;
1886 }
1887
1888 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1889 {
1890         u32 mask = iwl_trans_pcie_prph_msk(trans);
1891
1892         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1893                                ((reg & mask) | (3 << 24)));
1894         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1895 }
1896
1897 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1898                                       u32 val)
1899 {
1900         u32 mask = iwl_trans_pcie_prph_msk(trans);
1901
1902         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1903                                ((addr & mask) | (3 << 24)));
1904         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1905 }
1906
1907 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1908                                      const struct iwl_trans_config *trans_cfg)
1909 {
1910         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1911
1912         trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1913         trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1914         trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1915         trans->txqs.page_offs = trans_cfg->cb_data_offs;
1916         trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1917
1918         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1919                 trans_pcie->n_no_reclaim_cmds = 0;
1920         else
1921                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1922         if (trans_pcie->n_no_reclaim_cmds)
1923                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1924                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1925
1926         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1927         trans_pcie->rx_page_order =
1928                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1929         trans_pcie->rx_buf_bytes =
1930                 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1931         trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1932         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1933                 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1934
1935         trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1936         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1937         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1938
1939         trans->command_groups = trans_cfg->command_groups;
1940         trans->command_groups_size = trans_cfg->command_groups_size;
1941
1942         /* Initialize NAPI here - it should be before registering to mac80211
1943          * in the opmode but after the HW struct is allocated.
1944          * As this function may be called again in some corner cases don't
1945          * do anything if NAPI was already initialized.
1946          */
1947         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1948                 init_dummy_netdev(&trans_pcie->napi_dev);
1949 }
1950
1951 void iwl_trans_pcie_free(struct iwl_trans *trans)
1952 {
1953         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1954         int i;
1955
1956         iwl_pcie_synchronize_irqs(trans);
1957
1958         if (trans->trans_cfg->gen2)
1959                 iwl_txq_gen2_tx_free(trans);
1960         else
1961                 iwl_pcie_tx_free(trans);
1962         iwl_pcie_rx_free(trans);
1963
1964         if (trans_pcie->rba.alloc_wq) {
1965                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1966                 trans_pcie->rba.alloc_wq = NULL;
1967         }
1968
1969         if (trans_pcie->msix_enabled) {
1970                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1971                         irq_set_affinity_hint(
1972                                 trans_pcie->msix_entries[i].vector,
1973                                 NULL);
1974                 }
1975
1976                 trans_pcie->msix_enabled = false;
1977         } else {
1978                 iwl_pcie_free_ict(trans);
1979         }
1980
1981         iwl_pcie_free_fw_monitor(trans);
1982
1983         if (trans_pcie->pnvm_dram.size)
1984                 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
1985                                   trans_pcie->pnvm_dram.block,
1986                                   trans_pcie->pnvm_dram.physical);
1987
1988         mutex_destroy(&trans_pcie->mutex);
1989         iwl_trans_free(trans);
1990 }
1991
1992 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1993 {
1994         if (state)
1995                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1996         else
1997                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1998 }
1999
2000 struct iwl_trans_pcie_removal {
2001         struct pci_dev *pdev;
2002         struct work_struct work;
2003 };
2004
2005 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2006 {
2007         struct iwl_trans_pcie_removal *removal =
2008                 container_of(wk, struct iwl_trans_pcie_removal, work);
2009         struct pci_dev *pdev = removal->pdev;
2010         static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2011
2012         dev_err(&pdev->dev, "Device gone - attempting removal\n");
2013         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2014         pci_lock_rescan_remove();
2015         pci_dev_put(pdev);
2016         pci_stop_and_remove_bus_device(pdev);
2017         pci_unlock_rescan_remove();
2018
2019         kfree(removal);
2020         module_put(THIS_MODULE);
2021 }
2022
2023 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2024                                            unsigned long *flags)
2025 {
2026         int ret;
2027         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2028
2029         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
2030
2031         if (trans_pcie->cmd_hold_nic_awake)
2032                 goto out;
2033
2034         /* this bit wakes up the NIC */
2035         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
2036                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2037         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2038                 udelay(2);
2039
2040         /*
2041          * These bits say the device is running, and should keep running for
2042          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2043          * but they do not indicate that embedded SRAM is restored yet;
2044          * HW with volatile SRAM must save/restore contents to/from
2045          * host DRAM when sleeping/waking for power-saving.
2046          * Each direction takes approximately 1/4 millisecond; with this
2047          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2048          * series of register accesses are expected (e.g. reading Event Log),
2049          * to keep device from sleeping.
2050          *
2051          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2052          * SRAM is okay/restored.  We don't check that here because this call
2053          * is just for hardware register access; but GP1 MAC_SLEEP
2054          * check is a good idea before accessing the SRAM of HW with
2055          * volatile SRAM (e.g. reading Event Log).
2056          *
2057          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2058          * and do not save/restore SRAM when power cycling.
2059          */
2060         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2061                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2062                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2063                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2064         if (unlikely(ret < 0)) {
2065                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2066
2067                 WARN_ONCE(1,
2068                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2069                           cntrl);
2070
2071                 iwl_trans_pcie_dump_regs(trans);
2072
2073                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2074                         struct iwl_trans_pcie_removal *removal;
2075
2076                         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2077                                 goto err;
2078
2079                         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2080
2081                         /*
2082                          * get a module reference to avoid doing this
2083                          * while unloading anyway and to avoid
2084                          * scheduling a work with code that's being
2085                          * removed.
2086                          */
2087                         if (!try_module_get(THIS_MODULE)) {
2088                                 IWL_ERR(trans,
2089                                         "Module is being unloaded - abort\n");
2090                                 goto err;
2091                         }
2092
2093                         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2094                         if (!removal) {
2095                                 module_put(THIS_MODULE);
2096                                 goto err;
2097                         }
2098                         /*
2099                          * we don't need to clear this flag, because
2100                          * the trans will be freed and reallocated.
2101                         */
2102                         set_bit(STATUS_TRANS_DEAD, &trans->status);
2103
2104                         removal->pdev = to_pci_dev(trans->dev);
2105                         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2106                         pci_dev_get(removal->pdev);
2107                         schedule_work(&removal->work);
2108                 } else {
2109                         iwl_write32(trans, CSR_RESET,
2110                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2111                 }
2112
2113 err:
2114                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2115                 return false;
2116         }
2117
2118 out:
2119         /*
2120          * Fool sparse by faking we release the lock - sparse will
2121          * track nic_access anyway.
2122          */
2123         __release(&trans_pcie->reg_lock);
2124         return true;
2125 }
2126
2127 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2128                                               unsigned long *flags)
2129 {
2130         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2131
2132         lockdep_assert_held(&trans_pcie->reg_lock);
2133
2134         /*
2135          * Fool sparse by faking we acquiring the lock - sparse will
2136          * track nic_access anyway.
2137          */
2138         __acquire(&trans_pcie->reg_lock);
2139
2140         if (trans_pcie->cmd_hold_nic_awake)
2141                 goto out;
2142
2143         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2144                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2145         /*
2146          * Above we read the CSR_GP_CNTRL register, which will flush
2147          * any previous writes, but we need the write that clears the
2148          * MAC_ACCESS_REQ bit to be performed before any other writes
2149          * scheduled on different CPUs (after we drop reg_lock).
2150          */
2151 out:
2152         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2153 }
2154
2155 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2156                                    void *buf, int dwords)
2157 {
2158         unsigned long flags;
2159         int offs = 0;
2160         u32 *vals = buf;
2161
2162         while (offs < dwords) {
2163                 /* limit the time we spin here under lock to 1/2s */
2164                 ktime_t timeout = ktime_add_us(ktime_get(), 500 * USEC_PER_MSEC);
2165
2166                 if (iwl_trans_grab_nic_access(trans, &flags)) {
2167                         iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2168                                     addr + 4 * offs);
2169
2170                         while (offs < dwords) {
2171                                 vals[offs] = iwl_read32(trans,
2172                                                         HBUS_TARG_MEM_RDAT);
2173                                 offs++;
2174
2175                                 /* calling ktime_get is expensive so
2176                                  * do it once in 128 reads
2177                                  */
2178                                 if (offs % 128 == 0 && ktime_after(ktime_get(),
2179                                                                    timeout))
2180                                         break;
2181                         }
2182                         iwl_trans_release_nic_access(trans, &flags);
2183                 } else {
2184                         return -EBUSY;
2185                 }
2186         }
2187
2188         return 0;
2189 }
2190
2191 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2192                                     const void *buf, int dwords)
2193 {
2194         unsigned long flags;
2195         int offs, ret = 0;
2196         const u32 *vals = buf;
2197
2198         if (iwl_trans_grab_nic_access(trans, &flags)) {
2199                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2200                 for (offs = 0; offs < dwords; offs++)
2201                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2202                                     vals ? vals[offs] : 0);
2203                 iwl_trans_release_nic_access(trans, &flags);
2204         } else {
2205                 ret = -EBUSY;
2206         }
2207         return ret;
2208 }
2209
2210 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2211                                         u32 *val)
2212 {
2213         return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2214                                      ofs, val);
2215 }
2216
2217 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2218                                             unsigned long txqs,
2219                                             bool freeze)
2220 {
2221         int queue;
2222
2223         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2224                 struct iwl_txq *txq = trans->txqs.txq[queue];
2225                 unsigned long now;
2226
2227                 spin_lock_bh(&txq->lock);
2228
2229                 now = jiffies;
2230
2231                 if (txq->frozen == freeze)
2232                         goto next_queue;
2233
2234                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2235                                     freeze ? "Freezing" : "Waking", queue);
2236
2237                 txq->frozen = freeze;
2238
2239                 if (txq->read_ptr == txq->write_ptr)
2240                         goto next_queue;
2241
2242                 if (freeze) {
2243                         if (unlikely(time_after(now,
2244                                                 txq->stuck_timer.expires))) {
2245                                 /*
2246                                  * The timer should have fired, maybe it is
2247                                  * spinning right now on the lock.
2248                                  */
2249                                 goto next_queue;
2250                         }
2251                         /* remember how long until the timer fires */
2252                         txq->frozen_expiry_remainder =
2253                                 txq->stuck_timer.expires - now;
2254                         del_timer(&txq->stuck_timer);
2255                         goto next_queue;
2256                 }
2257
2258                 /*
2259                  * Wake a non-empty queue -> arm timer with the
2260                  * remainder before it froze
2261                  */
2262                 mod_timer(&txq->stuck_timer,
2263                           now + txq->frozen_expiry_remainder);
2264
2265 next_queue:
2266                 spin_unlock_bh(&txq->lock);
2267         }
2268 }
2269
2270 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2271 {
2272         int i;
2273
2274         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2275                 struct iwl_txq *txq = trans->txqs.txq[i];
2276
2277                 if (i == trans->txqs.cmd.q_id)
2278                         continue;
2279
2280                 spin_lock_bh(&txq->lock);
2281
2282                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2283                         txq->block--;
2284                         if (!txq->block) {
2285                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2286                                             txq->write_ptr | (i << 8));
2287                         }
2288                 } else if (block) {
2289                         txq->block++;
2290                 }
2291
2292                 spin_unlock_bh(&txq->lock);
2293         }
2294 }
2295
2296 #define IWL_FLUSH_WAIT_MS       2000
2297
2298 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2299                                        struct iwl_trans_rxq_dma_data *data)
2300 {
2301         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2302
2303         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2304                 return -EINVAL;
2305
2306         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2307         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2308         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2309         data->fr_bd_wid = 0;
2310
2311         return 0;
2312 }
2313
2314 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2315 {
2316         struct iwl_txq *txq;
2317         unsigned long now = jiffies;
2318         bool overflow_tx;
2319         u8 wr_ptr;
2320
2321         /* Make sure the NIC is still alive in the bus */
2322         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2323                 return -ENODEV;
2324
2325         if (!test_bit(txq_idx, trans->txqs.queue_used))
2326                 return -EINVAL;
2327
2328         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2329         txq = trans->txqs.txq[txq_idx];
2330
2331         spin_lock_bh(&txq->lock);
2332         overflow_tx = txq->overflow_tx ||
2333                       !skb_queue_empty(&txq->overflow_q);
2334         spin_unlock_bh(&txq->lock);
2335
2336         wr_ptr = READ_ONCE(txq->write_ptr);
2337
2338         while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2339                 overflow_tx) &&
2340                !time_after(jiffies,
2341                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2342                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2343
2344                 /*
2345                  * If write pointer moved during the wait, warn only
2346                  * if the TX came from op mode. In case TX came from
2347                  * trans layer (overflow TX) don't warn.
2348                  */
2349                 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2350                               "WR pointer moved while flushing %d -> %d\n",
2351                               wr_ptr, write_ptr))
2352                         return -ETIMEDOUT;
2353                 wr_ptr = write_ptr;
2354
2355                 usleep_range(1000, 2000);
2356
2357                 spin_lock_bh(&txq->lock);
2358                 overflow_tx = txq->overflow_tx ||
2359                               !skb_queue_empty(&txq->overflow_q);
2360                 spin_unlock_bh(&txq->lock);
2361         }
2362
2363         if (txq->read_ptr != txq->write_ptr) {
2364                 IWL_ERR(trans,
2365                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2366                 iwl_txq_log_scd_error(trans, txq);
2367                 return -ETIMEDOUT;
2368         }
2369
2370         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2371
2372         return 0;
2373 }
2374
2375 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2376 {
2377         int cnt;
2378         int ret = 0;
2379
2380         /* waiting for all the tx frames complete might take a while */
2381         for (cnt = 0;
2382              cnt < trans->trans_cfg->base_params->num_of_queues;
2383              cnt++) {
2384
2385                 if (cnt == trans->txqs.cmd.q_id)
2386                         continue;
2387                 if (!test_bit(cnt, trans->txqs.queue_used))
2388                         continue;
2389                 if (!(BIT(cnt) & txq_bm))
2390                         continue;
2391
2392                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2393                 if (ret)
2394                         break;
2395         }
2396
2397         return ret;
2398 }
2399
2400 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2401                                          u32 mask, u32 value)
2402 {
2403         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2404         unsigned long flags;
2405
2406         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2407         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2408         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2409 }
2410
2411 static const char *get_csr_string(int cmd)
2412 {
2413 #define IWL_CMD(x) case x: return #x
2414         switch (cmd) {
2415         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2416         IWL_CMD(CSR_INT_COALESCING);
2417         IWL_CMD(CSR_INT);
2418         IWL_CMD(CSR_INT_MASK);
2419         IWL_CMD(CSR_FH_INT_STATUS);
2420         IWL_CMD(CSR_GPIO_IN);
2421         IWL_CMD(CSR_RESET);
2422         IWL_CMD(CSR_GP_CNTRL);
2423         IWL_CMD(CSR_HW_REV);
2424         IWL_CMD(CSR_EEPROM_REG);
2425         IWL_CMD(CSR_EEPROM_GP);
2426         IWL_CMD(CSR_OTP_GP_REG);
2427         IWL_CMD(CSR_GIO_REG);
2428         IWL_CMD(CSR_GP_UCODE_REG);
2429         IWL_CMD(CSR_GP_DRIVER_REG);
2430         IWL_CMD(CSR_UCODE_DRV_GP1);
2431         IWL_CMD(CSR_UCODE_DRV_GP2);
2432         IWL_CMD(CSR_LED_REG);
2433         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2434         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2435         IWL_CMD(CSR_ANA_PLL_CFG);
2436         IWL_CMD(CSR_HW_REV_WA_REG);
2437         IWL_CMD(CSR_MONITOR_STATUS_REG);
2438         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2439         default:
2440                 return "UNKNOWN";
2441         }
2442 #undef IWL_CMD
2443 }
2444
2445 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2446 {
2447         int i;
2448         static const u32 csr_tbl[] = {
2449                 CSR_HW_IF_CONFIG_REG,
2450                 CSR_INT_COALESCING,
2451                 CSR_INT,
2452                 CSR_INT_MASK,
2453                 CSR_FH_INT_STATUS,
2454                 CSR_GPIO_IN,
2455                 CSR_RESET,
2456                 CSR_GP_CNTRL,
2457                 CSR_HW_REV,
2458                 CSR_EEPROM_REG,
2459                 CSR_EEPROM_GP,
2460                 CSR_OTP_GP_REG,
2461                 CSR_GIO_REG,
2462                 CSR_GP_UCODE_REG,
2463                 CSR_GP_DRIVER_REG,
2464                 CSR_UCODE_DRV_GP1,
2465                 CSR_UCODE_DRV_GP2,
2466                 CSR_LED_REG,
2467                 CSR_DRAM_INT_TBL_REG,
2468                 CSR_GIO_CHICKEN_BITS,
2469                 CSR_ANA_PLL_CFG,
2470                 CSR_MONITOR_STATUS_REG,
2471                 CSR_HW_REV_WA_REG,
2472                 CSR_DBG_HPET_MEM_REG
2473         };
2474         IWL_ERR(trans, "CSR values:\n");
2475         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2476                 "CSR_INT_PERIODIC_REG)\n");
2477         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2478                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2479                         get_csr_string(csr_tbl[i]),
2480                         iwl_read32(trans, csr_tbl[i]));
2481         }
2482 }
2483
2484 #ifdef CONFIG_IWLWIFI_DEBUGFS
2485 /* create and remove of files */
2486 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2487         debugfs_create_file(#name, mode, parent, trans,                 \
2488                             &iwl_dbgfs_##name##_ops);                   \
2489 } while (0)
2490
2491 /* file operation */
2492 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2493 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2494         .read = iwl_dbgfs_##name##_read,                                \
2495         .open = simple_open,                                            \
2496         .llseek = generic_file_llseek,                                  \
2497 };
2498
2499 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2500 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2501         .write = iwl_dbgfs_##name##_write,                              \
2502         .open = simple_open,                                            \
2503         .llseek = generic_file_llseek,                                  \
2504 };
2505
2506 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2507 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2508         .write = iwl_dbgfs_##name##_write,                              \
2509         .read = iwl_dbgfs_##name##_read,                                \
2510         .open = simple_open,                                            \
2511         .llseek = generic_file_llseek,                                  \
2512 };
2513
2514 struct iwl_dbgfs_tx_queue_priv {
2515         struct iwl_trans *trans;
2516 };
2517
2518 struct iwl_dbgfs_tx_queue_state {
2519         loff_t pos;
2520 };
2521
2522 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2523 {
2524         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2525         struct iwl_dbgfs_tx_queue_state *state;
2526
2527         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2528                 return NULL;
2529
2530         state = kmalloc(sizeof(*state), GFP_KERNEL);
2531         if (!state)
2532                 return NULL;
2533         state->pos = *pos;
2534         return state;
2535 }
2536
2537 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2538                                          void *v, loff_t *pos)
2539 {
2540         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2541         struct iwl_dbgfs_tx_queue_state *state = v;
2542
2543         *pos = ++state->pos;
2544
2545         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2546                 return NULL;
2547
2548         return state;
2549 }
2550
2551 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2552 {
2553         kfree(v);
2554 }
2555
2556 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2557 {
2558         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2559         struct iwl_dbgfs_tx_queue_state *state = v;
2560         struct iwl_trans *trans = priv->trans;
2561         struct iwl_txq *txq = trans->txqs.txq[state->pos];
2562
2563         seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2564                    (unsigned int)state->pos,
2565                    !!test_bit(state->pos, trans->txqs.queue_used),
2566                    !!test_bit(state->pos, trans->txqs.queue_stopped));
2567         if (txq)
2568                 seq_printf(seq,
2569                            "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2570                            txq->read_ptr, txq->write_ptr,
2571                            txq->need_update, txq->frozen,
2572                            txq->n_window, txq->ampdu);
2573         else
2574                 seq_puts(seq, "(unallocated)");
2575
2576         if (state->pos == trans->txqs.cmd.q_id)
2577                 seq_puts(seq, " (HCMD)");
2578         seq_puts(seq, "\n");
2579
2580         return 0;
2581 }
2582
2583 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2584         .start = iwl_dbgfs_tx_queue_seq_start,
2585         .next = iwl_dbgfs_tx_queue_seq_next,
2586         .stop = iwl_dbgfs_tx_queue_seq_stop,
2587         .show = iwl_dbgfs_tx_queue_seq_show,
2588 };
2589
2590 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2591 {
2592         struct iwl_dbgfs_tx_queue_priv *priv;
2593
2594         priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2595                                   sizeof(*priv));
2596
2597         if (!priv)
2598                 return -ENOMEM;
2599
2600         priv->trans = inode->i_private;
2601         return 0;
2602 }
2603
2604 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2605                                        char __user *user_buf,
2606                                        size_t count, loff_t *ppos)
2607 {
2608         struct iwl_trans *trans = file->private_data;
2609         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2610         char *buf;
2611         int pos = 0, i, ret;
2612         size_t bufsz;
2613
2614         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2615
2616         if (!trans_pcie->rxq)
2617                 return -EAGAIN;
2618
2619         buf = kzalloc(bufsz, GFP_KERNEL);
2620         if (!buf)
2621                 return -ENOMEM;
2622
2623         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2624                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2625
2626                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2627                                  i);
2628                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2629                                  rxq->read);
2630                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2631                                  rxq->write);
2632                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2633                                  rxq->write_actual);
2634                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2635                                  rxq->need_update);
2636                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2637                                  rxq->free_count);
2638                 if (rxq->rb_stts) {
2639                         u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2640                                                                      rxq));
2641                         pos += scnprintf(buf + pos, bufsz - pos,
2642                                          "\tclosed_rb_num: %u\n",
2643                                          r & 0x0FFF);
2644                 } else {
2645                         pos += scnprintf(buf + pos, bufsz - pos,
2646                                          "\tclosed_rb_num: Not Allocated\n");
2647                 }
2648         }
2649         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2650         kfree(buf);
2651
2652         return ret;
2653 }
2654
2655 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2656                                         char __user *user_buf,
2657                                         size_t count, loff_t *ppos)
2658 {
2659         struct iwl_trans *trans = file->private_data;
2660         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2661         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2662
2663         int pos = 0;
2664         char *buf;
2665         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2666         ssize_t ret;
2667
2668         buf = kzalloc(bufsz, GFP_KERNEL);
2669         if (!buf)
2670                 return -ENOMEM;
2671
2672         pos += scnprintf(buf + pos, bufsz - pos,
2673                         "Interrupt Statistics Report:\n");
2674
2675         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2676                 isr_stats->hw);
2677         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2678                 isr_stats->sw);
2679         if (isr_stats->sw || isr_stats->hw) {
2680                 pos += scnprintf(buf + pos, bufsz - pos,
2681                         "\tLast Restarting Code:  0x%X\n",
2682                         isr_stats->err_code);
2683         }
2684 #ifdef CONFIG_IWLWIFI_DEBUG
2685         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2686                 isr_stats->sch);
2687         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2688                 isr_stats->alive);
2689 #endif
2690         pos += scnprintf(buf + pos, bufsz - pos,
2691                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2692
2693         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2694                 isr_stats->ctkill);
2695
2696         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2697                 isr_stats->wakeup);
2698
2699         pos += scnprintf(buf + pos, bufsz - pos,
2700                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2701
2702         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2703                 isr_stats->tx);
2704
2705         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2706                 isr_stats->unhandled);
2707
2708         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2709         kfree(buf);
2710         return ret;
2711 }
2712
2713 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2714                                          const char __user *user_buf,
2715                                          size_t count, loff_t *ppos)
2716 {
2717         struct iwl_trans *trans = file->private_data;
2718         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2719         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2720         u32 reset_flag;
2721         int ret;
2722
2723         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2724         if (ret)
2725                 return ret;
2726         if (reset_flag == 0)
2727                 memset(isr_stats, 0, sizeof(*isr_stats));
2728
2729         return count;
2730 }
2731
2732 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2733                                    const char __user *user_buf,
2734                                    size_t count, loff_t *ppos)
2735 {
2736         struct iwl_trans *trans = file->private_data;
2737
2738         iwl_pcie_dump_csr(trans);
2739
2740         return count;
2741 }
2742
2743 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2744                                      char __user *user_buf,
2745                                      size_t count, loff_t *ppos)
2746 {
2747         struct iwl_trans *trans = file->private_data;
2748         char *buf = NULL;
2749         ssize_t ret;
2750
2751         ret = iwl_dump_fh(trans, &buf);
2752         if (ret < 0)
2753                 return ret;
2754         if (!buf)
2755                 return -EINVAL;
2756         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2757         kfree(buf);
2758         return ret;
2759 }
2760
2761 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2762                                      char __user *user_buf,
2763                                      size_t count, loff_t *ppos)
2764 {
2765         struct iwl_trans *trans = file->private_data;
2766         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2767         char buf[100];
2768         int pos;
2769
2770         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2771                         trans_pcie->debug_rfkill,
2772                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2773                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2774
2775         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2776 }
2777
2778 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2779                                       const char __user *user_buf,
2780                                       size_t count, loff_t *ppos)
2781 {
2782         struct iwl_trans *trans = file->private_data;
2783         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2784         bool new_value;
2785         int ret;
2786
2787         ret = kstrtobool_from_user(user_buf, count, &new_value);
2788         if (ret)
2789                 return ret;
2790         if (new_value == trans_pcie->debug_rfkill)
2791                 return count;
2792         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2793                  trans_pcie->debug_rfkill, new_value);
2794         trans_pcie->debug_rfkill = new_value;
2795         iwl_pcie_handle_rfkill_irq(trans);
2796
2797         return count;
2798 }
2799
2800 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2801                                        struct file *file)
2802 {
2803         struct iwl_trans *trans = inode->i_private;
2804         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2805
2806         if (!trans->dbg.dest_tlv ||
2807             trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2808                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2809                 return -ENOENT;
2810         }
2811
2812         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2813                 return -EBUSY;
2814
2815         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2816         return simple_open(inode, file);
2817 }
2818
2819 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2820                                           struct file *file)
2821 {
2822         struct iwl_trans_pcie *trans_pcie =
2823                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2824
2825         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2826                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2827         return 0;
2828 }
2829
2830 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2831                                   void *buf, ssize_t *size,
2832                                   ssize_t *bytes_copied)
2833 {
2834         int buf_size_left = count - *bytes_copied;
2835
2836         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2837         if (*size > buf_size_left)
2838                 *size = buf_size_left;
2839
2840         *size -= copy_to_user(user_buf, buf, *size);
2841         *bytes_copied += *size;
2842
2843         if (buf_size_left == *size)
2844                 return true;
2845         return false;
2846 }
2847
2848 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2849                                            char __user *user_buf,
2850                                            size_t count, loff_t *ppos)
2851 {
2852         struct iwl_trans *trans = file->private_data;
2853         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2854         void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2855         struct cont_rec *data = &trans_pcie->fw_mon_data;
2856         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2857         ssize_t size, bytes_copied = 0;
2858         bool b_full;
2859
2860         if (trans->dbg.dest_tlv) {
2861                 write_ptr_addr =
2862                         le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2863                 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2864         } else {
2865                 write_ptr_addr = MON_BUFF_WRPTR;
2866                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2867         }
2868
2869         if (unlikely(!trans->dbg.rec_on))
2870                 return 0;
2871
2872         mutex_lock(&data->mutex);
2873         if (data->state ==
2874             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2875                 mutex_unlock(&data->mutex);
2876                 return 0;
2877         }
2878
2879         /* write_ptr position in bytes rather then DW */
2880         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2881         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2882
2883         if (data->prev_wrap_cnt == wrap_cnt) {
2884                 size = write_ptr - data->prev_wr_ptr;
2885                 curr_buf = cpu_addr + data->prev_wr_ptr;
2886                 b_full = iwl_write_to_user_buf(user_buf, count,
2887                                                curr_buf, &size,
2888                                                &bytes_copied);
2889                 data->prev_wr_ptr += size;
2890
2891         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2892                    write_ptr < data->prev_wr_ptr) {
2893                 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2894                 curr_buf = cpu_addr + data->prev_wr_ptr;
2895                 b_full = iwl_write_to_user_buf(user_buf, count,
2896                                                curr_buf, &size,
2897                                                &bytes_copied);
2898                 data->prev_wr_ptr += size;
2899
2900                 if (!b_full) {
2901                         size = write_ptr;
2902                         b_full = iwl_write_to_user_buf(user_buf, count,
2903                                                        cpu_addr, &size,
2904                                                        &bytes_copied);
2905                         data->prev_wr_ptr = size;
2906                         data->prev_wrap_cnt++;
2907                 }
2908         } else {
2909                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2910                     write_ptr > data->prev_wr_ptr)
2911                         IWL_WARN(trans,
2912                                  "write pointer passed previous write pointer, start copying from the beginning\n");
2913                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2914                                    data->prev_wr_ptr == 0))
2915                         IWL_WARN(trans,
2916                                  "monitor data is out of sync, start copying from the beginning\n");
2917
2918                 size = write_ptr;
2919                 b_full = iwl_write_to_user_buf(user_buf, count,
2920                                                cpu_addr, &size,
2921                                                &bytes_copied);
2922                 data->prev_wr_ptr = size;
2923                 data->prev_wrap_cnt = wrap_cnt;
2924         }
2925
2926         mutex_unlock(&data->mutex);
2927
2928         return bytes_copied;
2929 }
2930
2931 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2932 DEBUGFS_READ_FILE_OPS(fh_reg);
2933 DEBUGFS_READ_FILE_OPS(rx_queue);
2934 DEBUGFS_WRITE_FILE_OPS(csr);
2935 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2936 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2937         .owner = THIS_MODULE,
2938         .open = iwl_dbgfs_tx_queue_open,
2939         .read = seq_read,
2940         .llseek = seq_lseek,
2941         .release = seq_release_private,
2942 };
2943
2944 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2945         .read = iwl_dbgfs_monitor_data_read,
2946         .open = iwl_dbgfs_monitor_data_open,
2947         .release = iwl_dbgfs_monitor_data_release,
2948 };
2949
2950 /* Create the debugfs files and directories */
2951 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2952 {
2953         struct dentry *dir = trans->dbgfs_dir;
2954
2955         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2956         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2957         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2958         DEBUGFS_ADD_FILE(csr, dir, 0200);
2959         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2960         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2961         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2962 }
2963
2964 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2965 {
2966         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2967         struct cont_rec *data = &trans_pcie->fw_mon_data;
2968
2969         mutex_lock(&data->mutex);
2970         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2971         mutex_unlock(&data->mutex);
2972 }
2973 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2974
2975 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2976 {
2977         u32 cmdlen = 0;
2978         int i;
2979
2980         for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
2981                 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
2982
2983         return cmdlen;
2984 }
2985
2986 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2987                                    struct iwl_fw_error_dump_data **data,
2988                                    int allocated_rb_nums)
2989 {
2990         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2991         int max_len = trans_pcie->rx_buf_bytes;
2992         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2993         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2994         u32 i, r, j, rb_len = 0;
2995
2996         spin_lock(&rxq->lock);
2997
2998         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2999
3000         for (i = rxq->read, j = 0;
3001              i != r && j < allocated_rb_nums;
3002              i = (i + 1) & RX_QUEUE_MASK, j++) {
3003                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3004                 struct iwl_fw_error_dump_rb *rb;
3005
3006                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
3007                                DMA_FROM_DEVICE);
3008
3009                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3010
3011                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3012                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3013                 rb = (void *)(*data)->data;
3014                 rb->index = cpu_to_le32(i);
3015                 memcpy(rb->data, page_address(rxb->page), max_len);
3016                 /* remap the page for the free benefit */
3017                 rxb->page_dma = dma_map_page(trans->dev, rxb->page,
3018                                              rxb->offset, max_len,
3019                                              DMA_FROM_DEVICE);
3020
3021                 *data = iwl_fw_error_next_data(*data);
3022         }
3023
3024         spin_unlock(&rxq->lock);
3025
3026         return rb_len;
3027 }
3028 #define IWL_CSR_TO_DUMP (0x250)
3029
3030 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3031                                    struct iwl_fw_error_dump_data **data)
3032 {
3033         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3034         __le32 *val;
3035         int i;
3036
3037         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3038         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3039         val = (void *)(*data)->data;
3040
3041         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3042                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3043
3044         *data = iwl_fw_error_next_data(*data);
3045
3046         return csr_len;
3047 }
3048
3049 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3050                                        struct iwl_fw_error_dump_data **data)
3051 {
3052         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3053         unsigned long flags;
3054         __le32 *val;
3055         int i;
3056
3057         if (!iwl_trans_grab_nic_access(trans, &flags))
3058                 return 0;
3059
3060         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3061         (*data)->len = cpu_to_le32(fh_regs_len);
3062         val = (void *)(*data)->data;
3063
3064         if (!trans->trans_cfg->gen2)
3065                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3066                      i += sizeof(u32))
3067                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3068         else
3069                 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3070                      i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3071                      i += sizeof(u32))
3072                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3073                                                                       i));
3074
3075         iwl_trans_release_nic_access(trans, &flags);
3076
3077         *data = iwl_fw_error_next_data(*data);
3078
3079         return sizeof(**data) + fh_regs_len;
3080 }
3081
3082 static u32
3083 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3084                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3085                                  u32 monitor_len)
3086 {
3087         u32 buf_size_in_dwords = (monitor_len >> 2);
3088         u32 *buffer = (u32 *)fw_mon_data->data;
3089         unsigned long flags;
3090         u32 i;
3091
3092         if (!iwl_trans_grab_nic_access(trans, &flags))
3093                 return 0;
3094
3095         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3096         for (i = 0; i < buf_size_in_dwords; i++)
3097                 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3098                                                        MON_DMARB_RD_DATA_ADDR);
3099         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3100
3101         iwl_trans_release_nic_access(trans, &flags);
3102
3103         return monitor_len;
3104 }
3105
3106 static void
3107 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3108                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3109 {
3110         u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3111
3112         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3113                 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3114                 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3115                 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3116                 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3117         } else if (trans->dbg.dest_tlv) {
3118                 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3119                 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3120                 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3121         } else {
3122                 base = MON_BUFF_BASE_ADDR;
3123                 write_ptr = MON_BUFF_WRPTR;
3124                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3125         }
3126
3127         write_ptr_val = iwl_read_prph(trans, write_ptr);
3128         fw_mon_data->fw_mon_cycle_cnt =
3129                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3130         fw_mon_data->fw_mon_base_ptr =
3131                 cpu_to_le32(iwl_read_prph(trans, base));
3132         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3133                 fw_mon_data->fw_mon_base_high_ptr =
3134                         cpu_to_le32(iwl_read_prph(trans, base_high));
3135                 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3136         }
3137         fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3138 }
3139
3140 static u32
3141 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3142                             struct iwl_fw_error_dump_data **data,
3143                             u32 monitor_len)
3144 {
3145         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3146         u32 len = 0;
3147
3148         if (trans->dbg.dest_tlv ||
3149             (fw_mon->size &&
3150              (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3151               trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3152                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3153
3154                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3155                 fw_mon_data = (void *)(*data)->data;
3156
3157                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3158
3159                 len += sizeof(**data) + sizeof(*fw_mon_data);
3160                 if (fw_mon->size) {
3161                         memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3162                         monitor_len = fw_mon->size;
3163                 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3164                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3165                         /*
3166                          * Update pointers to reflect actual values after
3167                          * shifting
3168                          */
3169                         if (trans->dbg.dest_tlv->version) {
3170                                 base = (iwl_read_prph(trans, base) &
3171                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3172                                        trans->dbg.dest_tlv->base_shift;
3173                                 base *= IWL_M2S_UNIT_SIZE;
3174                                 base += trans->cfg->smem_offset;
3175                         } else {
3176                                 base = iwl_read_prph(trans, base) <<
3177                                        trans->dbg.dest_tlv->base_shift;
3178                         }
3179
3180                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3181                                            monitor_len / sizeof(u32));
3182                 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3183                         monitor_len =
3184                                 iwl_trans_pci_dump_marbh_monitor(trans,
3185                                                                  fw_mon_data,
3186                                                                  monitor_len);
3187                 } else {
3188                         /* Didn't match anything - output no monitor data */
3189                         monitor_len = 0;
3190                 }
3191
3192                 len += monitor_len;
3193                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3194         }
3195
3196         return len;
3197 }
3198
3199 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3200 {
3201         if (trans->dbg.fw_mon.size) {
3202                 *len += sizeof(struct iwl_fw_error_dump_data) +
3203                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3204                         trans->dbg.fw_mon.size;
3205                 return trans->dbg.fw_mon.size;
3206         } else if (trans->dbg.dest_tlv) {
3207                 u32 base, end, cfg_reg, monitor_len;
3208
3209                 if (trans->dbg.dest_tlv->version == 1) {
3210                         cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3211                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3212                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3213                                 trans->dbg.dest_tlv->base_shift;
3214                         base *= IWL_M2S_UNIT_SIZE;
3215                         base += trans->cfg->smem_offset;
3216
3217                         monitor_len =
3218                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3219                                 trans->dbg.dest_tlv->end_shift;
3220                         monitor_len *= IWL_M2S_UNIT_SIZE;
3221                 } else {
3222                         base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3223                         end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3224
3225                         base = iwl_read_prph(trans, base) <<
3226                                trans->dbg.dest_tlv->base_shift;
3227                         end = iwl_read_prph(trans, end) <<
3228                               trans->dbg.dest_tlv->end_shift;
3229
3230                         /* Make "end" point to the actual end */
3231                         if (trans->trans_cfg->device_family >=
3232                             IWL_DEVICE_FAMILY_8000 ||
3233                             trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3234                                 end += (1 << trans->dbg.dest_tlv->end_shift);
3235                         monitor_len = end - base;
3236                 }
3237                 *len += sizeof(struct iwl_fw_error_dump_data) +
3238                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3239                         monitor_len;
3240                 return monitor_len;
3241         }
3242         return 0;
3243 }
3244
3245 static struct iwl_trans_dump_data
3246 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3247                           u32 dump_mask)
3248 {
3249         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3250         struct iwl_fw_error_dump_data *data;
3251         struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
3252         struct iwl_fw_error_dump_txcmd *txcmd;
3253         struct iwl_trans_dump_data *dump_data;
3254         u32 len, num_rbs = 0, monitor_len = 0;
3255         int i, ptr;
3256         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3257                         !trans->trans_cfg->mq_rx_supported &&
3258                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3259
3260         if (!dump_mask)
3261                 return NULL;
3262
3263         /* transport dump header */
3264         len = sizeof(*dump_data);
3265
3266         /* host commands */
3267         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3268                 len += sizeof(*data) +
3269                         cmdq->n_window * (sizeof(*txcmd) +
3270                                           TFD_MAX_PAYLOAD_SIZE);
3271
3272         /* FW monitor */
3273         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3274                 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3275
3276         /* CSR registers */
3277         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3278                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3279
3280         /* FH registers */
3281         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3282                 if (trans->trans_cfg->gen2)
3283                         len += sizeof(*data) +
3284                                (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3285                                 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3286                 else
3287                         len += sizeof(*data) +
3288                                (FH_MEM_UPPER_BOUND -
3289                                 FH_MEM_LOWER_BOUND);
3290         }
3291
3292         if (dump_rbs) {
3293                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3294                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3295                 /* RBs */
3296                 num_rbs =
3297                         le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3298                         & 0x0FFF;
3299                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3300                 len += num_rbs * (sizeof(*data) +
3301                                   sizeof(struct iwl_fw_error_dump_rb) +
3302                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3303         }
3304
3305         /* Paged memory for gen2 HW */
3306         if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3307                 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3308                         len += sizeof(*data) +
3309                                sizeof(struct iwl_fw_error_dump_paging) +
3310                                trans->init_dram.paging[i].size;
3311
3312         dump_data = vzalloc(len);
3313         if (!dump_data)
3314                 return NULL;
3315
3316         len = 0;
3317         data = (void *)dump_data->data;
3318
3319         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3320                 u16 tfd_size = trans->txqs.tfd.size;
3321
3322                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3323                 txcmd = (void *)data->data;
3324                 spin_lock_bh(&cmdq->lock);
3325                 ptr = cmdq->write_ptr;
3326                 for (i = 0; i < cmdq->n_window; i++) {
3327                         u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3328                         u8 tfdidx;
3329                         u32 caplen, cmdlen;
3330
3331                         if (trans->trans_cfg->use_tfh)
3332                                 tfdidx = idx;
3333                         else
3334                                 tfdidx = ptr;
3335
3336                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3337                                                            (u8 *)cmdq->tfds +
3338                                                            tfd_size * tfdidx);
3339                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3340
3341                         if (cmdlen) {
3342                                 len += sizeof(*txcmd) + caplen;
3343                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3344                                 txcmd->caplen = cpu_to_le32(caplen);
3345                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3346                                        caplen);
3347                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3348                         }
3349
3350                         ptr = iwl_txq_dec_wrap(trans, ptr);
3351                 }
3352                 spin_unlock_bh(&cmdq->lock);
3353
3354                 data->len = cpu_to_le32(len);
3355                 len += sizeof(*data);
3356                 data = iwl_fw_error_next_data(data);
3357         }
3358
3359         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3360                 len += iwl_trans_pcie_dump_csr(trans, &data);
3361         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3362                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3363         if (dump_rbs)
3364                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3365
3366         /* Paged memory for gen2 HW */
3367         if (trans->trans_cfg->gen2 &&
3368             dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3369                 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3370                         struct iwl_fw_error_dump_paging *paging;
3371                         u32 page_len = trans->init_dram.paging[i].size;
3372
3373                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3374                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3375                         paging = (void *)data->data;
3376                         paging->index = cpu_to_le32(i);
3377                         memcpy(paging->data,
3378                                trans->init_dram.paging[i].block, page_len);
3379                         data = iwl_fw_error_next_data(data);
3380
3381                         len += sizeof(*data) + sizeof(*paging) + page_len;
3382                 }
3383         }
3384         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3385                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3386
3387         dump_data->len = len;
3388
3389         return dump_data;
3390 }
3391
3392 #ifdef CONFIG_PM_SLEEP
3393 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3394 {
3395         return 0;
3396 }
3397
3398 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3399 {
3400 }
3401 #endif /* CONFIG_PM_SLEEP */
3402
3403 #define IWL_TRANS_COMMON_OPS                                            \
3404         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3405         .write8 = iwl_trans_pcie_write8,                                \
3406         .write32 = iwl_trans_pcie_write32,                              \
3407         .read32 = iwl_trans_pcie_read32,                                \
3408         .read_prph = iwl_trans_pcie_read_prph,                          \
3409         .write_prph = iwl_trans_pcie_write_prph,                        \
3410         .read_mem = iwl_trans_pcie_read_mem,                            \
3411         .write_mem = iwl_trans_pcie_write_mem,                          \
3412         .read_config32 = iwl_trans_pcie_read_config32,                  \
3413         .configure = iwl_trans_pcie_configure,                          \
3414         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3415         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3416         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3417         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3418         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3419         .dump_data = iwl_trans_pcie_dump_data,                          \
3420         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3421         .d3_resume = iwl_trans_pcie_d3_resume,                          \
3422         .sync_nmi = iwl_trans_pcie_sync_nmi
3423
3424 #ifdef CONFIG_PM_SLEEP
3425 #define IWL_TRANS_PM_OPS                                                \
3426         .suspend = iwl_trans_pcie_suspend,                              \
3427         .resume = iwl_trans_pcie_resume,
3428 #else
3429 #define IWL_TRANS_PM_OPS
3430 #endif /* CONFIG_PM_SLEEP */
3431
3432 static const struct iwl_trans_ops trans_ops_pcie = {
3433         IWL_TRANS_COMMON_OPS,
3434         IWL_TRANS_PM_OPS
3435         .start_hw = iwl_trans_pcie_start_hw,
3436         .fw_alive = iwl_trans_pcie_fw_alive,
3437         .start_fw = iwl_trans_pcie_start_fw,
3438         .stop_device = iwl_trans_pcie_stop_device,
3439
3440         .send_cmd = iwl_trans_pcie_send_hcmd,
3441
3442         .tx = iwl_trans_pcie_tx,
3443         .reclaim = iwl_trans_pcie_reclaim,
3444
3445         .txq_disable = iwl_trans_pcie_txq_disable,
3446         .txq_enable = iwl_trans_pcie_txq_enable,
3447
3448         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3449
3450         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3451
3452         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3453         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3454 #ifdef CONFIG_IWLWIFI_DEBUGFS
3455         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3456 #endif
3457 };
3458
3459 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3460         IWL_TRANS_COMMON_OPS,
3461         IWL_TRANS_PM_OPS
3462         .start_hw = iwl_trans_pcie_start_hw,
3463         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3464         .start_fw = iwl_trans_pcie_gen2_start_fw,
3465         .stop_device = iwl_trans_pcie_gen2_stop_device,
3466
3467         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3468
3469         .tx = iwl_txq_gen2_tx,
3470         .reclaim = iwl_trans_pcie_reclaim,
3471
3472         .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3473
3474         .txq_alloc = iwl_txq_dyn_alloc,
3475         .txq_free = iwl_txq_dyn_free,
3476         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3477         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3478         .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3479 #ifdef CONFIG_IWLWIFI_DEBUGFS
3480         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3481 #endif
3482 };
3483
3484 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3485                                const struct pci_device_id *ent,
3486                                const struct iwl_cfg_trans_params *cfg_trans)
3487 {
3488         struct iwl_trans_pcie *trans_pcie;
3489         struct iwl_trans *trans;
3490         int ret, addr_size;
3491         const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3492
3493         if (!cfg_trans->gen2)
3494                 ops = &trans_ops_pcie;
3495
3496         ret = pcim_enable_device(pdev);
3497         if (ret)
3498                 return ERR_PTR(ret);
3499
3500         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3501                                 cfg_trans);
3502         if (!trans)
3503                 return ERR_PTR(-ENOMEM);
3504
3505         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3506
3507         trans_pcie->trans = trans;
3508         trans_pcie->opmode_down = true;
3509         spin_lock_init(&trans_pcie->irq_lock);
3510         spin_lock_init(&trans_pcie->reg_lock);
3511         spin_lock_init(&trans_pcie->alloc_page_lock);
3512         mutex_init(&trans_pcie->mutex);
3513         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3514
3515         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3516                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3517         if (!trans_pcie->rba.alloc_wq) {
3518                 ret = -ENOMEM;
3519                 goto out_free_trans;
3520         }
3521         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3522
3523         trans_pcie->debug_rfkill = -1;
3524
3525         if (!cfg_trans->base_params->pcie_l1_allowed) {
3526                 /*
3527                  * W/A - seems to solve weird behavior. We need to remove this
3528                  * if we don't want to stay in L1 all the time. This wastes a
3529                  * lot of power.
3530                  */
3531                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3532                                        PCIE_LINK_STATE_L1 |
3533                                        PCIE_LINK_STATE_CLKPM);
3534         }
3535
3536         trans_pcie->def_rx_queue = 0;
3537
3538         pci_set_master(pdev);
3539
3540         addr_size = trans->txqs.tfd.addr_size;
3541         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3542         if (!ret)
3543                 ret = pci_set_consistent_dma_mask(pdev,
3544                                                   DMA_BIT_MASK(addr_size));
3545         if (ret) {
3546                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3547                 if (!ret)
3548                         ret = pci_set_consistent_dma_mask(pdev,
3549                                                           DMA_BIT_MASK(32));
3550                 /* both attempts failed: */
3551                 if (ret) {
3552                         dev_err(&pdev->dev, "No suitable DMA available\n");
3553                         goto out_no_pci;
3554                 }
3555         }
3556
3557         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3558         if (ret) {
3559                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3560                 goto out_no_pci;
3561         }
3562
3563         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3564         if (!trans_pcie->hw_base) {
3565                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3566                 ret = -ENODEV;
3567                 goto out_no_pci;
3568         }
3569
3570         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3571          * PCI Tx retries from interfering with C3 CPU state */
3572         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3573
3574         trans_pcie->pci_dev = pdev;
3575         iwl_disable_interrupts(trans);
3576
3577         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3578         if (trans->hw_rev == 0xffffffff) {
3579                 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3580                 ret = -EIO;
3581                 goto out_no_pci;
3582         }
3583
3584         /*
3585          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3586          * changed, and now the revision step also includes bit 0-1 (no more
3587          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3588          * in the old format.
3589          */
3590         if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
3591                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3592                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3593
3594                 ret = iwl_pcie_prepare_card_hw(trans);
3595                 if (ret) {
3596                         IWL_WARN(trans, "Exit HW not ready\n");
3597                         goto out_no_pci;
3598                 }
3599
3600                 /*
3601                  * in-order to recognize C step driver should read chip version
3602                  * id located at the AUX bus MISC address space.
3603                  */
3604                 ret = iwl_finish_nic_init(trans, cfg_trans);
3605                 if (ret)
3606                         goto out_no_pci;
3607
3608         }
3609
3610         IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3611
3612         iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3613         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3614         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3615                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3616
3617         /* Initialize the wait queue for commands */
3618         init_waitqueue_head(&trans_pcie->wait_command_queue);
3619
3620         init_waitqueue_head(&trans_pcie->sx_waitq);
3621
3622
3623         if (trans_pcie->msix_enabled) {
3624                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3625                 if (ret)
3626                         goto out_no_pci;
3627          } else {
3628                 ret = iwl_pcie_alloc_ict(trans);
3629                 if (ret)
3630                         goto out_no_pci;
3631
3632                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3633                                                 iwl_pcie_isr,
3634                                                 iwl_pcie_irq_handler,
3635                                                 IRQF_SHARED, DRV_NAME, trans);
3636                 if (ret) {
3637                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3638                         goto out_free_ict;
3639                 }
3640                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3641          }
3642
3643 #ifdef CONFIG_IWLWIFI_DEBUGFS
3644         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3645         mutex_init(&trans_pcie->fw_mon_data.mutex);
3646 #endif
3647
3648         iwl_dbg_tlv_init(trans);
3649
3650         return trans;
3651
3652 out_free_ict:
3653         iwl_pcie_free_ict(trans);
3654 out_no_pci:
3655         destroy_workqueue(trans_pcie->rba.alloc_wq);
3656 out_free_trans:
3657         iwl_trans_free(trans);
3658         return ERR_PTR(ret);
3659 }
3660
3661 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3662 {
3663         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3664         unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
3665         bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
3666         u32 inta_addr, sw_err_bit;
3667
3668         if (trans_pcie->msix_enabled) {
3669                 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3670                 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3671         } else {
3672                 inta_addr = CSR_INT;
3673                 sw_err_bit = CSR_INT_BIT_SW_ERR;
3674         }
3675
3676         /* if the interrupts were already disabled, there is no point in
3677          * calling iwl_disable_interrupts
3678          */
3679         if (interrupts_enabled)
3680                 iwl_disable_interrupts(trans);
3681
3682         iwl_force_nmi(trans);
3683         while (time_after(timeout, jiffies)) {
3684                 u32 inta_hw = iwl_read32(trans, inta_addr);
3685
3686                 /* Error detected by uCode */
3687                 if (inta_hw & sw_err_bit) {
3688                         /* Clear causes register */
3689                         iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
3690                         break;
3691                 }
3692
3693                 mdelay(1);
3694         }
3695
3696         /* enable interrupts only if there were already enabled before this
3697          * function to avoid a case were the driver enable interrupts before
3698          * proper configurations were made
3699          */
3700         if (interrupts_enabled)
3701                 iwl_enable_interrupts(trans);
3702
3703         iwl_trans_fw_error(trans);
3704 }