drivers/net/wireless/intel/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope that it will be useful, but WITHOUT
  18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20  * more details.
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <linuxwifi@intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  * BSD LICENSE
  30  *
  31  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 - 2019 Intel Corporation
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions
  39  * are met:
  40  *
  41  *  * Redistributions of source code must retain the above copyright
  42  *    notice, this list of conditions and the following disclaimer.
  43  *  * Redistributions in binary form must reproduce the above copyright
  44  *    notice, this list of conditions and the following disclaimer in
  45  *    the documentation and/or other materials provided with the
  46  *    distribution.
  47  *  * Neither the name Intel Corporation nor the names of its
  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  56  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  57  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  58  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  59  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/sched.h>
  65 #include <linux/wait.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-prph.h"
  69 #include "iwl-io.h"
  70 #include "internal.h"
  71 #include "iwl-op-mode.h"
  72 #include "iwl-context-info-gen3.h"
  73
  74 /******************************************************************************
  75  *
  76  * RX path functions
  77  *
  78  ******************************************************************************/
  79
  80 /*
  81  * Rx theory of operation
  82  *
  83  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  84  * each of which point to Receive Buffers to be filled by the NIC.  These get
  85  * used not only for Rx frames, but for any command response or notification
  86  * from the NIC.  The driver and NIC manage the Rx buffers by means
  87  * of indexes into the circular buffer.
  88  *
  89  * Rx Queue Indexes
  90  * The host/firmware share two index registers for managing the Rx buffers.
  91  *
  92  * The READ index maps to the first position that the firmware may be writing
  93  * to -- the driver can read up to (but not including) this position and get
  94  * good data.
  95  * The READ index is managed by the firmware once the card is enabled.
  96  *
  97  * The WRITE index maps to the last position the driver has read from -- the
  98  * position preceding WRITE is the last slot the firmware can place a packet.
  99  *
 100  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
 101  * WRITE = READ.
 102  *
 103  * During initialization, the host sets up the READ queue position to the first
 104  * INDEX position, and WRITE to the last (READ - 1 wrapped)
 105  *
 106  * When the firmware places a packet in a buffer, it will advance the READ index
 107  * and fire the RX interrupt.  The driver can then query the READ index and
 108  * process as many packets as possible, moving the WRITE index forward as it
 109  * resets the Rx queue buffers with new memory.
 110  *
 111  * The management in the driver is as follows:
 112  * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
 113  *   When the interrupt handler is called, the request is processed.
 114  *   The page is either stolen - transferred to the upper layer
 115  *   or reused - added immediately to the iwl->rxq->rx_free list.
 116  * + When the page is stolen - the driver updates the matching queue's used
 117  *   count, detaches the RBD and transfers it to the queue used list.
 118  *   When there are two used RBDs - they are transferred to the allocator empty
 119  *   list. Work is then scheduled for the allocator to start allocating
 120  *   eight buffers.
 121  *   When there are another 6 used RBDs - they are transferred to the allocator
 122  *   empty list and the driver tries to claim the pre-allocated buffers and
 123  *   add them to iwl->rxq->rx_free. If it fails - it continues to claim them
 124  *   until ready.
 125  *   When there are 8+ buffers in the free list - either from allocation or from
 126  *   8 reused unstolen pages - restock is called to update the FW and indexes.
 127  * + In order to make sure the allocator always has RBDs to use for allocation
 128  *   the allocator has initial pool in the size of num_queues*(8-2) - the
 129  *   maximum missing RBDs per allocation request (request posted with 2
 130  *    empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
 131  *   The queues supplies the recycle of the rest of the RBDs.
 132  * + A received packet is processed and handed to the kernel network stack,
 133  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 134  * + If there are no allocated buffers in iwl->rxq->rx_free,
 135  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
 136  *   If there were enough free buffers and RX_STALLED is set it is cleared.
 137  *
 138  *
 139  * Driver sequence:
 140  *
 141  * iwl_rxq_alloc()            Allocates rx_free
 142  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
 143  *                            iwl_pcie_rxq_restock.
 144  *                            Used only during initialization.
 145  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
 146  *                            queue, updates firmware pointers, and updates
 147  *                            the WRITE index.
 148  * iwl_pcie_rx_allocator()     Background work for allocating pages.
 149  *
 150  * -- enable interrupts --
 151  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 152  *                            READ INDEX, detaching the SKB from the pool.
 153  *                            Moves the packet buffer from queue to rx_used.
 154  *                            Posts and claims requests to the allocator.
 155  *                            Calls iwl_pcie_rxq_restock to refill any empty
 156  *                            slots.
 157  *
 158  * RBD life-cycle:
 159  *
 160  * Init:
 161  * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
 162  *
 163  * Regular Receive interrupt:
 164  * Page Stolen:
 165  * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
 166  * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
 167  * Page not Stolen:
 168  * rxq.queue -> rxq.rx_free -> rxq.queue
 169  * ...
 170  *
 171  */
 172
 173 /*
 174  * iwl_rxq_space - Return number of free slots available in queue.
 175  */
 176 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 177 {
 178         /* Make sure rx queue size is a power of 2 */
 179         WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
 180
 181         /*
 182          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 183          * between empty and completely full queues.
 184          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 185          * defined for negative dividends.
 186          */
 187         return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
 188 }
 189
 190 /*
 191  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 192  */
 193 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 194 {
 195         return cpu_to_le32((u32)(dma_addr >> 8));
 196 }
 197
 198 /*
 199  * iwl_pcie_rx_stop - stops the Rx DMA
 200  */
 201 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 202 {
 203         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
 204                 /* TODO: remove this once fw does it */
 205                 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
 206                 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3,
 207                                               RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 208         } else if (trans->trans_cfg->mq_rx_supported) {
 209                 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
 210                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
 211                                            RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 212         } else {
 213                 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 214                 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 215                                            FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 216                                            1000);
 217         }
 218 }
 219
 220 /*
 221  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 222  */
 223 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 224                                     struct iwl_rxq *rxq)
 225 {
 226         u32 reg;
 227
 228         lockdep_assert_held(&rxq->lock);
 229
 230         /*
 231          * explicitly wake up the NIC if:
 232          * 1. shadow registers aren't enabled
 233          * 2. there is a chance that the NIC is asleep
 234          */
 235         if (!trans->trans_cfg->base_params->shadow_reg_enable &&
 236             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 237                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 238
 239                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 240                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 241                                        reg);
 242                         iwl_set_bit(trans, CSR_GP_CNTRL,
 243                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 244                         rxq->need_update = true;
 245                         return;
 246                 }
 247         }
 248
 249         rxq->write_actual = round_down(rxq->write, 8);
 250         if (trans->trans_cfg->mq_rx_supported)
 251                 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
 252                             rxq->write_actual);
 253         else
 254                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 255 }
 256
 257 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 258 {
 259         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 260         int i;
 261
 262         for (i = 0; i < trans->num_rx_queues; i++) {
 263                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 264
 265                 if (!rxq->need_update)
 266                         continue;
 267                 spin_lock(&rxq->lock);
 268                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 269                 rxq->need_update = false;
 270                 spin_unlock(&rxq->lock);
 271         }
 272 }
 273
 274 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
 275                                 struct iwl_rxq *rxq,
 276                                 struct iwl_rx_mem_buffer *rxb)
 277 {
 278         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
 279                 struct iwl_rx_transfer_desc *bd = rxq->bd;
 280
 281                 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64));
 282
 283                 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
 284                 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
 285         } else {
 286                 __le64 *bd = rxq->bd;
 287
 288                 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
 289         }
 290
 291         IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
 292                      (u32)rxb->vid, rxq->id, rxq->write);
 293 }
 294
 295 /*
 296  * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
 297  */
 298 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
 299                                   struct iwl_rxq *rxq)
 300 {
 301         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 302         struct iwl_rx_mem_buffer *rxb;
 303
 304         /*
 305          * If the device isn't enabled - no need to try to add buffers...
 306          * This can happen when we stop the device and still have an interrupt
 307          * pending. We stop the APM before we sync the interrupts because we
 308          * have to (see comment there). On the other hand, since the APM is
 309          * stopped, we cannot access the HW (in particular not prph).
 310          * So don't try to restock if the APM has been already stopped.
 311          */
 312         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 313                 return;
 314
 315         spin_lock(&rxq->lock);
 316         while (rxq->free_count) {
 317                 /* Get next free Rx buffer, remove from free list */
 318                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 319                                        list);
 320                 list_del(&rxb->list);
 321                 rxb->invalid = false;
 322                 /* some low bits are expected to be unset (depending on hw) */
 323                 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask);
 324                 /* Point to Rx buffer via next RBD in circular buffer */
 325                 iwl_pcie_restock_bd(trans, rxq, rxb);
 326                 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1);
 327                 rxq->free_count--;
 328         }
 329         spin_unlock(&rxq->lock);
 330
 331         /*
 332          * If we've added more space for the firmware to place data, tell it.
 333          * Increment device's write pointer in multiples of 8.
 334          */
 335         if (rxq->write_actual != (rxq->write & ~0x7)) {
 336                 spin_lock(&rxq->lock);
 337                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 338                 spin_unlock(&rxq->lock);
 339         }
 340 }
 341
 342 /*
 343  * iwl_pcie_rxsq_restock - restock implementation for single queue rx
 344  */
 345 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
 346                                   struct iwl_rxq *rxq)
 347 {
 348         struct iwl_rx_mem_buffer *rxb;
 349
 350         /*
 351          * If the device isn't enabled - not need to try to add buffers...
 352          * This can happen when we stop the device and still have an interrupt
 353          * pending. We stop the APM before we sync the interrupts because we
 354          * have to (see comment there). On the other hand, since the APM is
 355          * stopped, we cannot access the HW (in particular not prph).
 356          * So don't try to restock if the APM has been already stopped.
 357          */
 358         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 359                 return;
 360
 361         spin_lock(&rxq->lock);
 362         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 363                 __le32 *bd = (__le32 *)rxq->bd;
 364                 /* The overwritten rxb must be a used one */
 365                 rxb = rxq->queue[rxq->write];
 366                 BUG_ON(rxb && rxb->page);
 367
 368                 /* Get next free Rx buffer, remove from free list */
 369                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 370                                        list);
 371                 list_del(&rxb->list);
 372                 rxb->invalid = false;
 373
 374                 /* Point to Rx buffer via next RBD in circular buffer */
 375                 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 376                 rxq->queue[rxq->write] = rxb;
 377                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 378                 rxq->free_count--;
 379         }
 380         spin_unlock(&rxq->lock);
 381
 382         /* If we've added more space for the firmware to place data, tell it.
 383          * Increment device's write pointer in multiples of 8. */
 384         if (rxq->write_actual != (rxq->write & ~0x7)) {
 385                 spin_lock(&rxq->lock);
 386                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 387                 spin_unlock(&rxq->lock);
 388         }
 389 }
 390
 391 /*
 392  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 393  *
 394  * If there are slots in the RX queue that need to be restocked,
 395  * and we have free pre-allocated buffers, fill the ranks as much
 396  * as we can, pulling from rx_free.
 397  *
 398  * This moves the 'write' index forward to catch up with 'processed', and
 399  * also updates the memory address in the firmware to reference the new
 400  * target buffer.
 401  */
 402 static
 403 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
 404 {
 405         if (trans->trans_cfg->mq_rx_supported)
 406                 iwl_pcie_rxmq_restock(trans, rxq);
 407         else
 408                 iwl_pcie_rxsq_restock(trans, rxq);
 409 }
 410
 411 /*
 412  * iwl_pcie_rx_alloc_page - allocates and returns a page.
 413  *
 414  */
 415 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
 416                                            u32 *offset, gfp_t priority)
 417 {
 418         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 419         unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
 420         unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order;
 421         struct page *page;
 422         gfp_t gfp_mask = priority;
 423
 424         if (trans_pcie->rx_page_order > 0)
 425                 gfp_mask |= __GFP_COMP;
 426
 427         if (trans_pcie->alloc_page) {
 428                 spin_lock_bh(&trans_pcie->alloc_page_lock);
 429                 /* recheck */
 430                 if (trans_pcie->alloc_page) {
 431                         *offset = trans_pcie->alloc_page_used;
 432                         page = trans_pcie->alloc_page;
 433                         trans_pcie->alloc_page_used += rbsize;
 434                         if (trans_pcie->alloc_page_used >= allocsize)
 435                                 trans_pcie->alloc_page = NULL;
 436                         else
 437                                 get_page(page);
 438                         spin_unlock_bh(&trans_pcie->alloc_page_lock);
 439                         return page;
 440                 }
 441                 spin_unlock_bh(&trans_pcie->alloc_page_lock);
 442         }
 443
 444         /* Alloc a new receive buffer */
 445         page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 446         if (!page) {
 447                 if (net_ratelimit())
 448                         IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
 449                                        trans_pcie->rx_page_order);
 450                 /*
 451                  * Issue an error if we don't have enough pre-allocated
 452                   * buffers.
 453                  */
 454                 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
 455                         IWL_CRIT(trans,
 456                                  "Failed to alloc_pages\n");
 457                 return NULL;
 458         }
 459
 460         if (2 * rbsize <= allocsize) {
 461                 spin_lock_bh(&trans_pcie->alloc_page_lock);
 462                 if (!trans_pcie->alloc_page) {
 463                         get_page(page);
 464                         trans_pcie->alloc_page = page;
 465                         trans_pcie->alloc_page_used = rbsize;
 466                 }
 467                 spin_unlock_bh(&trans_pcie->alloc_page_lock);
 468         }
 469
 470         *offset = 0;
 471         return page;
 472 }
 473
 474 /*
 475  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 476  *
 477  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 478  * a page must be allocated and the RBD must point to the page. This function
 479  * doesn't change the HW pointer but handles the list of pages that is used by
 480  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 481  * allocated buffers.
 482  */
 483 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
 484                             struct iwl_rxq *rxq)
 485 {
 486         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 487         struct iwl_rx_mem_buffer *rxb;
 488         struct page *page;
 489
 490         while (1) {
 491                 unsigned int offset;
 492
 493                 spin_lock(&rxq->lock);
 494                 if (list_empty(&rxq->rx_used)) {
 495                         spin_unlock(&rxq->lock);
 496                         return;
 497                 }
 498                 spin_unlock(&rxq->lock);
 499
 500                 page = iwl_pcie_rx_alloc_page(trans, &offset, priority);
 501                 if (!page)
 502                         return;
 503
 504                 spin_lock(&rxq->lock);
 505
 506                 if (list_empty(&rxq->rx_used)) {
 507                         spin_unlock(&rxq->lock);
 508                         __free_pages(page, trans_pcie->rx_page_order);
 509                         return;
 510                 }
 511                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 512                                        list);
 513                 list_del(&rxb->list);
 514                 spin_unlock(&rxq->lock);
 515
 516                 BUG_ON(rxb->page);
 517                 rxb->page = page;
 518                 rxb->offset = offset;
 519                 /* Get physical address of the RB */
 520                 rxb->page_dma =
 521                         dma_map_page(trans->dev, page, rxb->offset,
 522                                      trans_pcie->rx_buf_bytes,
 523                                      DMA_FROM_DEVICE);
 524                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 525                         rxb->page = NULL;
 526                         spin_lock(&rxq->lock);
 527                         list_add(&rxb->list, &rxq->rx_used);
 528                         spin_unlock(&rxq->lock);
 529                         __free_pages(page, trans_pcie->rx_page_order);
 530                         return;
 531                 }
 532
 533                 spin_lock(&rxq->lock);
 534
 535                 list_add_tail(&rxb->list, &rxq->rx_free);
 536                 rxq->free_count++;
 537
 538                 spin_unlock(&rxq->lock);
 539         }
 540 }
 541
 542 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
 543 {
 544         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 545         int i;
 546
 547         for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) {
 548                 if (!trans_pcie->rx_pool[i].page)
 549                         continue;
 550                 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
 551                                trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE);
 552                 __free_pages(trans_pcie->rx_pool[i].page,
 553                              trans_pcie->rx_page_order);
 554                 trans_pcie->rx_pool[i].page = NULL;
 555         }
 556 }
 557
 558 /*
 559  * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
 560  *
 561  * Allocates for each received request 8 pages
 562  * Called as a scheduled work item.
 563  */
 564 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
 565 {
 566         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 567         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 568         struct list_head local_empty;
 569         int pending = atomic_read(&rba->req_pending);
 570
 571         IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending);
 572
 573         /* If we were scheduled - there is at least one request */
 574         spin_lock(&rba->lock);
 575         /* swap out the rba->rbd_empty to a local list */
 576         list_replace_init(&rba->rbd_empty, &local_empty);
 577         spin_unlock(&rba->lock);
 578
 579         while (pending) {
 580                 int i;
 581                 LIST_HEAD(local_allocated);
 582                 gfp_t gfp_mask = GFP_KERNEL;
 583
 584                 /* Do not post a warning if there are only a few requests */
 585                 if (pending < RX_PENDING_WATERMARK)
 586                         gfp_mask |= __GFP_NOWARN;
 587
 588                 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
 589                         struct iwl_rx_mem_buffer *rxb;
 590                         struct page *page;
 591
 592                         /* List should never be empty - each reused RBD is
 593                          * returned to the list, and initial pool covers any
 594                          * possible gap between the time the page is allocated
 595                          * to the time the RBD is added.
 596                          */
 597                         BUG_ON(list_empty(&local_empty));
 598                         /* Get the first rxb from the rbd list */
 599                         rxb = list_first_entry(&local_empty,
 600                                                struct iwl_rx_mem_buffer, list);
 601                         BUG_ON(rxb->page);
 602
 603                         /* Alloc a new receive buffer */
 604                         page = iwl_pcie_rx_alloc_page(trans, &rxb->offset,
 605                                                       gfp_mask);
 606                         if (!page)
 607                                 continue;
 608                         rxb->page = page;
 609
 610                         /* Get physical address of the RB */
 611                         rxb->page_dma = dma_map_page(trans->dev, page,
 612                                                      rxb->offset,
 613                                                      trans_pcie->rx_buf_bytes,
 614                                                      DMA_FROM_DEVICE);
 615                         if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 616                                 rxb->page = NULL;
 617                                 __free_pages(page, trans_pcie->rx_page_order);
 618                                 continue;
 619                         }
 620
 621                         /* move the allocated entry to the out list */
 622                         list_move(&rxb->list, &local_allocated);
 623                         i++;
 624                 }
 625
 626                 atomic_dec(&rba->req_pending);
 627                 pending--;
 628
 629                 if (!pending) {
 630                         pending = atomic_read(&rba->req_pending);
 631                         if (pending)
 632                                 IWL_DEBUG_TPT(trans,
 633                                               "Got more pending allocation requests = %d\n",
 634                                               pending);
 635                 }
 636
 637                 spin_lock(&rba->lock);
 638                 /* add the allocated rbds to the allocator allocated list */
 639                 list_splice_tail(&local_allocated, &rba->rbd_allocated);
 640                 /* get more empty RBDs for current pending requests */
 641                 list_splice_tail_init(&rba->rbd_empty, &local_empty);
 642                 spin_unlock(&rba->lock);
 643
 644                 atomic_inc(&rba->req_ready);
 645
 646         }
 647
 648         spin_lock(&rba->lock);
 649         /* return unused rbds to the allocator empty list */
 650         list_splice_tail(&local_empty, &rba->rbd_empty);
 651         spin_unlock(&rba->lock);
 652
 653         IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__);
 654 }
 655
 656 /*
 657  * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
 658 .*
 659 .* Called by queue when the queue posted allocation request and
 660  * has freed 8 RBDs in order to restock itself.
 661  * This function directly moves the allocated RBs to the queue's ownership
 662  * and updates the relevant counters.
 663  */
 664 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
 665                                       struct iwl_rxq *rxq)
 666 {
 667         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 668         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 669         int i;
 670
 671         lockdep_assert_held(&rxq->lock);
 672
 673         /*
 674          * atomic_dec_if_positive returns req_ready - 1 for any scenario.
 675          * If req_ready is 0 atomic_dec_if_positive will return -1 and this
 676          * function will return early, as there are no ready requests.
 677          * atomic_dec_if_positive will perofrm the *actual* decrement only if
 678          * req_ready > 0, i.e. - there are ready requests and the function
 679          * hands one request to the caller.
 680          */
 681         if (atomic_dec_if_positive(&rba->req_ready) < 0)
 682                 return;
 683
 684         spin_lock(&rba->lock);
 685         for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
 686                 /* Get next free Rx buffer, remove it from free list */
 687                 struct iwl_rx_mem_buffer *rxb =
 688                         list_first_entry(&rba->rbd_allocated,
 689                                          struct iwl_rx_mem_buffer, list);
 690
 691                 list_move(&rxb->list, &rxq->rx_free);
 692         }
 693         spin_unlock(&rba->lock);
 694
 695         rxq->used_count -= RX_CLAIM_REQ_ALLOC;
 696         rxq->free_count += RX_CLAIM_REQ_ALLOC;
 697 }
 698
 699 void iwl_pcie_rx_allocator_work(struct work_struct *data)
 700 {
 701         struct iwl_rb_allocator *rba_p =
 702                 container_of(data, struct iwl_rb_allocator, rx_alloc);
 703         struct iwl_trans_pcie *trans_pcie =
 704                 container_of(rba_p, struct iwl_trans_pcie, rba);
 705
 706         iwl_pcie_rx_allocator(trans_pcie->trans);
 707 }
 708
 709 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
 710 {
 711         struct iwl_rx_transfer_desc *rx_td;
 712
 713         if (use_rx_td)
 714                 return sizeof(*rx_td);
 715         else
 716                 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) :
 717                         sizeof(__le32);
 718 }
 719
 720 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
 721                                   struct iwl_rxq *rxq)
 722 {
 723         struct device *dev = trans->dev;
 724         bool use_rx_td = (trans->trans_cfg->device_family >=
 725                           IWL_DEVICE_FAMILY_AX210);
 726         int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
 727
 728         if (rxq->bd)
 729                 dma_free_coherent(trans->dev,
 730                                   free_size * rxq->queue_size,
 731                                   rxq->bd, rxq->bd_dma);
 732         rxq->bd_dma = 0;
 733         rxq->bd = NULL;
 734
 735         rxq->rb_stts_dma = 0;
 736         rxq->rb_stts = NULL;
 737
 738         if (rxq->used_bd)
 739                 dma_free_coherent(trans->dev,
 740                                   (use_rx_td ? sizeof(*rxq->cd) :
 741                                    sizeof(__le32)) * rxq->queue_size,
 742                                   rxq->used_bd, rxq->used_bd_dma);
 743         rxq->used_bd_dma = 0;
 744         rxq->used_bd = NULL;
 745
 746         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
 747                 return;
 748
 749         if (rxq->tr_tail)
 750                 dma_free_coherent(dev, sizeof(__le16),
 751                                   rxq->tr_tail, rxq->tr_tail_dma);
 752         rxq->tr_tail_dma = 0;
 753         rxq->tr_tail = NULL;
 754
 755         if (rxq->cr_tail)
 756                 dma_free_coherent(dev, sizeof(__le16),
 757                                   rxq->cr_tail, rxq->cr_tail_dma);
 758         rxq->cr_tail_dma = 0;
 759         rxq->cr_tail = NULL;
 760 }
 761
 762 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
 763                                   struct iwl_rxq *rxq)
 764 {
 765         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 766         struct device *dev = trans->dev;
 767         int i;
 768         int free_size;
 769         bool use_rx_td = (trans->trans_cfg->device_family >=
 770                           IWL_DEVICE_FAMILY_AX210);
 771         size_t rb_stts_size = use_rx_td ? sizeof(__le16) :
 772                               sizeof(struct iwl_rb_status);
 773
 774         spin_lock_init(&rxq->lock);
 775         if (trans->trans_cfg->mq_rx_supported)
 776                 rxq->queue_size = trans->cfg->num_rbds;
 777         else
 778                 rxq->queue_size = RX_QUEUE_SIZE;
 779
 780         free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
 781
 782         /*
 783          * Allocate the circular buffer of Read Buffer Descriptors
 784          * (RBDs)
 785          */
 786         rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size,
 787                                      &rxq->bd_dma, GFP_KERNEL);
 788         if (!rxq->bd)
 789                 goto err;
 790
 791         if (trans->trans_cfg->mq_rx_supported) {
 792                 rxq->used_bd = dma_alloc_coherent(dev,
 793                                                   (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size,
 794                                                   &rxq->used_bd_dma,
 795                                                   GFP_KERNEL);
 796                 if (!rxq->used_bd)
 797                         goto err;
 798         }
 799
 800         rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size;
 801         rxq->rb_stts_dma =
 802                 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size;
 803
 804         if (!use_rx_td)
 805                 return 0;
 806
 807         /* Allocate the driver's pointer to TR tail */
 808         rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16),
 809                                           &rxq->tr_tail_dma, GFP_KERNEL);
 810         if (!rxq->tr_tail)
 811                 goto err;
 812
 813         /* Allocate the driver's pointer to CR tail */
 814         rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16),
 815                                           &rxq->cr_tail_dma, GFP_KERNEL);
 816         if (!rxq->cr_tail)
 817                 goto err;
 818
 819         return 0;
 820
 821 err:
 822         for (i = 0; i < trans->num_rx_queues; i++) {
 823                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 824
 825                 iwl_pcie_free_rxq_dma(trans, rxq);
 826         }
 827
 828         return -ENOMEM;
 829 }
 830
 831 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 832 {
 833         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 834         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 835         int i, ret;
 836         size_t rb_stts_size = trans->trans_cfg->device_family >=
 837                                 IWL_DEVICE_FAMILY_AX210 ?
 838                               sizeof(__le16) : sizeof(struct iwl_rb_status);
 839
 840         if (WARN_ON(trans_pcie->rxq))
 841                 return -EINVAL;
 842
 843         trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
 844                                   GFP_KERNEL);
 845         trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
 846                                       sizeof(trans_pcie->rx_pool[0]),
 847                                       GFP_KERNEL);
 848         trans_pcie->global_table =
 849                 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
 850                         sizeof(trans_pcie->global_table[0]),
 851                         GFP_KERNEL);
 852         if (!trans_pcie->rxq || !trans_pcie->rx_pool ||
 853             !trans_pcie->global_table) {
 854                 ret = -ENOMEM;
 855                 goto err;
 856         }
 857
 858         spin_lock_init(&rba->lock);
 859
 860         /*
 861          * Allocate the driver's pointer to receive buffer status.
 862          * Allocate for all queues continuously (HW requirement).
 863          */
 864         trans_pcie->base_rb_stts =
 865                         dma_alloc_coherent(trans->dev,
 866                                            rb_stts_size * trans->num_rx_queues,
 867                                            &trans_pcie->base_rb_stts_dma,
 868                                            GFP_KERNEL);
 869         if (!trans_pcie->base_rb_stts) {
 870                 ret = -ENOMEM;
 871                 goto err;
 872         }
 873
 874         for (i = 0; i < trans->num_rx_queues; i++) {
 875                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 876
 877                 rxq->id = i;
 878                 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
 879                 if (ret)
 880                         goto err;
 881         }
 882         return 0;
 883
 884 err:
 885         if (trans_pcie->base_rb_stts) {
 886                 dma_free_coherent(trans->dev,
 887                                   rb_stts_size * trans->num_rx_queues,
 888                                   trans_pcie->base_rb_stts,
 889                                   trans_pcie->base_rb_stts_dma);
 890                 trans_pcie->base_rb_stts = NULL;
 891                 trans_pcie->base_rb_stts_dma = 0;
 892         }
 893         kfree(trans_pcie->rx_pool);
 894         kfree(trans_pcie->global_table);
 895         kfree(trans_pcie->rxq);
 896
 897         return ret;
 898 }
 899
 900 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 901 {
 902         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 903         u32 rb_size;
 904         unsigned long flags;
 905         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 906
 907         switch (trans_pcie->rx_buf_size) {
 908         case IWL_AMSDU_4K:
 909                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 910                 break;
 911         case IWL_AMSDU_8K:
 912                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 913                 break;
 914         case IWL_AMSDU_12K:
 915                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
 916                 break;
 917         default:
 918                 WARN_ON(1);
 919                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 920         }
 921
 922         if (!iwl_trans_grab_nic_access(trans, &flags))
 923                 return;
 924
 925         /* Stop Rx DMA */
 926         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 927         /* reset and flush pointers */
 928         iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 929         iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 930         iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 931
 932         /* Reset driver's Rx queue write index */
 933         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 934
 935         /* Tell device where to find RBD circular buffer in DRAM */
 936         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 937                     (u32)(rxq->bd_dma >> 8));
 938
 939         /* Tell device where in DRAM to update its Rx status */
 940         iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 941                     rxq->rb_stts_dma >> 4);
 942
 943         /* Enable Rx DMA
 944          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 945          *      the credit mechanism in 5000 HW RX FIFO
 946          * Direct rx interrupts to hosts
 947          * Rx buffer size 4 or 8k or 12k
 948          * RB timeout 0x10
 949          * 256 RBDs
 950          */
 951         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 952                     FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 953                     FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 954                     FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 955                     rb_size |
 956                     (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 957                     (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 958
 959         iwl_trans_release_nic_access(trans, &flags);
 960
 961         /* Set interrupt coalescing timer to default (2048 usecs) */
 962         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 963
 964         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 965         if (trans->cfg->host_interrupt_operation_mode)
 966                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 967 }
 968
 969 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 970 {
 971         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 972         u32 rb_size, enabled = 0;
 973         unsigned long flags;
 974         int i;
 975
 976         switch (trans_pcie->rx_buf_size) {
 977         case IWL_AMSDU_2K:
 978                 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
 979                 break;
 980         case IWL_AMSDU_4K:
 981                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 982                 break;
 983         case IWL_AMSDU_8K:
 984                 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
 985                 break;
 986         case IWL_AMSDU_12K:
 987                 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
 988                 break;
 989         default:
 990                 WARN_ON(1);
 991                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 992         }
 993
 994         if (!iwl_trans_grab_nic_access(trans, &flags))
 995                 return;
 996
 997         /* Stop Rx DMA */
 998         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 999         /* disable free amd used rx queue operation */
1000         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
1001
1002         for (i = 0; i < trans->num_rx_queues; i++) {
1003                 /* Tell device where to find RBD free table in DRAM */
1004                 iwl_write_prph64_no_grab(trans,
1005                                          RFH_Q_FRBDCB_BA_LSB(i),
1006                                          trans_pcie->rxq[i].bd_dma);
1007                 /* Tell device where to find RBD used table in DRAM */
1008                 iwl_write_prph64_no_grab(trans,
1009                                          RFH_Q_URBDCB_BA_LSB(i),
1010                                          trans_pcie->rxq[i].used_bd_dma);
1011                 /* Tell device where in DRAM to update its Rx status */
1012                 iwl_write_prph64_no_grab(trans,
1013                                          RFH_Q_URBD_STTS_WPTR_LSB(i),
1014                                          trans_pcie->rxq[i].rb_stts_dma);
1015                 /* Reset device indice tables */
1016                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
1017                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
1018                 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
1019
1020                 enabled |= BIT(i) | BIT(i + 16);
1021         }
1022
1023         /*
1024          * Enable Rx DMA
1025          * Rx buffer size 4 or 8k or 12k
1026          * Min RB size 4 or 8
1027          * Drop frames that exceed RB size
1028          * 512 RBDs
1029          */
1030         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
1031                                RFH_DMA_EN_ENABLE_VAL | rb_size |
1032                                RFH_RXF_DMA_MIN_RB_4_8 |
1033                                RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
1034                                RFH_RXF_DMA_RBDCB_SIZE_512);
1035
1036         /*
1037          * Activate DMA snooping.
1038          * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
1039          * Default queue is 0
1040          */
1041         iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
1042                                RFH_GEN_CFG_RFH_DMA_SNOOP |
1043                                RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
1044                                RFH_GEN_CFG_SERVICE_DMA_SNOOP |
1045                                RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
1046                                                trans->trans_cfg->integrated ?
1047                                                RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
1048                                                RFH_GEN_CFG_RB_CHUNK_SIZE_128));
1049         /* Enable the relevant rx queues */
1050         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
1051
1052         iwl_trans_release_nic_access(trans, &flags);
1053
1054         /* Set interrupt coalescing timer to default (2048 usecs) */
1055         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1056 }
1057
1058 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
1059 {
1060         lockdep_assert_held(&rxq->lock);
1061
1062         INIT_LIST_HEAD(&rxq->rx_free);
1063         INIT_LIST_HEAD(&rxq->rx_used);
1064         rxq->free_count = 0;
1065         rxq->used_count = 0;
1066 }
1067
1068 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1069 {
1070         WARN_ON(1);
1071         return 0;
1072 }
1073
1074 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1075 {
1076         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1077         struct iwl_rxq *def_rxq;
1078         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1079         int i, err, queue_size, allocator_pool_size, num_alloc;
1080
1081         if (!trans_pcie->rxq) {
1082                 err = iwl_pcie_rx_alloc(trans);
1083                 if (err)
1084                         return err;
1085         }
1086         def_rxq = trans_pcie->rxq;
1087
1088         cancel_work_sync(&rba->rx_alloc);
1089
1090         spin_lock(&rba->lock);
1091         atomic_set(&rba->req_pending, 0);
1092         atomic_set(&rba->req_ready, 0);
1093         INIT_LIST_HEAD(&rba->rbd_allocated);
1094         INIT_LIST_HEAD(&rba->rbd_empty);
1095         spin_unlock(&rba->lock);
1096
1097         /* free all first - we might be reconfigured for a different size */
1098         iwl_pcie_free_rbs_pool(trans);
1099
1100         for (i = 0; i < RX_QUEUE_SIZE; i++)
1101                 def_rxq->queue[i] = NULL;
1102
1103         for (i = 0; i < trans->num_rx_queues; i++) {
1104                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1105
1106                 spin_lock(&rxq->lock);
1107                 /*
1108                  * Set read write pointer to reflect that we have processed
1109                  * and used all buffers, but have not restocked the Rx queue
1110                  * with fresh buffers
1111                  */
1112                 rxq->read = 0;
1113                 rxq->write = 0;
1114                 rxq->write_actual = 0;
1115                 memset(rxq->rb_stts, 0,
1116                        (trans->trans_cfg->device_family >=
1117                         IWL_DEVICE_FAMILY_AX210) ?
1118                        sizeof(__le16) : sizeof(struct iwl_rb_status));
1119
1120                 iwl_pcie_rx_init_rxb_lists(rxq);
1121
1122                 if (!rxq->napi.poll)
1123                         netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
1124                                        iwl_pcie_dummy_napi_poll, 64);
1125
1126                 spin_unlock(&rxq->lock);
1127         }
1128
1129         /* move the pool to the default queue and allocator ownerships */
1130         queue_size = trans->trans_cfg->mq_rx_supported ?
1131                         trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE;
1132         allocator_pool_size = trans->num_rx_queues *
1133                 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1134         num_alloc = queue_size + allocator_pool_size;
1135
1136         for (i = 0; i < num_alloc; i++) {
1137                 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1138
1139                 if (i < allocator_pool_size)
1140                         list_add(&rxb->list, &rba->rbd_empty);
1141                 else
1142                         list_add(&rxb->list, &def_rxq->rx_used);
1143                 trans_pcie->global_table[i] = rxb;
1144                 rxb->vid = (u16)(i + 1);
1145                 rxb->invalid = true;
1146         }
1147
1148         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1149
1150         return 0;
1151 }
1152
1153 int iwl_pcie_rx_init(struct iwl_trans *trans)
1154 {
1155         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1156         int ret = _iwl_pcie_rx_init(trans);
1157
1158         if (ret)
1159                 return ret;
1160
1161         if (trans->trans_cfg->mq_rx_supported)
1162                 iwl_pcie_rx_mq_hw_init(trans);
1163         else
1164                 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1165
1166         iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1167
1168         spin_lock(&trans_pcie->rxq->lock);
1169         iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1170         spin_unlock(&trans_pcie->rxq->lock);
1171
1172         return 0;
1173 }
1174
1175 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1176 {
1177         /* Set interrupt coalescing timer to default (2048 usecs) */
1178         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1179
1180         /*
1181          * We don't configure the RFH.
1182          * Restock will be done at alive, after firmware configured the RFH.
1183          */
1184         return _iwl_pcie_rx_init(trans);
1185 }
1186
1187 void iwl_pcie_rx_free(struct iwl_trans *trans)
1188 {
1189         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1190         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1191         int i;
1192         size_t rb_stts_size = trans->trans_cfg->device_family >=
1193                                 IWL_DEVICE_FAMILY_AX210 ?
1194                               sizeof(__le16) : sizeof(struct iwl_rb_status);
1195
1196         /*
1197          * if rxq is NULL, it means that nothing has been allocated,
1198          * exit now
1199          */
1200         if (!trans_pcie->rxq) {
1201                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1202                 return;
1203         }
1204
1205         cancel_work_sync(&rba->rx_alloc);
1206
1207         iwl_pcie_free_rbs_pool(trans);
1208
1209         if (trans_pcie->base_rb_stts) {
1210                 dma_free_coherent(trans->dev,
1211                                   rb_stts_size * trans->num_rx_queues,
1212                                   trans_pcie->base_rb_stts,
1213                                   trans_pcie->base_rb_stts_dma);
1214                 trans_pcie->base_rb_stts = NULL;
1215                 trans_pcie->base_rb_stts_dma = 0;
1216         }
1217
1218         for (i = 0; i < trans->num_rx_queues; i++) {
1219                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1220
1221                 iwl_pcie_free_rxq_dma(trans, rxq);
1222
1223                 if (rxq->napi.poll)
1224                         netif_napi_del(&rxq->napi);
1225         }
1226         kfree(trans_pcie->rx_pool);
1227         kfree(trans_pcie->global_table);
1228         kfree(trans_pcie->rxq);
1229
1230         if (trans_pcie->alloc_page)
1231                 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order);
1232 }
1233
1234 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1235                                           struct iwl_rb_allocator *rba)
1236 {
1237         spin_lock(&rba->lock);
1238         list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1239         spin_unlock(&rba->lock);
1240 }
1241
1242 /*
1243  * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1244  *
1245  * Called when a RBD can be reused. The RBD is transferred to the allocator.
1246  * When there are 2 empty RBDs - a request for allocation is posted
1247  */
1248 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1249                                   struct iwl_rx_mem_buffer *rxb,
1250                                   struct iwl_rxq *rxq, bool emergency)
1251 {
1252         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1253         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1254
1255         /* Move the RBD to the used list, will be moved to allocator in batches
1256          * before claiming or posting a request*/
1257         list_add_tail(&rxb->list, &rxq->rx_used);
1258
1259         if (unlikely(emergency))
1260                 return;
1261
1262         /* Count the allocator owned RBDs */
1263         rxq->used_count++;
1264
1265         /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1266          * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1267          * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1268          * after but we still need to post another request.
1269          */
1270         if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1271                 /* Move the 2 RBDs to the allocator ownership.
1272                  Allocator has another 6 from pool for the request completion*/
1273                 iwl_pcie_rx_move_to_allocator(rxq, rba);
1274
1275                 atomic_inc(&rba->req_pending);
1276                 queue_work(rba->alloc_wq, &rba->rx_alloc);
1277         }
1278 }
1279
1280 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1281                                 struct iwl_rxq *rxq,
1282                                 struct iwl_rx_mem_buffer *rxb,
1283                                 bool emergency,
1284                                 int i)
1285 {
1286         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1287         struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
1288         bool page_stolen = false;
1289         int max_len = trans_pcie->rx_buf_bytes;
1290         u32 offset = 0;
1291
1292         if (WARN_ON(!rxb))
1293                 return;
1294
1295         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1296
1297         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1298                 struct iwl_rx_packet *pkt;
1299                 u16 sequence;
1300                 bool reclaim;
1301                 int index, cmd_index, len;
1302                 struct iwl_rx_cmd_buffer rxcb = {
1303                         ._offset = rxb->offset + offset,
1304                         ._rx_page_order = trans_pcie->rx_page_order,
1305                         ._page = rxb->page,
1306                         ._page_stolen = false,
1307                         .truesize = max_len,
1308                 };
1309
1310                 pkt = rxb_addr(&rxcb);
1311
1312                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1313                         IWL_DEBUG_RX(trans,
1314                                      "Q %d: RB end marker at offset %d\n",
1315                                      rxq->id, offset);
1316                         break;
1317                 }
1318
1319                 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1320                         FH_RSCSR_RXQ_POS != rxq->id,
1321                      "frame on invalid queue - is on %d and indicates %d\n",
1322                      rxq->id,
1323                      (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1324                         FH_RSCSR_RXQ_POS);
1325
1326                 IWL_DEBUG_RX(trans,
1327                              "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1328                              rxq->id, offset,
1329                              iwl_get_cmd_string(trans,
1330                                                 iwl_cmd_id(pkt->hdr.cmd,
1331                                                            pkt->hdr.group_id,
1332                                                            0)),
1333                              pkt->hdr.group_id, pkt->hdr.cmd,
1334                              le16_to_cpu(pkt->hdr.sequence));
1335
1336                 len = iwl_rx_packet_len(pkt);
1337                 len += sizeof(u32); /* account for status word */
1338                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1339                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1340
1341                 /* Reclaim a command buffer only if this packet is a response
1342                  *   to a (driver-originated) command.
1343                  * If the packet (e.g. Rx frame) originated from uCode,
1344                  *   there is no command buffer to reclaim.
1345                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1346                  *   but apparently a few don't get set; catch them here. */
1347                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1348                 if (reclaim && !pkt->hdr.group_id) {
1349                         int i;
1350
1351                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1352                                 if (trans_pcie->no_reclaim_cmds[i] ==
1353                                                         pkt->hdr.cmd) {
1354                                         reclaim = false;
1355                                         break;
1356                                 }
1357                         }
1358                 }
1359
1360                 sequence = le16_to_cpu(pkt->hdr.sequence);
1361                 index = SEQ_TO_INDEX(sequence);
1362                 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1363
1364                 if (rxq->id == trans_pcie->def_rx_queue)
1365                         iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1366                                        &rxcb);
1367                 else
1368                         iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1369                                            &rxcb, rxq->id);
1370
1371                 if (reclaim) {
1372                         kfree_sensitive(txq->entries[cmd_index].free_buf);
1373                         txq->entries[cmd_index].free_buf = NULL;
1374                 }
1375
1376                 /*
1377                  * After here, we should always check rxcb._page_stolen,
1378                  * if it is true then one of the handlers took the page.
1379                  */
1380
1381                 if (reclaim) {
1382                         /* Invoke any callbacks, transfer the buffer to caller,
1383                          * and fire off the (possibly) blocking
1384                          * iwl_trans_send_cmd()
1385                          * as we reclaim the driver command queue */
1386                         if (!rxcb._page_stolen)
1387                                 iwl_pcie_hcmd_complete(trans, &rxcb);
1388                         else
1389                                 IWL_WARN(trans, "Claim null rxb?\n");
1390                 }
1391
1392                 page_stolen |= rxcb._page_stolen;
1393                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1394                         break;
1395                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1396         }
1397
1398         /* page was stolen from us -- free our reference */
1399         if (page_stolen) {
1400                 __free_pages(rxb->page, trans_pcie->rx_page_order);
1401                 rxb->page = NULL;
1402         }
1403
1404         /* Reuse the page if possible. For notification packets and
1405          * SKBs that fail to Rx correctly, add them back into the
1406          * rx_free list for reuse later. */
1407         if (rxb->page != NULL) {
1408                 rxb->page_dma =
1409                         dma_map_page(trans->dev, rxb->page, rxb->offset,
1410                                      trans_pcie->rx_buf_bytes,
1411                                      DMA_FROM_DEVICE);
1412                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1413                         /*
1414                          * free the page(s) as well to not break
1415                          * the invariant that the items on the used
1416                          * list have no page(s)
1417                          */
1418                         __free_pages(rxb->page, trans_pcie->rx_page_order);
1419                         rxb->page = NULL;
1420                         iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1421                 } else {
1422                         list_add_tail(&rxb->list, &rxq->rx_free);
1423                         rxq->free_count++;
1424                 }
1425         } else
1426                 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1427 }
1428
1429 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1430                                                   struct iwl_rxq *rxq, int i,
1431                                                   bool *join)
1432 {
1433         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1434         struct iwl_rx_mem_buffer *rxb;
1435         u16 vid;
1436
1437         BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32);
1438
1439         if (!trans->trans_cfg->mq_rx_supported) {
1440                 rxb = rxq->queue[i];
1441                 rxq->queue[i] = NULL;
1442                 return rxb;
1443         }
1444
1445         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1446                 vid = le16_to_cpu(rxq->cd[i].rbid);
1447                 *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED;
1448         } else {
1449                 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */
1450         }
1451
1452         if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs))
1453                 goto out_err;
1454
1455         rxb = trans_pcie->global_table[vid - 1];
1456         if (rxb->invalid)
1457                 goto out_err;
1458
1459         IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid);
1460
1461         rxb->invalid = true;
1462
1463         return rxb;
1464
1465 out_err:
1466         WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1467         iwl_force_nmi(trans);
1468         return NULL;
1469 }
1470
1471 /*
1472  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1473  */
1474 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1475 {
1476         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1477         struct napi_struct *napi;
1478         struct iwl_rxq *rxq;
1479         u32 r, i, count = 0;
1480         bool emergency = false;
1481
1482         if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1483                 return;
1484
1485         rxq = &trans_pcie->rxq[queue];
1486
1487 restart:
1488         spin_lock(&rxq->lock);
1489         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1490          * buffer that the driver may process (last buffer filled by ucode). */
1491         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
1492         i = rxq->read;
1493
1494         /* W/A 9000 device step A0 wrap-around bug */
1495         r &= (rxq->queue_size - 1);
1496
1497         /* Rx interrupt, but nothing sent from uCode */
1498         if (i == r)
1499                 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1500
1501         while (i != r) {
1502                 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1503                 struct iwl_rx_mem_buffer *rxb;
1504                 /* number of RBDs still waiting for page allocation */
1505                 u32 rb_pending_alloc =
1506                         atomic_read(&trans_pcie->rba.req_pending) *
1507                         RX_CLAIM_REQ_ALLOC;
1508                 bool join = false;
1509
1510                 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1511                              !emergency)) {
1512                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1513                         emergency = true;
1514                         IWL_DEBUG_TPT(trans,
1515                                       "RX path is in emergency. Pending allocations %d\n",
1516                                       rb_pending_alloc);
1517                 }
1518
1519                 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1520
1521                 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join);
1522                 if (!rxb)
1523                         goto out;
1524
1525                 if (unlikely(join || rxq->next_rb_is_fragment)) {
1526                         rxq->next_rb_is_fragment = join;
1527                         /*
1528                          * We can only get a multi-RB in the following cases:
1529                          *  - firmware issue, sending a too big notification
1530                          *  - sniffer mode with a large A-MSDU
1531                          *  - large MTU frames (>2k)
1532                          * since the multi-RB functionality is limited to newer
1533                          * hardware that cannot put multiple entries into a
1534                          * single RB.
1535                          *
1536                          * Right now, the higher layers aren't set up to deal
1537                          * with that, so discard all of these.
1538                          */
1539                         list_add_tail(&rxb->list, &rxq->rx_free);
1540                         rxq->free_count++;
1541                 } else {
1542                         iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1543                 }
1544
1545                 i = (i + 1) & (rxq->queue_size - 1);
1546
1547                 /*
1548                  * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1549                  * try to claim the pre-allocated buffers from the allocator.
1550                  * If not ready - will try to reclaim next time.
1551                  * There is no need to reschedule work - allocator exits only
1552                  * on success
1553                  */
1554                 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1555                         iwl_pcie_rx_allocator_get(trans, rxq);
1556
1557                 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1558                         /* Add the remaining empty RBDs for allocator use */
1559                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1560                 } else if (emergency) {
1561                         count++;
1562                         if (count == 8) {
1563                                 count = 0;
1564                                 if (rb_pending_alloc < rxq->queue_size / 3) {
1565                                         IWL_DEBUG_TPT(trans,
1566                                                       "RX path exited emergency. Pending allocations %d\n",
1567                                                       rb_pending_alloc);
1568                                         emergency = false;
1569                                 }
1570
1571                                 rxq->read = i;
1572                                 spin_unlock(&rxq->lock);
1573                                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1574                                 iwl_pcie_rxq_restock(trans, rxq);
1575                                 goto restart;
1576                         }
1577                 }
1578         }
1579 out:
1580         /* Backtrack one entry */
1581         rxq->read = i;
1582         /* update cr tail with the rxq read pointer */
1583         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1584                 *rxq->cr_tail = cpu_to_le16(r);
1585         spin_unlock(&rxq->lock);
1586
1587         /*
1588          * handle a case where in emergency there are some unallocated RBDs.
1589          * those RBDs are in the used list, but are not tracked by the queue's
1590          * used_count which counts allocator owned RBDs.
1591          * unallocated emergency RBDs must be allocated on exit, otherwise
1592          * when called again the function may not be in emergency mode and
1593          * they will be handed to the allocator with no tracking in the RBD
1594          * allocator counters, which will lead to them never being claimed back
1595          * by the queue.
1596          * by allocating them here, they are now in the queue free list, and
1597          * will be restocked by the next call of iwl_pcie_rxq_restock.
1598          */
1599         if (unlikely(emergency && count))
1600                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1601
1602         napi = &rxq->napi;
1603         if (napi->poll) {
1604                 napi_gro_flush(napi, false);
1605
1606                 if (napi->rx_count) {
1607                         netif_receive_skb_list(&napi->rx_list);
1608                         INIT_LIST_HEAD(&napi->rx_list);
1609                         napi->rx_count = 0;
1610                 }
1611         }
1612
1613         iwl_pcie_rxq_restock(trans, rxq);
1614 }
1615
1616 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1617 {
1618         u8 queue = entry->entry;
1619         struct msix_entry *entries = entry - queue;
1620
1621         return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1622 }
1623
1624 /*
1625  * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1626  * This interrupt handler should be used with RSS queue only.
1627  */
1628 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1629 {
1630         struct msix_entry *entry = dev_id;
1631         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1632         struct iwl_trans *trans = trans_pcie->trans;
1633
1634         trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1635
1636         if (WARN_ON(entry->entry >= trans->num_rx_queues))
1637                 return IRQ_NONE;
1638
1639         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1640
1641         local_bh_disable();
1642         iwl_pcie_rx_handle(trans, entry->entry);
1643         local_bh_enable();
1644
1645         iwl_pcie_clear_irq(trans, entry);
1646
1647         lock_map_release(&trans->sync_cmd_lockdep_map);
1648
1649         return IRQ_HANDLED;
1650 }
1651
1652 /*
1653  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1654  */
1655 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1656 {
1657         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1658         int i;
1659
1660         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1661         if (trans->cfg->internal_wimax_coex &&
1662             !trans->cfg->apmg_not_supported &&
1663             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1664                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
1665              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1666                             APMG_PS_CTRL_VAL_RESET_REQ))) {
1667                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1668                 iwl_op_mode_wimax_active(trans->op_mode);
1669                 wake_up(&trans_pcie->wait_command_queue);
1670                 return;
1671         }
1672
1673         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
1674                 if (!trans->txqs.txq[i])
1675                         continue;
1676                 del_timer(&trans->txqs.txq[i]->stuck_timer);
1677         }
1678
1679         /* The STATUS_FW_ERROR bit is set in this function. This must happen
1680          * before we wake up the command caller, to ensure a proper cleanup. */
1681         iwl_trans_fw_error(trans);
1682
1683         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1684         wake_up(&trans_pcie->wait_command_queue);
1685 }
1686
1687 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1688 {
1689         u32 inta;
1690
1691         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1692
1693         trace_iwlwifi_dev_irq(trans->dev);
1694
1695         /* Discover which interrupts are active/pending */
1696         inta = iwl_read32(trans, CSR_INT);
1697
1698         /* the thread will service interrupts and re-enable them */
1699         return inta;
1700 }
1701
1702 /* a device (PCI-E) page is 4096 bytes long */
1703 #define ICT_SHIFT       12
1704 #define ICT_SIZE        (1 << ICT_SHIFT)
1705 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1706
1707 /* interrupt handler using ict table, with this interrupt driver will
1708  * stop using INTA register to get device's interrupt, reading this register
1709  * is expensive, device will write interrupts in ICT dram table, increment
1710  * index then will fire interrupt to driver, driver will OR all ICT table
1711  * entries from current index up to table entry with 0 value. the result is
1712  * the interrupt we need to service, driver will set the entries back to 0 and
1713  * set index.
1714  */
1715 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1716 {
1717         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1718         u32 inta;
1719         u32 val = 0;
1720         u32 read;
1721
1722         trace_iwlwifi_dev_irq(trans->dev);
1723
1724         /* Ignore interrupt if there's nothing in NIC to service.
1725          * This may be due to IRQ shared with another device,
1726          * or due to sporadic interrupts thrown from our NIC. */
1727         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1728         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1729         if (!read)
1730                 return 0;
1731
1732         /*
1733          * Collect all entries up to the first 0, starting from ict_index;
1734          * note we already read at ict_index.
1735          */
1736         do {
1737                 val |= read;
1738                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1739                                 trans_pcie->ict_index, read);
1740                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1741                 trans_pcie->ict_index =
1742                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1743
1744                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1745                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1746                                            read);
1747         } while (read);
1748
1749         /* We should not get this value, just ignore it. */
1750         if (val == 0xffffffff)
1751                 val = 0;
1752
1753         /*
1754          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1755          * (bit 15 before shifting it to 31) to clear when using interrupt
1756          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1757          * so we use them to decide on the real state of the Rx bit.
1758          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1759          */
1760         if (val & 0xC0000)
1761                 val |= 0x8000;
1762
1763         inta = (0xff & val) | ((0xff00 & val) << 16);
1764         return inta;
1765 }
1766
1767 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1768 {
1769         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1770         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1771         bool hw_rfkill, prev, report;
1772
1773         mutex_lock(&trans_pcie->mutex);
1774         prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1775         hw_rfkill = iwl_is_rfkill_set(trans);
1776         if (hw_rfkill) {
1777                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1778                 set_bit(STATUS_RFKILL_HW, &trans->status);
1779         }
1780         if (trans_pcie->opmode_down)
1781                 report = hw_rfkill;
1782         else
1783                 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1784
1785         IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1786                  hw_rfkill ? "disable radio" : "enable radio");
1787
1788         isr_stats->rfkill++;
1789
1790         if (prev != report)
1791                 iwl_trans_pcie_rf_kill(trans, report);
1792         mutex_unlock(&trans_pcie->mutex);
1793
1794         if (hw_rfkill) {
1795                 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1796                                        &trans->status))
1797                         IWL_DEBUG_RF_KILL(trans,
1798                                           "Rfkill while SYNC HCMD in flight\n");
1799                 wake_up(&trans_pcie->wait_command_queue);
1800         } else {
1801                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1802                 if (trans_pcie->opmode_down)
1803                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1804         }
1805 }
1806
1807 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1808 {
1809         struct iwl_trans *trans = dev_id;
1810         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1811         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1812         u32 inta = 0;
1813         u32 handled = 0;
1814
1815         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1816
1817         spin_lock(&trans_pcie->irq_lock);
1818
1819         /* dram interrupt table not set yet,
1820          * use legacy interrupt.
1821          */
1822         if (likely(trans_pcie->use_ict))
1823                 inta = iwl_pcie_int_cause_ict(trans);
1824         else
1825                 inta = iwl_pcie_int_cause_non_ict(trans);
1826
1827         if (iwl_have_debug_level(IWL_DL_ISR)) {
1828                 IWL_DEBUG_ISR(trans,
1829                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1830                               inta, trans_pcie->inta_mask,
1831                               iwl_read32(trans, CSR_INT_MASK),
1832                               iwl_read32(trans, CSR_FH_INT_STATUS));
1833                 if (inta & (~trans_pcie->inta_mask))
1834                         IWL_DEBUG_ISR(trans,
1835                                       "We got a masked interrupt (0x%08x)\n",
1836                                       inta & (~trans_pcie->inta_mask));
1837         }
1838
1839         inta &= trans_pcie->inta_mask;
1840
1841         /*
1842          * Ignore interrupt if there's nothing in NIC to service.
1843          * This may be due to IRQ shared with another device,
1844          * or due to sporadic interrupts thrown from our NIC.
1845          */
1846         if (unlikely(!inta)) {
1847                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1848                 /*
1849                  * Re-enable interrupts here since we don't
1850                  * have anything to service
1851                  */
1852                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1853                         _iwl_enable_interrupts(trans);
1854                 spin_unlock(&trans_pcie->irq_lock);
1855                 lock_map_release(&trans->sync_cmd_lockdep_map);
1856                 return IRQ_NONE;
1857         }
1858
1859         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1860                 /*
1861                  * Hardware disappeared. It might have
1862                  * already raised an interrupt.
1863                  */
1864                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1865                 spin_unlock(&trans_pcie->irq_lock);
1866                 goto out;
1867         }
1868
1869         /* Ack/clear/reset pending uCode interrupts.
1870          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1871          */
1872         /* There is a hardware bug in the interrupt mask function that some
1873          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1874          * they are disabled in the CSR_INT_MASK register. Furthermore the
1875          * ICT interrupt handling mechanism has another bug that might cause
1876          * these unmasked interrupts fail to be detected. We workaround the
1877          * hardware bugs here by ACKing all the possible interrupts so that
1878          * interrupt coalescing can still be achieved.
1879          */
1880         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1881
1882         if (iwl_have_debug_level(IWL_DL_ISR))
1883                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1884                               inta, iwl_read32(trans, CSR_INT_MASK));
1885
1886         spin_unlock(&trans_pcie->irq_lock);
1887
1888         /* Now service all interrupt bits discovered above. */
1889         if (inta & CSR_INT_BIT_HW_ERR) {
1890                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
1891
1892                 /* Tell the device to stop sending interrupts */
1893                 iwl_disable_interrupts(trans);
1894
1895                 isr_stats->hw++;
1896                 iwl_pcie_irq_handle_error(trans);
1897
1898                 handled |= CSR_INT_BIT_HW_ERR;
1899
1900                 goto out;
1901         }
1902
1903         /* NIC fires this, but we don't use it, redundant with WAKEUP */
1904         if (inta & CSR_INT_BIT_SCD) {
1905                 IWL_DEBUG_ISR(trans,
1906                               "Scheduler finished to transmit the frame/frames.\n");
1907                 isr_stats->sch++;
1908         }
1909
1910         /* Alive notification via Rx interrupt will do the real work */
1911         if (inta & CSR_INT_BIT_ALIVE) {
1912                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1913                 isr_stats->alive++;
1914                 if (trans->trans_cfg->gen2) {
1915                         /*
1916                          * We can restock, since firmware configured
1917                          * the RFH
1918                          */
1919                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1920                 }
1921
1922                 handled |= CSR_INT_BIT_ALIVE;
1923         }
1924
1925         /* Safely ignore these bits for debug checks below */
1926         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1927
1928         /* HW RF KILL switch toggled */
1929         if (inta & CSR_INT_BIT_RF_KILL) {
1930                 iwl_pcie_handle_rfkill_irq(trans);
1931                 handled |= CSR_INT_BIT_RF_KILL;
1932         }
1933
1934         /* Chip got too hot and stopped itself */
1935         if (inta & CSR_INT_BIT_CT_KILL) {
1936                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1937                 isr_stats->ctkill++;
1938                 handled |= CSR_INT_BIT_CT_KILL;
1939         }
1940
1941         /* Error detected by uCode */
1942         if (inta & CSR_INT_BIT_SW_ERR) {
1943                 IWL_ERR(trans, "Microcode SW error detected. "
1944                         " Restarting 0x%X.\n", inta);
1945                 isr_stats->sw++;
1946                 iwl_pcie_irq_handle_error(trans);
1947                 handled |= CSR_INT_BIT_SW_ERR;
1948         }
1949
1950         /* uCode wakes up after power-down sleep */
1951         if (inta & CSR_INT_BIT_WAKEUP) {
1952                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1953                 iwl_pcie_rxq_check_wrptr(trans);
1954                 iwl_pcie_txq_check_wrptrs(trans);
1955
1956                 isr_stats->wakeup++;
1957
1958                 handled |= CSR_INT_BIT_WAKEUP;
1959         }
1960
1961         /* All uCode command responses, including Tx command responses,
1962          * Rx "responses" (frame-received notification), and other
1963          * notifications from uCode come through here*/
1964         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1965                     CSR_INT_BIT_RX_PERIODIC)) {
1966                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1967                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1968                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1969                         iwl_write32(trans, CSR_FH_INT_STATUS,
1970                                         CSR_FH_INT_RX_MASK);
1971                 }
1972                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1973                         handled |= CSR_INT_BIT_RX_PERIODIC;
1974                         iwl_write32(trans,
1975                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1976                 }
1977                 /* Sending RX interrupt require many steps to be done in the
1978                  * the device:
1979                  * 1- write interrupt to current index in ICT table.
1980                  * 2- dma RX frame.
1981                  * 3- update RX shared data to indicate last write index.
1982                  * 4- send interrupt.
1983                  * This could lead to RX race, driver could receive RX interrupt
1984                  * but the shared data changes does not reflect this;
1985                  * periodic interrupt will detect any dangling Rx activity.
1986                  */
1987
1988                 /* Disable periodic interrupt; we use it as just a one-shot. */
1989                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1990                             CSR_INT_PERIODIC_DIS);
1991
1992                 /*
1993                  * Enable periodic interrupt in 8 msec only if we received
1994                  * real RX interrupt (instead of just periodic int), to catch
1995                  * any dangling Rx interrupt.  If it was just the periodic
1996                  * interrupt, there was no dangling Rx activity, and no need
1997                  * to extend the periodic interrupt; one-shot is enough.
1998                  */
1999                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
2000                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
2001                                    CSR_INT_PERIODIC_ENA);
2002
2003                 isr_stats->rx++;
2004
2005                 local_bh_disable();
2006                 iwl_pcie_rx_handle(trans, 0);
2007                 local_bh_enable();
2008         }
2009
2010         /* This "Tx" DMA channel is used only for loading uCode */
2011         if (inta & CSR_INT_BIT_FH_TX) {
2012                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
2013                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2014                 isr_stats->tx++;
2015                 handled |= CSR_INT_BIT_FH_TX;
2016                 /* Wake up uCode load routine, now that load is complete */
2017                 trans_pcie->ucode_write_complete = true;
2018                 wake_up(&trans_pcie->ucode_write_waitq);
2019         }
2020
2021         if (inta & ~handled) {
2022                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
2023                 isr_stats->unhandled++;
2024         }
2025
2026         if (inta & ~(trans_pcie->inta_mask)) {
2027                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
2028                          inta & ~trans_pcie->inta_mask);
2029         }
2030
2031         spin_lock(&trans_pcie->irq_lock);
2032         /* only Re-enable all interrupt if disabled by irq */
2033         if (test_bit(STATUS_INT_ENABLED, &trans->status))
2034                 _iwl_enable_interrupts(trans);
2035         /* we are loading the firmware, enable FH_TX interrupt only */
2036         else if (handled & CSR_INT_BIT_FH_TX)
2037                 iwl_enable_fw_load_int(trans);
2038         /* Re-enable RF_KILL if it occurred */
2039         else if (handled & CSR_INT_BIT_RF_KILL)
2040                 iwl_enable_rfkill_int(trans);
2041         /* Re-enable the ALIVE / Rx interrupt if it occurred */
2042         else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX))
2043                 iwl_enable_fw_load_int_ctx_info(trans);
2044         spin_unlock(&trans_pcie->irq_lock);
2045
2046 out:
2047         lock_map_release(&trans->sync_cmd_lockdep_map);
2048         return IRQ_HANDLED;
2049 }
2050
2051 /******************************************************************************
2052  *
2053  * ICT functions
2054  *
2055  ******************************************************************************/
2056
2057 /* Free dram table */
2058 void iwl_pcie_free_ict(struct iwl_trans *trans)
2059 {
2060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2061
2062         if (trans_pcie->ict_tbl) {
2063                 dma_free_coherent(trans->dev, ICT_SIZE,
2064                                   trans_pcie->ict_tbl,
2065                                   trans_pcie->ict_tbl_dma);
2066                 trans_pcie->ict_tbl = NULL;
2067                 trans_pcie->ict_tbl_dma = 0;
2068         }
2069 }
2070
2071 /*
2072  * allocate dram shared table, it is an aligned memory
2073  * block of ICT_SIZE.
2074  * also reset all data related to ICT table interrupt.
2075  */
2076 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
2077 {
2078         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2079
2080         trans_pcie->ict_tbl =
2081                 dma_alloc_coherent(trans->dev, ICT_SIZE,
2082                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
2083         if (!trans_pcie->ict_tbl)
2084                 return -ENOMEM;
2085
2086         /* just an API sanity check ... it is guaranteed to be aligned */
2087         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
2088                 iwl_pcie_free_ict(trans);
2089                 return -EINVAL;
2090         }
2091
2092         return 0;
2093 }
2094
2095 /* Device is going up inform it about using ICT interrupt table,
2096  * also we need to tell the driver to start using ICT interrupt.
2097  */
2098 void iwl_pcie_reset_ict(struct iwl_trans *trans)
2099 {
2100         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2101         u32 val;
2102
2103         if (!trans_pcie->ict_tbl)
2104                 return;
2105
2106         spin_lock(&trans_pcie->irq_lock);
2107         _iwl_disable_interrupts(trans);
2108
2109         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
2110
2111         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
2112
2113         val |= CSR_DRAM_INT_TBL_ENABLE |
2114                CSR_DRAM_INIT_TBL_WRAP_CHECK |
2115                CSR_DRAM_INIT_TBL_WRITE_POINTER;
2116
2117         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2118
2119         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2120         trans_pcie->use_ict = true;
2121         trans_pcie->ict_index = 0;
2122         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2123         _iwl_enable_interrupts(trans);
2124         spin_unlock(&trans_pcie->irq_lock);
2125 }
2126
2127 /* Device is going down disable ict interrupt usage */
2128 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2129 {
2130         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2131
2132         spin_lock(&trans_pcie->irq_lock);
2133         trans_pcie->use_ict = false;
2134         spin_unlock(&trans_pcie->irq_lock);
2135 }
2136
2137 irqreturn_t iwl_pcie_isr(int irq, void *data)
2138 {
2139         struct iwl_trans *trans = data;
2140
2141         if (!trans)
2142                 return IRQ_NONE;
2143
2144         /* Disable (but don't clear!) interrupts here to avoid
2145          * back-to-back ISRs and sporadic interrupts from our NIC.
2146          * If we have something to service, the tasklet will re-enable ints.
2147          * If we *don't* have something, we'll re-enable before leaving here.
2148          */
2149         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2150
2151         return IRQ_WAKE_THREAD;
2152 }
2153
2154 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2155 {
2156         return IRQ_WAKE_THREAD;
2157 }
2158
2159 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2160 {
2161         struct msix_entry *entry = dev_id;
2162         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2163         struct iwl_trans *trans = trans_pcie->trans;
2164         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2165         u32 inta_fh, inta_hw;
2166
2167         lock_map_acquire(&trans->sync_cmd_lockdep_map);
2168
2169         spin_lock(&trans_pcie->irq_lock);
2170         inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2171         inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2172         /*
2173          * Clear causes registers to avoid being handling the same cause.
2174          */
2175         iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
2176         iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2177         spin_unlock(&trans_pcie->irq_lock);
2178
2179         trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2180
2181         if (unlikely(!(inta_fh | inta_hw))) {
2182                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2183                 lock_map_release(&trans->sync_cmd_lockdep_map);
2184                 return IRQ_NONE;
2185         }
2186
2187         if (iwl_have_debug_level(IWL_DL_ISR)) {
2188                 IWL_DEBUG_ISR(trans,
2189                               "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2190                               inta_fh, trans_pcie->fh_mask,
2191                               iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2192                 if (inta_fh & ~trans_pcie->fh_mask)
2193                         IWL_DEBUG_ISR(trans,
2194                                       "We got a masked interrupt (0x%08x)\n",
2195                                       inta_fh & ~trans_pcie->fh_mask);
2196         }
2197
2198         inta_fh &= trans_pcie->fh_mask;
2199
2200         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2201             inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2202                 local_bh_disable();
2203                 iwl_pcie_rx_handle(trans, 0);
2204                 local_bh_enable();
2205         }
2206
2207         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2208             inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2209                 local_bh_disable();
2210                 iwl_pcie_rx_handle(trans, 1);
2211                 local_bh_enable();
2212         }
2213
2214         /* This "Tx" DMA channel is used only for loading uCode */
2215         if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2216                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2217                 isr_stats->tx++;
2218                 /*
2219                  * Wake up uCode load routine,
2220                  * now that load is complete
2221                  */
2222                 trans_pcie->ucode_write_complete = true;
2223                 wake_up(&trans_pcie->ucode_write_waitq);
2224         }
2225
2226         /* Error detected by uCode */
2227         if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
2228             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) {
2229                 IWL_ERR(trans,
2230                         "Microcode SW error detected. Restarting 0x%X.\n",
2231                         inta_fh);
2232                 isr_stats->sw++;
2233                 iwl_pcie_irq_handle_error(trans);
2234         }
2235
2236         /* After checking FH register check HW register */
2237         if (iwl_have_debug_level(IWL_DL_ISR)) {
2238                 IWL_DEBUG_ISR(trans,
2239                               "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2240                               inta_hw, trans_pcie->hw_mask,
2241                               iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2242                 if (inta_hw & ~trans_pcie->hw_mask)
2243                         IWL_DEBUG_ISR(trans,
2244                                       "We got a masked interrupt 0x%08x\n",
2245                                       inta_hw & ~trans_pcie->hw_mask);
2246         }
2247
2248         inta_hw &= trans_pcie->hw_mask;
2249
2250         /* Alive notification via Rx interrupt will do the real work */
2251         if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2252                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2253                 isr_stats->alive++;
2254                 if (trans->trans_cfg->gen2) {
2255                         /* We can restock, since firmware configured the RFH */
2256                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2257                 }
2258         }
2259
2260         if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2261                 u32 sleep_notif =
2262                         le32_to_cpu(trans_pcie->prph_info->sleep_notif);
2263                 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND ||
2264                     sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) {
2265                         IWL_DEBUG_ISR(trans,
2266                                       "Sx interrupt: sleep notification = 0x%x\n",
2267                                       sleep_notif);
2268                         trans_pcie->sx_complete = true;
2269                         wake_up(&trans_pcie->sx_waitq);
2270                 } else {
2271                         /* uCode wakes up after power-down sleep */
2272                         IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2273                         iwl_pcie_rxq_check_wrptr(trans);
2274                         iwl_pcie_txq_check_wrptrs(trans);
2275
2276                         isr_stats->wakeup++;
2277                 }
2278         }
2279
2280         if (inta_hw & MSIX_HW_INT_CAUSES_REG_IML) {
2281                 /* Reflect IML transfer status */
2282                 int res = iwl_read32(trans, CSR_IML_RESP_ADDR);
2283
2284                 IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res);
2285                 if (res == IWL_IMAGE_RESP_FAIL) {
2286                         isr_stats->sw++;
2287                         iwl_pcie_irq_handle_error(trans);
2288                 }
2289         }
2290
2291         /* Chip got too hot and stopped itself */
2292         if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2293                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2294                 isr_stats->ctkill++;
2295         }
2296
2297         /* HW RF KILL switch toggled */
2298         if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2299                 iwl_pcie_handle_rfkill_irq(trans);
2300
2301         if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2302                 IWL_ERR(trans,
2303                         "Hardware error detected. Restarting.\n");
2304
2305                 isr_stats->hw++;
2306                 trans->dbg.hw_error = true;
2307                 iwl_pcie_irq_handle_error(trans);
2308         }
2309
2310         iwl_pcie_clear_irq(trans, entry);
2311
2312         lock_map_release(&trans->sync_cmd_lockdep_map);
2313
2314         return IRQ_HANDLED;
2315 }