drivers/net/wireless/intel/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope that it will be useful, but WITHOUT
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  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20  * more details.
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <linuxwifi@intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  * BSD LICENSE
  30  *
  31  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 - 2019 Intel Corporation
  35  * All rights reserved.
  36  *
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  38  * modification, are permitted provided that the following conditions
  39  * are met:
  40  *
  41  *  * Redistributions of source code must retain the above copyright
  42  *    notice, this list of conditions and the following disclaimer.
  43  *  * Redistributions in binary form must reproduce the above copyright
  44  *    notice, this list of conditions and the following disclaimer in
  45  *    the documentation and/or other materials provided with the
  46  *    distribution.
  47  *  * Neither the name Intel Corporation nor the names of its
  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  56  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  57  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  58  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  59  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/sched.h>
  65 #include <linux/wait.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-prph.h"
  69 #include "iwl-io.h"
  70 #include "internal.h"
  71 #include "iwl-op-mode.h"
  72 #include "iwl-context-info-gen3.h"
  73
  74 /******************************************************************************
  75  *
  76  * RX path functions
  77  *
  78  ******************************************************************************/
  79
  80 /*
  81  * Rx theory of operation
  82  *
  83  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  84  * each of which point to Receive Buffers to be filled by the NIC.  These get
  85  * used not only for Rx frames, but for any command response or notification
  86  * from the NIC.  The driver and NIC manage the Rx buffers by means
  87  * of indexes into the circular buffer.
  88  *
  89  * Rx Queue Indexes
  90  * The host/firmware share two index registers for managing the Rx buffers.
  91  *
  92  * The READ index maps to the first position that the firmware may be writing
  93  * to -- the driver can read up to (but not including) this position and get
  94  * good data.
  95  * The READ index is managed by the firmware once the card is enabled.
  96  *
  97  * The WRITE index maps to the last position the driver has read from -- the
  98  * position preceding WRITE is the last slot the firmware can place a packet.
  99  *
 100  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
 101  * WRITE = READ.
 102  *
 103  * During initialization, the host sets up the READ queue position to the first
 104  * INDEX position, and WRITE to the last (READ - 1 wrapped)
 105  *
 106  * When the firmware places a packet in a buffer, it will advance the READ index
 107  * and fire the RX interrupt.  The driver can then query the READ index and
 108  * process as many packets as possible, moving the WRITE index forward as it
 109  * resets the Rx queue buffers with new memory.
 110  *
 111  * The management in the driver is as follows:
 112  * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
 113  *   When the interrupt handler is called, the request is processed.
 114  *   The page is either stolen - transferred to the upper layer
 115  *   or reused - added immediately to the iwl->rxq->rx_free list.
 116  * + When the page is stolen - the driver updates the matching queue's used
 117  *   count, detaches the RBD and transfers it to the queue used list.
 118  *   When there are two used RBDs - they are transferred to the allocator empty
 119  *   list. Work is then scheduled for the allocator to start allocating
 120  *   eight buffers.
 121  *   When there are another 6 used RBDs - they are transferred to the allocator
 122  *   empty list and the driver tries to claim the pre-allocated buffers and
 123  *   add them to iwl->rxq->rx_free. If it fails - it continues to claim them
 124  *   until ready.
 125  *   When there are 8+ buffers in the free list - either from allocation or from
 126  *   8 reused unstolen pages - restock is called to update the FW and indexes.
 127  * + In order to make sure the allocator always has RBDs to use for allocation
 128  *   the allocator has initial pool in the size of num_queues*(8-2) - the
 129  *   maximum missing RBDs per allocation request (request posted with 2
 130  *    empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
 131  *   The queues supplies the recycle of the rest of the RBDs.
 132  * + A received packet is processed and handed to the kernel network stack,
 133  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 134  * + If there are no allocated buffers in iwl->rxq->rx_free,
 135  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
 136  *   If there were enough free buffers and RX_STALLED is set it is cleared.
 137  *
 138  *
 139  * Driver sequence:
 140  *
 141  * iwl_rxq_alloc()            Allocates rx_free
 142  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
 143  *                            iwl_pcie_rxq_restock.
 144  *                            Used only during initialization.
 145  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
 146  *                            queue, updates firmware pointers, and updates
 147  *                            the WRITE index.
 148  * iwl_pcie_rx_allocator()     Background work for allocating pages.
 149  *
 150  * -- enable interrupts --
 151  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 152  *                            READ INDEX, detaching the SKB from the pool.
 153  *                            Moves the packet buffer from queue to rx_used.
 154  *                            Posts and claims requests to the allocator.
 155  *                            Calls iwl_pcie_rxq_restock to refill any empty
 156  *                            slots.
 157  *
 158  * RBD life-cycle:
 159  *
 160  * Init:
 161  * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
 162  *
 163  * Regular Receive interrupt:
 164  * Page Stolen:
 165  * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
 166  * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
 167  * Page not Stolen:
 168  * rxq.queue -> rxq.rx_free -> rxq.queue
 169  * ...
 170  *
 171  */
 172
 173 /*
 174  * iwl_rxq_space - Return number of free slots available in queue.
 175  */
 176 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 177 {
 178         /* Make sure rx queue size is a power of 2 */
 179         WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
 180
 181         /*
 182          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 183          * between empty and completely full queues.
 184          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 185          * defined for negative dividends.
 186          */
 187         return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
 188 }
 189
 190 /*
 191  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 192  */
 193 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 194 {
 195         return cpu_to_le32((u32)(dma_addr >> 8));
 196 }
 197
 198 /*
 199  * iwl_pcie_rx_stop - stops the Rx DMA
 200  */
 201 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 202 {
 203         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
 204                 /* TODO: remove this once fw does it */
 205                 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
 206                 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3,
 207                                               RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 208         } else if (trans->trans_cfg->mq_rx_supported) {
 209                 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
 210                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
 211                                            RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 212         } else {
 213                 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 214                 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 215                                            FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 216                                            1000);
 217         }
 218 }
 219
 220 /*
 221  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 222  */
 223 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 224                                     struct iwl_rxq *rxq)
 225 {
 226         u32 reg;
 227
 228         lockdep_assert_held(&rxq->lock);
 229
 230         /*
 231          * explicitly wake up the NIC if:
 232          * 1. shadow registers aren't enabled
 233          * 2. there is a chance that the NIC is asleep
 234          */
 235         if (!trans->trans_cfg->base_params->shadow_reg_enable &&
 236             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 237                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 238
 239                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 240                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 241                                        reg);
 242                         iwl_set_bit(trans, CSR_GP_CNTRL,
 243                                     BIT(trans->trans_cfg->csr->flag_mac_access_req));
 244                         rxq->need_update = true;
 245                         return;
 246                 }
 247         }
 248
 249         rxq->write_actual = round_down(rxq->write, 8);
 250         if (trans->trans_cfg->mq_rx_supported)
 251                 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
 252                             rxq->write_actual);
 253         else
 254                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 255 }
 256
 257 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 258 {
 259         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 260         int i;
 261
 262         for (i = 0; i < trans->num_rx_queues; i++) {
 263                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 264
 265                 if (!rxq->need_update)
 266                         continue;
 267                 spin_lock(&rxq->lock);
 268                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 269                 rxq->need_update = false;
 270                 spin_unlock(&rxq->lock);
 271         }
 272 }
 273
 274 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
 275                                 struct iwl_rxq *rxq,
 276                                 struct iwl_rx_mem_buffer *rxb)
 277 {
 278         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
 279                 struct iwl_rx_transfer_desc *bd = rxq->bd;
 280
 281                 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64));
 282
 283                 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
 284                 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
 285         } else {
 286                 __le64 *bd = rxq->bd;
 287
 288                 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
 289         }
 290
 291         IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
 292                      (u32)rxb->vid, rxq->id, rxq->write);
 293 }
 294
 295 /*
 296  * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
 297  */
 298 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
 299                                   struct iwl_rxq *rxq)
 300 {
 301         struct iwl_rx_mem_buffer *rxb;
 302
 303         /*
 304          * If the device isn't enabled - no need to try to add buffers...
 305          * This can happen when we stop the device and still have an interrupt
 306          * pending. We stop the APM before we sync the interrupts because we
 307          * have to (see comment there). On the other hand, since the APM is
 308          * stopped, we cannot access the HW (in particular not prph).
 309          * So don't try to restock if the APM has been already stopped.
 310          */
 311         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 312                 return;
 313
 314         spin_lock(&rxq->lock);
 315         while (rxq->free_count) {
 316                 /* Get next free Rx buffer, remove from free list */
 317                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 318                                        list);
 319                 list_del(&rxb->list);
 320                 rxb->invalid = false;
 321                 /* 12 first bits are expected to be empty */
 322                 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
 323                 /* Point to Rx buffer via next RBD in circular buffer */
 324                 iwl_pcie_restock_bd(trans, rxq, rxb);
 325                 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1);
 326                 rxq->free_count--;
 327         }
 328         spin_unlock(&rxq->lock);
 329
 330         /*
 331          * If we've added more space for the firmware to place data, tell it.
 332          * Increment device's write pointer in multiples of 8.
 333          */
 334         if (rxq->write_actual != (rxq->write & ~0x7)) {
 335                 spin_lock(&rxq->lock);
 336                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 337                 spin_unlock(&rxq->lock);
 338         }
 339 }
 340
 341 /*
 342  * iwl_pcie_rxsq_restock - restock implementation for single queue rx
 343  */
 344 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
 345                                   struct iwl_rxq *rxq)
 346 {
 347         struct iwl_rx_mem_buffer *rxb;
 348
 349         /*
 350          * If the device isn't enabled - not need to try to add buffers...
 351          * This can happen when we stop the device and still have an interrupt
 352          * pending. We stop the APM before we sync the interrupts because we
 353          * have to (see comment there). On the other hand, since the APM is
 354          * stopped, we cannot access the HW (in particular not prph).
 355          * So don't try to restock if the APM has been already stopped.
 356          */
 357         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 358                 return;
 359
 360         spin_lock(&rxq->lock);
 361         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 362                 __le32 *bd = (__le32 *)rxq->bd;
 363                 /* The overwritten rxb must be a used one */
 364                 rxb = rxq->queue[rxq->write];
 365                 BUG_ON(rxb && rxb->page);
 366
 367                 /* Get next free Rx buffer, remove from free list */
 368                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 369                                        list);
 370                 list_del(&rxb->list);
 371                 rxb->invalid = false;
 372
 373                 /* Point to Rx buffer via next RBD in circular buffer */
 374                 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 375                 rxq->queue[rxq->write] = rxb;
 376                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 377                 rxq->free_count--;
 378         }
 379         spin_unlock(&rxq->lock);
 380
 381         /* If we've added more space for the firmware to place data, tell it.
 382          * Increment device's write pointer in multiples of 8. */
 383         if (rxq->write_actual != (rxq->write & ~0x7)) {
 384                 spin_lock(&rxq->lock);
 385                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 386                 spin_unlock(&rxq->lock);
 387         }
 388 }
 389
 390 /*
 391  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 392  *
 393  * If there are slots in the RX queue that need to be restocked,
 394  * and we have free pre-allocated buffers, fill the ranks as much
 395  * as we can, pulling from rx_free.
 396  *
 397  * This moves the 'write' index forward to catch up with 'processed', and
 398  * also updates the memory address in the firmware to reference the new
 399  * target buffer.
 400  */
 401 static
 402 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
 403 {
 404         if (trans->trans_cfg->mq_rx_supported)
 405                 iwl_pcie_rxmq_restock(trans, rxq);
 406         else
 407                 iwl_pcie_rxsq_restock(trans, rxq);
 408 }
 409
 410 /*
 411  * iwl_pcie_rx_alloc_page - allocates and returns a page.
 412  *
 413  */
 414 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
 415                                            gfp_t priority)
 416 {
 417         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 418         struct page *page;
 419         gfp_t gfp_mask = priority;
 420
 421         if (trans_pcie->rx_page_order > 0)
 422                 gfp_mask |= __GFP_COMP;
 423
 424         /* Alloc a new receive buffer */
 425         page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 426         if (!page) {
 427                 if (net_ratelimit())
 428                         IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
 429                                        trans_pcie->rx_page_order);
 430                 /*
 431                  * Issue an error if we don't have enough pre-allocated
 432                   * buffers.
 433                  */
 434                 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
 435                         IWL_CRIT(trans,
 436                                  "Failed to alloc_pages\n");
 437                 return NULL;
 438         }
 439         return page;
 440 }
 441
 442 /*
 443  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 444  *
 445  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 446  * a page must be allocated and the RBD must point to the page. This function
 447  * doesn't change the HW pointer but handles the list of pages that is used by
 448  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 449  * allocated buffers.
 450  */
 451 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
 452                             struct iwl_rxq *rxq)
 453 {
 454         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 455         struct iwl_rx_mem_buffer *rxb;
 456         struct page *page;
 457
 458         while (1) {
 459                 spin_lock(&rxq->lock);
 460                 if (list_empty(&rxq->rx_used)) {
 461                         spin_unlock(&rxq->lock);
 462                         return;
 463                 }
 464                 spin_unlock(&rxq->lock);
 465
 466                 /* Alloc a new receive buffer */
 467                 page = iwl_pcie_rx_alloc_page(trans, priority);
 468                 if (!page)
 469                         return;
 470
 471                 spin_lock(&rxq->lock);
 472
 473                 if (list_empty(&rxq->rx_used)) {
 474                         spin_unlock(&rxq->lock);
 475                         __free_pages(page, trans_pcie->rx_page_order);
 476                         return;
 477                 }
 478                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 479                                        list);
 480                 list_del(&rxb->list);
 481                 spin_unlock(&rxq->lock);
 482
 483                 BUG_ON(rxb->page);
 484                 rxb->page = page;
 485                 /* Get physical address of the RB */
 486                 rxb->page_dma =
 487                         dma_map_page(trans->dev, page, 0,
 488                                      PAGE_SIZE << trans_pcie->rx_page_order,
 489                                      DMA_FROM_DEVICE);
 490                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 491                         rxb->page = NULL;
 492                         spin_lock(&rxq->lock);
 493                         list_add(&rxb->list, &rxq->rx_used);
 494                         spin_unlock(&rxq->lock);
 495                         __free_pages(page, trans_pcie->rx_page_order);
 496                         return;
 497                 }
 498
 499                 spin_lock(&rxq->lock);
 500
 501                 list_add_tail(&rxb->list, &rxq->rx_free);
 502                 rxq->free_count++;
 503
 504                 spin_unlock(&rxq->lock);
 505         }
 506 }
 507
 508 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
 509 {
 510         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 511         int i;
 512
 513         for (i = 0; i < RX_POOL_SIZE; i++) {
 514                 if (!trans_pcie->rx_pool[i].page)
 515                         continue;
 516                 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
 517                                PAGE_SIZE << trans_pcie->rx_page_order,
 518                                DMA_FROM_DEVICE);
 519                 __free_pages(trans_pcie->rx_pool[i].page,
 520                              trans_pcie->rx_page_order);
 521                 trans_pcie->rx_pool[i].page = NULL;
 522         }
 523 }
 524
 525 /*
 526  * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
 527  *
 528  * Allocates for each received request 8 pages
 529  * Called as a scheduled work item.
 530  */
 531 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
 532 {
 533         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 534         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 535         struct list_head local_empty;
 536         int pending = atomic_read(&rba->req_pending);
 537
 538         IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending);
 539
 540         /* If we were scheduled - there is at least one request */
 541         spin_lock(&rba->lock);
 542         /* swap out the rba->rbd_empty to a local list */
 543         list_replace_init(&rba->rbd_empty, &local_empty);
 544         spin_unlock(&rba->lock);
 545
 546         while (pending) {
 547                 int i;
 548                 LIST_HEAD(local_allocated);
 549                 gfp_t gfp_mask = GFP_KERNEL;
 550
 551                 /* Do not post a warning if there are only a few requests */
 552                 if (pending < RX_PENDING_WATERMARK)
 553                         gfp_mask |= __GFP_NOWARN;
 554
 555                 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
 556                         struct iwl_rx_mem_buffer *rxb;
 557                         struct page *page;
 558
 559                         /* List should never be empty - each reused RBD is
 560                          * returned to the list, and initial pool covers any
 561                          * possible gap between the time the page is allocated
 562                          * to the time the RBD is added.
 563                          */
 564                         BUG_ON(list_empty(&local_empty));
 565                         /* Get the first rxb from the rbd list */
 566                         rxb = list_first_entry(&local_empty,
 567                                                struct iwl_rx_mem_buffer, list);
 568                         BUG_ON(rxb->page);
 569
 570                         /* Alloc a new receive buffer */
 571                         page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
 572                         if (!page)
 573                                 continue;
 574                         rxb->page = page;
 575
 576                         /* Get physical address of the RB */
 577                         rxb->page_dma = dma_map_page(trans->dev, page, 0,
 578                                         PAGE_SIZE << trans_pcie->rx_page_order,
 579                                         DMA_FROM_DEVICE);
 580                         if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 581                                 rxb->page = NULL;
 582                                 __free_pages(page, trans_pcie->rx_page_order);
 583                                 continue;
 584                         }
 585
 586                         /* move the allocated entry to the out list */
 587                         list_move(&rxb->list, &local_allocated);
 588                         i++;
 589                 }
 590
 591                 atomic_dec(&rba->req_pending);
 592                 pending--;
 593
 594                 if (!pending) {
 595                         pending = atomic_read(&rba->req_pending);
 596                         if (pending)
 597                                 IWL_DEBUG_TPT(trans,
 598                                               "Got more pending allocation requests = %d\n",
 599                                               pending);
 600                 }
 601
 602                 spin_lock(&rba->lock);
 603                 /* add the allocated rbds to the allocator allocated list */
 604                 list_splice_tail(&local_allocated, &rba->rbd_allocated);
 605                 /* get more empty RBDs for current pending requests */
 606                 list_splice_tail_init(&rba->rbd_empty, &local_empty);
 607                 spin_unlock(&rba->lock);
 608
 609                 atomic_inc(&rba->req_ready);
 610
 611         }
 612
 613         spin_lock(&rba->lock);
 614         /* return unused rbds to the allocator empty list */
 615         list_splice_tail(&local_empty, &rba->rbd_empty);
 616         spin_unlock(&rba->lock);
 617
 618         IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__);
 619 }
 620
 621 /*
 622  * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
 623 .*
 624 .* Called by queue when the queue posted allocation request and
 625  * has freed 8 RBDs in order to restock itself.
 626  * This function directly moves the allocated RBs to the queue's ownership
 627  * and updates the relevant counters.
 628  */
 629 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
 630                                       struct iwl_rxq *rxq)
 631 {
 632         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 633         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 634         int i;
 635
 636         lockdep_assert_held(&rxq->lock);
 637
 638         /*
 639          * atomic_dec_if_positive returns req_ready - 1 for any scenario.
 640          * If req_ready is 0 atomic_dec_if_positive will return -1 and this
 641          * function will return early, as there are no ready requests.
 642          * atomic_dec_if_positive will perofrm the *actual* decrement only if
 643          * req_ready > 0, i.e. - there are ready requests and the function
 644          * hands one request to the caller.
 645          */
 646         if (atomic_dec_if_positive(&rba->req_ready) < 0)
 647                 return;
 648
 649         spin_lock(&rba->lock);
 650         for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
 651                 /* Get next free Rx buffer, remove it from free list */
 652                 struct iwl_rx_mem_buffer *rxb =
 653                         list_first_entry(&rba->rbd_allocated,
 654                                          struct iwl_rx_mem_buffer, list);
 655
 656                 list_move(&rxb->list, &rxq->rx_free);
 657         }
 658         spin_unlock(&rba->lock);
 659
 660         rxq->used_count -= RX_CLAIM_REQ_ALLOC;
 661         rxq->free_count += RX_CLAIM_REQ_ALLOC;
 662 }
 663
 664 void iwl_pcie_rx_allocator_work(struct work_struct *data)
 665 {
 666         struct iwl_rb_allocator *rba_p =
 667                 container_of(data, struct iwl_rb_allocator, rx_alloc);
 668         struct iwl_trans_pcie *trans_pcie =
 669                 container_of(rba_p, struct iwl_trans_pcie, rba);
 670
 671         iwl_pcie_rx_allocator(trans_pcie->trans);
 672 }
 673
 674 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
 675 {
 676         struct iwl_rx_transfer_desc *rx_td;
 677
 678         if (use_rx_td)
 679                 return sizeof(*rx_td);
 680         else
 681                 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) :
 682                         sizeof(__le32);
 683 }
 684
 685 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
 686                                   struct iwl_rxq *rxq)
 687 {
 688         struct device *dev = trans->dev;
 689         bool use_rx_td = (trans->trans_cfg->device_family >=
 690                           IWL_DEVICE_FAMILY_AX210);
 691         int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
 692
 693         if (rxq->bd)
 694                 dma_free_coherent(trans->dev,
 695                                   free_size * rxq->queue_size,
 696                                   rxq->bd, rxq->bd_dma);
 697         rxq->bd_dma = 0;
 698         rxq->bd = NULL;
 699
 700         rxq->rb_stts_dma = 0;
 701         rxq->rb_stts = NULL;
 702
 703         if (rxq->used_bd)
 704                 dma_free_coherent(trans->dev,
 705                                   (use_rx_td ? sizeof(*rxq->cd) :
 706                                    sizeof(__le32)) * rxq->queue_size,
 707                                   rxq->used_bd, rxq->used_bd_dma);
 708         rxq->used_bd_dma = 0;
 709         rxq->used_bd = NULL;
 710
 711         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
 712                 return;
 713
 714         if (rxq->tr_tail)
 715                 dma_free_coherent(dev, sizeof(__le16),
 716                                   rxq->tr_tail, rxq->tr_tail_dma);
 717         rxq->tr_tail_dma = 0;
 718         rxq->tr_tail = NULL;
 719
 720         if (rxq->cr_tail)
 721                 dma_free_coherent(dev, sizeof(__le16),
 722                                   rxq->cr_tail, rxq->cr_tail_dma);
 723         rxq->cr_tail_dma = 0;
 724         rxq->cr_tail = NULL;
 725 }
 726
 727 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
 728                                   struct iwl_rxq *rxq)
 729 {
 730         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 731         struct device *dev = trans->dev;
 732         int i;
 733         int free_size;
 734         bool use_rx_td = (trans->trans_cfg->device_family >=
 735                           IWL_DEVICE_FAMILY_AX210);
 736         size_t rb_stts_size = use_rx_td ? sizeof(__le16) :
 737                               sizeof(struct iwl_rb_status);
 738
 739         spin_lock_init(&rxq->lock);
 740         if (trans->trans_cfg->mq_rx_supported)
 741                 rxq->queue_size = MQ_RX_TABLE_SIZE;
 742         else
 743                 rxq->queue_size = RX_QUEUE_SIZE;
 744
 745         free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
 746
 747         /*
 748          * Allocate the circular buffer of Read Buffer Descriptors
 749          * (RBDs)
 750          */
 751         rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size,
 752                                      &rxq->bd_dma, GFP_KERNEL);
 753         if (!rxq->bd)
 754                 goto err;
 755
 756         if (trans->trans_cfg->mq_rx_supported) {
 757                 rxq->used_bd = dma_alloc_coherent(dev,
 758                                                   (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size,
 759                                                   &rxq->used_bd_dma,
 760                                                   GFP_KERNEL);
 761                 if (!rxq->used_bd)
 762                         goto err;
 763         }
 764
 765         rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size;
 766         rxq->rb_stts_dma =
 767                 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size;
 768
 769         if (!use_rx_td)
 770                 return 0;
 771
 772         /* Allocate the driver's pointer to TR tail */
 773         rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16),
 774                                           &rxq->tr_tail_dma, GFP_KERNEL);
 775         if (!rxq->tr_tail)
 776                 goto err;
 777
 778         /* Allocate the driver's pointer to CR tail */
 779         rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16),
 780                                           &rxq->cr_tail_dma, GFP_KERNEL);
 781         if (!rxq->cr_tail)
 782                 goto err;
 783
 784         return 0;
 785
 786 err:
 787         for (i = 0; i < trans->num_rx_queues; i++) {
 788                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 789
 790                 iwl_pcie_free_rxq_dma(trans, rxq);
 791         }
 792
 793         return -ENOMEM;
 794 }
 795
 796 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 797 {
 798         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 799         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 800         int i, ret;
 801         size_t rb_stts_size = trans->trans_cfg->device_family >=
 802                                 IWL_DEVICE_FAMILY_AX210 ?
 803                               sizeof(__le16) : sizeof(struct iwl_rb_status);
 804
 805         if (WARN_ON(trans_pcie->rxq))
 806                 return -EINVAL;
 807
 808         trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
 809                                   GFP_KERNEL);
 810         if (!trans_pcie->rxq)
 811                 return -ENOMEM;
 812
 813         spin_lock_init(&rba->lock);
 814
 815         /*
 816          * Allocate the driver's pointer to receive buffer status.
 817          * Allocate for all queues continuously (HW requirement).
 818          */
 819         trans_pcie->base_rb_stts =
 820                         dma_alloc_coherent(trans->dev,
 821                                            rb_stts_size * trans->num_rx_queues,
 822                                            &trans_pcie->base_rb_stts_dma,
 823                                            GFP_KERNEL);
 824         if (!trans_pcie->base_rb_stts) {
 825                 ret = -ENOMEM;
 826                 goto err;
 827         }
 828
 829         for (i = 0; i < trans->num_rx_queues; i++) {
 830                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 831
 832                 rxq->id = i;
 833                 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
 834                 if (ret)
 835                         goto err;
 836         }
 837         return 0;
 838
 839 err:
 840         if (trans_pcie->base_rb_stts) {
 841                 dma_free_coherent(trans->dev,
 842                                   rb_stts_size * trans->num_rx_queues,
 843                                   trans_pcie->base_rb_stts,
 844                                   trans_pcie->base_rb_stts_dma);
 845                 trans_pcie->base_rb_stts = NULL;
 846                 trans_pcie->base_rb_stts_dma = 0;
 847         }
 848         kfree(trans_pcie->rxq);
 849
 850         return ret;
 851 }
 852
 853 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 854 {
 855         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 856         u32 rb_size;
 857         unsigned long flags;
 858         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 859
 860         switch (trans_pcie->rx_buf_size) {
 861         case IWL_AMSDU_4K:
 862                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 863                 break;
 864         case IWL_AMSDU_8K:
 865                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 866                 break;
 867         case IWL_AMSDU_12K:
 868                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
 869                 break;
 870         default:
 871                 WARN_ON(1);
 872                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 873         }
 874
 875         if (!iwl_trans_grab_nic_access(trans, &flags))
 876                 return;
 877
 878         /* Stop Rx DMA */
 879         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 880         /* reset and flush pointers */
 881         iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 882         iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 883         iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 884
 885         /* Reset driver's Rx queue write index */
 886         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 887
 888         /* Tell device where to find RBD circular buffer in DRAM */
 889         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 890                     (u32)(rxq->bd_dma >> 8));
 891
 892         /* Tell device where in DRAM to update its Rx status */
 893         iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 894                     rxq->rb_stts_dma >> 4);
 895
 896         /* Enable Rx DMA
 897          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 898          *      the credit mechanism in 5000 HW RX FIFO
 899          * Direct rx interrupts to hosts
 900          * Rx buffer size 4 or 8k or 12k
 901          * RB timeout 0x10
 902          * 256 RBDs
 903          */
 904         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 905                     FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 906                     FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 907                     FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 908                     rb_size |
 909                     (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 910                     (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 911
 912         iwl_trans_release_nic_access(trans, &flags);
 913
 914         /* Set interrupt coalescing timer to default (2048 usecs) */
 915         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 916
 917         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 918         if (trans->cfg->host_interrupt_operation_mode)
 919                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 920 }
 921
 922 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 923 {
 924         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 925         u32 rb_size, enabled = 0;
 926         unsigned long flags;
 927         int i;
 928
 929         switch (trans_pcie->rx_buf_size) {
 930         case IWL_AMSDU_2K:
 931                 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
 932                 break;
 933         case IWL_AMSDU_4K:
 934                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 935                 break;
 936         case IWL_AMSDU_8K:
 937                 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
 938                 break;
 939         case IWL_AMSDU_12K:
 940                 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
 941                 break;
 942         default:
 943                 WARN_ON(1);
 944                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 945         }
 946
 947         if (!iwl_trans_grab_nic_access(trans, &flags))
 948                 return;
 949
 950         /* Stop Rx DMA */
 951         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 952         /* disable free amd used rx queue operation */
 953         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
 954
 955         for (i = 0; i < trans->num_rx_queues; i++) {
 956                 /* Tell device where to find RBD free table in DRAM */
 957                 iwl_write_prph64_no_grab(trans,
 958                                          RFH_Q_FRBDCB_BA_LSB(i),
 959                                          trans_pcie->rxq[i].bd_dma);
 960                 /* Tell device where to find RBD used table in DRAM */
 961                 iwl_write_prph64_no_grab(trans,
 962                                          RFH_Q_URBDCB_BA_LSB(i),
 963                                          trans_pcie->rxq[i].used_bd_dma);
 964                 /* Tell device where in DRAM to update its Rx status */
 965                 iwl_write_prph64_no_grab(trans,
 966                                          RFH_Q_URBD_STTS_WPTR_LSB(i),
 967                                          trans_pcie->rxq[i].rb_stts_dma);
 968                 /* Reset device indice tables */
 969                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
 970                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
 971                 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
 972
 973                 enabled |= BIT(i) | BIT(i + 16);
 974         }
 975
 976         /*
 977          * Enable Rx DMA
 978          * Rx buffer size 4 or 8k or 12k
 979          * Min RB size 4 or 8
 980          * Drop frames that exceed RB size
 981          * 512 RBDs
 982          */
 983         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
 984                                RFH_DMA_EN_ENABLE_VAL | rb_size |
 985                                RFH_RXF_DMA_MIN_RB_4_8 |
 986                                RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
 987                                RFH_RXF_DMA_RBDCB_SIZE_512);
 988
 989         /*
 990          * Activate DMA snooping.
 991          * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
 992          * Default queue is 0
 993          */
 994         iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
 995                                RFH_GEN_CFG_RFH_DMA_SNOOP |
 996                                RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
 997                                RFH_GEN_CFG_SERVICE_DMA_SNOOP |
 998                                RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
 999                                                trans->cfg->integrated ?
1000                                                RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
1001                                                RFH_GEN_CFG_RB_CHUNK_SIZE_128));
1002         /* Enable the relevant rx queues */
1003         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
1004
1005         iwl_trans_release_nic_access(trans, &flags);
1006
1007         /* Set interrupt coalescing timer to default (2048 usecs) */
1008         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1009 }
1010
1011 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
1012 {
1013         lockdep_assert_held(&rxq->lock);
1014
1015         INIT_LIST_HEAD(&rxq->rx_free);
1016         INIT_LIST_HEAD(&rxq->rx_used);
1017         rxq->free_count = 0;
1018         rxq->used_count = 0;
1019 }
1020
1021 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1022 {
1023         WARN_ON(1);
1024         return 0;
1025 }
1026
1027 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1028 {
1029         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1030         struct iwl_rxq *def_rxq;
1031         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1032         int i, err, queue_size, allocator_pool_size, num_alloc;
1033
1034         if (!trans_pcie->rxq) {
1035                 err = iwl_pcie_rx_alloc(trans);
1036                 if (err)
1037                         return err;
1038         }
1039         def_rxq = trans_pcie->rxq;
1040
1041         cancel_work_sync(&rba->rx_alloc);
1042
1043         spin_lock(&rba->lock);
1044         atomic_set(&rba->req_pending, 0);
1045         atomic_set(&rba->req_ready, 0);
1046         INIT_LIST_HEAD(&rba->rbd_allocated);
1047         INIT_LIST_HEAD(&rba->rbd_empty);
1048         spin_unlock(&rba->lock);
1049
1050         /* free all first - we might be reconfigured for a different size */
1051         iwl_pcie_free_rbs_pool(trans);
1052
1053         for (i = 0; i < RX_QUEUE_SIZE; i++)
1054                 def_rxq->queue[i] = NULL;
1055
1056         for (i = 0; i < trans->num_rx_queues; i++) {
1057                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1058
1059                 spin_lock(&rxq->lock);
1060                 /*
1061                  * Set read write pointer to reflect that we have processed
1062                  * and used all buffers, but have not restocked the Rx queue
1063                  * with fresh buffers
1064                  */
1065                 rxq->read = 0;
1066                 rxq->write = 0;
1067                 rxq->write_actual = 0;
1068                 memset(rxq->rb_stts, 0,
1069                        (trans->trans_cfg->device_family >=
1070                         IWL_DEVICE_FAMILY_AX210) ?
1071                        sizeof(__le16) : sizeof(struct iwl_rb_status));
1072
1073                 iwl_pcie_rx_init_rxb_lists(rxq);
1074
1075                 if (!rxq->napi.poll)
1076                         netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
1077                                        iwl_pcie_dummy_napi_poll, 64);
1078
1079                 spin_unlock(&rxq->lock);
1080         }
1081
1082         /* move the pool to the default queue and allocator ownerships */
1083         queue_size = trans->trans_cfg->mq_rx_supported ?
1084                      MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
1085         allocator_pool_size = trans->num_rx_queues *
1086                 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1087         num_alloc = queue_size + allocator_pool_size;
1088         BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
1089                      ARRAY_SIZE(trans_pcie->rx_pool));
1090         for (i = 0; i < num_alloc; i++) {
1091                 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1092
1093                 if (i < allocator_pool_size)
1094                         list_add(&rxb->list, &rba->rbd_empty);
1095                 else
1096                         list_add(&rxb->list, &def_rxq->rx_used);
1097                 trans_pcie->global_table[i] = rxb;
1098                 rxb->vid = (u16)(i + 1);
1099                 rxb->invalid = true;
1100         }
1101
1102         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1103
1104         return 0;
1105 }
1106
1107 int iwl_pcie_rx_init(struct iwl_trans *trans)
1108 {
1109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1110         int ret = _iwl_pcie_rx_init(trans);
1111
1112         if (ret)
1113                 return ret;
1114
1115         if (trans->trans_cfg->mq_rx_supported)
1116                 iwl_pcie_rx_mq_hw_init(trans);
1117         else
1118                 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1119
1120         iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1121
1122         spin_lock(&trans_pcie->rxq->lock);
1123         iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1124         spin_unlock(&trans_pcie->rxq->lock);
1125
1126         return 0;
1127 }
1128
1129 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1130 {
1131         /* Set interrupt coalescing timer to default (2048 usecs) */
1132         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1133
1134         /*
1135          * We don't configure the RFH.
1136          * Restock will be done at alive, after firmware configured the RFH.
1137          */
1138         return _iwl_pcie_rx_init(trans);
1139 }
1140
1141 void iwl_pcie_rx_free(struct iwl_trans *trans)
1142 {
1143         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1144         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1145         int i;
1146         size_t rb_stts_size = trans->trans_cfg->device_family >=
1147                                 IWL_DEVICE_FAMILY_AX210 ?
1148                               sizeof(__le16) : sizeof(struct iwl_rb_status);
1149
1150         /*
1151          * if rxq is NULL, it means that nothing has been allocated,
1152          * exit now
1153          */
1154         if (!trans_pcie->rxq) {
1155                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1156                 return;
1157         }
1158
1159         cancel_work_sync(&rba->rx_alloc);
1160
1161         iwl_pcie_free_rbs_pool(trans);
1162
1163         if (trans_pcie->base_rb_stts) {
1164                 dma_free_coherent(trans->dev,
1165                                   rb_stts_size * trans->num_rx_queues,
1166                                   trans_pcie->base_rb_stts,
1167                                   trans_pcie->base_rb_stts_dma);
1168                 trans_pcie->base_rb_stts = NULL;
1169                 trans_pcie->base_rb_stts_dma = 0;
1170         }
1171
1172         for (i = 0; i < trans->num_rx_queues; i++) {
1173                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1174
1175                 iwl_pcie_free_rxq_dma(trans, rxq);
1176
1177                 if (rxq->napi.poll)
1178                         netif_napi_del(&rxq->napi);
1179         }
1180         kfree(trans_pcie->rxq);
1181 }
1182
1183 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1184                                           struct iwl_rb_allocator *rba)
1185 {
1186         spin_lock(&rba->lock);
1187         list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1188         spin_unlock(&rba->lock);
1189 }
1190
1191 /*
1192  * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1193  *
1194  * Called when a RBD can be reused. The RBD is transferred to the allocator.
1195  * When there are 2 empty RBDs - a request for allocation is posted
1196  */
1197 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1198                                   struct iwl_rx_mem_buffer *rxb,
1199                                   struct iwl_rxq *rxq, bool emergency)
1200 {
1201         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1202         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1203
1204         /* Move the RBD to the used list, will be moved to allocator in batches
1205          * before claiming or posting a request*/
1206         list_add_tail(&rxb->list, &rxq->rx_used);
1207
1208         if (unlikely(emergency))
1209                 return;
1210
1211         /* Count the allocator owned RBDs */
1212         rxq->used_count++;
1213
1214         /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1215          * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1216          * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1217          * after but we still need to post another request.
1218          */
1219         if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1220                 /* Move the 2 RBDs to the allocator ownership.
1221                  Allocator has another 6 from pool for the request completion*/
1222                 iwl_pcie_rx_move_to_allocator(rxq, rba);
1223
1224                 atomic_inc(&rba->req_pending);
1225                 queue_work(rba->alloc_wq, &rba->rx_alloc);
1226         }
1227 }
1228
1229 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1230                                 struct iwl_rxq *rxq,
1231                                 struct iwl_rx_mem_buffer *rxb,
1232                                 bool emergency,
1233                                 int i)
1234 {
1235         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1236         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1237         bool page_stolen = false;
1238         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1239         u32 offset = 0;
1240
1241         if (WARN_ON(!rxb))
1242                 return;
1243
1244         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1245
1246         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1247                 struct iwl_rx_packet *pkt;
1248                 u16 sequence;
1249                 bool reclaim;
1250                 int index, cmd_index, len;
1251                 struct iwl_rx_cmd_buffer rxcb = {
1252                         ._offset = offset,
1253                         ._rx_page_order = trans_pcie->rx_page_order,
1254                         ._page = rxb->page,
1255                         ._page_stolen = false,
1256                         .truesize = max_len,
1257                 };
1258
1259                 pkt = rxb_addr(&rxcb);
1260
1261                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1262                         IWL_DEBUG_RX(trans,
1263                                      "Q %d: RB end marker at offset %d\n",
1264                                      rxq->id, offset);
1265                         break;
1266                 }
1267
1268                 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1269                         FH_RSCSR_RXQ_POS != rxq->id,
1270                      "frame on invalid queue - is on %d and indicates %d\n",
1271                      rxq->id,
1272                      (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1273                         FH_RSCSR_RXQ_POS);
1274
1275                 IWL_DEBUG_RX(trans,
1276                              "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1277                              rxq->id, offset,
1278                              iwl_get_cmd_string(trans,
1279                                                 iwl_cmd_id(pkt->hdr.cmd,
1280                                                            pkt->hdr.group_id,
1281                                                            0)),
1282                              pkt->hdr.group_id, pkt->hdr.cmd,
1283                              le16_to_cpu(pkt->hdr.sequence));
1284
1285                 len = iwl_rx_packet_len(pkt);
1286                 len += sizeof(u32); /* account for status word */
1287                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1288                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1289
1290                 /* Reclaim a command buffer only if this packet is a response
1291                  *   to a (driver-originated) command.
1292                  * If the packet (e.g. Rx frame) originated from uCode,
1293                  *   there is no command buffer to reclaim.
1294                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1295                  *   but apparently a few don't get set; catch them here. */
1296                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1297                 if (reclaim && !pkt->hdr.group_id) {
1298                         int i;
1299
1300                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1301                                 if (trans_pcie->no_reclaim_cmds[i] ==
1302                                                         pkt->hdr.cmd) {
1303                                         reclaim = false;
1304                                         break;
1305                                 }
1306                         }
1307                 }
1308
1309                 sequence = le16_to_cpu(pkt->hdr.sequence);
1310                 index = SEQ_TO_INDEX(sequence);
1311                 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1312
1313                 if (rxq->id == trans_pcie->def_rx_queue)
1314                         iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1315                                        &rxcb);
1316                 else
1317                         iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1318                                            &rxcb, rxq->id);
1319
1320                 if (reclaim) {
1321                         kzfree(txq->entries[cmd_index].free_buf);
1322                         txq->entries[cmd_index].free_buf = NULL;
1323                 }
1324
1325                 /*
1326                  * After here, we should always check rxcb._page_stolen,
1327                  * if it is true then one of the handlers took the page.
1328                  */
1329
1330                 if (reclaim) {
1331                         /* Invoke any callbacks, transfer the buffer to caller,
1332                          * and fire off the (possibly) blocking
1333                          * iwl_trans_send_cmd()
1334                          * as we reclaim the driver command queue */
1335                         if (!rxcb._page_stolen)
1336                                 iwl_pcie_hcmd_complete(trans, &rxcb);
1337                         else
1338                                 IWL_WARN(trans, "Claim null rxb?\n");
1339                 }
1340
1341                 page_stolen |= rxcb._page_stolen;
1342                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1343                         break;
1344                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1345         }
1346
1347         /* page was stolen from us -- free our reference */
1348         if (page_stolen) {
1349                 __free_pages(rxb->page, trans_pcie->rx_page_order);
1350                 rxb->page = NULL;
1351         }
1352
1353         /* Reuse the page if possible. For notification packets and
1354          * SKBs that fail to Rx correctly, add them back into the
1355          * rx_free list for reuse later. */
1356         if (rxb->page != NULL) {
1357                 rxb->page_dma =
1358                         dma_map_page(trans->dev, rxb->page, 0,
1359                                      PAGE_SIZE << trans_pcie->rx_page_order,
1360                                      DMA_FROM_DEVICE);
1361                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1362                         /*
1363                          * free the page(s) as well to not break
1364                          * the invariant that the items on the used
1365                          * list have no page(s)
1366                          */
1367                         __free_pages(rxb->page, trans_pcie->rx_page_order);
1368                         rxb->page = NULL;
1369                         iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1370                 } else {
1371                         list_add_tail(&rxb->list, &rxq->rx_free);
1372                         rxq->free_count++;
1373                 }
1374         } else
1375                 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1376 }
1377
1378 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1379                                                   struct iwl_rxq *rxq, int i)
1380 {
1381         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1382         struct iwl_rx_mem_buffer *rxb;
1383         u16 vid;
1384
1385         BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32);
1386
1387         if (!trans->trans_cfg->mq_rx_supported) {
1388                 rxb = rxq->queue[i];
1389                 rxq->queue[i] = NULL;
1390                 return rxb;
1391         }
1392
1393         /* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */
1394         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1395                 vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF;
1396         else
1397                 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF;
1398
1399         if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table))
1400                 goto out_err;
1401
1402         rxb = trans_pcie->global_table[vid - 1];
1403         if (rxb->invalid)
1404                 goto out_err;
1405
1406         IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid);
1407
1408         rxb->invalid = true;
1409
1410         return rxb;
1411
1412 out_err:
1413         WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1414         iwl_force_nmi(trans);
1415         return NULL;
1416 }
1417
1418 /*
1419  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1420  */
1421 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1422 {
1423         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1424         struct napi_struct *napi;
1425         struct iwl_rxq *rxq;
1426         u32 r, i, count = 0;
1427         bool emergency = false;
1428
1429         if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1430                 return;
1431
1432         rxq = &trans_pcie->rxq[queue];
1433
1434 restart:
1435         spin_lock(&rxq->lock);
1436         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1437          * buffer that the driver may process (last buffer filled by ucode). */
1438         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
1439         i = rxq->read;
1440
1441         /* W/A 9000 device step A0 wrap-around bug */
1442         r &= (rxq->queue_size - 1);
1443
1444         /* Rx interrupt, but nothing sent from uCode */
1445         if (i == r)
1446                 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1447
1448         while (i != r) {
1449                 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1450                 struct iwl_rx_mem_buffer *rxb;
1451                 /* number of RBDs still waiting for page allocation */
1452                 u32 rb_pending_alloc =
1453                         atomic_read(&trans_pcie->rba.req_pending) *
1454                         RX_CLAIM_REQ_ALLOC;
1455
1456                 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1457                              !emergency)) {
1458                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1459                         emergency = true;
1460                         IWL_DEBUG_TPT(trans,
1461                                       "RX path is in emergency. Pending allocations %d\n",
1462                                       rb_pending_alloc);
1463                 }
1464
1465                 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1466
1467                 rxb = iwl_pcie_get_rxb(trans, rxq, i);
1468                 if (!rxb)
1469                         goto out;
1470
1471                 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1472
1473                 i = (i + 1) & (rxq->queue_size - 1);
1474
1475                 /*
1476                  * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1477                  * try to claim the pre-allocated buffers from the allocator.
1478                  * If not ready - will try to reclaim next time.
1479                  * There is no need to reschedule work - allocator exits only
1480                  * on success
1481                  */
1482                 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1483                         iwl_pcie_rx_allocator_get(trans, rxq);
1484
1485                 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1486                         /* Add the remaining empty RBDs for allocator use */
1487                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1488                 } else if (emergency) {
1489                         count++;
1490                         if (count == 8) {
1491                                 count = 0;
1492                                 if (rb_pending_alloc < rxq->queue_size / 3) {
1493                                         IWL_DEBUG_TPT(trans,
1494                                                       "RX path exited emergency. Pending allocations %d\n",
1495                                                       rb_pending_alloc);
1496                                         emergency = false;
1497                                 }
1498
1499                                 rxq->read = i;
1500                                 spin_unlock(&rxq->lock);
1501                                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1502                                 iwl_pcie_rxq_restock(trans, rxq);
1503                                 goto restart;
1504                         }
1505                 }
1506         }
1507 out:
1508         /* Backtrack one entry */
1509         rxq->read = i;
1510         /* update cr tail with the rxq read pointer */
1511         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1512                 *rxq->cr_tail = cpu_to_le16(r);
1513         spin_unlock(&rxq->lock);
1514
1515         /*
1516          * handle a case where in emergency there are some unallocated RBDs.
1517          * those RBDs are in the used list, but are not tracked by the queue's
1518          * used_count which counts allocator owned RBDs.
1519          * unallocated emergency RBDs must be allocated on exit, otherwise
1520          * when called again the function may not be in emergency mode and
1521          * they will be handed to the allocator with no tracking in the RBD
1522          * allocator counters, which will lead to them never being claimed back
1523          * by the queue.
1524          * by allocating them here, they are now in the queue free list, and
1525          * will be restocked by the next call of iwl_pcie_rxq_restock.
1526          */
1527         if (unlikely(emergency && count))
1528                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1529
1530         napi = &rxq->napi;
1531         if (napi->poll) {
1532                 if (napi->rx_count) {
1533                         netif_receive_skb_list(&napi->rx_list);
1534                         INIT_LIST_HEAD(&napi->rx_list);
1535                         napi->rx_count = 0;
1536                 }
1537
1538                 napi_gro_flush(napi, false);
1539         }
1540
1541         iwl_pcie_rxq_restock(trans, rxq);
1542 }
1543
1544 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1545 {
1546         u8 queue = entry->entry;
1547         struct msix_entry *entries = entry - queue;
1548
1549         return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1550 }
1551
1552 /*
1553  * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1554  * This interrupt handler should be used with RSS queue only.
1555  */
1556 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1557 {
1558         struct msix_entry *entry = dev_id;
1559         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1560         struct iwl_trans *trans = trans_pcie->trans;
1561
1562         trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1563
1564         if (WARN_ON(entry->entry >= trans->num_rx_queues))
1565                 return IRQ_NONE;
1566
1567         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1568
1569         local_bh_disable();
1570         iwl_pcie_rx_handle(trans, entry->entry);
1571         local_bh_enable();
1572
1573         iwl_pcie_clear_irq(trans, entry);
1574
1575         lock_map_release(&trans->sync_cmd_lockdep_map);
1576
1577         return IRQ_HANDLED;
1578 }
1579
1580 /*
1581  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1582  */
1583 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1584 {
1585         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1586         int i;
1587
1588         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1589         if (trans->cfg->internal_wimax_coex &&
1590             !trans->cfg->apmg_not_supported &&
1591             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1592                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
1593              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1594                             APMG_PS_CTRL_VAL_RESET_REQ))) {
1595                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1596                 iwl_op_mode_wimax_active(trans->op_mode);
1597                 wake_up(&trans_pcie->wait_command_queue);
1598                 return;
1599         }
1600
1601         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
1602                 if (!trans_pcie->txq[i])
1603                         continue;
1604                 del_timer(&trans_pcie->txq[i]->stuck_timer);
1605         }
1606
1607         /* The STATUS_FW_ERROR bit is set in this function. This must happen
1608          * before we wake up the command caller, to ensure a proper cleanup. */
1609         iwl_trans_fw_error(trans);
1610
1611         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1612         wake_up(&trans_pcie->wait_command_queue);
1613 }
1614
1615 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1616 {
1617         u32 inta;
1618
1619         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1620
1621         trace_iwlwifi_dev_irq(trans->dev);
1622
1623         /* Discover which interrupts are active/pending */
1624         inta = iwl_read32(trans, CSR_INT);
1625
1626         /* the thread will service interrupts and re-enable them */
1627         return inta;
1628 }
1629
1630 /* a device (PCI-E) page is 4096 bytes long */
1631 #define ICT_SHIFT       12
1632 #define ICT_SIZE        (1 << ICT_SHIFT)
1633 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1634
1635 /* interrupt handler using ict table, with this interrupt driver will
1636  * stop using INTA register to get device's interrupt, reading this register
1637  * is expensive, device will write interrupts in ICT dram table, increment
1638  * index then will fire interrupt to driver, driver will OR all ICT table
1639  * entries from current index up to table entry with 0 value. the result is
1640  * the interrupt we need to service, driver will set the entries back to 0 and
1641  * set index.
1642  */
1643 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1644 {
1645         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1646         u32 inta;
1647         u32 val = 0;
1648         u32 read;
1649
1650         trace_iwlwifi_dev_irq(trans->dev);
1651
1652         /* Ignore interrupt if there's nothing in NIC to service.
1653          * This may be due to IRQ shared with another device,
1654          * or due to sporadic interrupts thrown from our NIC. */
1655         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1656         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1657         if (!read)
1658                 return 0;
1659
1660         /*
1661          * Collect all entries up to the first 0, starting from ict_index;
1662          * note we already read at ict_index.
1663          */
1664         do {
1665                 val |= read;
1666                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1667                                 trans_pcie->ict_index, read);
1668                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1669                 trans_pcie->ict_index =
1670                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1671
1672                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1673                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1674                                            read);
1675         } while (read);
1676
1677         /* We should not get this value, just ignore it. */
1678         if (val == 0xffffffff)
1679                 val = 0;
1680
1681         /*
1682          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1683          * (bit 15 before shifting it to 31) to clear when using interrupt
1684          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1685          * so we use them to decide on the real state of the Rx bit.
1686          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1687          */
1688         if (val & 0xC0000)
1689                 val |= 0x8000;
1690
1691         inta = (0xff & val) | ((0xff00 & val) << 16);
1692         return inta;
1693 }
1694
1695 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1696 {
1697         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1698         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1699         bool hw_rfkill, prev, report;
1700
1701         mutex_lock(&trans_pcie->mutex);
1702         prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1703         hw_rfkill = iwl_is_rfkill_set(trans);
1704         if (hw_rfkill) {
1705                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1706                 set_bit(STATUS_RFKILL_HW, &trans->status);
1707         }
1708         if (trans_pcie->opmode_down)
1709                 report = hw_rfkill;
1710         else
1711                 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1712
1713         IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1714                  hw_rfkill ? "disable radio" : "enable radio");
1715
1716         isr_stats->rfkill++;
1717
1718         if (prev != report)
1719                 iwl_trans_pcie_rf_kill(trans, report);
1720         mutex_unlock(&trans_pcie->mutex);
1721
1722         if (hw_rfkill) {
1723                 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1724                                        &trans->status))
1725                         IWL_DEBUG_RF_KILL(trans,
1726                                           "Rfkill while SYNC HCMD in flight\n");
1727                 wake_up(&trans_pcie->wait_command_queue);
1728         } else {
1729                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1730                 if (trans_pcie->opmode_down)
1731                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1732         }
1733 }
1734
1735 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1736 {
1737         struct iwl_trans *trans = dev_id;
1738         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1739         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1740         u32 inta = 0;
1741         u32 handled = 0;
1742
1743         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1744
1745         spin_lock(&trans_pcie->irq_lock);
1746
1747         /* dram interrupt table not set yet,
1748          * use legacy interrupt.
1749          */
1750         if (likely(trans_pcie->use_ict))
1751                 inta = iwl_pcie_int_cause_ict(trans);
1752         else
1753                 inta = iwl_pcie_int_cause_non_ict(trans);
1754
1755         if (iwl_have_debug_level(IWL_DL_ISR)) {
1756                 IWL_DEBUG_ISR(trans,
1757                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1758                               inta, trans_pcie->inta_mask,
1759                               iwl_read32(trans, CSR_INT_MASK),
1760                               iwl_read32(trans, CSR_FH_INT_STATUS));
1761                 if (inta & (~trans_pcie->inta_mask))
1762                         IWL_DEBUG_ISR(trans,
1763                                       "We got a masked interrupt (0x%08x)\n",
1764                                       inta & (~trans_pcie->inta_mask));
1765         }
1766
1767         inta &= trans_pcie->inta_mask;
1768
1769         /*
1770          * Ignore interrupt if there's nothing in NIC to service.
1771          * This may be due to IRQ shared with another device,
1772          * or due to sporadic interrupts thrown from our NIC.
1773          */
1774         if (unlikely(!inta)) {
1775                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1776                 /*
1777                  * Re-enable interrupts here since we don't
1778                  * have anything to service
1779                  */
1780                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1781                         _iwl_enable_interrupts(trans);
1782                 spin_unlock(&trans_pcie->irq_lock);
1783                 lock_map_release(&trans->sync_cmd_lockdep_map);
1784                 return IRQ_NONE;
1785         }
1786
1787         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1788                 /*
1789                  * Hardware disappeared. It might have
1790                  * already raised an interrupt.
1791                  */
1792                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1793                 spin_unlock(&trans_pcie->irq_lock);
1794                 goto out;
1795         }
1796
1797         /* Ack/clear/reset pending uCode interrupts.
1798          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1799          */
1800         /* There is a hardware bug in the interrupt mask function that some
1801          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1802          * they are disabled in the CSR_INT_MASK register. Furthermore the
1803          * ICT interrupt handling mechanism has another bug that might cause
1804          * these unmasked interrupts fail to be detected. We workaround the
1805          * hardware bugs here by ACKing all the possible interrupts so that
1806          * interrupt coalescing can still be achieved.
1807          */
1808         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1809
1810         if (iwl_have_debug_level(IWL_DL_ISR))
1811                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1812                               inta, iwl_read32(trans, CSR_INT_MASK));
1813
1814         spin_unlock(&trans_pcie->irq_lock);
1815
1816         /* Now service all interrupt bits discovered above. */
1817         if (inta & CSR_INT_BIT_HW_ERR) {
1818                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
1819
1820                 /* Tell the device to stop sending interrupts */
1821                 iwl_disable_interrupts(trans);
1822
1823                 isr_stats->hw++;
1824                 iwl_pcie_irq_handle_error(trans);
1825
1826                 handled |= CSR_INT_BIT_HW_ERR;
1827
1828                 goto out;
1829         }
1830
1831         /* NIC fires this, but we don't use it, redundant with WAKEUP */
1832         if (inta & CSR_INT_BIT_SCD) {
1833                 IWL_DEBUG_ISR(trans,
1834                               "Scheduler finished to transmit the frame/frames.\n");
1835                 isr_stats->sch++;
1836         }
1837
1838         /* Alive notification via Rx interrupt will do the real work */
1839         if (inta & CSR_INT_BIT_ALIVE) {
1840                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1841                 isr_stats->alive++;
1842                 if (trans->trans_cfg->gen2) {
1843                         /*
1844                          * We can restock, since firmware configured
1845                          * the RFH
1846                          */
1847                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1848                 }
1849
1850                 handled |= CSR_INT_BIT_ALIVE;
1851         }
1852
1853         /* Safely ignore these bits for debug checks below */
1854         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1855
1856         /* HW RF KILL switch toggled */
1857         if (inta & CSR_INT_BIT_RF_KILL) {
1858                 iwl_pcie_handle_rfkill_irq(trans);
1859                 handled |= CSR_INT_BIT_RF_KILL;
1860         }
1861
1862         /* Chip got too hot and stopped itself */
1863         if (inta & CSR_INT_BIT_CT_KILL) {
1864                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1865                 isr_stats->ctkill++;
1866                 handled |= CSR_INT_BIT_CT_KILL;
1867         }
1868
1869         /* Error detected by uCode */
1870         if (inta & CSR_INT_BIT_SW_ERR) {
1871                 IWL_ERR(trans, "Microcode SW error detected. "
1872                         " Restarting 0x%X.\n", inta);
1873                 isr_stats->sw++;
1874                 iwl_pcie_irq_handle_error(trans);
1875                 handled |= CSR_INT_BIT_SW_ERR;
1876         }
1877
1878         /* uCode wakes up after power-down sleep */
1879         if (inta & CSR_INT_BIT_WAKEUP) {
1880                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1881                 iwl_pcie_rxq_check_wrptr(trans);
1882                 iwl_pcie_txq_check_wrptrs(trans);
1883
1884                 isr_stats->wakeup++;
1885
1886                 handled |= CSR_INT_BIT_WAKEUP;
1887         }
1888
1889         /* All uCode command responses, including Tx command responses,
1890          * Rx "responses" (frame-received notification), and other
1891          * notifications from uCode come through here*/
1892         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1893                     CSR_INT_BIT_RX_PERIODIC)) {
1894                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1895                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1896                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1897                         iwl_write32(trans, CSR_FH_INT_STATUS,
1898                                         CSR_FH_INT_RX_MASK);
1899                 }
1900                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1901                         handled |= CSR_INT_BIT_RX_PERIODIC;
1902                         iwl_write32(trans,
1903                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1904                 }
1905                 /* Sending RX interrupt require many steps to be done in the
1906                  * the device:
1907                  * 1- write interrupt to current index in ICT table.
1908                  * 2- dma RX frame.
1909                  * 3- update RX shared data to indicate last write index.
1910                  * 4- send interrupt.
1911                  * This could lead to RX race, driver could receive RX interrupt
1912                  * but the shared data changes does not reflect this;
1913                  * periodic interrupt will detect any dangling Rx activity.
1914                  */
1915
1916                 /* Disable periodic interrupt; we use it as just a one-shot. */
1917                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1918                             CSR_INT_PERIODIC_DIS);
1919
1920                 /*
1921                  * Enable periodic interrupt in 8 msec only if we received
1922                  * real RX interrupt (instead of just periodic int), to catch
1923                  * any dangling Rx interrupt.  If it was just the periodic
1924                  * interrupt, there was no dangling Rx activity, and no need
1925                  * to extend the periodic interrupt; one-shot is enough.
1926                  */
1927                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1928                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1929                                    CSR_INT_PERIODIC_ENA);
1930
1931                 isr_stats->rx++;
1932
1933                 local_bh_disable();
1934                 iwl_pcie_rx_handle(trans, 0);
1935                 local_bh_enable();
1936         }
1937
1938         /* This "Tx" DMA channel is used only for loading uCode */
1939         if (inta & CSR_INT_BIT_FH_TX) {
1940                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1941                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1942                 isr_stats->tx++;
1943                 handled |= CSR_INT_BIT_FH_TX;
1944                 /* Wake up uCode load routine, now that load is complete */
1945                 trans_pcie->ucode_write_complete = true;
1946                 wake_up(&trans_pcie->ucode_write_waitq);
1947         }
1948
1949         if (inta & ~handled) {
1950                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1951                 isr_stats->unhandled++;
1952         }
1953
1954         if (inta & ~(trans_pcie->inta_mask)) {
1955                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1956                          inta & ~trans_pcie->inta_mask);
1957         }
1958
1959         spin_lock(&trans_pcie->irq_lock);
1960         /* only Re-enable all interrupt if disabled by irq */
1961         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1962                 _iwl_enable_interrupts(trans);
1963         /* we are loading the firmware, enable FH_TX interrupt only */
1964         else if (handled & CSR_INT_BIT_FH_TX)
1965                 iwl_enable_fw_load_int(trans);
1966         /* Re-enable RF_KILL if it occurred */
1967         else if (handled & CSR_INT_BIT_RF_KILL)
1968                 iwl_enable_rfkill_int(trans);
1969         /* Re-enable the ALIVE / Rx interrupt if it occurred */
1970         else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX))
1971                 iwl_enable_fw_load_int_ctx_info(trans);
1972         spin_unlock(&trans_pcie->irq_lock);
1973
1974 out:
1975         lock_map_release(&trans->sync_cmd_lockdep_map);
1976         return IRQ_HANDLED;
1977 }
1978
1979 /******************************************************************************
1980  *
1981  * ICT functions
1982  *
1983  ******************************************************************************/
1984
1985 /* Free dram table */
1986 void iwl_pcie_free_ict(struct iwl_trans *trans)
1987 {
1988         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1989
1990         if (trans_pcie->ict_tbl) {
1991                 dma_free_coherent(trans->dev, ICT_SIZE,
1992                                   trans_pcie->ict_tbl,
1993                                   trans_pcie->ict_tbl_dma);
1994                 trans_pcie->ict_tbl = NULL;
1995                 trans_pcie->ict_tbl_dma = 0;
1996         }
1997 }
1998
1999 /*
2000  * allocate dram shared table, it is an aligned memory
2001  * block of ICT_SIZE.
2002  * also reset all data related to ICT table interrupt.
2003  */
2004 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
2005 {
2006         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2007
2008         trans_pcie->ict_tbl =
2009                 dma_alloc_coherent(trans->dev, ICT_SIZE,
2010                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
2011         if (!trans_pcie->ict_tbl)
2012                 return -ENOMEM;
2013
2014         /* just an API sanity check ... it is guaranteed to be aligned */
2015         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
2016                 iwl_pcie_free_ict(trans);
2017                 return -EINVAL;
2018         }
2019
2020         return 0;
2021 }
2022
2023 /* Device is going up inform it about using ICT interrupt table,
2024  * also we need to tell the driver to start using ICT interrupt.
2025  */
2026 void iwl_pcie_reset_ict(struct iwl_trans *trans)
2027 {
2028         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2029         u32 val;
2030
2031         if (!trans_pcie->ict_tbl)
2032                 return;
2033
2034         spin_lock(&trans_pcie->irq_lock);
2035         _iwl_disable_interrupts(trans);
2036
2037         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
2038
2039         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
2040
2041         val |= CSR_DRAM_INT_TBL_ENABLE |
2042                CSR_DRAM_INIT_TBL_WRAP_CHECK |
2043                CSR_DRAM_INIT_TBL_WRITE_POINTER;
2044
2045         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2046
2047         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2048         trans_pcie->use_ict = true;
2049         trans_pcie->ict_index = 0;
2050         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2051         _iwl_enable_interrupts(trans);
2052         spin_unlock(&trans_pcie->irq_lock);
2053 }
2054
2055 /* Device is going down disable ict interrupt usage */
2056 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2057 {
2058         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2059
2060         spin_lock(&trans_pcie->irq_lock);
2061         trans_pcie->use_ict = false;
2062         spin_unlock(&trans_pcie->irq_lock);
2063 }
2064
2065 irqreturn_t iwl_pcie_isr(int irq, void *data)
2066 {
2067         struct iwl_trans *trans = data;
2068
2069         if (!trans)
2070                 return IRQ_NONE;
2071
2072         /* Disable (but don't clear!) interrupts here to avoid
2073          * back-to-back ISRs and sporadic interrupts from our NIC.
2074          * If we have something to service, the tasklet will re-enable ints.
2075          * If we *don't* have something, we'll re-enable before leaving here.
2076          */
2077         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2078
2079         return IRQ_WAKE_THREAD;
2080 }
2081
2082 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2083 {
2084         return IRQ_WAKE_THREAD;
2085 }
2086
2087 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2088 {
2089         struct msix_entry *entry = dev_id;
2090         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2091         struct iwl_trans *trans = trans_pcie->trans;
2092         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2093         u32 inta_fh, inta_hw;
2094
2095         lock_map_acquire(&trans->sync_cmd_lockdep_map);
2096
2097         spin_lock(&trans_pcie->irq_lock);
2098         inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2099         inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2100         /*
2101          * Clear causes registers to avoid being handling the same cause.
2102          */
2103         iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
2104         iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2105         spin_unlock(&trans_pcie->irq_lock);
2106
2107         trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2108
2109         if (unlikely(!(inta_fh | inta_hw))) {
2110                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2111                 lock_map_release(&trans->sync_cmd_lockdep_map);
2112                 return IRQ_NONE;
2113         }
2114
2115         if (iwl_have_debug_level(IWL_DL_ISR)) {
2116                 IWL_DEBUG_ISR(trans,
2117                               "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2118                               inta_fh, trans_pcie->fh_mask,
2119                               iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2120                 if (inta_fh & ~trans_pcie->fh_mask)
2121                         IWL_DEBUG_ISR(trans,
2122                                       "We got a masked interrupt (0x%08x)\n",
2123                                       inta_fh & ~trans_pcie->fh_mask);
2124         }
2125
2126         inta_fh &= trans_pcie->fh_mask;
2127
2128         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2129             inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2130                 local_bh_disable();
2131                 iwl_pcie_rx_handle(trans, 0);
2132                 local_bh_enable();
2133         }
2134
2135         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2136             inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2137                 local_bh_disable();
2138                 iwl_pcie_rx_handle(trans, 1);
2139                 local_bh_enable();
2140         }
2141
2142         /* This "Tx" DMA channel is used only for loading uCode */
2143         if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2144                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2145                 isr_stats->tx++;
2146                 /*
2147                  * Wake up uCode load routine,
2148                  * now that load is complete
2149                  */
2150                 trans_pcie->ucode_write_complete = true;
2151                 wake_up(&trans_pcie->ucode_write_waitq);
2152         }
2153
2154         /* Error detected by uCode */
2155         if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
2156             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) {
2157                 IWL_ERR(trans,
2158                         "Microcode SW error detected. Restarting 0x%X.\n",
2159                         inta_fh);
2160                 isr_stats->sw++;
2161                 iwl_pcie_irq_handle_error(trans);
2162         }
2163
2164         /* After checking FH register check HW register */
2165         if (iwl_have_debug_level(IWL_DL_ISR)) {
2166                 IWL_DEBUG_ISR(trans,
2167                               "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2168                               inta_hw, trans_pcie->hw_mask,
2169                               iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2170                 if (inta_hw & ~trans_pcie->hw_mask)
2171                         IWL_DEBUG_ISR(trans,
2172                                       "We got a masked interrupt 0x%08x\n",
2173                                       inta_hw & ~trans_pcie->hw_mask);
2174         }
2175
2176         inta_hw &= trans_pcie->hw_mask;
2177
2178         /* Alive notification via Rx interrupt will do the real work */
2179         if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2180                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2181                 isr_stats->alive++;
2182                 if (trans->trans_cfg->gen2) {
2183                         /* We can restock, since firmware configured the RFH */
2184                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2185                 }
2186         }
2187
2188         if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2189                 u32 sleep_notif =
2190                         le32_to_cpu(trans_pcie->prph_info->sleep_notif);
2191                 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND ||
2192                     sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) {
2193                         IWL_DEBUG_ISR(trans,
2194                                       "Sx interrupt: sleep notification = 0x%x\n",
2195                                       sleep_notif);
2196                         trans_pcie->sx_complete = true;
2197                         wake_up(&trans_pcie->sx_waitq);
2198                 } else {
2199                         /* uCode wakes up after power-down sleep */
2200                         IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2201                         iwl_pcie_rxq_check_wrptr(trans);
2202                         iwl_pcie_txq_check_wrptrs(trans);
2203
2204                         isr_stats->wakeup++;
2205                 }
2206         }
2207
2208         if (inta_hw & MSIX_HW_INT_CAUSES_REG_IML) {
2209                 /* Reflect IML transfer status */
2210                 int res = iwl_read32(trans, CSR_IML_RESP_ADDR);
2211
2212                 IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res);
2213                 if (res == IWL_IMAGE_RESP_FAIL) {
2214                         isr_stats->sw++;
2215                         iwl_pcie_irq_handle_error(trans);
2216                 }
2217         }
2218
2219         /* Chip got too hot and stopped itself */
2220         if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2221                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2222                 isr_stats->ctkill++;
2223         }
2224
2225         /* HW RF KILL switch toggled */
2226         if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2227                 iwl_pcie_handle_rfkill_irq(trans);
2228
2229         if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2230                 IWL_ERR(trans,
2231                         "Hardware error detected. Restarting.\n");
2232
2233                 isr_stats->hw++;
2234                 trans->dbg.hw_error = true;
2235                 iwl_pcie_irq_handle_error(trans);
2236         }
2237
2238         iwl_pcie_clear_irq(trans, entry);
2239
2240         lock_map_release(&trans->sync_cmd_lockdep_map);
2241
2242         return IRQ_HANDLED;
2243 }