1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #ifndef __iwl_trans_int_pcie_h__
8 #define __iwl_trans_int_pcie_h__
10 #include <linux/spinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/skbuff.h>
13 #include <linux/wait.h>
14 #include <linux/pci.h>
15 #include <linux/timer.h>
16 #include <linux/cpu.h>
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
23 #include "iwl-op-mode.h"
26 #include "iwl-context-info.h"
29 * RX related structures and functions
31 #define RX_NUM_QUEUES 1
32 #define RX_POST_REQ_ALLOC 2
33 #define RX_CLAIM_REQ_ALLOC 8
34 #define RX_PENDING_WATERMARK 16
35 #define FIRST_RX_QUEUE 512
39 /*This file includes the declaration that are internal to the
43 * struct iwl_rx_mem_buffer
44 * @page_dma: bus address of rxb page
45 * @page: driver's pointer to the rxb page
46 * @list: list entry for the membuffer
47 * @invalid: rxb is in driver ownership - not owned by HW
48 * @vid: index of this rxb in the global table
49 * @offset: indicates which offset of the page (in bytes)
50 * this buffer uses (if multiple RBs fit into one page)
52 struct iwl_rx_mem_buffer {
55 struct list_head list;
61 /* interrupt statistics */
62 struct isr_statistics {
77 * struct iwl_rx_transfer_desc - transfer descriptor
78 * @addr: ptr to free buffer start address
79 * @rbid: unique tag of the buffer
82 struct iwl_rx_transfer_desc {
88 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
91 * struct iwl_rx_completion_desc - completion descriptor
92 * @reserved1: reserved
93 * @rbid: unique tag of the received buffer
94 * @flags: flags (0: fragmented, all others: reserved)
95 * @reserved2: reserved
97 struct iwl_rx_completion_desc {
105 * struct iwl_rx_completion_desc_bz - Bz completion descriptor
106 * @rbid: unique tag of the received buffer
107 * @flags: flags (0: fragmented, all others: reserved)
108 * @reserved: reserved
110 struct iwl_rx_completion_desc_bz {
117 * struct iwl_rxq - Rx queue
119 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
120 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
121 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
122 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
123 * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
124 * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
125 * @read: Shared index to newest available Rx buffer
126 * @write: Shared index to oldest written Rx packet
127 * @write_actual: actual write pointer written to device, since we update in
129 * @free_count: Number of pre-allocated buffers in rx_free
130 * @used_count: Number of RBDs handled to allocator to use for allocation
132 * @rx_free: list of RBDs with allocated RB ready for use
133 * @rx_used: list of RBDs with no RB attached
134 * @need_update: flag to indicate we need to update read/write index
135 * @rb_stts: driver's pointer to receive buffer status
136 * @rb_stts_dma: bus address of receive buffer status
137 * @lock: per-queue lock
138 * @queue: actual rx queue. Not used for multi-rx queue.
139 * @next_rb_is_fragment: indicates that the previous RB that we handled set
140 * the fragmented flag, so the next one is still another fragment
141 * @napi: NAPI struct for this queue
142 * @queue_size: size of this queue
144 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
151 dma_addr_t used_bd_dma;
158 struct list_head rx_free;
159 struct list_head rx_used;
160 bool need_update, next_rb_is_fragment;
162 dma_addr_t rb_stts_dma;
164 struct napi_struct napi;
165 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
169 * struct iwl_rb_allocator - Rx allocator
170 * @req_pending: number of requests the allcator had not processed yet
171 * @req_ready: number of requests honored and ready for claiming
172 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
173 * the queue. This is a list of &struct iwl_rx_mem_buffer
174 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
175 * of &struct iwl_rx_mem_buffer
176 * @lock: protects the rbd_allocated and rbd_empty lists
177 * @alloc_wq: work queue for background calls
178 * @rx_alloc: work struct for background calls
180 struct iwl_rb_allocator {
181 atomic_t req_pending;
183 struct list_head rbd_allocated;
184 struct list_head rbd_empty;
186 struct workqueue_struct *alloc_wq;
187 struct work_struct rx_alloc;
191 * iwl_get_closed_rb_stts - get closed rb stts from different structs
192 * @trans: transport pointer (for configuration)
193 * @rxq: the rxq to get the rb stts from
195 static inline u16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
198 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
199 __le16 *rb_stts = rxq->rb_stts;
201 return le16_to_cpu(READ_ONCE(*rb_stts));
203 struct iwl_rb_status *rb_stts = rxq->rb_stts;
205 return le16_to_cpu(READ_ONCE(rb_stts->closed_rb_num)) & 0xFFF;
209 #ifdef CONFIG_IWLWIFI_DEBUGFS
211 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
214 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
215 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
216 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
217 * set the file can no longer be used.
219 enum iwl_fw_mon_dbgfs_state {
220 IWL_FW_MON_DBGFS_STATE_CLOSED,
221 IWL_FW_MON_DBGFS_STATE_OPEN,
222 IWL_FW_MON_DBGFS_STATE_DISABLED,
227 * enum iwl_shared_irq_flags - level of sharing for irq
228 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
229 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
231 enum iwl_shared_irq_flags {
232 IWL_SHARED_IRQ_NON_RX = BIT(0),
233 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
237 * enum iwl_image_response_code - image response values
238 * @IWL_IMAGE_RESP_DEF: the default value of the register
239 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
240 * @IWL_IMAGE_RESP_FAIL: iml reading failed
242 enum iwl_image_response_code {
243 IWL_IMAGE_RESP_DEF = 0,
244 IWL_IMAGE_RESP_SUCCESS = 1,
245 IWL_IMAGE_RESP_FAIL = 2,
248 #ifdef CONFIG_IWLWIFI_DEBUGFS
250 * struct cont_rec: continuous recording data structure
251 * @prev_wr_ptr: the last address that was read in monitor_data
253 * @prev_wrap_cnt: the wrap count that was used during the last read in
254 * monitor_data debugfs file
255 * @state: the state of monitor_data debugfs file as described
256 * in &iwl_fw_mon_dbgfs_state enum
257 * @mutex: locked while reading from monitor_data debugfs file
263 /* Used to sync monitor_data debugfs file with driver unload flow */
268 enum iwl_pcie_fw_reset_state {
276 * enum wl_pcie_imr_status - imr dma transfer state
277 * @IMR_D2S_IDLE: default value of the dma transfer
278 * @IMR_D2S_REQUESTED: dma transfer requested
279 * @IMR_D2S_COMPLETED: dma transfer completed
280 * @IMR_D2S_ERROR: dma transfer error
282 enum iwl_pcie_imr_status {
290 * struct iwl_trans_pcie - PCIe transport specific data
291 * @rxq: all the RX queue data
292 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
293 * @global_table: table mapping received VID from hw to rxb
294 * @rba: allocator for RX replenishing
295 * @ctxt_info: context information for FW self init
296 * @ctxt_info_gen3: context information for gen3 devices
297 * @prph_info: prph info for self init
298 * @prph_scratch: prph scratch for self init
299 * @ctxt_info_dma_addr: dma addr of context information
300 * @prph_info_dma_addr: dma addr of prph info
301 * @prph_scratch_dma_addr: dma addr of prph scratch
302 * @ctxt_info_dma_addr: dma addr of context information
303 * @iml: image loader image virtual address
304 * @iml_dma_addr: image loader image DMA address
305 * @trans: pointer to the generic transport area
306 * @scd_base_addr: scheduler sram base address in SRAM
307 * @kw: keep warm address
308 * @pnvm_data: holds info about pnvm payloads allocated in DRAM
309 * @reduced_tables_data: holds info about power reduced tablse
310 * payloads allocated in DRAM
311 * @pci_dev: basic pci-network driver stuff
312 * @hw_base: pci hardware address support
313 * @ucode_write_complete: indicates that the ucode has been copied.
314 * @ucode_write_waitq: wait queue for uCode load
315 * @cmd_queue - command queue number
316 * @rx_buf_size: Rx buffer size
317 * @scd_set_active: should the transport configure the SCD for HCMD queue
318 * @rx_page_order: page order for receive buffer size
319 * @rx_buf_bytes: RX buffer (RB) size in bytes
320 * @reg_lock: protect hw register access
321 * @mutex: to protect stop_device / start_fw / start_hw
322 * @fw_mon_data: fw continuous recording data
323 * @cmd_hold_nic_awake: indicates NIC is held awake for APMG workaround
324 * during commands in flight
325 * @msix_entries: array of MSI-X entries
326 * @msix_enabled: true if managed to enable MSI-X
327 * @shared_vec_mask: the type of causes the shared vector handles
328 * (see iwl_shared_irq_flags).
329 * @alloc_vecs: the number of interrupt vectors allocated by the OS
330 * @def_irq: default irq for non rx causes
331 * @fh_init_mask: initial unmasked fh causes
332 * @hw_init_mask: initial unmasked hw causes
333 * @fh_mask: current unmasked fh causes
334 * @hw_mask: current unmasked hw causes
335 * @in_rescan: true if we have triggered a device rescan
336 * @base_rb_stts: base virtual address of receive buffer status for all queues
337 * @base_rb_stts_dma: base physical address of receive buffer status
338 * @supported_dma_mask: DMA mask to validate the actual address against,
339 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
340 * @alloc_page_lock: spinlock for the page allocator
341 * @alloc_page: allocated page to still use parts of
342 * @alloc_page_used: how much of the allocated page was already used (bytes)
343 * @imr_status: imr dma state machine
344 * @imr_waitq: imr wait queue for dma completion
345 * @rf_name: name/version of the CRF, if any
346 * @use_ict: whether or not ICT (interrupt table) is used
347 * @ict_index: current ICT read index
348 * @ict_tbl: ICT table pointer
349 * @ict_tbl_dma: ICT table DMA address
350 * @inta_mask: interrupt (INT-A) mask
351 * @irq_lock: lock to synchronize IRQ handling
352 * @txq_memory: TXQ allocation array
353 * @sx_waitq: waitqueue for Sx transitions
354 * @sx_complete: completion for Sx transitions
355 * @pcie_dbg_dumped_once: indicates PCIe regs were dumped already
356 * @opmode_down: indicates opmode went away
357 * @num_rx_bufs: number of RX buffers to allocate/use
358 * @no_reclaim_cmds: special commands not using reclaim flow
359 * (firmware workaround)
360 * @n_no_reclaim_cmds: number of special commands not using reclaim flow
361 * @affinity_mask: IRQ affinity mask for each RX queue
362 * @debug_rfkill: RF-kill debugging state, -1 for unset, 0/1 for radio
364 * @fw_reset_handshake: indicates FW reset handshake is needed
365 * @fw_reset_state: state of FW reset handshake
366 * @fw_reset_waitq: waitqueue for FW reset handshake
367 * @is_down: indicates the NIC is down
368 * @isr_stats: interrupt statistics
369 * @napi_dev: (fake) netdev for NAPI registration
371 struct iwl_trans_pcie {
373 struct iwl_rx_mem_buffer *rx_pool;
374 struct iwl_rx_mem_buffer **global_table;
375 struct iwl_rb_allocator rba;
377 struct iwl_context_info *ctxt_info;
378 struct iwl_context_info_gen3 *ctxt_info_gen3;
380 struct iwl_prph_info *prph_info;
381 struct iwl_prph_scratch *prph_scratch;
383 dma_addr_t ctxt_info_dma_addr;
384 dma_addr_t prph_info_dma_addr;
385 dma_addr_t prph_scratch_dma_addr;
386 dma_addr_t iml_dma_addr;
387 struct iwl_trans *trans;
389 struct net_device napi_dev;
393 dma_addr_t ict_tbl_dma;
396 bool is_down, opmode_down;
398 struct isr_statistics isr_stats;
404 struct iwl_dma_ptr kw;
407 struct iwl_dram_regions pnvm_data;
408 struct iwl_dram_regions reduced_tables_data;
410 struct iwl_txq *txq_memory;
412 /* PCI bus related data */
413 struct pci_dev *pci_dev;
416 bool ucode_write_complete;
418 wait_queue_head_t ucode_write_waitq;
419 wait_queue_head_t sx_waitq;
421 u8 n_no_reclaim_cmds;
422 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
425 enum iwl_amsdu_size rx_buf_size;
427 bool pcie_dbg_dumped_once;
430 u32 supported_dma_mask;
432 /* allocator lock for the two values below */
433 spinlock_t alloc_page_lock;
434 struct page *alloc_page;
437 /*protect hw register */
439 bool cmd_hold_nic_awake;
441 #ifdef CONFIG_IWLWIFI_DEBUGFS
442 struct cont_rec fw_mon_data;
445 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
454 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
455 u16 tx_cmd_queue_size;
459 dma_addr_t base_rb_stts_dma;
461 bool fw_reset_handshake;
462 enum iwl_pcie_fw_reset_state fw_reset_state;
463 wait_queue_head_t fw_reset_waitq;
464 enum iwl_pcie_imr_status imr_status;
465 wait_queue_head_t imr_waitq;
469 static inline struct iwl_trans_pcie *
470 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
472 return (void *)trans->trans_specific;
475 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
478 * Before sending the interrupt the HW disables it to prevent
479 * a nested interrupt. This is done by writing 1 to the corresponding
480 * bit in the mask register. After handling the interrupt, it should be
481 * re-enabled by clearing this bit. This register is defined as
482 * write 1 clear (W1C) register, meaning that it's being clear
483 * by writing 1 to the bit.
485 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
488 static inline struct iwl_trans *
489 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
491 return container_of((void *)trans_pcie, struct iwl_trans,
496 * Convention: trans API functions: iwl_trans_pcie_XXX
497 * Other functions: iwl_pcie_XXX
500 *iwl_trans_pcie_alloc(struct pci_dev *pdev,
501 const struct pci_device_id *ent,
502 const struct iwl_cfg_trans_params *cfg_trans);
503 void iwl_trans_pcie_free(struct iwl_trans *trans);
504 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
507 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
508 #define _iwl_trans_pcie_grab_nic_access(trans) \
509 __cond_lock(nic_access_nobh, \
510 likely(__iwl_trans_pcie_grab_nic_access(trans)))
512 /*****************************************************
514 ******************************************************/
515 int iwl_pcie_rx_init(struct iwl_trans *trans);
516 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
517 irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
518 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
519 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
520 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
521 int iwl_pcie_rx_stop(struct iwl_trans *trans);
522 void iwl_pcie_rx_free(struct iwl_trans *trans);
523 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
524 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
525 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans);
526 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
527 struct iwl_rxq *rxq);
529 /*****************************************************
530 * ICT - interrupt handling
531 ******************************************************/
532 irqreturn_t iwl_pcie_isr(int irq, void *data);
533 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
534 void iwl_pcie_free_ict(struct iwl_trans *trans);
535 void iwl_pcie_reset_ict(struct iwl_trans *trans);
536 void iwl_pcie_disable_ict(struct iwl_trans *trans);
538 /*****************************************************
540 ******************************************************/
541 int iwl_pcie_tx_init(struct iwl_trans *trans);
542 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
543 int iwl_pcie_tx_stop(struct iwl_trans *trans);
544 void iwl_pcie_tx_free(struct iwl_trans *trans);
545 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
546 const struct iwl_trans_txq_scd_cfg *cfg,
547 unsigned int wdg_timeout);
548 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
550 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
552 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
553 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
554 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
555 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
556 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
557 struct iwl_rx_cmd_buffer *rxb);
558 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
560 /*****************************************************
562 ******************************************************/
563 void iwl_pcie_dump_csr(struct iwl_trans *trans);
565 /*****************************************************
567 ******************************************************/
568 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
572 clear_bit(STATUS_INT_ENABLED, &trans->status);
573 if (!trans_pcie->msix_enabled) {
574 /* disable interrupts from uCode/NIC to host */
575 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
577 /* acknowledge/clear/reset any interrupts still pending
578 * from uCode or flow handler (Rx/Tx DMA) */
579 iwl_write32(trans, CSR_INT, 0xffffffff);
580 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
582 /* disable all the interrupt we might use */
583 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
584 trans_pcie->fh_init_mask);
585 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
586 trans_pcie->hw_init_mask);
588 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
591 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
596 while (start < fw->num_sec &&
597 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
598 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
606 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
608 struct iwl_self_init_dram *dram = &trans->init_dram;
612 WARN_ON(dram->fw_cnt);
616 for (i = 0; i < dram->fw_cnt; i++)
617 dma_free_coherent(trans->dev, dram->fw[i].size,
618 dram->fw[i].block, dram->fw[i].physical);
625 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
629 spin_lock_bh(&trans_pcie->irq_lock);
630 _iwl_disable_interrupts(trans);
631 spin_unlock_bh(&trans_pcie->irq_lock);
634 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
636 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
638 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
639 set_bit(STATUS_INT_ENABLED, &trans->status);
640 if (!trans_pcie->msix_enabled) {
641 trans_pcie->inta_mask = CSR_INI_SET_MASK;
642 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
645 * fh/hw_mask keeps all the unmasked causes.
646 * Unlike msi, in msix cause is enabled when it is unset.
648 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
649 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
650 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
651 ~trans_pcie->fh_mask);
652 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
653 ~trans_pcie->hw_mask);
657 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
659 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
661 spin_lock_bh(&trans_pcie->irq_lock);
662 _iwl_enable_interrupts(trans);
663 spin_unlock_bh(&trans_pcie->irq_lock);
665 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
667 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
669 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
670 trans_pcie->hw_mask = msk;
673 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
675 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
677 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
678 trans_pcie->fh_mask = msk;
681 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
683 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
685 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
686 if (!trans_pcie->msix_enabled) {
687 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
688 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
690 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
691 trans_pcie->hw_init_mask);
692 iwl_enable_fh_int_msk_msix(trans,
693 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
697 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
699 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
701 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
703 if (!trans_pcie->msix_enabled) {
705 * When we'll receive the ALIVE interrupt, the ISR will call
706 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
707 * interrupt (which is not really needed anymore) but also the
708 * RX interrupt which will allow us to receive the ALIVE
709 * notification (which is Rx) and continue the flow.
711 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
712 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
714 iwl_enable_hw_int_msk_msix(trans,
715 MSIX_HW_INT_CAUSES_REG_ALIVE);
717 * Leave all the FH causes enabled to get the ALIVE
720 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
724 static inline const char *queue_name(struct device *dev,
725 struct iwl_trans_pcie *trans_p, int i)
727 if (trans_p->shared_vec_mask) {
728 int vec = trans_p->shared_vec_mask &
729 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
732 return DRV_NAME ":shared_IRQ";
734 return devm_kasprintf(dev, GFP_KERNEL,
735 DRV_NAME ":queue_%d", i + vec);
738 return DRV_NAME ":default_queue";
740 if (i == trans_p->alloc_vecs - 1)
741 return DRV_NAME ":exception";
743 return devm_kasprintf(dev, GFP_KERNEL,
744 DRV_NAME ":queue_%d", i);
747 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
749 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
751 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
752 if (!trans_pcie->msix_enabled) {
753 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
754 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
756 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
757 trans_pcie->fh_init_mask);
758 iwl_enable_hw_int_msk_msix(trans,
759 MSIX_HW_INT_CAUSES_REG_RF_KILL);
762 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
764 * On 9000-series devices this bit isn't enabled by default, so
765 * when we power down the device we need set the bit to allow it
766 * to wake up the PCI-E bus for RF-kill interrupts.
768 iwl_set_bit(trans, CSR_GP_CNTRL,
769 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
773 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
775 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
777 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
779 lockdep_assert_held(&trans_pcie->mutex);
781 if (trans_pcie->debug_rfkill == 1)
784 return !(iwl_read32(trans, CSR_GP_CNTRL) &
785 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
788 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
789 u32 reg, u32 mask, u32 value)
793 #ifdef CONFIG_IWLWIFI_DEBUG
794 WARN_ON_ONCE(value & ~mask);
797 v = iwl_read32(trans, reg);
800 iwl_write32(trans, reg, v);
803 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
806 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
809 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
812 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
815 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
817 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
820 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
821 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
823 #ifdef CONFIG_IWLWIFI_DEBUGFS
824 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
826 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
829 void iwl_pcie_rx_allocator_work(struct work_struct *data);
831 /* common functions that are used by gen2 transport */
832 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
833 void iwl_pcie_apm_config(struct iwl_trans *trans);
834 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
835 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
836 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
837 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
839 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
840 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
841 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
842 struct iwl_dma_ptr *ptr, size_t size);
843 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
844 void iwl_pcie_apply_destination(struct iwl_trans *trans);
846 /* common functions that are used by gen3 transport */
847 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
849 /* transport gen 2 exported functions */
850 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
851 const struct fw_img *fw, bool run_in_rfkill);
852 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
853 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
854 struct iwl_host_cmd *cmd);
855 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
856 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
857 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
858 bool test, bool reset);
859 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
860 struct iwl_host_cmd *cmd);
861 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
862 struct iwl_host_cmd *cmd);
863 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
864 u32 dst_addr, u64 src_addr, u32 byte_cnt);
865 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
866 u32 dst_addr, u64 src_addr, u32 byte_cnt);
868 #endif /* __iwl_trans_int_pcie_h__ */