drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018-2020 Intel Corporation
   4  */
   5 #include "iwl-trans.h"
   6 #include "iwl-fh.h"
   7 #include "iwl-context-info-gen3.h"
   8 #include "internal.h"
   9 #include "iwl-prph.h"
  10
  11 static void
  12 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
  13                               struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
  14                               u32 *control_flags)
  15 {
  16         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
  17         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
  18         u32 dbg_flags = 0;
  19
  20         if (!iwl_trans_dbg_ini_valid(trans)) {
  21                 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
  22
  23                 iwl_pcie_alloc_fw_monitor(trans, 0);
  24
  25                 if (fw_mon->size) {
  26                         dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
  27
  28                         IWL_DEBUG_FW(trans,
  29                                      "WRT: Applying DRAM buffer destination\n");
  30
  31                         dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
  32                         dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
  33                 }
  34
  35                 goto out;
  36         }
  37
  38         fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
  39
  40         switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
  41         case IWL_FW_INI_LOCATION_SRAM_PATH:
  42                 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
  43                 IWL_DEBUG_FW(trans,
  44                                 "WRT: Applying SMEM buffer destination\n");
  45                 break;
  46
  47         case IWL_FW_INI_LOCATION_NPK_PATH:
  48                 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
  49                 IWL_DEBUG_FW(trans,
  50                              "WRT: Applying NPK buffer destination\n");
  51                 break;
  52
  53         case IWL_FW_INI_LOCATION_DRAM_PATH:
  54                 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
  55                         struct iwl_dram_data *frag =
  56                                 &trans->dbg.fw_mon_ini[alloc_id].frags[0];
  57                         dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
  58                         dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
  59                         dbg_cfg->hwm_size = cpu_to_le32(frag->size);
  60                         IWL_DEBUG_FW(trans,
  61                                      "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
  62                                      alloc_id,
  63                                      trans->dbg.fw_mon_ini[alloc_id].num_frags);
  64                 }
  65                 break;
  66         default:
  67                 IWL_ERR(trans, "WRT: Invalid buffer destination\n");
  68         }
  69 out:
  70         if (dbg_flags)
  71                 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
  72 }
  73
  74 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
  75                                  const struct fw_img *fw)
  76 {
  77         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  78         u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
  79                       u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
  80                                       CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
  81                       u32_encode_bits(250,
  82                                       CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
  83                       CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
  84                       u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
  85                                       CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
  86                       u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
  87         struct iwl_context_info_gen3 *ctxt_info_gen3;
  88         struct iwl_prph_scratch *prph_scratch;
  89         struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
  90         struct iwl_prph_info *prph_info;
  91         void *iml_img;
  92         u32 control_flags = 0;
  93         int ret;
  94         int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
  95                               trans->cfg->min_txq_size);
  96
  97         switch (trans_pcie->rx_buf_size) {
  98         case IWL_AMSDU_DEF:
  99                 return -EINVAL;
 100         case IWL_AMSDU_2K:
 101                 break;
 102         case IWL_AMSDU_4K:
 103                 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
 104                 break;
 105         case IWL_AMSDU_8K:
 106                 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
 107                 /* if firmware supports the ext size, tell it */
 108                 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
 109                 break;
 110         case IWL_AMSDU_12K:
 111                 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
 112                 /* if firmware supports the ext size, tell it */
 113                 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K;
 114                 break;
 115         }
 116
 117         /* Allocate prph scratch */
 118         prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
 119                                           &trans_pcie->prph_scratch_dma_addr,
 120                                           GFP_KERNEL);
 121         if (!prph_scratch)
 122                 return -ENOMEM;
 123
 124         prph_sc_ctrl = &prph_scratch->ctrl_cfg;
 125
 126         prph_sc_ctrl->version.version = 0;
 127         prph_sc_ctrl->version.mac_id =
 128                 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
 129         prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
 130
 131         control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
 132         control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
 133
 134         /* initialize RX default queue */
 135         prph_sc_ctrl->rbd_cfg.free_rbd_addr =
 136                 cpu_to_le64(trans_pcie->rxq->bd_dma);
 137
 138         iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
 139                                       &control_flags);
 140         prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
 141
 142         /* allocate ucode sections in dram and set addresses */
 143         ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
 144         if (ret)
 145                 goto err_free_prph_scratch;
 146
 147
 148         /* Allocate prph information
 149          * currently we don't assign to the prph info anything, but it would get
 150          * assigned later */
 151         prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
 152                                        &trans_pcie->prph_info_dma_addr,
 153                                        GFP_KERNEL);
 154         if (!prph_info) {
 155                 ret = -ENOMEM;
 156                 goto err_free_prph_scratch;
 157         }
 158
 159         /* Allocate context info */
 160         ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
 161                                             sizeof(*ctxt_info_gen3),
 162                                             &trans_pcie->ctxt_info_dma_addr,
 163                                             GFP_KERNEL);
 164         if (!ctxt_info_gen3) {
 165                 ret = -ENOMEM;
 166                 goto err_free_prph_info;
 167         }
 168
 169         ctxt_info_gen3->prph_info_base_addr =
 170                 cpu_to_le64(trans_pcie->prph_info_dma_addr);
 171         ctxt_info_gen3->prph_scratch_base_addr =
 172                 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
 173         ctxt_info_gen3->prph_scratch_size =
 174                 cpu_to_le32(sizeof(*prph_scratch));
 175         ctxt_info_gen3->cr_head_idx_arr_base_addr =
 176                 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
 177         ctxt_info_gen3->tr_tail_idx_arr_base_addr =
 178                 cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
 179         ctxt_info_gen3->cr_tail_idx_arr_base_addr =
 180                 cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
 181         ctxt_info_gen3->cr_idx_arr_size =
 182                 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
 183         ctxt_info_gen3->tr_idx_arr_size =
 184                 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
 185         ctxt_info_gen3->mtr_base_addr =
 186                 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
 187         ctxt_info_gen3->mcr_base_addr =
 188                 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
 189         ctxt_info_gen3->mtr_size =
 190                 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
 191         ctxt_info_gen3->mcr_size =
 192                 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
 193
 194         trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
 195         trans_pcie->prph_info = prph_info;
 196         trans_pcie->prph_scratch = prph_scratch;
 197
 198         /* Allocate IML */
 199         iml_img = dma_alloc_coherent(trans->dev, trans->iml_len,
 200                                      &trans_pcie->iml_dma_addr, GFP_KERNEL);
 201         if (!iml_img) {
 202                 ret = -ENOMEM;
 203                 goto err_free_ctxt_info;
 204         }
 205
 206         memcpy(iml_img, trans->iml, trans->iml_len);
 207
 208         iwl_enable_fw_load_int_ctx_info(trans);
 209
 210         /* kick FW self load */
 211         iwl_write64(trans, CSR_CTXT_INFO_ADDR,
 212                     trans_pcie->ctxt_info_dma_addr);
 213         iwl_write64(trans, CSR_IML_DATA_ADDR,
 214                     trans_pcie->iml_dma_addr);
 215         iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
 216
 217         iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
 218                     CSR_AUTO_FUNC_BOOT_ENA);
 219
 220         /*
 221          * To workaround hardware latency issues during the boot process,
 222          * initialize the LTR to ~250 usec (see ltr_val above).
 223          * The firmware initializes this again later (to a smaller value).
 224          */
 225         if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
 226              trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
 227             !trans->trans_cfg->integrated) {
 228                 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
 229         } else if (trans->trans_cfg->integrated &&
 230                    trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
 231                 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
 232                 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
 233         }
 234
 235         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
 236                 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
 237         else
 238                 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
 239
 240         return 0;
 241
 242 err_free_ctxt_info:
 243         dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
 244                           trans_pcie->ctxt_info_gen3,
 245                           trans_pcie->ctxt_info_dma_addr);
 246         trans_pcie->ctxt_info_gen3 = NULL;
 247 err_free_prph_info:
 248         dma_free_coherent(trans->dev,
 249                           sizeof(*prph_info),
 250                         prph_info,
 251                         trans_pcie->prph_info_dma_addr);
 252
 253 err_free_prph_scratch:
 254         dma_free_coherent(trans->dev,
 255                           sizeof(*prph_scratch),
 256                         prph_scratch,
 257                         trans_pcie->prph_scratch_dma_addr);
 258         return ret;
 259
 260 }
 261
 262 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
 263 {
 264         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 265
 266         if (!trans_pcie->ctxt_info_gen3)
 267                 return;
 268
 269         dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
 270                           trans_pcie->ctxt_info_gen3,
 271                           trans_pcie->ctxt_info_dma_addr);
 272         trans_pcie->ctxt_info_dma_addr = 0;
 273         trans_pcie->ctxt_info_gen3 = NULL;
 274
 275         iwl_pcie_ctxt_info_free_fw_img(trans);
 276
 277         dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
 278                           trans_pcie->prph_scratch,
 279                           trans_pcie->prph_scratch_dma_addr);
 280         trans_pcie->prph_scratch_dma_addr = 0;
 281         trans_pcie->prph_scratch = NULL;
 282
 283         dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
 284                           trans_pcie->prph_info,
 285                           trans_pcie->prph_info_dma_addr);
 286         trans_pcie->prph_info_dma_addr = 0;
 287         trans_pcie->prph_info = NULL;
 288 }
 289
 290 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
 291                                           const void *data, u32 len)
 292 {
 293         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 294         struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
 295                 &trans_pcie->prph_scratch->ctrl_cfg;
 296         int ret;
 297
 298         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
 299                 return 0;
 300
 301         /* only allocate the DRAM if not allocated yet */
 302         if (!trans->pnvm_loaded) {
 303                 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
 304                         return -EBUSY;
 305
 306                 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
 307                                                    &trans_pcie->pnvm_dram);
 308                 if (ret < 0) {
 309                         IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
 310                                      ret);
 311                         return ret;
 312                 }
 313         }
 314
 315         prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
 316                 cpu_to_le64(trans_pcie->pnvm_dram.physical);
 317         prph_sc_ctrl->pnvm_cfg.pnvm_size =
 318                 cpu_to_le32(trans_pcie->pnvm_dram.size);
 319
 320         return 0;
 321 }