drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
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  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * General Public License for more details.
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  22  * The full GNU General Public License is included in this distribution
  23  * in the file called COPYING.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <linuxwifi@intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  * BSD LICENSE
  30  *
  31  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 - 2019 Intel Corporation
  35  * All rights reserved.
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  38  * modification, are permitted provided that the following conditions
  39  * are met:
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  42  *    notice, this list of conditions and the following disclaimer.
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  45  *    the documentation and/or other materials provided with the
  46  *    distribution.
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  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  56  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *****************************************************************************/
  63 #include <linux/types.h>
  64 #include <linux/slab.h>
  65 #include <linux/export.h>
  66 #include <linux/etherdevice.h>
  67 #include <linux/pci.h>
  68 #include <linux/firmware.h>
  69
  70 #include "iwl-drv.h"
  71 #include "iwl-modparams.h"
  72 #include "iwl-nvm-parse.h"
  73 #include "iwl-prph.h"
  74 #include "iwl-io.h"
  75 #include "iwl-csr.h"
  76 #include "fw/acpi.h"
  77 #include "fw/api/nvm-reg.h"
  78 #include "fw/api/commands.h"
  79 #include "fw/api/cmdhdr.h"
  80 #include "fw/img.h"
  81
  82 /* NVM offsets (in words) definitions */
  83 enum nvm_offsets {
  84         /* NVM HW-Section offset (in words) definitions */
  85         SUBSYSTEM_ID = 0x0A,
  86         HW_ADDR = 0x15,
  87
  88         /* NVM SW-Section offset (in words) definitions */
  89         NVM_SW_SECTION = 0x1C0,
  90         NVM_VERSION = 0,
  91         RADIO_CFG = 1,
  92         SKU = 2,
  93         N_HW_ADDRS = 3,
  94         NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  95
  96         /* NVM calibration section offset (in words) definitions */
  97         NVM_CALIB_SECTION = 0x2B8,
  98         XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
  99
 100         /* NVM REGULATORY -Section offset (in words) definitions */
 101         NVM_CHANNELS_SDP = 0,
 102 };
 103
 104 enum ext_nvm_offsets {
 105         /* NVM HW-Section offset (in words) definitions */
 106         MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
 107
 108         /* NVM SW-Section offset (in words) definitions */
 109         NVM_VERSION_EXT_NVM = 0,
 110         RADIO_CFG_FAMILY_EXT_NVM = 0,
 111         SKU_FAMILY_8000 = 2,
 112         N_HW_ADDRS_FAMILY_8000 = 3,
 113
 114         /* NVM REGULATORY -Section offset (in words) definitions */
 115         NVM_CHANNELS_EXTENDED = 0,
 116         NVM_LAR_OFFSET_OLD = 0x4C7,
 117         NVM_LAR_OFFSET = 0x507,
 118         NVM_LAR_ENABLED = 0x7,
 119 };
 120
 121 /* SKU Capabilities (actual values from NVM definition) */
 122 enum nvm_sku_bits {
 123         NVM_SKU_CAP_BAND_24GHZ          = BIT(0),
 124         NVM_SKU_CAP_BAND_52GHZ          = BIT(1),
 125         NVM_SKU_CAP_11N_ENABLE          = BIT(2),
 126         NVM_SKU_CAP_11AC_ENABLE         = BIT(3),
 127         NVM_SKU_CAP_MIMO_DISABLE        = BIT(5),
 128 };
 129
 130 /*
 131  * These are the channel numbers in the order that they are stored in the NVM
 132  */
 133 static const u8 iwl_nvm_channels[] = {
 134         /* 2.4 GHz */
 135         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 136         /* 5 GHz */
 137         36, 40, 44 , 48, 52, 56, 60, 64,
 138         100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
 139         149, 153, 157, 161, 165
 140 };
 141
 142 static const u8 iwl_ext_nvm_channels[] = {
 143         /* 2.4 GHz */
 144         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 145         /* 5 GHz */
 146         36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
 147         96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
 148         149, 153, 157, 161, 165, 169, 173, 177, 181
 149 };
 150
 151 #define IWL_NVM_NUM_CHANNELS            ARRAY_SIZE(iwl_nvm_channels)
 152 #define IWL_NVM_NUM_CHANNELS_EXT        ARRAY_SIZE(iwl_ext_nvm_channels)
 153 #define NUM_2GHZ_CHANNELS               14
 154 #define NUM_2GHZ_CHANNELS_EXT   14
 155 #define FIRST_2GHZ_HT_MINUS             5
 156 #define LAST_2GHZ_HT_PLUS               9
 157 #define LAST_5GHZ_HT                    165
 158 #define LAST_5GHZ_HT_FAMILY_8000        181
 159 #define N_HW_ADDR_MASK                  0xF
 160
 161 /* rate data (static) */
 162 static struct ieee80211_rate iwl_cfg80211_rates[] = {
 163         { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
 164         { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
 165           .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 166         { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
 167           .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 168         { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
 169           .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 170         { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
 171         { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
 172         { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
 173         { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
 174         { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
 175         { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
 176         { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
 177         { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
 178 };
 179 #define RATES_24_OFFS   0
 180 #define N_RATES_24      ARRAY_SIZE(iwl_cfg80211_rates)
 181 #define RATES_52_OFFS   4
 182 #define N_RATES_52      (N_RATES_24 - RATES_52_OFFS)
 183
 184 /**
 185  * enum iwl_nvm_channel_flags - channel flags in NVM
 186  * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
 187  * @NVM_CHANNEL_IBSS: usable as an IBSS channel
 188  * @NVM_CHANNEL_ACTIVE: active scanning allowed
 189  * @NVM_CHANNEL_RADAR: radar detection required
 190  * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
 191  * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
 192  *      on same channel on 2.4 or same UNII band on 5.2
 193  * @NVM_CHANNEL_UNIFORM: uniform spreading required
 194  * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
 195  * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
 196  * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
 197  * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
 198  * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
 199  */
 200 enum iwl_nvm_channel_flags {
 201         NVM_CHANNEL_VALID               = BIT(0),
 202         NVM_CHANNEL_IBSS                = BIT(1),
 203         NVM_CHANNEL_ACTIVE              = BIT(3),
 204         NVM_CHANNEL_RADAR               = BIT(4),
 205         NVM_CHANNEL_INDOOR_ONLY         = BIT(5),
 206         NVM_CHANNEL_GO_CONCURRENT       = BIT(6),
 207         NVM_CHANNEL_UNIFORM             = BIT(7),
 208         NVM_CHANNEL_20MHZ               = BIT(8),
 209         NVM_CHANNEL_40MHZ               = BIT(9),
 210         NVM_CHANNEL_80MHZ               = BIT(10),
 211         NVM_CHANNEL_160MHZ              = BIT(11),
 212         NVM_CHANNEL_DC_HIGH             = BIT(12),
 213 };
 214
 215 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
 216                                                int chan, u16 flags)
 217 {
 218 #define CHECK_AND_PRINT_I(x)    \
 219         ((flags & NVM_CHANNEL_##x) ? " " #x : "")
 220
 221         if (!(flags & NVM_CHANNEL_VALID)) {
 222                 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
 223                               chan, flags);
 224                 return;
 225         }
 226
 227         /* Note: already can print up to 101 characters, 110 is the limit! */
 228         IWL_DEBUG_DEV(dev, level,
 229                       "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
 230                       chan, flags,
 231                       CHECK_AND_PRINT_I(VALID),
 232                       CHECK_AND_PRINT_I(IBSS),
 233                       CHECK_AND_PRINT_I(ACTIVE),
 234                       CHECK_AND_PRINT_I(RADAR),
 235                       CHECK_AND_PRINT_I(INDOOR_ONLY),
 236                       CHECK_AND_PRINT_I(GO_CONCURRENT),
 237                       CHECK_AND_PRINT_I(UNIFORM),
 238                       CHECK_AND_PRINT_I(20MHZ),
 239                       CHECK_AND_PRINT_I(40MHZ),
 240                       CHECK_AND_PRINT_I(80MHZ),
 241                       CHECK_AND_PRINT_I(160MHZ),
 242                       CHECK_AND_PRINT_I(DC_HIGH));
 243 #undef CHECK_AND_PRINT_I
 244 }
 245
 246 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
 247                                  u16 nvm_flags, const struct iwl_cfg *cfg)
 248 {
 249         u32 flags = IEEE80211_CHAN_NO_HT40;
 250         u32 last_5ghz_ht = LAST_5GHZ_HT;
 251
 252         if (cfg->nvm_type == IWL_NVM_EXT)
 253                 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
 254
 255         if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
 256                 if (ch_num <= LAST_2GHZ_HT_PLUS)
 257                         flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
 258                 if (ch_num >= FIRST_2GHZ_HT_MINUS)
 259                         flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
 260         } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
 261                 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
 262                         flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
 263                 else
 264                         flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
 265         }
 266         if (!(nvm_flags & NVM_CHANNEL_80MHZ))
 267                 flags |= IEEE80211_CHAN_NO_80MHZ;
 268         if (!(nvm_flags & NVM_CHANNEL_160MHZ))
 269                 flags |= IEEE80211_CHAN_NO_160MHZ;
 270
 271         if (!(nvm_flags & NVM_CHANNEL_IBSS))
 272                 flags |= IEEE80211_CHAN_NO_IR;
 273
 274         if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
 275                 flags |= IEEE80211_CHAN_NO_IR;
 276
 277         if (nvm_flags & NVM_CHANNEL_RADAR)
 278                 flags |= IEEE80211_CHAN_RADAR;
 279
 280         if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
 281                 flags |= IEEE80211_CHAN_INDOOR_ONLY;
 282
 283         /* Set the GO concurrent flag only in case that NO_IR is set.
 284          * Otherwise it is meaningless
 285          */
 286         if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
 287             (flags & IEEE80211_CHAN_NO_IR))
 288                 flags |= IEEE80211_CHAN_IR_CONCURRENT;
 289
 290         return flags;
 291 }
 292
 293 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
 294                                 struct iwl_nvm_data *data,
 295                                 const __le16 * const nvm_ch_flags,
 296                                 u32 sbands_flags)
 297 {
 298         int ch_idx;
 299         int n_channels = 0;
 300         struct ieee80211_channel *channel;
 301         u16 ch_flags;
 302         int num_of_ch, num_2ghz_channels;
 303         const u8 *nvm_chan;
 304
 305         if (cfg->nvm_type != IWL_NVM_EXT) {
 306                 num_of_ch = IWL_NVM_NUM_CHANNELS;
 307                 nvm_chan = &iwl_nvm_channels[0];
 308                 num_2ghz_channels = NUM_2GHZ_CHANNELS;
 309         } else {
 310                 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
 311                 nvm_chan = &iwl_ext_nvm_channels[0];
 312                 num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT;
 313         }
 314
 315         for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
 316                 bool is_5ghz = (ch_idx >= num_2ghz_channels);
 317
 318                 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
 319
 320                 if (is_5ghz && !data->sku_cap_band_52ghz_enable)
 321                         continue;
 322
 323                 /* workaround to disable wide channels in 5GHz */
 324                 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
 325                     is_5ghz) {
 326                         ch_flags &= ~(NVM_CHANNEL_40MHZ |
 327                                      NVM_CHANNEL_80MHZ |
 328                                      NVM_CHANNEL_160MHZ);
 329                 }
 330
 331                 if (ch_flags & NVM_CHANNEL_160MHZ)
 332                         data->vht160_supported = true;
 333
 334                 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
 335                     !(ch_flags & NVM_CHANNEL_VALID)) {
 336                         /*
 337                          * Channels might become valid later if lar is
 338                          * supported, hence we still want to add them to
 339                          * the list of supported channels to cfg80211.
 340                          */
 341                         iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
 342                                                     nvm_chan[ch_idx], ch_flags);
 343                         continue;
 344                 }
 345
 346                 channel = &data->channels[n_channels];
 347                 n_channels++;
 348
 349                 channel->hw_value = nvm_chan[ch_idx];
 350                 channel->band = is_5ghz ?
 351                                 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
 352                 channel->center_freq =
 353                         ieee80211_channel_to_frequency(
 354                                 channel->hw_value, channel->band);
 355
 356                 /* Initialize regulatory-based run-time data */
 357
 358                 /*
 359                  * Default value - highest tx power value.  max_power
 360                  * is not used in mvm, and is used for backwards compatibility
 361                  */
 362                 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
 363
 364                 /* don't put limitations in case we're using LAR */
 365                 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
 366                         channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
 367                                                                ch_idx, is_5ghz,
 368                                                                ch_flags, cfg);
 369                 else
 370                         channel->flags = 0;
 371
 372                 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
 373                                             channel->hw_value, ch_flags);
 374                 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
 375                                  channel->hw_value, channel->max_power);
 376         }
 377
 378         return n_channels;
 379 }
 380
 381 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
 382                                   struct iwl_nvm_data *data,
 383                                   struct ieee80211_sta_vht_cap *vht_cap,
 384                                   u8 tx_chains, u8 rx_chains)
 385 {
 386         int num_rx_ants = num_of_ant(rx_chains);
 387         int num_tx_ants = num_of_ant(tx_chains);
 388         unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
 389                                            IEEE80211_VHT_MAX_AMPDU_1024K);
 390
 391         vht_cap->vht_supported = true;
 392
 393         vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
 394                        IEEE80211_VHT_CAP_RXSTBC_1 |
 395                        IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
 396                        3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
 397                        max_ampdu_exponent <<
 398                        IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
 399
 400         if (data->vht160_supported)
 401                 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
 402                                 IEEE80211_VHT_CAP_SHORT_GI_160;
 403
 404         if (cfg->vht_mu_mimo_supported)
 405                 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
 406
 407         if (cfg->ht_params->ldpc)
 408                 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
 409
 410         if (data->sku_cap_mimo_disabled) {
 411                 num_rx_ants = 1;
 412                 num_tx_ants = 1;
 413         }
 414
 415         if (num_tx_ants > 1)
 416                 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
 417         else
 418                 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
 419
 420         switch (iwlwifi_mod_params.amsdu_size) {
 421         case IWL_AMSDU_DEF:
 422                 if (cfg->mq_rx_supported)
 423                         vht_cap->cap |=
 424                                 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 425                 else
 426                         vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
 427                 break;
 428         case IWL_AMSDU_2K:
 429                 if (cfg->mq_rx_supported)
 430                         vht_cap->cap |=
 431                                 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 432                 else
 433                         WARN(1, "RB size of 2K is not supported by this device\n");
 434                 break;
 435         case IWL_AMSDU_4K:
 436                 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
 437                 break;
 438         case IWL_AMSDU_8K:
 439                 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
 440                 break;
 441         case IWL_AMSDU_12K:
 442                 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 443                 break;
 444         default:
 445                 break;
 446         }
 447
 448         vht_cap->vht_mcs.rx_mcs_map =
 449                 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
 450                             IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
 451                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
 452                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
 453                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
 454                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
 455                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
 456                             IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
 457
 458         if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
 459                 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
 460                 /* this works because NOT_SUPPORTED == 3 */
 461                 vht_cap->vht_mcs.rx_mcs_map |=
 462                         cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
 463         }
 464
 465         vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
 466
 467         vht_cap->vht_mcs.tx_highest |=
 468                 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
 469 }
 470
 471 static struct ieee80211_sband_iftype_data iwl_he_capa[] = {
 472         {
 473                 .types_mask = BIT(NL80211_IFTYPE_STATION),
 474                 .he_cap = {
 475                         .has_he = true,
 476                         .he_cap_elem = {
 477                                 .mac_cap_info[0] =
 478                                         IEEE80211_HE_MAC_CAP0_HTC_HE |
 479                                         IEEE80211_HE_MAC_CAP0_TWT_REQ,
 480                                 .mac_cap_info[1] =
 481                                         IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
 482                                         IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
 483                                 .mac_cap_info[2] =
 484                                         IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP |
 485                                         IEEE80211_HE_MAC_CAP2_ACK_EN,
 486                                 .mac_cap_info[3] =
 487                                         IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
 488                                         IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
 489                                 .mac_cap_info[4] =
 490                                         IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU |
 491                                         IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
 492                                 .mac_cap_info[5] =
 493                                         IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
 494                                         IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
 495                                         IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
 496                                         IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
 497                                         IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
 498                                 .phy_cap_info[0] =
 499                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
 500                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
 501                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
 502                                 .phy_cap_info[1] =
 503                                         IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
 504                                         IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
 505                                         IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
 506                                 .phy_cap_info[2] =
 507                                         IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
 508                                 .phy_cap_info[3] =
 509                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
 510                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
 511                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
 512                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
 513                                 .phy_cap_info[4] =
 514                                         IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
 515                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
 516                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
 517                                 .phy_cap_info[5] =
 518                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
 519                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
 520                                 .phy_cap_info[6] =
 521                                         IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
 522                                 .phy_cap_info[7] =
 523                                         IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
 524                                         IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
 525                                         IEEE80211_HE_PHY_CAP7_MAX_NC_1,
 526                                 .phy_cap_info[8] =
 527                                         IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
 528                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
 529                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
 530                                         IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
 531                                         IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
 532                                 .phy_cap_info[9] =
 533                                         IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
 534                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
 535                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
 536                                         IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
 537                         },
 538                         /*
 539                          * Set default Tx/Rx HE MCS NSS Support field.
 540                          * Indicate support for up to 2 spatial streams and all
 541                          * MCS, without any special cases
 542                          */
 543                         .he_mcs_nss_supp = {
 544                                 .rx_mcs_80 = cpu_to_le16(0xfffa),
 545                                 .tx_mcs_80 = cpu_to_le16(0xfffa),
 546                                 .rx_mcs_160 = cpu_to_le16(0xfffa),
 547                                 .tx_mcs_160 = cpu_to_le16(0xfffa),
 548                                 .rx_mcs_80p80 = cpu_to_le16(0xffff),
 549                                 .tx_mcs_80p80 = cpu_to_le16(0xffff),
 550                         },
 551                         /*
 552                          * Set default PPE thresholds, with PPET16 set to 0,
 553                          * PPET8 set to 7
 554                          */
 555                         .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
 556                 },
 557         },
 558         {
 559                 .types_mask = BIT(NL80211_IFTYPE_AP),
 560                 .he_cap = {
 561                         .has_he = true,
 562                         .he_cap_elem = {
 563                                 .mac_cap_info[0] =
 564                                         IEEE80211_HE_MAC_CAP0_HTC_HE,
 565                                 .mac_cap_info[1] =
 566                                         IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
 567                                         IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
 568                                 .mac_cap_info[2] =
 569                                         IEEE80211_HE_MAC_CAP2_BSR |
 570                                         IEEE80211_HE_MAC_CAP2_ACK_EN,
 571                                 .mac_cap_info[3] =
 572                                         IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
 573                                         IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
 574                                 .mac_cap_info[4] =
 575                                         IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
 576                                 .mac_cap_info[5] =
 577                                         IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
 578                                 .phy_cap_info[0] =
 579                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
 580                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
 581                                         IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
 582                                 .phy_cap_info[1] =
 583                                         IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
 584                                 .phy_cap_info[2] =
 585                                         IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
 586                                 .phy_cap_info[3] =
 587                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
 588                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
 589                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
 590                                         IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
 591                                 .phy_cap_info[4] =
 592                                         IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
 593                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
 594                                         IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
 595                                 .phy_cap_info[5] =
 596                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
 597                                         IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
 598                                 .phy_cap_info[6] =
 599                                         IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
 600                                 .phy_cap_info[7] =
 601                                         IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
 602                                         IEEE80211_HE_PHY_CAP7_MAX_NC_1,
 603                                 .phy_cap_info[8] =
 604                                         IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
 605                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
 606                                         IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
 607                                         IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
 608                                         IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
 609                                 .phy_cap_info[9] =
 610                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
 611                                         IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
 612                                         IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
 613                         },
 614                         /*
 615                          * Set default Tx/Rx HE MCS NSS Support field.
 616                          * Indicate support for up to 2 spatial streams and all
 617                          * MCS, without any special cases
 618                          */
 619                         .he_mcs_nss_supp = {
 620                                 .rx_mcs_80 = cpu_to_le16(0xfffa),
 621                                 .tx_mcs_80 = cpu_to_le16(0xfffa),
 622                                 .rx_mcs_160 = cpu_to_le16(0xfffa),
 623                                 .tx_mcs_160 = cpu_to_le16(0xfffa),
 624                                 .rx_mcs_80p80 = cpu_to_le16(0xffff),
 625                                 .tx_mcs_80p80 = cpu_to_le16(0xffff),
 626                         },
 627                         /*
 628                          * Set default PPE thresholds, with PPET16 set to 0,
 629                          * PPET8 set to 7
 630                          */
 631                         .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
 632                 },
 633         },
 634 };
 635
 636 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband,
 637                                  u8 tx_chains, u8 rx_chains)
 638 {
 639         if (sband->band == NL80211_BAND_2GHZ ||
 640             sband->band == NL80211_BAND_5GHZ)
 641                 sband->iftype_data = iwl_he_capa;
 642         else
 643                 return;
 644
 645         sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
 646
 647         /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
 648         if ((tx_chains & rx_chains) != ANT_AB) {
 649                 int i;
 650
 651                 for (i = 0; i < sband->n_iftype_data; i++) {
 652                         iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &=
 653                                 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
 654                         iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &=
 655                                 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
 656                         iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &=
 657                                 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
 658                 }
 659         }
 660 }
 661
 662 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
 663                             struct iwl_nvm_data *data,
 664                             const __le16 *nvm_ch_flags, u8 tx_chains,
 665                             u8 rx_chains, u32 sbands_flags)
 666 {
 667         int n_channels;
 668         int n_used = 0;
 669         struct ieee80211_supported_band *sband;
 670
 671         n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
 672                                           sbands_flags);
 673         sband = &data->bands[NL80211_BAND_2GHZ];
 674         sband->band = NL80211_BAND_2GHZ;
 675         sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
 676         sband->n_bitrates = N_RATES_24;
 677         n_used += iwl_init_sband_channels(data, sband, n_channels,
 678                                           NL80211_BAND_2GHZ);
 679         iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ,
 680                              tx_chains, rx_chains);
 681
 682         if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
 683                 iwl_init_he_hw_capab(sband, tx_chains, rx_chains);
 684
 685         sband = &data->bands[NL80211_BAND_5GHZ];
 686         sband->band = NL80211_BAND_5GHZ;
 687         sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
 688         sband->n_bitrates = N_RATES_52;
 689         n_used += iwl_init_sband_channels(data, sband, n_channels,
 690                                           NL80211_BAND_5GHZ);
 691         iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ,
 692                              tx_chains, rx_chains);
 693         if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
 694                 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
 695                                       tx_chains, rx_chains);
 696
 697         if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
 698                 iwl_init_he_hw_capab(sband, tx_chains, rx_chains);
 699
 700         if (n_channels != n_used)
 701                 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
 702                             n_used, n_channels);
 703 }
 704
 705 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
 706                        const __le16 *phy_sku)
 707 {
 708         if (cfg->nvm_type != IWL_NVM_EXT)
 709                 return le16_to_cpup(nvm_sw + SKU);
 710
 711         return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
 712 }
 713
 714 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
 715 {
 716         if (cfg->nvm_type != IWL_NVM_EXT)
 717                 return le16_to_cpup(nvm_sw + NVM_VERSION);
 718         else
 719                 return le32_to_cpup((__le32 *)(nvm_sw +
 720                                                NVM_VERSION_EXT_NVM));
 721 }
 722
 723 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
 724                              const __le16 *phy_sku)
 725 {
 726         if (cfg->nvm_type != IWL_NVM_EXT)
 727                 return le16_to_cpup(nvm_sw + RADIO_CFG);
 728
 729         return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
 730
 731 }
 732
 733 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
 734 {
 735         int n_hw_addr;
 736
 737         if (cfg->nvm_type != IWL_NVM_EXT)
 738                 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
 739
 740         n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
 741
 742         return n_hw_addr & N_HW_ADDR_MASK;
 743 }
 744
 745 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
 746                               struct iwl_nvm_data *data,
 747                               u32 radio_cfg)
 748 {
 749         if (cfg->nvm_type != IWL_NVM_EXT) {
 750                 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
 751                 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
 752                 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
 753                 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
 754                 return;
 755         }
 756
 757         /* set the radio configuration for family 8000 */
 758         data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
 759         data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
 760         data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
 761         data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
 762         data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
 763         data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
 764 }
 765
 766 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
 767 {
 768         const u8 *hw_addr;
 769
 770         hw_addr = (const u8 *)&mac_addr0;
 771         dest[0] = hw_addr[3];
 772         dest[1] = hw_addr[2];
 773         dest[2] = hw_addr[1];
 774         dest[3] = hw_addr[0];
 775
 776         hw_addr = (const u8 *)&mac_addr1;
 777         dest[4] = hw_addr[1];
 778         dest[5] = hw_addr[0];
 779 }
 780
 781 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
 782                                         struct iwl_nvm_data *data)
 783 {
 784         __le32 mac_addr0 =
 785                 cpu_to_le32(iwl_read32(trans,
 786                                        trans->cfg->csr->mac_addr0_strap));
 787         __le32 mac_addr1 =
 788                 cpu_to_le32(iwl_read32(trans,
 789                                        trans->cfg->csr->mac_addr1_strap));
 790
 791         iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 792         /*
 793          * If the OEM fused a valid address, use it instead of the one in the
 794          * OTP
 795          */
 796         if (is_valid_ether_addr(data->hw_addr))
 797                 return;
 798
 799         mac_addr0 = cpu_to_le32(iwl_read32(trans,
 800                                            trans->cfg->csr->mac_addr0_otp));
 801         mac_addr1 = cpu_to_le32(iwl_read32(trans,
 802                                            trans->cfg->csr->mac_addr1_otp));
 803
 804         iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 805 }
 806
 807 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
 808                                            const struct iwl_cfg *cfg,
 809                                            struct iwl_nvm_data *data,
 810                                            const __le16 *mac_override,
 811                                            const __be16 *nvm_hw)
 812 {
 813         const u8 *hw_addr;
 814
 815         if (mac_override) {
 816                 static const u8 reserved_mac[] = {
 817                         0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
 818                 };
 819
 820                 hw_addr = (const u8 *)(mac_override +
 821                                  MAC_ADDRESS_OVERRIDE_EXT_NVM);
 822
 823                 /*
 824                  * Store the MAC address from MAO section.
 825                  * No byte swapping is required in MAO section
 826                  */
 827                 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
 828
 829                 /*
 830                  * Force the use of the OTP MAC address in case of reserved MAC
 831                  * address in the NVM, or if address is given but invalid.
 832                  */
 833                 if (is_valid_ether_addr(data->hw_addr) &&
 834                     memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
 835                         return;
 836
 837                 IWL_ERR(trans,
 838                         "mac address from nvm override section is not valid\n");
 839         }
 840
 841         if (nvm_hw) {
 842                 /* read the mac address from WFMP registers */
 843                 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
 844                                                 WFMP_MAC_ADDR_0));
 845                 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
 846                                                 WFMP_MAC_ADDR_1));
 847
 848                 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 849
 850                 return;
 851         }
 852
 853         IWL_ERR(trans, "mac address is not found\n");
 854 }
 855
 856 static int iwl_set_hw_address(struct iwl_trans *trans,
 857                               const struct iwl_cfg *cfg,
 858                               struct iwl_nvm_data *data, const __be16 *nvm_hw,
 859                               const __le16 *mac_override)
 860 {
 861         if (cfg->mac_addr_from_csr) {
 862                 iwl_set_hw_address_from_csr(trans, data);
 863         } else if (cfg->nvm_type != IWL_NVM_EXT) {
 864                 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
 865
 866                 /* The byte order is little endian 16 bit, meaning 214365 */
 867                 data->hw_addr[0] = hw_addr[1];
 868                 data->hw_addr[1] = hw_addr[0];
 869                 data->hw_addr[2] = hw_addr[3];
 870                 data->hw_addr[3] = hw_addr[2];
 871                 data->hw_addr[4] = hw_addr[5];
 872                 data->hw_addr[5] = hw_addr[4];
 873         } else {
 874                 iwl_set_hw_address_family_8000(trans, cfg, data,
 875                                                mac_override, nvm_hw);
 876         }
 877
 878         if (!is_valid_ether_addr(data->hw_addr)) {
 879                 IWL_ERR(trans, "no valid mac address was found\n");
 880                 return -EINVAL;
 881         }
 882
 883         IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
 884
 885         return 0;
 886 }
 887
 888 static bool
 889 iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg,
 890                         const __be16 *nvm_hw)
 891 {
 892         /*
 893          * Workaround a bug in Indonesia SKUs where the regulatory in
 894          * some 7000-family OTPs erroneously allow wide channels in
 895          * 5GHz.  To check for Indonesia, we take the SKU value from
 896          * bits 1-4 in the subsystem ID and check if it is either 5 or
 897          * 9.  In those cases, we need to force-disable wide channels
 898          * in 5GHz otherwise the FW will throw a sysassert when we try
 899          * to use them.
 900          */
 901         if (cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 902                 /*
 903                  * Unlike the other sections in the NVM, the hw
 904                  * section uses big-endian.
 905                  */
 906                 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
 907                 u8 sku = (subsystem_id & 0x1e) >> 1;
 908
 909                 if (sku == 5 || sku == 9) {
 910                         IWL_DEBUG_EEPROM(dev,
 911                                          "disabling wide channels in 5GHz (0x%0x %d)\n",
 912                                          subsystem_id, sku);
 913                         return true;
 914                 }
 915         }
 916
 917         return false;
 918 }
 919
 920 struct iwl_nvm_data *
 921 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
 922                    const __be16 *nvm_hw, const __le16 *nvm_sw,
 923                    const __le16 *nvm_calib, const __le16 *regulatory,
 924                    const __le16 *mac_override, const __le16 *phy_sku,
 925                    u8 tx_chains, u8 rx_chains, bool lar_fw_supported)
 926 {
 927         struct device *dev = trans->dev;
 928         struct iwl_nvm_data *data;
 929         bool lar_enabled;
 930         u32 sku, radio_cfg;
 931         u32 sbands_flags = 0;
 932         u16 lar_config;
 933         const __le16 *ch_section;
 934
 935         if (cfg->nvm_type != IWL_NVM_EXT)
 936                 data = kzalloc(struct_size(data, channels,
 937                                            IWL_NVM_NUM_CHANNELS),
 938                                            GFP_KERNEL);
 939         else
 940                 data = kzalloc(struct_size(data, channels,
 941                                            IWL_NVM_NUM_CHANNELS_EXT),
 942                                            GFP_KERNEL);
 943         if (!data)
 944                 return NULL;
 945
 946         data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
 947
 948         radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
 949         iwl_set_radio_cfg(cfg, data, radio_cfg);
 950         if (data->valid_tx_ant)
 951                 tx_chains &= data->valid_tx_ant;
 952         if (data->valid_rx_ant)
 953                 rx_chains &= data->valid_rx_ant;
 954
 955         sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
 956         data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
 957         data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
 958         data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
 959         if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
 960                 data->sku_cap_11n_enable = false;
 961         data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
 962                                     (sku & NVM_SKU_CAP_11AC_ENABLE);
 963         data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
 964
 965         data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
 966
 967         if (cfg->nvm_type != IWL_NVM_EXT) {
 968                 /* Checking for required sections */
 969                 if (!nvm_calib) {
 970                         IWL_ERR(trans,
 971                                 "Can't parse empty Calib NVM sections\n");
 972                         kfree(data);
 973                         return NULL;
 974                 }
 975
 976                 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
 977                              &regulatory[NVM_CHANNELS_SDP] :
 978                              &nvm_sw[NVM_CHANNELS];
 979
 980                 /* in family 8000 Xtal calibration values moved to OTP */
 981                 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
 982                 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
 983                 lar_enabled = true;
 984         } else {
 985                 u16 lar_offset = data->nvm_version < 0xE39 ?
 986                                  NVM_LAR_OFFSET_OLD :
 987                                  NVM_LAR_OFFSET;
 988
 989                 lar_config = le16_to_cpup(regulatory + lar_offset);
 990                 data->lar_enabled = !!(lar_config &
 991                                        NVM_LAR_ENABLED);
 992                 lar_enabled = data->lar_enabled;
 993                 ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
 994         }
 995
 996         /* If no valid mac address was found - bail out */
 997         if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
 998                 kfree(data);
 999                 return NULL;
1000         }
1001
1002         if (lar_fw_supported && lar_enabled)
1003                 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1004
1005         if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw))
1006                 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1007
1008         iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains,
1009                         sbands_flags);
1010         data->calib_version = 255;
1011
1012         return data;
1013 }
1014 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1015
1016 static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
1017                                        int ch_idx, u16 nvm_flags,
1018                                        const struct iwl_cfg *cfg)
1019 {
1020         u32 flags = NL80211_RRF_NO_HT40;
1021         u32 last_5ghz_ht = LAST_5GHZ_HT;
1022
1023         if (cfg->nvm_type == IWL_NVM_EXT)
1024                 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
1025
1026         if (ch_idx < NUM_2GHZ_CHANNELS &&
1027             (nvm_flags & NVM_CHANNEL_40MHZ)) {
1028                 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1029                         flags &= ~NL80211_RRF_NO_HT40PLUS;
1030                 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1031                         flags &= ~NL80211_RRF_NO_HT40MINUS;
1032         } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
1033                    (nvm_flags & NVM_CHANNEL_40MHZ)) {
1034                 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1035                         flags &= ~NL80211_RRF_NO_HT40PLUS;
1036                 else
1037                         flags &= ~NL80211_RRF_NO_HT40MINUS;
1038         }
1039
1040         if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1041                 flags |= NL80211_RRF_NO_80MHZ;
1042         if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1043                 flags |= NL80211_RRF_NO_160MHZ;
1044
1045         if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1046                 flags |= NL80211_RRF_NO_IR;
1047
1048         if (nvm_flags & NVM_CHANNEL_RADAR)
1049                 flags |= NL80211_RRF_DFS;
1050
1051         if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1052                 flags |= NL80211_RRF_NO_OUTDOOR;
1053
1054         /* Set the GO concurrent flag only in case that NO_IR is set.
1055          * Otherwise it is meaningless
1056          */
1057         if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1058             (flags & NL80211_RRF_NO_IR))
1059                 flags |= NL80211_RRF_GO_CONCURRENT;
1060
1061         return flags;
1062 }
1063
1064 struct regdb_ptrs {
1065         struct ieee80211_wmm_rule *rule;
1066         u32 token;
1067 };
1068
1069 struct ieee80211_regdomain *
1070 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1071                        int num_of_ch, __le32 *channels, u16 fw_mcc,
1072                        u16 geo_info)
1073 {
1074         int ch_idx;
1075         u16 ch_flags;
1076         u32 reg_rule_flags, prev_reg_rule_flags = 0;
1077         const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ?
1078                              iwl_ext_nvm_channels : iwl_nvm_channels;
1079         struct ieee80211_regdomain *regd, *copy_rd;
1080         int size_of_regd, regd_to_copy;
1081         struct ieee80211_reg_rule *rule;
1082         struct regdb_ptrs *regdb_ptrs;
1083         enum nl80211_band band;
1084         int center_freq, prev_center_freq = 0;
1085         int valid_rules = 0;
1086         bool new_rule;
1087         int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ?
1088                          IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS;
1089
1090         if (WARN_ON(num_of_ch > max_num_ch))
1091                 num_of_ch = max_num_ch;
1092
1093         if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1094                 return ERR_PTR(-EINVAL);
1095
1096         IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1097                       num_of_ch);
1098
1099         /* build a regdomain rule for every valid channel */
1100         size_of_regd =
1101                 sizeof(struct ieee80211_regdomain) +
1102                 num_of_ch * sizeof(struct ieee80211_reg_rule);
1103
1104         regd = kzalloc(size_of_regd, GFP_KERNEL);
1105         if (!regd)
1106                 return ERR_PTR(-ENOMEM);
1107
1108         regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL);
1109         if (!regdb_ptrs) {
1110                 copy_rd = ERR_PTR(-ENOMEM);
1111                 goto out;
1112         }
1113
1114         /* set alpha2 from FW. */
1115         regd->alpha2[0] = fw_mcc >> 8;
1116         regd->alpha2[1] = fw_mcc & 0xff;
1117
1118         for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1119                 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1120                 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
1121                        NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1122                 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1123                                                              band);
1124                 new_rule = false;
1125
1126                 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1127                         iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1128                                                     nvm_chan[ch_idx], ch_flags);
1129                         continue;
1130                 }
1131
1132                 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1133                                                              ch_flags, cfg);
1134
1135                 /* we can't continue the same rule */
1136                 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1137                     center_freq - prev_center_freq > 20) {
1138                         valid_rules++;
1139                         new_rule = true;
1140                 }
1141
1142                 rule = &regd->reg_rules[valid_rules - 1];
1143
1144                 if (new_rule)
1145                         rule->freq_range.start_freq_khz =
1146                                                 MHZ_TO_KHZ(center_freq - 10);
1147
1148                 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1149
1150                 /* this doesn't matter - not used by FW */
1151                 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1152                 rule->power_rule.max_eirp =
1153                         DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1154
1155                 rule->flags = reg_rule_flags;
1156
1157                 /* rely on auto-calculation to merge BW of contiguous chans */
1158                 rule->flags |= NL80211_RRF_AUTO_BW;
1159                 rule->freq_range.max_bandwidth_khz = 0;
1160
1161                 prev_center_freq = center_freq;
1162                 prev_reg_rule_flags = reg_rule_flags;
1163
1164                 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1165                                             nvm_chan[ch_idx], ch_flags);
1166
1167                 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1168                     band == NL80211_BAND_2GHZ)
1169                         continue;
1170
1171                 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1172         }
1173
1174         regd->n_reg_rules = valid_rules;
1175
1176         /*
1177          * Narrow down regdom for unused regulatory rules to prevent hole
1178          * between reg rules to wmm rules.
1179          */
1180         regd_to_copy = sizeof(struct ieee80211_regdomain) +
1181                 valid_rules * sizeof(struct ieee80211_reg_rule);
1182
1183         copy_rd = kmemdup(regd, regd_to_copy, GFP_KERNEL);
1184         if (!copy_rd) {
1185                 copy_rd = ERR_PTR(-ENOMEM);
1186                 goto out;
1187         }
1188
1189 out:
1190         kfree(regdb_ptrs);
1191         kfree(regd);
1192         return copy_rd;
1193 }
1194 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1195
1196 #define IWL_MAX_NVM_SECTION_SIZE        0x1b58
1197 #define IWL_MAX_EXT_NVM_SECTION_SIZE    0x1ffc
1198 #define MAX_NVM_FILE_LEN        16384
1199
1200 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1201                     unsigned int len)
1202 {
1203 #define IWL_4165_DEVICE_ID      0x5501
1204 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1205
1206         if (section == NVM_SECTION_TYPE_PHY_SKU &&
1207             hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1208             (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1209                 /* OTP 0x52 bug work around: it's a 1x1 device */
1210                 data[3] = ANT_B | (ANT_B << 4);
1211 }
1212 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1213
1214 /*
1215  * Reads external NVM from a file into mvm->nvm_sections
1216  *
1217  * HOW TO CREATE THE NVM FILE FORMAT:
1218  * ------------------------------
1219  * 1. create hex file, format:
1220  *      3800 -> header
1221  *      0000 -> header
1222  *      5a40 -> data
1223  *
1224  *   rev - 6 bit (word1)
1225  *   len - 10 bit (word1)
1226  *   id - 4 bit (word2)
1227  *   rsv - 12 bit (word2)
1228  *
1229  * 2. flip 8bits with 8 bits per line to get the right NVM file format
1230  *
1231  * 3. create binary file from the hex file
1232  *
1233  * 4. save as "iNVM_xxx.bin" under /lib/firmware
1234  */
1235 int iwl_read_external_nvm(struct iwl_trans *trans,
1236                           const char *nvm_file_name,
1237                           struct iwl_nvm_section *nvm_sections)
1238 {
1239         int ret, section_size;
1240         u16 section_id;
1241         const struct firmware *fw_entry;
1242         const struct {
1243                 __le16 word1;
1244                 __le16 word2;
1245                 u8 data[];
1246         } *file_sec;
1247         const u8 *eof;
1248         u8 *temp;
1249         int max_section_size;
1250         const __le32 *dword_buff;
1251
1252 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1253 #define NVM_WORD2_ID(x) (x >> 12)
1254 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1255 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1256 #define NVM_HEADER_0    (0x2A504C54)
1257 #define NVM_HEADER_1    (0x4E564D2A)
1258 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1259
1260         IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1261
1262         /* Maximal size depends on NVM version */
1263         if (trans->cfg->nvm_type != IWL_NVM_EXT)
1264                 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1265         else
1266                 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1267
1268         /*
1269          * Obtain NVM image via request_firmware. Since we already used
1270          * request_firmware_nowait() for the firmware binary load and only
1271          * get here after that we assume the NVM request can be satisfied
1272          * synchronously.
1273          */
1274         ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1275         if (ret) {
1276                 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1277                         nvm_file_name, ret);
1278                 return ret;
1279         }
1280
1281         IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1282                  nvm_file_name, fw_entry->size);
1283
1284         if (fw_entry->size > MAX_NVM_FILE_LEN) {
1285                 IWL_ERR(trans, "NVM file too large\n");
1286                 ret = -EINVAL;
1287                 goto out;
1288         }
1289
1290         eof = fw_entry->data + fw_entry->size;
1291         dword_buff = (__le32 *)fw_entry->data;
1292
1293         /* some NVM file will contain a header.
1294          * The header is identified by 2 dwords header as follow:
1295          * dword[0] = 0x2A504C54
1296          * dword[1] = 0x4E564D2A
1297          *
1298          * This header must be skipped when providing the NVM data to the FW.
1299          */
1300         if (fw_entry->size > NVM_HEADER_SIZE &&
1301             dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1302             dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1303                 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1304                 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1305                 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1306                          le32_to_cpu(dword_buff[3]));
1307
1308                 /* nvm file validation, dword_buff[2] holds the file version */
1309                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1310                     CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1311                     le32_to_cpu(dword_buff[2]) < 0xE4A) {
1312                         ret = -EFAULT;
1313                         goto out;
1314                 }
1315         } else {
1316                 file_sec = (void *)fw_entry->data;
1317         }
1318
1319         while (true) {
1320                 if (file_sec->data > eof) {
1321                         IWL_ERR(trans,
1322                                 "ERROR - NVM file too short for section header\n");
1323                         ret = -EINVAL;
1324                         break;
1325                 }
1326
1327                 /* check for EOF marker */
1328                 if (!file_sec->word1 && !file_sec->word2) {
1329                         ret = 0;
1330                         break;
1331                 }
1332
1333                 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1334                         section_size =
1335                                 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1336                         section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1337                 } else {
1338                         section_size = 2 * EXT_NVM_WORD2_LEN(
1339                                                 le16_to_cpu(file_sec->word2));
1340                         section_id = EXT_NVM_WORD1_ID(
1341                                                 le16_to_cpu(file_sec->word1));
1342                 }
1343
1344                 if (section_size > max_section_size) {
1345                         IWL_ERR(trans, "ERROR - section too large (%d)\n",
1346                                 section_size);
1347                         ret = -EINVAL;
1348                         break;
1349                 }
1350
1351                 if (!section_size) {
1352                         IWL_ERR(trans, "ERROR - section empty\n");
1353                         ret = -EINVAL;
1354                         break;
1355                 }
1356
1357                 if (file_sec->data + section_size > eof) {
1358                         IWL_ERR(trans,
1359                                 "ERROR - NVM file too short for section (%d bytes)\n",
1360                                 section_size);
1361                         ret = -EINVAL;
1362                         break;
1363                 }
1364
1365                 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1366                          "Invalid NVM section ID %d\n", section_id)) {
1367                         ret = -EINVAL;
1368                         break;
1369                 }
1370
1371                 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1372                 if (!temp) {
1373                         ret = -ENOMEM;
1374                         break;
1375                 }
1376
1377                 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1378
1379                 kfree(nvm_sections[section_id].data);
1380                 nvm_sections[section_id].data = temp;
1381                 nvm_sections[section_id].length = section_size;
1382
1383                 /* advance to the next section */
1384                 file_sec = (void *)(file_sec->data + section_size);
1385         }
1386 out:
1387         release_firmware(fw_entry);
1388         return ret;
1389 }
1390 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1391
1392 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1393                                  const struct iwl_fw *fw)
1394 {
1395         struct iwl_nvm_get_info cmd = {};
1396         struct iwl_nvm_get_info_rsp *rsp;
1397         struct iwl_nvm_data *nvm;
1398         struct iwl_host_cmd hcmd = {
1399                 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1400                 .data = { &cmd, },
1401                 .len = { sizeof(cmd) },
1402                 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1403         };
1404         int  ret;
1405         bool lar_fw_supported = !iwlwifi_mod_params.lar_disable &&
1406                                 fw_has_capa(&fw->ucode_capa,
1407                                             IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
1408         bool empty_otp;
1409         u32 mac_flags;
1410         u32 sbands_flags = 0;
1411
1412         ret = iwl_trans_send_cmd(trans, &hcmd);
1413         if (ret)
1414                 return ERR_PTR(ret);
1415
1416         if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp),
1417                  "Invalid payload len in NVM response from FW %d",
1418                  iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1419                 ret = -EINVAL;
1420                 goto out;
1421         }
1422
1423         rsp = (void *)hcmd.resp_pkt->data;
1424         empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1425                        NVM_GENERAL_FLAGS_EMPTY_OTP);
1426         if (empty_otp)
1427                 IWL_INFO(trans, "OTP is empty\n");
1428
1429         nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1430         if (!nvm) {
1431                 ret = -ENOMEM;
1432                 goto out;
1433         }
1434
1435         iwl_set_hw_address_from_csr(trans, nvm);
1436         /* TODO: if platform NVM has MAC address - override it here */
1437
1438         if (!is_valid_ether_addr(nvm->hw_addr)) {
1439                 IWL_ERR(trans, "no valid mac address was found\n");
1440                 ret = -EINVAL;
1441                 goto err_free;
1442         }
1443
1444         IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1445
1446         /* Initialize general data */
1447         nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1448         nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1449         if (nvm->n_hw_addrs == 0)
1450                 IWL_WARN(trans,
1451                          "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1452                          empty_otp);
1453
1454         /* Initialize MAC sku data */
1455         mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1456         nvm->sku_cap_11ac_enable =
1457                 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1458         nvm->sku_cap_11n_enable =
1459                 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1460         nvm->sku_cap_11ax_enable =
1461                 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1462         nvm->sku_cap_band_24ghz_enable =
1463                 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1464         nvm->sku_cap_band_52ghz_enable =
1465                 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1466         nvm->sku_cap_mimo_disabled =
1467                 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1468
1469         /* Initialize PHY sku data */
1470         nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1471         nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1472
1473         if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) {
1474                 nvm->lar_enabled = true;
1475                 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1476         }
1477
1478         iwl_init_sbands(trans->dev, trans->cfg, nvm,
1479                         rsp->regulatory.channel_profile,
1480                         nvm->valid_tx_ant & fw->valid_tx_ant,
1481                         nvm->valid_rx_ant & fw->valid_rx_ant,
1482                         sbands_flags);
1483
1484         iwl_free_resp(&hcmd);
1485         return nvm;
1486
1487 err_free:
1488         kfree(nvm);
1489 out:
1490         iwl_free_resp(&hcmd);
1491         return ERR_PTR(ret);
1492 }
1493 IWL_EXPORT_SYMBOL(iwl_get_nvm);