1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
33 * Copyright(c) 2018 - 2019 Intel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
66 * CSR (control and status registers)
68 * CSR registers are mapped directly into PCI bus space, and are accessible
69 * whenever platform supplies power to device, even when device is in
70 * low power states due to driver-invoked device resets
71 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
73 * Use iwl_write32() and iwl_read32() family to access these registers;
74 * these provide simple PCI bus access, without waking up the MAC.
75 * Do not use iwl_write_direct32() family for these registers;
76 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
77 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
80 * NOTE: Device does need to be awake in order to read this memory
81 * via CSR_EEPROM and CSR_OTP registers
83 #define CSR_BASE (0x000)
85 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
87 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
88 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
89 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
90 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
91 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
92 #define CSR_GP_CNTRL (CSR_BASE+0x024)
94 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
95 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
98 * Hardware revision info
101 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
103 * 1-0: "Dash" (-) value, as in A-1, etc.
105 #define CSR_HW_REV (CSR_BASE+0x028)
108 * RF ID revision info
110 * 31:24: Reserved (set to 0x0)
112 * 11:8: Step (A - 0x0, B - 0x1, etc)
116 #define CSR_HW_RF_ID (CSR_BASE+0x09c)
119 * EEPROM and OTP (one-time-programmable) memory reads
121 * NOTE: Device must be awake, initialized via apm_ops.init(),
124 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
125 #define CSR_EEPROM_GP (CSR_BASE+0x030)
126 #define CSR_OTP_GP_REG (CSR_BASE+0x034)
128 #define CSR_GIO_REG (CSR_BASE+0x03C)
129 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
130 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
133 * UCODE-DRIVER GP (general purpose) mailbox registers.
134 * SET/CLR registers set/clear bit(s) if "1" is written.
136 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
137 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
138 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
139 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
141 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
143 #define CSR_LED_REG (CSR_BASE+0x094)
144 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
145 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
146 #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
147 #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
148 #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
150 /* LTR control (since IWL_DEVICE_FAMILY_22000) */
151 #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4)
152 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000
153 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000
154 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000
155 #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000
156 #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00
157 #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff
158 #define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2
160 /* GIO Chicken Bits (PCI Express bus link power management) */
161 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
163 /* host chicken bits */
164 #define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
165 #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19)
167 /* Analog phase-lock-loop configuration */
168 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
171 * CSR HW resources monitor registers
173 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
174 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
175 #define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
178 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
179 * "step" determines CCK backoff for txpower calculation.
180 * See also CSR_HW_REV register.
182 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
183 * 1-0: "Dash" (-) value, as in C-1, etc.
185 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
187 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
188 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
190 /* Bits for CSR_HW_IF_CONFIG_REG */
191 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
192 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
193 #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080)
194 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
195 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
196 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
197 #define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200)
198 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
199 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
200 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
202 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
203 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
204 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
205 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
206 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
207 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
209 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
210 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
211 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
212 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
213 #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
214 #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
215 #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
217 #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
219 #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
220 #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
222 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
223 * acknowledged (reset) by host writing "1" to flagged bits. */
224 #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
225 #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
226 #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
227 #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
228 #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
229 #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
230 #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
231 #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
232 #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
233 #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
234 #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
236 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
237 CSR_INT_BIT_HW_ERR | \
238 CSR_INT_BIT_FH_TX | \
239 CSR_INT_BIT_SW_ERR | \
240 CSR_INT_BIT_RF_KILL | \
241 CSR_INT_BIT_SW_RX | \
242 CSR_INT_BIT_WAKEUP | \
243 CSR_INT_BIT_ALIVE | \
244 CSR_INT_BIT_RX_PERIODIC)
246 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
247 #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
248 #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
249 #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
250 #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
251 #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
252 #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
254 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
255 CSR_FH_INT_BIT_RX_CHNL1 | \
256 CSR_FH_INT_BIT_RX_CHNL0)
258 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
259 CSR_FH_INT_BIT_TX_CHNL0)
262 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
263 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
264 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
267 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
268 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
269 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
270 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
271 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
272 #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
275 * GP (general purpose) CONTROL REGISTER
278 * Indicates state of (platform's) hardware RF-Kill switch
279 * 26-24: POWER_SAVE_TYPE
280 * Indicates current power-saving mode:
281 * 000 -- No power saving
282 * 001 -- MAC power-down
283 * 010 -- PHY (radio) power-down
285 * 10: XTAL ON request
287 * Indicates current system configuration, reflecting pins on chip
288 * as forced high/low by device circuit board.
290 * Indicates MAC is entering a power-saving sleep power-down.
291 * Not a good time to access device-internal resources.
293 * Host sets this to request and maintain MAC wakeup, to allow host
294 * access to device-internal resources. Host must wait for
295 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
298 * Host sets this to put device into fully operational D0 power mode.
299 * Host resets this after SW_RESET to put device into low power mode.
301 * Indicates MAC (ucode processor, etc.) is powered up and can run.
302 * Internal resources are accessible.
303 * NOTE: This does not indicate that the processor is actually running.
304 * NOTE: This does not indicate that device has completed
305 * init or post-power-down restore of internal SRAM memory.
306 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
307 * SRAM is restored and uCode is in normal operation mode.
308 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
309 * do not need to save/restore it.
310 * NOTE: After device reset, this bit remains "0" until host sets
313 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
314 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
315 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
316 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
317 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
319 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
321 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
322 #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
323 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
327 #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
328 #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
329 #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4)
332 #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
333 #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
334 #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
335 #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
347 #define CSR_HW_REV_TYPE_MSK (0x000FFF0)
348 #define CSR_HW_REV_TYPE_5300 (0x0000020)
349 #define CSR_HW_REV_TYPE_5350 (0x0000030)
350 #define CSR_HW_REV_TYPE_5100 (0x0000050)
351 #define CSR_HW_REV_TYPE_5150 (0x0000040)
352 #define CSR_HW_REV_TYPE_1000 (0x0000060)
353 #define CSR_HW_REV_TYPE_6x00 (0x0000070)
354 #define CSR_HW_REV_TYPE_6x50 (0x0000080)
355 #define CSR_HW_REV_TYPE_6150 (0x0000084)
356 #define CSR_HW_REV_TYPE_6x05 (0x00000B0)
357 #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
358 #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
359 #define CSR_HW_REV_TYPE_2x30 (0x00000C0)
360 #define CSR_HW_REV_TYPE_2x00 (0x0000100)
361 #define CSR_HW_REV_TYPE_105 (0x0000110)
362 #define CSR_HW_REV_TYPE_135 (0x0000120)
363 #define CSR_HW_REV_TYPE_7265D (0x0000210)
364 #define CSR_HW_REV_TYPE_NONE (0x00001F0)
365 #define CSR_HW_REV_TYPE_QNJ (0x0000360)
366 #define CSR_HW_REV_TYPE_QNJ_B0 (0x0000364)
367 #define CSR_HW_REV_TYPE_QU_B0 (0x0000334)
368 #define CSR_HW_REV_TYPE_QU_C0 (0x0000338)
369 #define CSR_HW_REV_TYPE_QUZ (0x0000354)
370 #define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
371 #define CSR_HW_REV_TYPE_SO (0x0000370)
372 #define CSR_HW_REV_TYPE_TY (0x0000420)
375 #define CSR_HW_RF_ID_TYPE_JF (0x00105100)
376 #define CSR_HW_RF_ID_TYPE_HR (0x0010A000)
377 #define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100)
378 #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00)
379 #define CSR_HW_RF_ID_TYPE_GF (0x0010D000)
380 #define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000)
383 #define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF)
385 /* HW_RF CHIP STEP */
386 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
389 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
390 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
391 #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
392 #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
395 #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
396 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
397 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
398 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
399 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
400 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
402 /* One-time-programmable memory general purpose reg */
403 #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
404 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
405 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
406 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
409 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
410 #define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
411 #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
412 #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
413 #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
417 #define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002)
420 * UCODE-DRIVER GP (general purpose) mailbox register 1
421 * Host driver and uCode write and/or read this register to communicate with
425 * Host sets this to request permanent halt of uCode, same as
426 * sending CARD_STATE command with "halt" bit set.
428 * Host sets this to request exit from CT_KILL state, i.e. host thinks
429 * device temperature is low enough to continue normal operation.
431 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
432 * to release uCode to clear all Tx and command queues, enter
433 * unassociated mode, and power down.
434 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
436 * Host sets this when issuing CARD_STATE command to request
439 * uCode sets this when preparing a power-saving power-down.
440 * uCode resets this when power-up is complete and SRAM is sane.
441 * NOTE: device saves internal SRAM data to host when powering down,
442 * and must restore this data after powering back up.
443 * MAC_SLEEP is the best indication that restore is complete.
444 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
445 * do not need to save/restore it.
447 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
448 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
449 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
450 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
451 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
454 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
455 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
456 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
457 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
458 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
459 #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
461 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
463 /* GIO Chicken Bits (PCI Express bus link power management) */
464 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
465 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
468 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
469 #define CSR_LED_REG_TURN_ON (0x60)
470 #define CSR_LED_REG_TURN_OFF (0x20)
473 #define CSR50_ANA_PLL_CFG_VAL (0x00880300)
476 #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
479 #define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
480 #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
481 #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
484 * SHR target access (Shared block memory space)
486 * Shared internal registers can be accessed directly from PCI bus through SHR
487 * arbiter without need for the MAC HW to be powered up. This is possible due to
488 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
489 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
491 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
492 * need not be powered up so no "grab inc access" is required.
496 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
497 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
498 * first, write to the control register:
499 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
500 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
501 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
503 * To write the register, first, write to the data register
504 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
505 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
506 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
508 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
509 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
512 * HBUS (Host-side Bus)
514 * HBUS registers are mapped directly into PCI bus space, but are used
515 * to indirectly access device's internal memory or registers that
516 * may be powered-down.
518 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
519 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
520 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
521 * internal resources.
523 * Do not use iwl_write32()/iwl_read32() family to access these registers;
524 * these provide only simple PCI bus access, without waking up the MAC.
526 #define HBUS_BASE (0x400)
529 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
530 * structures, error log, event log, verifying uCode load).
531 * First write to address register, then read from or write to data register
532 * to complete the job. Once the address register is set up, accesses to
533 * data registers auto-increment the address by one dword.
534 * Bit usage for address registers (read or write):
535 * 0-31: memory address within device
537 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
538 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
539 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
540 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
542 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
543 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
544 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
547 * Registers for accessing device's internal peripheral registers
548 * (e.g. SCD, BSM, etc.). First write to address register,
549 * then read from or write to data register to complete the job.
550 * Bit usage for address registers (read or write):
551 * 0-15: register address (offset) within device
552 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
554 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
555 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
556 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
557 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
559 /* Used to enable DBGM */
560 #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
563 * Per-Tx-queue write pointer (index, really!)
564 * Indicates index to next TFD that driver will fill (1 past latest filled).
566 * 0-7: queue write index
567 * 11-8: queue selector
569 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
571 /**********************************************************
573 **********************************************************/
575 * host interrupt timeout value
576 * used with setting interrupt coalescing timer
577 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
579 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
581 #define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
582 #define IWL_HOST_INT_TIMEOUT_DEF (0x40)
583 #define IWL_HOST_INT_TIMEOUT_MIN (0x0)
584 #define IWL_HOST_INT_OPER_MODE BIT(31)
586 /*****************************************************************************
587 * 7000/3000 series SHR DTS addresses *
588 *****************************************************************************/
590 /* Diode Results Register Structure: */
592 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
593 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
594 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
595 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
596 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
597 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
598 /* Those are the masks INSIDE the flags bit-field: */
599 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
600 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
601 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
602 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
605 /*****************************************************************************
606 * MSIX related registers *
607 *****************************************************************************/
609 #define CSR_MSIX_BASE (0x2000)
610 #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
611 #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
612 #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
613 #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
614 #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
615 #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
616 #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
617 #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
618 #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
619 #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
621 #define MSIX_FH_INT_CAUSES_Q(q) (q)
624 * Causes for the FH register interrupts
626 enum msix_fh_int_causes {
627 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
628 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
629 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
630 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
631 MSIX_FH_INT_CAUSES_S2D = BIT(19),
632 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
636 * Causes for the HW register interrupts
638 enum msix_hw_int_causes {
639 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
640 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
641 MSIX_HW_INT_CAUSES_REG_IML = BIT(2),
642 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
643 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
644 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
645 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
646 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
647 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
648 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
649 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
652 #define MSIX_MIN_INTERRUPT_VECTORS 2
653 #define MSIX_AUTO_CLEAR_CAUSE 0
654 #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
656 /*****************************************************************************
657 * HW address related registers *
658 *****************************************************************************/
660 #define CSR_ADDR_BASE (0x380)
661 #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE)
662 #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4)
663 #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8)
664 #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC)
666 #endif /* !__iwl_csr_h__ */