2 * Copyright (c) 2014 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/list.h>
19 #include <linux/ssb/ssb_regs.h>
20 #include <linux/bcma/bcma.h>
21 #include <linux/bcma/bcma_regs.h>
25 #include <brcm_hw_ids.h>
26 #include <brcmu_utils.h>
27 #include <chipcommon.h>
31 /* SOC Interconnect types (aka chip types) */
35 /* PL-368 DMP definitions */
36 #define DMP_DESC_TYPE_MSK 0x0000000F
37 #define DMP_DESC_EMPTY 0x00000000
38 #define DMP_DESC_VALID 0x00000001
39 #define DMP_DESC_COMPONENT 0x00000001
40 #define DMP_DESC_MASTER_PORT 0x00000003
41 #define DMP_DESC_ADDRESS 0x00000005
42 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
43 #define DMP_DESC_EOT 0x0000000F
45 #define DMP_COMP_DESIGNER 0xFFF00000
46 #define DMP_COMP_DESIGNER_S 20
47 #define DMP_COMP_PARTNUM 0x000FFF00
48 #define DMP_COMP_PARTNUM_S 8
49 #define DMP_COMP_CLASS 0x000000F0
50 #define DMP_COMP_CLASS_S 4
51 #define DMP_COMP_REVISION 0xFF000000
52 #define DMP_COMP_REVISION_S 24
53 #define DMP_COMP_NUM_SWRAP 0x00F80000
54 #define DMP_COMP_NUM_SWRAP_S 19
55 #define DMP_COMP_NUM_MWRAP 0x0007C000
56 #define DMP_COMP_NUM_MWRAP_S 14
57 #define DMP_COMP_NUM_SPORT 0x00003E00
58 #define DMP_COMP_NUM_SPORT_S 9
59 #define DMP_COMP_NUM_MPORT 0x000001F0
60 #define DMP_COMP_NUM_MPORT_S 4
62 #define DMP_MASTER_PORT_UID 0x0000FF00
63 #define DMP_MASTER_PORT_UID_S 8
64 #define DMP_MASTER_PORT_NUM 0x000000F0
65 #define DMP_MASTER_PORT_NUM_S 4
67 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
68 #define DMP_SLAVE_ADDR_BASE_S 12
69 #define DMP_SLAVE_PORT_NUM 0x00000F00
70 #define DMP_SLAVE_PORT_NUM_S 8
71 #define DMP_SLAVE_TYPE 0x000000C0
72 #define DMP_SLAVE_TYPE_S 6
73 #define DMP_SLAVE_TYPE_SLAVE 0
74 #define DMP_SLAVE_TYPE_BRIDGE 1
75 #define DMP_SLAVE_TYPE_SWRAP 2
76 #define DMP_SLAVE_TYPE_MWRAP 3
77 #define DMP_SLAVE_SIZE_TYPE 0x00000030
78 #define DMP_SLAVE_SIZE_TYPE_S 4
79 #define DMP_SLAVE_SIZE_4K 0
80 #define DMP_SLAVE_SIZE_8K 1
81 #define DMP_SLAVE_SIZE_16K 2
82 #define DMP_SLAVE_SIZE_DESC 3
85 #define CIB_REV_MASK 0xff000000
86 #define CIB_REV_SHIFT 24
88 /* ARM CR4 core specific control flag bits */
89 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
91 /* D11 core specific control flag bits */
92 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
93 #define D11_BCMA_IOCTL_PHYRESET 0x0008
95 /* chip core base & ramsize */
97 /* SDIO device core, ID 0x829 */
98 #define BCM4329_CORE_BUS_BASE 0x18011000
99 /* internal memory core, ID 0x80e */
100 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
101 /* ARM Cortex M3 core, ID 0x82a */
102 #define BCM4329_CORE_ARM_BASE 0x18002000
104 /* Max possibly supported memory size (limited by IO mapped memory) */
105 #define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
107 #define CORE_SB(base, field) \
108 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
109 #define SBCOREREV(sbidh) \
110 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
111 ((sbidh) & SSB_IDHIGH_RCLO))
115 u32 sbipsflag; /* initiator port ocp slave flag */
117 u32 sbtpsflag; /* target port ocp slave flag */
119 u32 sbtmerrloga; /* (sonics >= 2.3) */
121 u32 sbtmerrlog; /* (sonics >= 2.3) */
123 u32 sbadmatch3; /* address match3 */
125 u32 sbadmatch2; /* address match2 */
127 u32 sbadmatch1; /* address match1 */
129 u32 sbimstate; /* initiator agent state */
130 u32 sbintvec; /* interrupt mask */
131 u32 sbtmstatelow; /* target state */
132 u32 sbtmstatehigh; /* target state */
133 u32 sbbwa0; /* bandwidth allocation table0 */
135 u32 sbimconfiglow; /* initiator configuration */
136 u32 sbimconfighigh; /* initiator configuration */
137 u32 sbadmatch0; /* address match0 */
139 u32 sbtmconfiglow; /* target configuration */
140 u32 sbtmconfighigh; /* target configuration */
141 u32 sbbconfig; /* broadcast configuration */
143 u32 sbbstate; /* broadcast state */
145 u32 sbactcnfg; /* activate configuration */
147 u32 sbflagst; /* current sbflags */
149 u32 sbidlow; /* identification */
150 u32 sbidhigh; /* identification */
153 /* bankidx and bankinfo reg defines corerev >= 8 */
154 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
155 #define SOCRAM_BANKINFO_SZMASK 0x0000007f
156 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100
158 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
159 /* socram bankinfo memtype */
160 #define SOCRAM_MEMTYPE_RAM 0
161 #define SOCRAM_MEMTYPE_R0M 1
162 #define SOCRAM_MEMTYPE_DEVRAM 2
164 #define SOCRAM_BANKINFO_SZBASE 8192
165 #define SRCI_LSS_MASK 0x00f00000
166 #define SRCI_LSS_SHIFT 20
167 #define SRCI_SRNB_MASK 0xf0
168 #define SRCI_SRNB_SHIFT 4
169 #define SRCI_SRBSZ_MASK 0xf
170 #define SRCI_SRBSZ_SHIFT 0
171 #define SR_BSZ_BASE 14
173 struct sbsocramregs {
181 u32 errlogstatus; /* rev 6 */
182 u32 errlogaddr; /* rev 6 */
183 /* used for patching rev 3 & 5 */
185 u32 cambankstandbyctrl;
186 u32 cambankpatchctrl;
187 u32 cambankpatchtblbaseaddr;
192 u32 bankinfo; /* corev 8 */
197 u32 extmemparityerrdata;
198 u32 extmemparityerrcnt;
199 u32 extmemwrctrlandsize;
202 u32 pwrctl; /* corerev >= 2 */
204 u32 sr_control; /* corerev >= 15 */
205 u32 sr_status; /* corerev >= 15 */
206 u32 sr_address; /* corerev >= 15 */
207 u32 sr_data; /* corerev >= 15 */
210 #define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
211 #define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
213 #define ARMCR4_CAP (0x04)
214 #define ARMCR4_BANKIDX (0x40)
215 #define ARMCR4_BANKINFO (0x44)
216 #define ARMCR4_BANKPDA (0x4C)
218 #define ARMCR4_TCBBNB_MASK 0xf0
219 #define ARMCR4_TCBBNB_SHIFT 4
220 #define ARMCR4_TCBANB_MASK 0xf
221 #define ARMCR4_TCBANB_SHIFT 0
223 #define ARMCR4_BSZ_MASK 0x3f
224 #define ARMCR4_BSZ_MULT 8192
226 struct brcmf_core_priv {
227 struct brcmf_core pub;
229 struct list_head list;
230 struct brcmf_chip_priv *chip;
233 struct brcmf_chip_priv {
234 struct brcmf_chip pub;
235 const struct brcmf_buscore_ops *ops;
237 /* assured first core is chipcommon, second core is buscore */
238 struct list_head cores;
241 bool (*iscoreup)(struct brcmf_core_priv *core);
242 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
244 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
248 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
249 struct brcmf_core *core)
253 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
254 core->rev = SBCOREREV(regdata);
257 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
259 struct brcmf_chip_priv *ci;
264 address = CORE_SB(core->pub.base, sbtmstatelow);
265 regdata = ci->ops->read32(ci->ctx, address);
266 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
267 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
268 return SSB_TMSLOW_CLOCK == regdata;
271 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
273 struct brcmf_chip_priv *ci;
278 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
279 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
281 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
282 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
287 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
288 u32 prereset, u32 reset)
290 struct brcmf_chip_priv *ci;
294 base = core->pub.base;
295 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
296 if (val & SSB_TMSLOW_RESET)
299 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
300 if ((val & SSB_TMSLOW_CLOCK) != 0) {
302 * set target reject and spin until busy is clear
303 * (preserve core-specific bits)
305 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
306 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
307 val | SSB_TMSLOW_REJECT);
309 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
311 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
312 & SSB_TMSHIGH_BUSY), 100000);
314 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
315 if (val & SSB_TMSHIGH_BUSY)
316 brcmf_err("core state still busy\n");
318 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
319 if (val & SSB_IDLOW_INITIATOR) {
320 val = ci->ops->read32(ci->ctx,
321 CORE_SB(base, sbimstate));
322 val |= SSB_IMSTATE_REJECT;
323 ci->ops->write32(ci->ctx,
324 CORE_SB(base, sbimstate), val);
325 val = ci->ops->read32(ci->ctx,
326 CORE_SB(base, sbimstate));
328 SPINWAIT((ci->ops->read32(ci->ctx,
329 CORE_SB(base, sbimstate)) &
330 SSB_IMSTATE_BUSY), 100000);
333 /* set reset and reject while enabling the clocks */
334 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
335 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
336 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
337 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
340 /* clear the initiator reject bit */
341 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
342 if (val & SSB_IDLOW_INITIATOR) {
343 val = ci->ops->read32(ci->ctx,
344 CORE_SB(base, sbimstate));
345 val &= ~SSB_IMSTATE_REJECT;
346 ci->ops->write32(ci->ctx,
347 CORE_SB(base, sbimstate), val);
351 /* leave reset and reject asserted */
352 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
353 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
357 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
358 u32 prereset, u32 reset)
360 struct brcmf_chip_priv *ci;
365 /* if core is already in reset, skip reset */
366 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
367 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
368 goto in_reset_configure;
370 /* configure reset */
371 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
372 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
373 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
376 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
377 BCMA_RESET_CTL_RESET);
378 usleep_range(10, 20);
380 /* wait till reset is 1 */
381 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
382 BCMA_RESET_CTL_RESET, 300);
385 /* in-reset configure */
386 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
387 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
388 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
391 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
392 u32 reset, u32 postreset)
394 struct brcmf_chip_priv *ci;
399 base = core->pub.base;
401 * Must do the disable sequence first to work for
402 * arbitrary current core state.
404 brcmf_chip_sb_coredisable(core, 0, 0);
407 * Now do the initialization sequence.
408 * set reset while enabling the clock and
409 * forcing them on throughout the core
411 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
412 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
414 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
417 /* clear any serror */
418 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
419 if (regdata & SSB_TMSHIGH_SERR)
420 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
422 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
423 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
424 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
425 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
428 /* clear reset and allow it to propagate throughout the core */
429 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
430 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
431 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
434 /* leave clock enabled */
435 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
437 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
441 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
442 u32 reset, u32 postreset)
444 struct brcmf_chip_priv *ci;
449 /* must disable first to work for arbitrary current core state */
450 brcmf_chip_ai_coredisable(core, prereset, reset);
453 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
454 BCMA_RESET_CTL_RESET) {
455 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
459 usleep_range(40, 60);
462 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
463 postreset | BCMA_IOCTL_CLK);
464 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
467 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
471 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u";
472 snprintf(buf, len, fmt, id, rev);
476 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
477 u16 coreid, u32 base,
480 struct brcmf_core_priv *core;
482 core = kzalloc(sizeof(*core), GFP_KERNEL);
484 return ERR_PTR(-ENOMEM);
486 core->pub.id = coreid;
487 core->pub.base = base;
489 core->wrapbase = wrapbase;
491 list_add_tail(&core->list, &ci->cores);
495 /* safety check for chipinfo */
496 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
498 struct brcmf_core_priv *core;
499 bool need_socram = false;
500 bool has_socram = false;
501 bool cpu_found = false;
504 list_for_each_entry(core, &ci->cores, list) {
505 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
506 idx++, core->pub.id, core->pub.rev, core->pub.base,
509 switch (core->pub.id) {
510 case BCMA_CORE_ARM_CM3:
514 case BCMA_CORE_INTERNAL_MEM:
517 case BCMA_CORE_ARM_CR4:
520 case BCMA_CORE_ARM_CA7:
529 brcmf_err("CPU core not detected\n");
532 /* check RAM core presence for ARM CM3 core */
533 if (need_socram && !has_socram) {
534 brcmf_err("RAM core not provided with ARM CM3 core\n");
540 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
542 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
545 static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
548 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
551 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
555 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
558 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
559 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
560 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
561 *banksize *= SOCRAM_BANKINFO_SZBASE;
562 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
565 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
569 uint nb, banksize, lss;
576 if (WARN_ON(sr->pub.rev < 4))
579 if (!brcmf_chip_iscoreup(&sr->pub))
580 brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
582 /* Get info for determining size */
583 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
584 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
586 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
587 banksize = (coreinfo & SRCI_SRBSZ_MASK);
588 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
591 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
593 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
595 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
596 for (i = 0; i < nb; i++) {
597 retent = brcmf_chip_socram_banksize(sr, i, &banksize);
598 *ramsize += banksize;
604 /* hardcoded save&restore memory sizes */
605 switch (sr->chip->pub.chip) {
606 case BRCM_CC_4334_CHIP_ID:
607 if (sr->chip->pub.chiprev < 2)
608 *srsize = (32 * 1024);
610 case BRCM_CC_43430_CHIP_ID:
611 /* assume sr for now as we can not check
612 * firmware sr capability at this point.
614 *srsize = (64 * 1024);
621 /** Return the SYS MEM size */
622 static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
630 if (!brcmf_chip_iscoreup(&sysmem->pub))
631 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0);
633 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo));
634 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
636 for (idx = 0; idx < nb; idx++) {
637 brcmf_chip_socram_banksize(sysmem, idx, &banksize);
644 /** Return the TCM-RAM size of the ARMCR4 core. */
645 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
655 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
657 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
658 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
661 for (idx = 0; idx < totb; idx++) {
662 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
663 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
664 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
670 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
672 switch (ci->pub.chip) {
673 case BRCM_CC_4345_CHIP_ID:
675 case BRCM_CC_4335_CHIP_ID:
676 case BRCM_CC_4339_CHIP_ID:
677 case BRCM_CC_4350_CHIP_ID:
678 case BRCM_CC_4354_CHIP_ID:
679 case BRCM_CC_4356_CHIP_ID:
680 case BRCM_CC_43567_CHIP_ID:
681 case BRCM_CC_43569_CHIP_ID:
682 case BRCM_CC_43570_CHIP_ID:
683 case BRCM_CC_4358_CHIP_ID:
684 case BRCM_CC_4359_CHIP_ID:
685 case BRCM_CC_43602_CHIP_ID:
686 case BRCM_CC_4371_CHIP_ID:
688 case BRCM_CC_43465_CHIP_ID:
689 case BRCM_CC_43525_CHIP_ID:
690 case BRCM_CC_4365_CHIP_ID:
691 case BRCM_CC_4366_CHIP_ID:
692 case BRCM_CC_43664_CHIP_ID:
694 case CY_CC_4373_CHIP_ID:
697 brcmf_err("unknown chip: %s\n", ci->pub.name);
703 static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
705 struct brcmf_core_priv *mem_core;
706 struct brcmf_core *mem;
708 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
710 mem_core = container_of(mem, struct brcmf_core_priv, pub);
711 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
712 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
713 if (!ci->pub.rambase) {
714 brcmf_err("RAM base not provided with ARM CR4 core\n");
718 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
720 mem_core = container_of(mem, struct brcmf_core_priv,
722 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
723 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
724 if (!ci->pub.rambase) {
725 brcmf_err("RAM base not provided with ARM CA7 core\n");
729 mem = brcmf_chip_get_core(&ci->pub,
730 BCMA_CORE_INTERNAL_MEM);
732 brcmf_err("No memory cores found\n");
735 mem_core = container_of(mem, struct brcmf_core_priv,
737 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
741 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
742 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
743 ci->pub.srsize, ci->pub.srsize);
745 if (!ci->pub.ramsize) {
746 brcmf_err("RAM size is undetermined\n");
750 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
751 brcmf_err("RAM size is incorrect\n");
758 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
763 /* read next descriptor */
764 val = ci->ops->read32(ci->ctx, *eromaddr);
770 /* determine descriptor type */
771 *type = (val & DMP_DESC_TYPE_MSK);
772 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
773 *type = DMP_DESC_ADDRESS;
778 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
779 u32 *regbase, u32 *wrapbase)
784 u8 stype, sztype, wraptype;
789 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
790 if (desc == DMP_DESC_MASTER_PORT) {
791 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
792 wraptype = DMP_SLAVE_TYPE_MWRAP;
793 } else if (desc == DMP_DESC_ADDRESS) {
794 /* revert erom address */
796 wraptype = DMP_SLAVE_TYPE_SWRAP;
803 /* locate address descriptor */
805 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
806 /* unexpected table end */
807 if (desc == DMP_DESC_EOT) {
811 } while (desc != DMP_DESC_ADDRESS &&
812 desc != DMP_DESC_COMPONENT);
814 /* stop if we crossed current component border */
815 if (desc == DMP_DESC_COMPONENT) {
820 /* skip upper 32-bit address descriptor */
821 if (val & DMP_DESC_ADDRSIZE_GT32)
822 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
824 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
826 /* next size descriptor can be skipped */
827 if (sztype == DMP_SLAVE_SIZE_DESC) {
828 val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
829 /* skip upper size descriptor if present */
830 if (val & DMP_DESC_ADDRSIZE_GT32)
831 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
834 /* only look for 4K register regions */
835 if (sztype != DMP_SLAVE_SIZE_4K)
838 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
840 /* only regular slave and wrapper */
841 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
842 *regbase = val & DMP_SLAVE_ADDR_BASE;
843 if (*wrapbase == 0 && stype == wraptype)
844 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
845 } while (*regbase == 0 || *wrapbase == 0);
851 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
853 struct brcmf_core *core;
858 u8 nmp, nsp, nmw, nsw, rev;
862 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
864 while (desc_type != DMP_DESC_EOT) {
865 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
866 if (!(val & DMP_DESC_VALID))
869 if (desc_type == DMP_DESC_EMPTY)
872 /* need a component descriptor */
873 if (desc_type != DMP_DESC_COMPONENT)
876 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
878 /* next descriptor must be component as well */
879 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
880 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
883 /* only look at cores with master port(s) */
884 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
885 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
886 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
887 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
888 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
890 /* need core with ports */
891 if (nmw + nsw == 0 &&
895 /* try to obtain register address info */
896 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
900 /* finally a core to be added */
901 core = brcmf_chip_add_core(ci, id, base, wrap);
903 return PTR_ERR(core);
911 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
913 struct brcmf_core *core;
919 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
920 * For different chiptypes or old sdio hosts w/o chipcommon,
921 * other ways of recognition should be added here.
923 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
924 ci->pub.chip = regdata & CID_ID_MASK;
925 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
926 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
928 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
929 ci->pub.name, sizeof(ci->pub.name));
930 brcmf_dbg(INFO, "found %s chip: %s\n",
931 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
933 if (socitype == SOCI_SB) {
934 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
935 brcmf_err("SB chip is not supported\n");
938 ci->iscoreup = brcmf_chip_sb_iscoreup;
939 ci->coredisable = brcmf_chip_sb_coredisable;
940 ci->resetcore = brcmf_chip_sb_resetcore;
942 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
944 brcmf_chip_sb_corerev(ci, core);
945 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
946 BCM4329_CORE_BUS_BASE, 0);
947 brcmf_chip_sb_corerev(ci, core);
948 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
949 BCM4329_CORE_SOCRAM_BASE, 0);
950 brcmf_chip_sb_corerev(ci, core);
951 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
952 BCM4329_CORE_ARM_BASE, 0);
953 brcmf_chip_sb_corerev(ci, core);
955 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
956 brcmf_chip_sb_corerev(ci, core);
957 } else if (socitype == SOCI_AI) {
958 ci->iscoreup = brcmf_chip_ai_iscoreup;
959 ci->coredisable = brcmf_chip_ai_coredisable;
960 ci->resetcore = brcmf_chip_ai_resetcore;
962 brcmf_chip_dmp_erom_scan(ci);
964 brcmf_err("chip backplane type %u is not supported\n",
969 ret = brcmf_chip_cores_check(ci);
973 /* assure chip is passive for core access */
974 brcmf_chip_set_passive(&ci->pub);
976 /* Call bus specific reset function now. Cores have been determined
977 * but further access may require a chip specific reset at this point.
979 if (ci->ops->reset) {
980 ci->ops->reset(ci->ctx, &ci->pub);
981 brcmf_chip_set_passive(&ci->pub);
984 return brcmf_chip_get_raminfo(ci);
987 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
989 struct brcmf_core *core;
990 struct brcmf_core_priv *cpu;
994 core = brcmf_chip_get_core(&chip->pub, id);
999 case BCMA_CORE_ARM_CM3:
1000 brcmf_chip_coredisable(core, 0, 0);
1002 case BCMA_CORE_ARM_CR4:
1003 case BCMA_CORE_ARM_CA7:
1004 cpu = container_of(core, struct brcmf_core_priv, pub);
1006 /* clear all IOCTL bits except HALT bit */
1007 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
1008 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
1009 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
1010 ARMCR4_BCMA_IOCTL_CPUHALT);
1013 brcmf_err("unknown id: %u\n", id);
1018 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
1020 struct brcmf_chip *pub;
1021 struct brcmf_core_priv *cc;
1022 struct brcmf_core *pmu;
1028 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1029 base = cc->pub.base;
1031 /* get chipcommon capabilites */
1032 pub->cc_caps = chip->ops->read32(chip->ctx,
1033 CORE_CC_REG(base, capabilities));
1034 pub->cc_caps_ext = chip->ops->read32(chip->ctx,
1038 /* get pmu caps & rev */
1039 pmu = brcmf_chip_get_pmu(pub); /* after reading cc_caps_ext */
1040 if (pub->cc_caps & CC_CAP_PMU) {
1041 val = chip->ops->read32(chip->ctx,
1042 CORE_CC_REG(pmu->base, pmucapabilities));
1043 pub->pmurev = val & PCAP_REV_MASK;
1047 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
1048 cc->pub.rev, pub->pmurev, pub->pmucaps);
1050 /* execute bus core specific setup */
1051 if (chip->ops->setup)
1052 ret = chip->ops->setup(chip->ctx, pub);
1057 struct brcmf_chip *brcmf_chip_attach(void *ctx,
1058 const struct brcmf_buscore_ops *ops)
1060 struct brcmf_chip_priv *chip;
1063 if (WARN_ON(!ops->read32))
1065 if (WARN_ON(!ops->write32))
1067 if (WARN_ON(!ops->prepare))
1069 if (WARN_ON(!ops->activate))
1072 return ERR_PTR(-EINVAL);
1074 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1076 return ERR_PTR(-ENOMEM);
1078 INIT_LIST_HEAD(&chip->cores);
1079 chip->num_cores = 0;
1083 err = ops->prepare(ctx);
1087 err = brcmf_chip_recognition(chip);
1091 err = brcmf_chip_setup(chip);
1098 brcmf_chip_detach(&chip->pub);
1099 return ERR_PTR(err);
1102 void brcmf_chip_detach(struct brcmf_chip *pub)
1104 struct brcmf_chip_priv *chip;
1105 struct brcmf_core_priv *core;
1106 struct brcmf_core_priv *tmp;
1108 chip = container_of(pub, struct brcmf_chip_priv, pub);
1109 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1110 list_del(&core->list);
1116 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1118 struct brcmf_chip_priv *chip;
1119 struct brcmf_core_priv *core;
1121 chip = container_of(pub, struct brcmf_chip_priv, pub);
1122 list_for_each_entry(core, &chip->cores, list)
1123 if (core->pub.id == coreid)
1129 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1131 struct brcmf_chip_priv *chip;
1132 struct brcmf_core_priv *cc;
1134 chip = container_of(pub, struct brcmf_chip_priv, pub);
1135 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1136 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1137 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1141 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
1143 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
1144 struct brcmf_core *pmu;
1146 /* See if there is separated PMU core available */
1147 if (cc->rev >= 35 &&
1148 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
1149 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
1154 /* Fallback to ChipCommon core for older hardware */
1158 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1160 struct brcmf_core_priv *core;
1162 core = container_of(pub, struct brcmf_core_priv, pub);
1163 return core->chip->iscoreup(core);
1166 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1168 struct brcmf_core_priv *core;
1170 core = container_of(pub, struct brcmf_core_priv, pub);
1171 core->chip->coredisable(core, prereset, reset);
1174 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1177 struct brcmf_core_priv *core;
1179 core = container_of(pub, struct brcmf_core_priv, pub);
1180 core->chip->resetcore(core, prereset, reset, postreset);
1184 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1186 struct brcmf_core *core;
1187 struct brcmf_core_priv *sr;
1189 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1190 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1191 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1192 D11_BCMA_IOCTL_PHYCLOCKEN,
1193 D11_BCMA_IOCTL_PHYCLOCKEN,
1194 D11_BCMA_IOCTL_PHYCLOCKEN);
1195 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1196 brcmf_chip_resetcore(core, 0, 0, 0);
1198 /* disable bank #3 remap for this device */
1199 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1200 sr = container_of(core, struct brcmf_core_priv, pub);
1201 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1202 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1206 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1208 struct brcmf_core *core;
1210 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1211 if (!brcmf_chip_iscoreup(core)) {
1212 brcmf_err("SOCRAM core is down after reset?\n");
1216 chip->ops->activate(chip->ctx, &chip->pub, 0);
1218 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1219 brcmf_chip_resetcore(core, 0, 0, 0);
1225 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1227 struct brcmf_core *core;
1229 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1231 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1232 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1233 D11_BCMA_IOCTL_PHYCLOCKEN,
1234 D11_BCMA_IOCTL_PHYCLOCKEN,
1235 D11_BCMA_IOCTL_PHYCLOCKEN);
1238 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1240 struct brcmf_core *core;
1242 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1245 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1246 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1252 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip)
1254 struct brcmf_core *core;
1256 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7);
1258 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1259 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1260 D11_BCMA_IOCTL_PHYCLOCKEN,
1261 D11_BCMA_IOCTL_PHYCLOCKEN,
1262 D11_BCMA_IOCTL_PHYCLOCKEN);
1265 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1267 struct brcmf_core *core;
1269 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1272 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
1273 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1278 void brcmf_chip_set_passive(struct brcmf_chip *pub)
1280 struct brcmf_chip_priv *chip;
1281 struct brcmf_core *arm;
1283 brcmf_dbg(TRACE, "Enter\n");
1285 chip = container_of(pub, struct brcmf_chip_priv, pub);
1286 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1288 brcmf_chip_cr4_set_passive(chip);
1291 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1293 brcmf_chip_ca7_set_passive(chip);
1296 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1298 brcmf_chip_cm3_set_passive(chip);
1303 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1305 struct brcmf_chip_priv *chip;
1306 struct brcmf_core *arm;
1308 brcmf_dbg(TRACE, "Enter\n");
1310 chip = container_of(pub, struct brcmf_chip_priv, pub);
1311 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1313 return brcmf_chip_cr4_set_active(chip, rstvec);
1314 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1316 return brcmf_chip_ca7_set_active(chip, rstvec);
1317 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1319 return brcmf_chip_cm3_set_active(chip);
1324 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1326 u32 base, addr, reg, pmu_cc3_mask = ~0;
1327 struct brcmf_chip_priv *chip;
1328 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
1330 brcmf_dbg(TRACE, "Enter\n");
1332 /* old chips with PMU version less than 17 don't support save restore */
1333 if (pub->pmurev < 17)
1336 base = brcmf_chip_get_chipcommon(pub)->base;
1337 chip = container_of(pub, struct brcmf_chip_priv, pub);
1339 switch (pub->chip) {
1340 case BRCM_CC_4354_CHIP_ID:
1341 case BRCM_CC_4356_CHIP_ID:
1342 case BRCM_CC_4345_CHIP_ID:
1343 /* explicitly check SR engine enable bit */
1344 pmu_cc3_mask = BIT(2);
1346 case BRCM_CC_43241_CHIP_ID:
1347 case BRCM_CC_4335_CHIP_ID:
1348 case BRCM_CC_4339_CHIP_ID:
1349 /* read PMU chipcontrol register 3 */
1350 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
1351 chip->ops->write32(chip->ctx, addr, 3);
1352 addr = CORE_CC_REG(pmu->base, chipcontrol_data);
1353 reg = chip->ops->read32(chip->ctx, addr);
1354 return (reg & pmu_cc3_mask) != 0;
1355 case BRCM_CC_43430_CHIP_ID:
1356 addr = CORE_CC_REG(base, sr_control1);
1357 reg = chip->ops->read32(chip->ctx, addr);
1360 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
1361 reg = chip->ops->read32(chip->ctx, addr);
1362 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1365 addr = CORE_CC_REG(pmu->base, retention_ctl);
1366 reg = chip->ops->read32(chip->ctx, addr);
1367 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1368 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;