2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
40 /********************/
41 /* Helper Functions */
42 /********************/
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
63 return ath9k_hw_mac_usec(ah, clks);
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
84 return ath9k_hw_mac_clks(ah, usecs);
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
91 BUG_ON(timeout < AH_TIME_QUANTUM);
93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
94 if ((REG_READ(ah, reg) & mask) == val)
97 udelay(AH_TIME_QUANTUM);
100 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val);
107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
112 for (i = 0, retval = 0; i < n; i++) {
113 retval = (retval << 1) | (val & 1);
119 bool ath9k_get_channel_edges(struct ath_hw *ah,
123 struct ath9k_hw_capabilities *pCap = &ah->caps;
125 if (flags & CHANNEL_5GHZ) {
126 *low = pCap->low_5ghz_chan;
127 *high = pCap->high_5ghz_chan;
130 if ((flags & CHANNEL_2GHZ)) {
131 *low = pCap->low_2ghz_chan;
132 *high = pCap->high_2ghz_chan;
138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
139 struct ath_rate_table *rates,
140 u32 frameLen, u16 rateix,
143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
146 kbps = rates->info[rateix].ratekbps;
151 switch (rates->info[rateix].phy) {
152 case WLAN_RC_PHY_CCK:
153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
154 if (shortPreamble && rates->info[rateix].short_preamble)
156 numBits = frameLen << 3;
157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
159 case WLAN_RC_PHY_OFDM:
160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
167 } else if (ah->curchan &&
168 IS_CHAN_HALF_RATE(ah->curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_HALF +
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177 numBits = OFDM_PLCP_BITS + (frameLen << 3);
178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180 + (numSymbols * OFDM_SYMBOL_TIME);
184 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix);
194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
195 struct ath9k_channel *chan,
196 struct chan_centers *centers)
200 if (!IS_CHAN_HT40(chan)) {
201 centers->ctl_center = centers->ext_center =
202 centers->synth_center = chan->channel;
206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208 centers->synth_center =
209 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
212 centers->synth_center =
213 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
217 centers->ctl_center =
218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219 centers->ext_center =
220 centers->synth_center + (extoff *
221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
222 HT40_CHANNEL_CENTER_SHIFT : 15));
229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macVersion =
238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
242 if (!AR_SREV_9100(ah))
243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
245 ah->hw_version.macRev = val & AR_SREV_REVISION;
247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
248 ah->is_pciexpress = true;
252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
259 for (i = 0; i < 8; i++)
260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
264 return ath9k_hw_reverse_bits(val, 8);
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
273 if (AR_SREV_9100(ah))
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
293 u32 patternData[4] = { 0x55555555,
299 for (i = 0; i < 2; i++) {
300 u32 addr = regAddr[i];
303 regHold[i] = REG_READ(ah, addr);
304 for (j = 0; j < 0x100; j++) {
305 wrData = (j << 16) | j;
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData);
316 for (j = 0; j < 4; j++) {
317 wrData = patternData[j];
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData);
328 REG_WRITE(ah, regAddr[i], regHold[i]);
335 static const char *ath9k_hw_devname(u16 devid)
338 case AR5416_DEVID_PCI:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_l1skp_enable = 0;
367 ah->config.pcie_clock_req = 0;
368 ah->config.pcie_power_reset = 0x100;
369 ah->config.pcie_restore = 0;
370 ah->config.pcie_waen = 0;
371 ah->config.analog_shiftreg = 1;
372 ah->config.ht_enable = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377 ah->config.enable_ani = 1;
378 ah->config.noise_immunity_level = 4;
379 ah->config.ofdm_weaksignal_det = 1;
380 ah->config.cck_weaksignal_thr = 0;
381 ah->config.spur_immunity_level = 2;
382 ah->config.firstep_level = 0;
383 ah->config.rssi_thr_high = 40;
384 ah->config.rssi_thr_low = 7;
385 ah->config.diversity_control = 0;
386 ah->config.antenna_switch_swap = 0;
388 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
389 ah->config.spurchans[i][0] = AR_NO_SPUR;
390 ah->config.spurchans[i][1] = AR_NO_SPUR;
393 ah->config.intr_mitigation = 1;
396 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
401 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
403 DPRINTF(sc, ATH_DBG_FATAL,
404 "Cannot allocate memory for state block\n");
410 ah->hw_version.magic = AR5416_MAGIC;
411 ah->regulatory.country_code = CTRY_DEFAULT;
412 ah->hw_version.devid = devid;
413 ah->hw_version.subvendorid = 0;
416 if ((devid == AR5416_AR9100_DEVID))
417 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
418 if (!AR_SREV_9100(ah))
419 ah->ah_flags = AH_USE_EEPROM;
421 ah->regulatory.power_limit = MAX_RATE_POWER;
422 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
424 ah->diversity_control = ah->config.diversity_control;
425 ah->antenna_switch_swap =
426 ah->config.antenna_switch_swap;
427 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
428 ah->beacon_interval = 100;
429 ah->enable_32kHz_clock = DONT_USE_32KHZ;
430 ah->slottime = (u32) -1;
431 ah->acktimeout = (u32) -1;
432 ah->ctstimeout = (u32) -1;
433 ah->globaltxtimeout = (u32) -1;
435 ah->gbeacon_rate = 0;
440 static int ath9k_hw_rfattach(struct ath_hw *ah)
442 bool rfStatus = false;
445 rfStatus = ath9k_hw_init_rf(ah, &ecode);
447 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
448 "RF setup failed, status %u\n", ecode);
455 static int ath9k_hw_rf_claim(struct ath_hw *ah)
459 REG_WRITE(ah, AR_PHY(0), 0x00000007);
461 val = ath9k_hw_get_radiorev(ah);
462 switch (val & AR_RADIO_SREV_MAJOR) {
464 val = AR_RAD5133_SREV_MAJOR;
466 case AR_RAD5133_SREV_MAJOR:
467 case AR_RAD5122_SREV_MAJOR:
468 case AR_RAD2133_SREV_MAJOR:
469 case AR_RAD2122_SREV_MAJOR:
472 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
473 "5G Radio Chip Rev 0x%02X is not "
474 "supported by this driver\n",
475 ah->hw_version.analog5GhzRev);
479 ah->hw_version.analog5GhzRev = val;
484 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
491 for (i = 0; i < 3; i++) {
492 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
494 ah->macaddr[2 * i] = eeval >> 8;
495 ah->macaddr[2 * i + 1] = eeval & 0xff;
497 if (sum == 0 || sum == 0xffff * 3) {
498 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
499 "mac address read failed: %pM\n",
501 return -EADDRNOTAVAIL;
507 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
511 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
512 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
514 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
515 INIT_INI_ARRAY(&ah->iniModesRxGain,
516 ar9280Modes_backoff_13db_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
518 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
519 INIT_INI_ARRAY(&ah->iniModesRxGain,
520 ar9280Modes_backoff_23db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
523 INIT_INI_ARRAY(&ah->iniModesRxGain,
524 ar9280Modes_original_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
527 INIT_INI_ARRAY(&ah->iniModesRxGain,
528 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
533 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
537 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
538 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
540 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
541 INIT_INI_ARRAY(&ah->iniModesTxGain,
542 ar9280Modes_high_power_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
545 INIT_INI_ARRAY(&ah->iniModesTxGain,
546 ar9280Modes_original_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
549 INIT_INI_ARRAY(&ah->iniModesTxGain,
550 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
555 static int ath9k_hw_post_attach(struct ath_hw *ah)
559 if (!ath9k_hw_chip_test(ah)) {
560 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
561 "hardware self-test failed\n");
565 ecode = ath9k_hw_rf_claim(ah);
569 ecode = ath9k_hw_eeprom_attach(ah);
572 ecode = ath9k_hw_rfattach(ah);
576 if (!AR_SREV_9100(ah)) {
577 ath9k_hw_ani_setup(ah);
578 ath9k_hw_ani_attach(ah);
584 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
591 ah = ath9k_hw_newstate(devid, sc, status);
595 ath9k_hw_set_defaults(ah);
597 if (ah->config.intr_mitigation != 0)
598 ah->intr_mitigation = true;
600 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
601 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
606 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
607 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
612 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
613 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
614 ah->config.serialize_regmode =
617 ah->config.serialize_regmode =
622 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
623 ah->config.serialize_regmode);
625 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
626 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
627 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
628 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
629 DPRINTF(sc, ATH_DBG_RESET,
630 "Mac Chip Rev 0x%02x.%x is not supported by "
631 "this driver\n", ah->hw_version.macVersion,
632 ah->hw_version.macRev);
637 if (AR_SREV_9100(ah)) {
638 ah->iq_caldata.calData = &iq_cal_multi_sample;
639 ah->supp_cals = IQ_MISMATCH_CAL;
640 ah->is_pciexpress = false;
642 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
644 if (AR_SREV_9160_10_OR_LATER(ah)) {
645 if (AR_SREV_9280_10_OR_LATER(ah)) {
646 ah->iq_caldata.calData = &iq_cal_single_sample;
647 ah->adcgain_caldata.calData =
648 &adc_gain_cal_single_sample;
649 ah->adcdc_caldata.calData =
650 &adc_dc_cal_single_sample;
651 ah->adcdc_calinitdata.calData =
654 ah->iq_caldata.calData = &iq_cal_multi_sample;
655 ah->adcgain_caldata.calData =
656 &adc_gain_cal_multi_sample;
657 ah->adcdc_caldata.calData =
658 &adc_dc_cal_multi_sample;
659 ah->adcdc_calinitdata.calData =
662 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
665 if (AR_SREV_9160(ah)) {
666 ah->config.enable_ani = 1;
667 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
668 ATH9K_ANI_FIRSTEP_LEVEL);
670 ah->ani_function = ATH9K_ANI_ALL;
671 if (AR_SREV_9280_10_OR_LATER(ah)) {
672 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
676 DPRINTF(sc, ATH_DBG_RESET,
677 "This Mac Chip Rev 0x%02x.%x is \n",
678 ah->hw_version.macVersion, ah->hw_version.macRev);
680 if (AR_SREV_9285_12_OR_LATER(ah)) {
681 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
682 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
684 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
686 if (ah->config.pcie_clock_req) {
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
688 ar9285PciePhy_clkreq_off_L1_9285_1_2,
689 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
692 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
693 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
696 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
697 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
698 ARRAY_SIZE(ar9285Modes_9285), 6);
699 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
700 ARRAY_SIZE(ar9285Common_9285), 2);
702 if (ah->config.pcie_clock_req) {
703 INIT_INI_ARRAY(&ah->iniPcieSerdes,
704 ar9285PciePhy_clkreq_off_L1_9285,
705 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
707 INIT_INI_ARRAY(&ah->iniPcieSerdes,
708 ar9285PciePhy_clkreq_always_on_L1_9285,
709 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
711 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
712 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
713 ARRAY_SIZE(ar9280Modes_9280_2), 6);
714 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
715 ARRAY_SIZE(ar9280Common_9280_2), 2);
717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
719 ar9280PciePhy_clkreq_off_L1_9280,
720 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
723 ar9280PciePhy_clkreq_always_on_L1_9280,
724 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
726 INIT_INI_ARRAY(&ah->iniModesAdditional,
727 ar9280Modes_fast_clock_9280_2,
728 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
729 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
730 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
731 ARRAY_SIZE(ar9280Modes_9280), 6);
732 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
733 ARRAY_SIZE(ar9280Common_9280), 2);
734 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
735 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
736 ARRAY_SIZE(ar5416Modes_9160), 6);
737 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
738 ARRAY_SIZE(ar5416Common_9160), 2);
739 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
740 ARRAY_SIZE(ar5416Bank0_9160), 2);
741 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
742 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
743 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
744 ARRAY_SIZE(ar5416Bank1_9160), 2);
745 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
746 ARRAY_SIZE(ar5416Bank2_9160), 2);
747 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
748 ARRAY_SIZE(ar5416Bank3_9160), 3);
749 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
750 ARRAY_SIZE(ar5416Bank6_9160), 3);
751 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
752 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
753 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
754 ARRAY_SIZE(ar5416Bank7_9160), 2);
755 if (AR_SREV_9160_11(ah)) {
756 INIT_INI_ARRAY(&ah->iniAddac,
758 ARRAY_SIZE(ar5416Addac_91601_1), 2);
760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
761 ARRAY_SIZE(ar5416Addac_9160), 2);
763 } else if (AR_SREV_9100_OR_LATER(ah)) {
764 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
765 ARRAY_SIZE(ar5416Modes_9100), 6);
766 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
767 ARRAY_SIZE(ar5416Common_9100), 2);
768 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
769 ARRAY_SIZE(ar5416Bank0_9100), 2);
770 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
771 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
772 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
773 ARRAY_SIZE(ar5416Bank1_9100), 2);
774 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
775 ARRAY_SIZE(ar5416Bank2_9100), 2);
776 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
777 ARRAY_SIZE(ar5416Bank3_9100), 3);
778 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
779 ARRAY_SIZE(ar5416Bank6_9100), 3);
780 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
781 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
782 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
783 ARRAY_SIZE(ar5416Bank7_9100), 2);
784 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
785 ARRAY_SIZE(ar5416Addac_9100), 2);
787 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
788 ARRAY_SIZE(ar5416Modes), 6);
789 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
790 ARRAY_SIZE(ar5416Common), 2);
791 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
792 ARRAY_SIZE(ar5416Bank0), 2);
793 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
794 ARRAY_SIZE(ar5416BB_RfGain), 3);
795 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
796 ARRAY_SIZE(ar5416Bank1), 2);
797 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
798 ARRAY_SIZE(ar5416Bank2), 2);
799 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
800 ARRAY_SIZE(ar5416Bank3), 3);
801 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
802 ARRAY_SIZE(ar5416Bank6), 3);
803 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
804 ARRAY_SIZE(ar5416Bank6TPC), 3);
805 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
806 ARRAY_SIZE(ar5416Bank7), 2);
807 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
808 ARRAY_SIZE(ar5416Addac), 2);
811 if (ah->is_pciexpress)
812 ath9k_hw_configpcipowersave(ah, 0);
814 ath9k_hw_disablepcie(ah);
816 ecode = ath9k_hw_post_attach(ah);
821 if (AR_SREV_9280_20(ah))
822 ath9k_hw_init_rxgain_ini(ah);
825 if (AR_SREV_9280_20(ah))
826 ath9k_hw_init_txgain_ini(ah);
828 if (!ath9k_hw_fill_cap_info(ah)) {
829 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
834 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
835 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
838 for (i = 0; i < ah->iniModes.ia_rows; i++) {
839 u32 reg = INI_RA(&ah->iniModes, i, 0);
841 for (j = 1; j < ah->iniModes.ia_columns; j++) {
842 u32 val = INI_RA(&ah->iniModes, i, j);
844 INI_RA(&ah->iniModes, i, j) =
845 ath9k_hw_ini_fixup(ah,
852 ecode = ath9k_hw_init_macaddr(ah);
854 DPRINTF(sc, ATH_DBG_RESET,
855 "failed initializing mac address\n");
859 if (AR_SREV_9285(ah))
860 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
862 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
864 ath9k_init_nfcal_hist_buffer(ah);
876 static void ath9k_hw_init_bb(struct ath_hw *ah,
877 struct ath9k_channel *chan)
881 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
883 synthDelay = (4 * synthDelay) / 22;
887 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
889 udelay(synthDelay + BASE_ACTIVATE_DELAY);
892 static void ath9k_hw_init_qos(struct ath_hw *ah)
894 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
895 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
897 REG_WRITE(ah, AR_QOS_NO_ACK,
898 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
899 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
900 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
902 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
903 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
904 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
905 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
906 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
909 static void ath9k_hw_init_pll(struct ath_hw *ah,
910 struct ath9k_channel *chan)
914 if (AR_SREV_9100(ah)) {
915 if (chan && IS_CHAN_5GHZ(chan))
920 if (AR_SREV_9280_10_OR_LATER(ah)) {
921 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
923 if (chan && IS_CHAN_HALF_RATE(chan))
924 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
925 else if (chan && IS_CHAN_QUARTER_RATE(chan))
926 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
928 if (chan && IS_CHAN_5GHZ(chan)) {
929 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
932 if (AR_SREV_9280_20(ah)) {
933 if (((chan->channel % 20) == 0)
934 || ((chan->channel % 10) == 0))
940 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
943 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
945 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
947 if (chan && IS_CHAN_HALF_RATE(chan))
948 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
949 else if (chan && IS_CHAN_QUARTER_RATE(chan))
950 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
952 if (chan && IS_CHAN_5GHZ(chan))
953 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
955 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
957 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
959 if (chan && IS_CHAN_HALF_RATE(chan))
960 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
961 else if (chan && IS_CHAN_QUARTER_RATE(chan))
962 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
964 if (chan && IS_CHAN_5GHZ(chan))
965 pll |= SM(0xa, AR_RTC_PLL_DIV);
967 pll |= SM(0xb, AR_RTC_PLL_DIV);
970 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
972 udelay(RTC_PLL_SETTLE_DELAY);
974 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
977 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
979 int rx_chainmask, tx_chainmask;
981 rx_chainmask = ah->rxchainmask;
982 tx_chainmask = ah->txchainmask;
984 switch (rx_chainmask) {
986 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
987 AR_PHY_SWAP_ALT_CHAIN);
989 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
990 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
991 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
997 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
998 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1004 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1005 if (tx_chainmask == 0x5) {
1006 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1007 AR_PHY_SWAP_ALT_CHAIN);
1009 if (AR_SREV_9100(ah))
1010 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1011 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1014 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1015 enum nl80211_iftype opmode)
1017 ah->mask_reg = AR_IMR_TXERR |
1023 if (ah->intr_mitigation)
1024 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1026 ah->mask_reg |= AR_IMR_RXOK;
1028 ah->mask_reg |= AR_IMR_TXOK;
1030 if (opmode == NL80211_IFTYPE_AP)
1031 ah->mask_reg |= AR_IMR_MIB;
1033 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1034 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1036 if (!AR_SREV_9100(ah)) {
1037 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1038 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1039 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1043 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1045 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1046 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1047 ah->acktimeout = (u32) -1;
1050 REG_RMW_FIELD(ah, AR_TIME_OUT,
1051 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1052 ah->acktimeout = us;
1057 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1059 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1060 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1061 ah->ctstimeout = (u32) -1;
1064 REG_RMW_FIELD(ah, AR_TIME_OUT,
1065 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1066 ah->ctstimeout = us;
1071 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1074 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1075 "bad global tx timeout %u\n", tu);
1076 ah->globaltxtimeout = (u32) -1;
1079 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1080 ah->globaltxtimeout = tu;
1085 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1087 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1090 if (ah->misc_mode != 0)
1091 REG_WRITE(ah, AR_PCU_MISC,
1092 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1093 if (ah->slottime != (u32) -1)
1094 ath9k_hw_setslottime(ah, ah->slottime);
1095 if (ah->acktimeout != (u32) -1)
1096 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1097 if (ah->ctstimeout != (u32) -1)
1098 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1099 if (ah->globaltxtimeout != (u32) -1)
1100 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1103 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1105 return vendorid == ATHEROS_VENDOR_ID ?
1106 ath9k_hw_devname(devid) : NULL;
1109 void ath9k_hw_detach(struct ath_hw *ah)
1111 if (!AR_SREV_9100(ah))
1112 ath9k_hw_ani_detach(ah);
1114 ath9k_hw_rfdetach(ah);
1115 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1119 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1121 struct ath_hw *ah = NULL;
1124 case AR5416_DEVID_PCI:
1125 case AR5416_DEVID_PCIE:
1126 case AR5416_AR9100_DEVID:
1127 case AR9160_DEVID_PCI:
1128 case AR9280_DEVID_PCI:
1129 case AR9280_DEVID_PCIE:
1130 case AR9285_DEVID_PCIE:
1131 ah = ath9k_hw_do_attach(devid, sc, error);
1145 static void ath9k_hw_override_ini(struct ath_hw *ah,
1146 struct ath9k_channel *chan)
1149 * Set the RX_ABORT and RX_DIS and clear if off only after
1150 * RXE is set for MAC. This prevents frames with corrupted
1151 * descriptor status.
1153 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1156 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1157 AR_SREV_9280_10_OR_LATER(ah))
1160 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1163 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1164 struct ar5416_eeprom_def *pEepData,
1167 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1169 switch (ah->hw_version.devid) {
1170 case AR9280_DEVID_PCI:
1171 if (reg == 0x7894) {
1172 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1173 "ini VAL: %x EEPROM: %x\n", value,
1174 (pBase->version & 0xff));
1176 if ((pBase->version & 0xff) > 0x0a) {
1177 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1180 value &= ~AR_AN_TOP2_PWDCLKIND;
1181 value |= AR_AN_TOP2_PWDCLKIND &
1182 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1184 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1185 "PWDCLKIND Earlier Rev\n");
1188 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1189 "final ini VAL: %x\n", value);
1197 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1198 struct ar5416_eeprom_def *pEepData,
1201 if (ah->eep_map == EEP_MAP_4KBITS)
1204 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1207 static void ath9k_olc_init(struct ath_hw *ah)
1211 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1212 ah->originalGain[i] =
1213 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1218 static int ath9k_hw_process_ini(struct ath_hw *ah,
1219 struct ath9k_channel *chan,
1220 enum ath9k_ht_macmode macmode)
1222 int i, regWrites = 0;
1223 struct ieee80211_channel *channel = chan->chan;
1224 u32 modesIndex, freqIndex;
1227 switch (chan->chanmode) {
1229 case CHANNEL_A_HT20:
1233 case CHANNEL_A_HT40PLUS:
1234 case CHANNEL_A_HT40MINUS:
1239 case CHANNEL_G_HT20:
1244 case CHANNEL_G_HT40PLUS:
1245 case CHANNEL_G_HT40MINUS:
1254 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1255 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1256 ah->eep_ops->set_addac(ah, chan);
1258 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1259 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1261 struct ar5416IniArray temp;
1263 sizeof(u32) * ah->iniAddac.ia_rows *
1264 ah->iniAddac.ia_columns;
1266 memcpy(ah->addac5416_21,
1267 ah->iniAddac.ia_array, addacSize);
1269 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1271 temp.ia_array = ah->addac5416_21;
1272 temp.ia_columns = ah->iniAddac.ia_columns;
1273 temp.ia_rows = ah->iniAddac.ia_rows;
1274 REG_WRITE_ARRAY(&temp, 1, regWrites);
1277 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1279 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1280 u32 reg = INI_RA(&ah->iniModes, i, 0);
1281 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1283 REG_WRITE(ah, reg, val);
1285 if (reg >= 0x7800 && reg < 0x78a0
1286 && ah->config.analog_shiftreg) {
1290 DO_DELAY(regWrites);
1293 if (AR_SREV_9280(ah))
1294 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1296 if (AR_SREV_9280(ah))
1297 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1299 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1300 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1301 u32 val = INI_RA(&ah->iniCommon, i, 1);
1303 REG_WRITE(ah, reg, val);
1305 if (reg >= 0x7800 && reg < 0x78a0
1306 && ah->config.analog_shiftreg) {
1310 DO_DELAY(regWrites);
1313 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1315 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1316 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1320 ath9k_hw_override_ini(ah, chan);
1321 ath9k_hw_set_regs(ah, chan, macmode);
1322 ath9k_hw_init_chain_masks(ah);
1324 if (OLC_FOR_AR9280_20_LATER)
1327 status = ah->eep_ops->set_txpower(ah, chan,
1328 ath9k_regd_get_ctl(ah, chan),
1329 channel->max_antenna_gain * 2,
1330 channel->max_power * 2,
1331 min((u32) MAX_RATE_POWER,
1332 (u32) ah->regulatory.power_limit));
1334 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1335 "error init'ing transmit power\n");
1339 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1340 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1341 "ar5416SetRfRegs failed\n");
1348 /****************************************/
1349 /* Reset and Channel Switching Routines */
1350 /****************************************/
1352 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1359 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1360 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1362 if (!AR_SREV_9280_10_OR_LATER(ah))
1363 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1364 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1366 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1367 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1369 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1372 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1374 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1377 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1381 regval = REG_READ(ah, AR_AHB_MODE);
1382 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1384 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1385 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1387 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1389 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1390 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1392 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1394 if (AR_SREV_9285(ah)) {
1395 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1396 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1398 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1399 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1403 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1407 val = REG_READ(ah, AR_STA_ID1);
1408 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1410 case NL80211_IFTYPE_AP:
1411 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1412 | AR_STA_ID1_KSRCH_MODE);
1413 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1415 case NL80211_IFTYPE_ADHOC:
1416 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1417 | AR_STA_ID1_KSRCH_MODE);
1418 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1420 case NL80211_IFTYPE_STATION:
1421 case NL80211_IFTYPE_MONITOR:
1422 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1427 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1432 u32 coef_exp, coef_man;
1434 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1435 if ((coef_scaled >> coef_exp) & 0x1)
1438 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1440 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1442 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1443 *coef_exponent = coef_exp - 16;
1446 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1447 struct ath9k_channel *chan)
1449 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1450 u32 clockMhzScaled = 0x64000000;
1451 struct chan_centers centers;
1453 if (IS_CHAN_HALF_RATE(chan))
1454 clockMhzScaled = clockMhzScaled >> 1;
1455 else if (IS_CHAN_QUARTER_RATE(chan))
1456 clockMhzScaled = clockMhzScaled >> 2;
1458 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1459 coef_scaled = clockMhzScaled / centers.synth_center;
1461 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1464 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1465 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1466 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1467 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1469 coef_scaled = (9 * coef_scaled) / 10;
1471 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1474 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1475 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1476 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1477 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1480 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1485 if (AR_SREV_9100(ah)) {
1486 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1487 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1488 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1489 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1490 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1493 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1494 AR_RTC_FORCE_WAKE_ON_INT);
1496 if (AR_SREV_9100(ah)) {
1497 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1498 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1500 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1502 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1503 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1504 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1505 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1507 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1510 rst_flags = AR_RTC_RC_MAC_WARM;
1511 if (type == ATH9K_RESET_COLD)
1512 rst_flags |= AR_RTC_RC_MAC_COLD;
1515 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1518 REG_WRITE(ah, AR_RTC_RC, 0);
1519 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1520 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1521 "RTC stuck in MAC reset\n");
1525 if (!AR_SREV_9100(ah))
1526 REG_WRITE(ah, AR_RC, 0);
1528 ath9k_hw_init_pll(ah, NULL);
1530 if (AR_SREV_9100(ah))
1536 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1538 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1539 AR_RTC_FORCE_WAKE_ON_INT);
1541 REG_WRITE(ah, AR_RTC_RESET, 0);
1543 REG_WRITE(ah, AR_RTC_RESET, 1);
1545 if (!ath9k_hw_wait(ah,
1550 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1554 ath9k_hw_read_revisions(ah);
1556 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1559 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1561 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1562 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1565 case ATH9K_RESET_POWER_ON:
1566 return ath9k_hw_set_reset_power_on(ah);
1568 case ATH9K_RESET_WARM:
1569 case ATH9K_RESET_COLD:
1570 return ath9k_hw_set_reset(ah, type);
1577 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1578 enum ath9k_ht_macmode macmode)
1581 u32 enableDacFifo = 0;
1583 if (AR_SREV_9285_10_OR_LATER(ah))
1584 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1585 AR_PHY_FC_ENABLE_DAC_FIFO);
1587 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1588 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1590 if (IS_CHAN_HT40(chan)) {
1591 phymode |= AR_PHY_FC_DYN2040_EN;
1593 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1594 (chan->chanmode == CHANNEL_G_HT40PLUS))
1595 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1597 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1598 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1600 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1602 ath9k_hw_set11nmac2040(ah, macmode);
1604 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1605 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1608 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1609 struct ath9k_channel *chan)
1611 if (OLC_FOR_AR9280_20_LATER) {
1612 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1614 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1617 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1620 ah->chip_fullsleep = false;
1621 ath9k_hw_init_pll(ah, chan);
1622 ath9k_hw_set_rfmode(ah, chan);
1627 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1628 struct ath9k_channel *chan,
1629 enum ath9k_ht_macmode macmode)
1631 struct ieee80211_channel *channel = chan->chan;
1632 u32 synthDelay, qnum;
1634 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1635 if (ath9k_hw_numtxpending(ah, qnum)) {
1636 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1637 "Transmit frames pending on queue %d\n", qnum);
1642 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1643 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1644 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1645 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1646 "Could not kill baseband RX\n");
1650 ath9k_hw_set_regs(ah, chan, macmode);
1652 if (AR_SREV_9280_10_OR_LATER(ah)) {
1653 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1654 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1655 "failed to set channel\n");
1659 if (!(ath9k_hw_set_channel(ah, chan))) {
1660 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1661 "failed to set channel\n");
1666 if (ah->eep_ops->set_txpower(ah, chan,
1667 ath9k_regd_get_ctl(ah, chan),
1668 channel->max_antenna_gain * 2,
1669 channel->max_power * 2,
1670 min((u32) MAX_RATE_POWER,
1671 (u32) ah->regulatory.power_limit)) != 0) {
1672 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1673 "error init'ing transmit power\n");
1677 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1678 if (IS_CHAN_B(chan))
1679 synthDelay = (4 * synthDelay) / 22;
1683 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1685 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1687 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1688 ath9k_hw_set_delta_slope(ah, chan);
1690 if (AR_SREV_9280_10_OR_LATER(ah))
1691 ath9k_hw_9280_spur_mitigate(ah, chan);
1693 ath9k_hw_spur_mitigate(ah, chan);
1695 if (!chan->oneTimeCalsDone)
1696 chan->oneTimeCalsDone = true;
1701 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1703 int bb_spur = AR_NO_SPUR;
1706 int bb_spur_off, spur_subchannel_sd;
1708 int spur_delta_phase;
1710 int upper, lower, cur_vit_mask;
1713 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1714 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1716 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1717 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1719 int inc[4] = { 0, 100, 0, 0 };
1720 struct chan_centers centers;
1727 bool is2GHz = IS_CHAN_2GHZ(chan);
1729 memset(&mask_m, 0, sizeof(int8_t) * 123);
1730 memset(&mask_p, 0, sizeof(int8_t) * 123);
1732 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1733 freq = centers.synth_center;
1735 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1736 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1737 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1740 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1742 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1744 if (AR_NO_SPUR == cur_bb_spur)
1746 cur_bb_spur = cur_bb_spur - freq;
1748 if (IS_CHAN_HT40(chan)) {
1749 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1750 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1751 bb_spur = cur_bb_spur;
1754 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1755 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1756 bb_spur = cur_bb_spur;
1761 if (AR_NO_SPUR == bb_spur) {
1762 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1763 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1766 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1767 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1770 bin = bb_spur * 320;
1772 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1774 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1775 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1776 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1777 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1778 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1780 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1781 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1782 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1783 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1784 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1785 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1787 if (IS_CHAN_HT40(chan)) {
1789 spur_subchannel_sd = 1;
1790 bb_spur_off = bb_spur + 10;
1792 spur_subchannel_sd = 0;
1793 bb_spur_off = bb_spur - 10;
1796 spur_subchannel_sd = 0;
1797 bb_spur_off = bb_spur;
1800 if (IS_CHAN_HT40(chan))
1802 ((bb_spur * 262144) /
1803 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1806 ((bb_spur * 524288) /
1807 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1809 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1810 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1812 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1813 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1814 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1815 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1817 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1818 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1824 for (i = 0; i < 4; i++) {
1828 for (bp = 0; bp < 30; bp++) {
1829 if ((cur_bin > lower) && (cur_bin < upper)) {
1830 pilot_mask = pilot_mask | 0x1 << bp;
1831 chan_mask = chan_mask | 0x1 << bp;
1836 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1837 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1840 cur_vit_mask = 6100;
1844 for (i = 0; i < 123; i++) {
1845 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1847 /* workaround for gcc bug #37014 */
1848 volatile int tmp_v = abs(cur_vit_mask - bin);
1854 if (cur_vit_mask < 0)
1855 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1857 mask_p[cur_vit_mask / 100] = mask_amt;
1859 cur_vit_mask -= 100;
1862 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1863 | (mask_m[48] << 26) | (mask_m[49] << 24)
1864 | (mask_m[50] << 22) | (mask_m[51] << 20)
1865 | (mask_m[52] << 18) | (mask_m[53] << 16)
1866 | (mask_m[54] << 14) | (mask_m[55] << 12)
1867 | (mask_m[56] << 10) | (mask_m[57] << 8)
1868 | (mask_m[58] << 6) | (mask_m[59] << 4)
1869 | (mask_m[60] << 2) | (mask_m[61] << 0);
1870 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1871 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1873 tmp_mask = (mask_m[31] << 28)
1874 | (mask_m[32] << 26) | (mask_m[33] << 24)
1875 | (mask_m[34] << 22) | (mask_m[35] << 20)
1876 | (mask_m[36] << 18) | (mask_m[37] << 16)
1877 | (mask_m[48] << 14) | (mask_m[39] << 12)
1878 | (mask_m[40] << 10) | (mask_m[41] << 8)
1879 | (mask_m[42] << 6) | (mask_m[43] << 4)
1880 | (mask_m[44] << 2) | (mask_m[45] << 0);
1881 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1882 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1884 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1885 | (mask_m[18] << 26) | (mask_m[18] << 24)
1886 | (mask_m[20] << 22) | (mask_m[20] << 20)
1887 | (mask_m[22] << 18) | (mask_m[22] << 16)
1888 | (mask_m[24] << 14) | (mask_m[24] << 12)
1889 | (mask_m[25] << 10) | (mask_m[26] << 8)
1890 | (mask_m[27] << 6) | (mask_m[28] << 4)
1891 | (mask_m[29] << 2) | (mask_m[30] << 0);
1892 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1893 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1895 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1896 | (mask_m[2] << 26) | (mask_m[3] << 24)
1897 | (mask_m[4] << 22) | (mask_m[5] << 20)
1898 | (mask_m[6] << 18) | (mask_m[7] << 16)
1899 | (mask_m[8] << 14) | (mask_m[9] << 12)
1900 | (mask_m[10] << 10) | (mask_m[11] << 8)
1901 | (mask_m[12] << 6) | (mask_m[13] << 4)
1902 | (mask_m[14] << 2) | (mask_m[15] << 0);
1903 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1904 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1906 tmp_mask = (mask_p[15] << 28)
1907 | (mask_p[14] << 26) | (mask_p[13] << 24)
1908 | (mask_p[12] << 22) | (mask_p[11] << 20)
1909 | (mask_p[10] << 18) | (mask_p[9] << 16)
1910 | (mask_p[8] << 14) | (mask_p[7] << 12)
1911 | (mask_p[6] << 10) | (mask_p[5] << 8)
1912 | (mask_p[4] << 6) | (mask_p[3] << 4)
1913 | (mask_p[2] << 2) | (mask_p[1] << 0);
1914 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1915 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1917 tmp_mask = (mask_p[30] << 28)
1918 | (mask_p[29] << 26) | (mask_p[28] << 24)
1919 | (mask_p[27] << 22) | (mask_p[26] << 20)
1920 | (mask_p[25] << 18) | (mask_p[24] << 16)
1921 | (mask_p[23] << 14) | (mask_p[22] << 12)
1922 | (mask_p[21] << 10) | (mask_p[20] << 8)
1923 | (mask_p[19] << 6) | (mask_p[18] << 4)
1924 | (mask_p[17] << 2) | (mask_p[16] << 0);
1925 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1926 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1928 tmp_mask = (mask_p[45] << 28)
1929 | (mask_p[44] << 26) | (mask_p[43] << 24)
1930 | (mask_p[42] << 22) | (mask_p[41] << 20)
1931 | (mask_p[40] << 18) | (mask_p[39] << 16)
1932 | (mask_p[38] << 14) | (mask_p[37] << 12)
1933 | (mask_p[36] << 10) | (mask_p[35] << 8)
1934 | (mask_p[34] << 6) | (mask_p[33] << 4)
1935 | (mask_p[32] << 2) | (mask_p[31] << 0);
1936 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1937 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1939 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1940 | (mask_p[59] << 26) | (mask_p[58] << 24)
1941 | (mask_p[57] << 22) | (mask_p[56] << 20)
1942 | (mask_p[55] << 18) | (mask_p[54] << 16)
1943 | (mask_p[53] << 14) | (mask_p[52] << 12)
1944 | (mask_p[51] << 10) | (mask_p[50] << 8)
1945 | (mask_p[49] << 6) | (mask_p[48] << 4)
1946 | (mask_p[47] << 2) | (mask_p[46] << 0);
1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1948 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1951 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1953 int bb_spur = AR_NO_SPUR;
1956 int spur_delta_phase;
1958 int upper, lower, cur_vit_mask;
1961 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1962 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1964 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1965 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1967 int inc[4] = { 0, 100, 0, 0 };
1974 bool is2GHz = IS_CHAN_2GHZ(chan);
1976 memset(&mask_m, 0, sizeof(int8_t) * 123);
1977 memset(&mask_p, 0, sizeof(int8_t) * 123);
1979 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1980 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1981 if (AR_NO_SPUR == cur_bb_spur)
1983 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1984 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1985 bb_spur = cur_bb_spur;
1990 if (AR_NO_SPUR == bb_spur)
1995 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1996 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1997 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1998 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1999 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2001 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2003 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2004 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2005 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2006 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2007 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2008 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2010 spur_delta_phase = ((bb_spur * 524288) / 100) &
2011 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2013 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2014 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2016 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2017 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2018 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2019 REG_WRITE(ah, AR_PHY_TIMING11, new);
2025 for (i = 0; i < 4; i++) {
2029 for (bp = 0; bp < 30; bp++) {
2030 if ((cur_bin > lower) && (cur_bin < upper)) {
2031 pilot_mask = pilot_mask | 0x1 << bp;
2032 chan_mask = chan_mask | 0x1 << bp;
2037 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2038 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2041 cur_vit_mask = 6100;
2045 for (i = 0; i < 123; i++) {
2046 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2048 /* workaround for gcc bug #37014 */
2049 volatile int tmp_v = abs(cur_vit_mask - bin);
2055 if (cur_vit_mask < 0)
2056 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2058 mask_p[cur_vit_mask / 100] = mask_amt;
2060 cur_vit_mask -= 100;
2063 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2064 | (mask_m[48] << 26) | (mask_m[49] << 24)
2065 | (mask_m[50] << 22) | (mask_m[51] << 20)
2066 | (mask_m[52] << 18) | (mask_m[53] << 16)
2067 | (mask_m[54] << 14) | (mask_m[55] << 12)
2068 | (mask_m[56] << 10) | (mask_m[57] << 8)
2069 | (mask_m[58] << 6) | (mask_m[59] << 4)
2070 | (mask_m[60] << 2) | (mask_m[61] << 0);
2071 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2072 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2074 tmp_mask = (mask_m[31] << 28)
2075 | (mask_m[32] << 26) | (mask_m[33] << 24)
2076 | (mask_m[34] << 22) | (mask_m[35] << 20)
2077 | (mask_m[36] << 18) | (mask_m[37] << 16)
2078 | (mask_m[48] << 14) | (mask_m[39] << 12)
2079 | (mask_m[40] << 10) | (mask_m[41] << 8)
2080 | (mask_m[42] << 6) | (mask_m[43] << 4)
2081 | (mask_m[44] << 2) | (mask_m[45] << 0);
2082 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2083 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2085 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2086 | (mask_m[18] << 26) | (mask_m[18] << 24)
2087 | (mask_m[20] << 22) | (mask_m[20] << 20)
2088 | (mask_m[22] << 18) | (mask_m[22] << 16)
2089 | (mask_m[24] << 14) | (mask_m[24] << 12)
2090 | (mask_m[25] << 10) | (mask_m[26] << 8)
2091 | (mask_m[27] << 6) | (mask_m[28] << 4)
2092 | (mask_m[29] << 2) | (mask_m[30] << 0);
2093 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2094 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2096 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2097 | (mask_m[2] << 26) | (mask_m[3] << 24)
2098 | (mask_m[4] << 22) | (mask_m[5] << 20)
2099 | (mask_m[6] << 18) | (mask_m[7] << 16)
2100 | (mask_m[8] << 14) | (mask_m[9] << 12)
2101 | (mask_m[10] << 10) | (mask_m[11] << 8)
2102 | (mask_m[12] << 6) | (mask_m[13] << 4)
2103 | (mask_m[14] << 2) | (mask_m[15] << 0);
2104 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2107 tmp_mask = (mask_p[15] << 28)
2108 | (mask_p[14] << 26) | (mask_p[13] << 24)
2109 | (mask_p[12] << 22) | (mask_p[11] << 20)
2110 | (mask_p[10] << 18) | (mask_p[9] << 16)
2111 | (mask_p[8] << 14) | (mask_p[7] << 12)
2112 | (mask_p[6] << 10) | (mask_p[5] << 8)
2113 | (mask_p[4] << 6) | (mask_p[3] << 4)
2114 | (mask_p[2] << 2) | (mask_p[1] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2118 tmp_mask = (mask_p[30] << 28)
2119 | (mask_p[29] << 26) | (mask_p[28] << 24)
2120 | (mask_p[27] << 22) | (mask_p[26] << 20)
2121 | (mask_p[25] << 18) | (mask_p[24] << 16)
2122 | (mask_p[23] << 14) | (mask_p[22] << 12)
2123 | (mask_p[21] << 10) | (mask_p[20] << 8)
2124 | (mask_p[19] << 6) | (mask_p[18] << 4)
2125 | (mask_p[17] << 2) | (mask_p[16] << 0);
2126 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2129 tmp_mask = (mask_p[45] << 28)
2130 | (mask_p[44] << 26) | (mask_p[43] << 24)
2131 | (mask_p[42] << 22) | (mask_p[41] << 20)
2132 | (mask_p[40] << 18) | (mask_p[39] << 16)
2133 | (mask_p[38] << 14) | (mask_p[37] << 12)
2134 | (mask_p[36] << 10) | (mask_p[35] << 8)
2135 | (mask_p[34] << 6) | (mask_p[33] << 4)
2136 | (mask_p[32] << 2) | (mask_p[31] << 0);
2137 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2138 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2140 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2141 | (mask_p[59] << 26) | (mask_p[58] << 24)
2142 | (mask_p[57] << 22) | (mask_p[56] << 20)
2143 | (mask_p[55] << 18) | (mask_p[54] << 16)
2144 | (mask_p[53] << 14) | (mask_p[52] << 12)
2145 | (mask_p[51] << 10) | (mask_p[50] << 8)
2146 | (mask_p[49] << 6) | (mask_p[48] << 4)
2147 | (mask_p[47] << 2) | (mask_p[46] << 0);
2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2149 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2152 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2153 bool bChannelChange)
2156 struct ath_softc *sc = ah->ah_sc;
2157 struct ath9k_channel *curchan = ah->curchan;
2160 int i, rx_chainmask, r;
2162 ah->extprotspacing = sc->ht_extprotspacing;
2163 ah->txchainmask = sc->tx_chainmask;
2164 ah->rxchainmask = sc->rx_chainmask;
2166 if (AR_SREV_9285(ah)) {
2167 ah->txchainmask &= 0x1;
2168 ah->rxchainmask &= 0x1;
2169 } else if (AR_SREV_9280(ah)) {
2170 ah->txchainmask &= 0x3;
2171 ah->rxchainmask &= 0x3;
2174 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2178 ath9k_hw_getnf(ah, curchan);
2180 if (bChannelChange &&
2181 (ah->chip_fullsleep != true) &&
2182 (ah->curchan != NULL) &&
2183 (chan->channel != ah->curchan->channel) &&
2184 ((chan->channelFlags & CHANNEL_ALL) ==
2185 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2186 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2187 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2189 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2190 ath9k_hw_loadnf(ah, ah->curchan);
2191 ath9k_hw_start_nfcal(ah);
2196 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2197 if (saveDefAntenna == 0)
2200 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2202 saveLedState = REG_READ(ah, AR_CFG_LED) &
2203 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2204 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2206 ath9k_hw_mark_phy_inactive(ah);
2208 if (!ath9k_hw_chip_reset(ah, chan)) {
2209 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2213 if (AR_SREV_9280_10_OR_LATER(ah))
2214 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2216 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2220 /* Setup MFP options for CCMP */
2221 if (AR_SREV_9280_20_OR_LATER(ah)) {
2222 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2223 * frames when constructing CCMP AAD. */
2224 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2226 ah->sw_mgmt_crypto = false;
2227 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2228 /* Disable hardware crypto for management frames */
2229 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2230 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2231 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2232 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2233 ah->sw_mgmt_crypto = true;
2235 ah->sw_mgmt_crypto = true;
2237 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2238 ath9k_hw_set_delta_slope(ah, chan);
2240 if (AR_SREV_9280_10_OR_LATER(ah))
2241 ath9k_hw_9280_spur_mitigate(ah, chan);
2243 ath9k_hw_spur_mitigate(ah, chan);
2245 if (!ah->eep_ops->set_board_values(ah, chan)) {
2246 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2247 "error setting board options\n");
2251 ath9k_hw_decrease_chain_power(ah, chan);
2253 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2254 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2256 | AR_STA_ID1_RTS_USE_DEF
2258 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2259 | ah->sta_id1_defaults);
2260 ath9k_hw_set_operating_mode(ah, ah->opmode);
2262 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2263 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2265 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2267 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2268 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2269 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2271 REG_WRITE(ah, AR_ISR, ~0);
2273 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2275 if (AR_SREV_9280_10_OR_LATER(ah)) {
2276 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2279 if (!(ath9k_hw_set_channel(ah, chan)))
2283 for (i = 0; i < AR_NUM_DCU; i++)
2284 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2287 for (i = 0; i < ah->caps.total_queues; i++)
2288 ath9k_hw_resettxqueue(ah, i);
2290 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2291 ath9k_hw_init_qos(ah);
2293 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2294 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2295 ath9k_enable_rfkill(ah);
2297 ath9k_hw_init_user_settings(ah);
2299 REG_WRITE(ah, AR_STA_ID1,
2300 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2302 ath9k_hw_set_dma(ah);
2304 REG_WRITE(ah, AR_OBS, 8);
2306 if (ah->intr_mitigation) {
2308 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2309 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2312 ath9k_hw_init_bb(ah, chan);
2314 if (!ath9k_hw_init_cal(ah, chan))
2317 rx_chainmask = ah->rxchainmask;
2318 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2319 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2320 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2323 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2325 if (AR_SREV_9100(ah)) {
2327 mask = REG_READ(ah, AR_CFG);
2328 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2329 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2330 "CFG Byte Swap Set 0x%x\n", mask);
2333 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2334 REG_WRITE(ah, AR_CFG, mask);
2335 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2336 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2340 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2347 /************************/
2348 /* Key Cache Management */
2349 /************************/
2351 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2355 if (entry >= ah->caps.keycache_size) {
2356 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2357 "entry %u out of range\n", entry);
2361 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2363 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2364 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2366 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2367 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2368 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2369 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2370 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2372 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2373 u16 micentry = entry + 64;
2375 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2376 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2377 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2378 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2382 if (ah->curchan == NULL)
2388 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2392 if (entry >= ah->caps.keycache_size) {
2393 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2394 "entry %u out of range\n", entry);
2399 macHi = (mac[5] << 8) | mac[4];
2400 macLo = (mac[3] << 24) |
2405 macLo |= (macHi & 1) << 31;
2410 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2411 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2416 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2417 const struct ath9k_keyval *k,
2418 const u8 *mac, int xorKey)
2420 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2421 u32 key0, key1, key2, key3, key4;
2423 u32 xorMask = xorKey ?
2424 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2425 | ATH9K_KEY_XOR) : 0;
2427 if (entry >= pCap->keycache_size) {
2428 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2429 "entry %u out of range\n", entry);
2433 switch (k->kv_type) {
2434 case ATH9K_CIPHER_AES_OCB:
2435 keyType = AR_KEYTABLE_TYPE_AES;
2437 case ATH9K_CIPHER_AES_CCM:
2438 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2439 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2440 "AES-CCM not supported by mac rev 0x%x\n",
2441 ah->hw_version.macRev);
2444 keyType = AR_KEYTABLE_TYPE_CCM;
2446 case ATH9K_CIPHER_TKIP:
2447 keyType = AR_KEYTABLE_TYPE_TKIP;
2448 if (ATH9K_IS_MIC_ENABLED(ah)
2449 && entry + 64 >= pCap->keycache_size) {
2450 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2451 "entry %u inappropriate for TKIP\n", entry);
2455 case ATH9K_CIPHER_WEP:
2456 if (k->kv_len < LEN_WEP40) {
2457 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2458 "WEP key length %u too small\n", k->kv_len);
2461 if (k->kv_len <= LEN_WEP40)
2462 keyType = AR_KEYTABLE_TYPE_40;
2463 else if (k->kv_len <= LEN_WEP104)
2464 keyType = AR_KEYTABLE_TYPE_104;
2466 keyType = AR_KEYTABLE_TYPE_128;
2468 case ATH9K_CIPHER_CLR:
2469 keyType = AR_KEYTABLE_TYPE_CLR;
2472 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2473 "cipher %u not supported\n", k->kv_type);
2477 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2478 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2479 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2480 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2481 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2482 if (k->kv_len <= LEN_WEP104)
2485 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2486 u16 micentry = entry + 64;
2488 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2489 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2490 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2491 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2492 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2493 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2494 (void) ath9k_hw_keysetmac(ah, entry, mac);
2496 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2497 u32 mic0, mic1, mic2, mic3, mic4;
2499 mic0 = get_unaligned_le32(k->kv_mic + 0);
2500 mic2 = get_unaligned_le32(k->kv_mic + 4);
2501 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2502 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2503 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2504 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2505 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2506 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2507 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2508 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2509 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2510 AR_KEYTABLE_TYPE_CLR);
2515 mic0 = get_unaligned_le32(k->kv_mic + 0);
2516 mic2 = get_unaligned_le32(k->kv_mic + 4);
2517 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2518 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2519 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2520 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2521 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2522 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2523 AR_KEYTABLE_TYPE_CLR);
2525 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2526 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2527 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2528 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2530 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2531 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2532 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2533 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2534 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2535 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2537 (void) ath9k_hw_keysetmac(ah, entry, mac);
2540 if (ah->curchan == NULL)
2546 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2548 if (entry < ah->caps.keycache_size) {
2549 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2550 if (val & AR_KEYTABLE_VALID)
2556 /******************************/
2557 /* Power Management (Chipset) */
2558 /******************************/
2560 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2562 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2564 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2565 AR_RTC_FORCE_WAKE_EN);
2566 if (!AR_SREV_9100(ah))
2567 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2569 REG_CLR_BIT(ah, (AR_RTC_RESET),
2574 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2576 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2578 struct ath9k_hw_capabilities *pCap = &ah->caps;
2580 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2581 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2582 AR_RTC_FORCE_WAKE_ON_INT);
2584 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2585 AR_RTC_FORCE_WAKE_EN);
2590 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2596 if ((REG_READ(ah, AR_RTC_STATUS) &
2597 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2598 if (ath9k_hw_set_reset_reg(ah,
2599 ATH9K_RESET_POWER_ON) != true) {
2603 if (AR_SREV_9100(ah))
2604 REG_SET_BIT(ah, AR_RTC_RESET,
2607 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2608 AR_RTC_FORCE_WAKE_EN);
2611 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2612 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2613 if (val == AR_RTC_STATUS_ON)
2616 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2617 AR_RTC_FORCE_WAKE_EN);
2620 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2621 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2626 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2631 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2633 int status = true, setChip = true;
2634 static const char *modes[] = {
2641 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2642 modes[ah->power_mode], modes[mode],
2643 setChip ? "set chip " : "");
2646 case ATH9K_PM_AWAKE:
2647 status = ath9k_hw_set_power_awake(ah, setChip);
2649 case ATH9K_PM_FULL_SLEEP:
2650 ath9k_set_power_sleep(ah, setChip);
2651 ah->chip_fullsleep = true;
2653 case ATH9K_PM_NETWORK_SLEEP:
2654 ath9k_set_power_network_sleep(ah, setChip);
2657 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2658 "Unknown power mode %u\n", mode);
2661 ah->power_mode = mode;
2667 * Helper for ASPM support.
2669 * Disable PLL when in L0s as well as receiver clock when in L1.
2670 * This power saving option must be enabled through the SerDes.
2672 * Programming the SerDes must go through the same 288 bit serial shift
2673 * register as the other analog registers. Hence the 9 writes.
2675 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2679 if (ah->is_pciexpress != true)
2682 /* Do not touch SerDes registers */
2683 if (ah->config.pcie_powersave_enable == 2)
2686 /* Nothing to do on restore for 11N */
2690 if (AR_SREV_9280_20_OR_LATER(ah)) {
2692 * AR9280 2.0 or later chips use SerDes values from the
2693 * initvals.h initialized depending on chipset during
2694 * ath9k_hw_do_attach()
2696 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2697 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2698 INI_RA(&ah->iniPcieSerdes, i, 1));
2700 } else if (AR_SREV_9280(ah) &&
2701 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2702 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2703 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2705 /* RX shut off when elecidle is asserted */
2706 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2707 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2708 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2710 /* Shut off CLKREQ active in L1 */
2711 if (ah->config.pcie_clock_req)
2712 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2714 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2716 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2717 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2718 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2720 /* Load the new settings */
2721 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2724 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2725 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2727 /* RX shut off when elecidle is asserted */
2728 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2729 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2730 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2733 * Ignore ah->ah_config.pcie_clock_req setting for
2736 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2738 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2739 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2740 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2742 /* Load the new settings */
2743 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2748 /* set bit 19 to allow forcing of pcie core into L1 state */
2749 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2751 /* Several PCIe massages to ensure proper behaviour */
2752 if (ah->config.pcie_waen) {
2753 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2755 if (AR_SREV_9285(ah))
2756 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2758 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2759 * otherwise card may disappear.
2761 else if (AR_SREV_9280(ah))
2762 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2764 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2768 /**********************/
2769 /* Interrupt Handling */
2770 /**********************/
2772 bool ath9k_hw_intrpend(struct ath_hw *ah)
2776 if (AR_SREV_9100(ah))
2779 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2780 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2783 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2784 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2785 && (host_isr != AR_INTR_SPURIOUS))
2791 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2795 struct ath9k_hw_capabilities *pCap = &ah->caps;
2797 bool fatal_int = false;
2799 if (!AR_SREV_9100(ah)) {
2800 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2801 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2802 == AR_RTC_STATUS_ON) {
2803 isr = REG_READ(ah, AR_ISR);
2807 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2808 AR_INTR_SYNC_DEFAULT;
2812 if (!isr && !sync_cause)
2816 isr = REG_READ(ah, AR_ISR);
2820 if (isr & AR_ISR_BCNMISC) {
2822 isr2 = REG_READ(ah, AR_ISR_S2);
2823 if (isr2 & AR_ISR_S2_TIM)
2824 mask2 |= ATH9K_INT_TIM;
2825 if (isr2 & AR_ISR_S2_DTIM)
2826 mask2 |= ATH9K_INT_DTIM;
2827 if (isr2 & AR_ISR_S2_DTIMSYNC)
2828 mask2 |= ATH9K_INT_DTIMSYNC;
2829 if (isr2 & (AR_ISR_S2_CABEND))
2830 mask2 |= ATH9K_INT_CABEND;
2831 if (isr2 & AR_ISR_S2_GTT)
2832 mask2 |= ATH9K_INT_GTT;
2833 if (isr2 & AR_ISR_S2_CST)
2834 mask2 |= ATH9K_INT_CST;
2835 if (isr2 & AR_ISR_S2_TSFOOR)
2836 mask2 |= ATH9K_INT_TSFOOR;
2839 isr = REG_READ(ah, AR_ISR_RAC);
2840 if (isr == 0xffffffff) {
2845 *masked = isr & ATH9K_INT_COMMON;
2847 if (ah->intr_mitigation) {
2848 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2849 *masked |= ATH9K_INT_RX;
2852 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2853 *masked |= ATH9K_INT_RX;
2855 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2859 *masked |= ATH9K_INT_TX;
2861 s0_s = REG_READ(ah, AR_ISR_S0_S);
2862 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2863 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2865 s1_s = REG_READ(ah, AR_ISR_S1_S);
2866 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2867 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2870 if (isr & AR_ISR_RXORN) {
2871 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2872 "receive FIFO overrun interrupt\n");
2875 if (!AR_SREV_9100(ah)) {
2876 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2877 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2878 if (isr5 & AR_ISR_S5_TIM_TIMER)
2879 *masked |= ATH9K_INT_TIM_TIMER;
2886 if (AR_SREV_9100(ah))
2892 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2896 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2897 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2898 "received PCI FATAL interrupt\n");
2900 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2901 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2902 "received PCI PERR interrupt\n");
2905 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2906 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2907 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2908 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2909 REG_WRITE(ah, AR_RC, 0);
2910 *masked |= ATH9K_INT_FATAL;
2912 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2913 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2914 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2917 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2918 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2924 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2926 return ah->mask_reg;
2929 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2931 u32 omask = ah->mask_reg;
2933 struct ath9k_hw_capabilities *pCap = &ah->caps;
2935 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2937 if (omask & ATH9K_INT_GLOBAL) {
2938 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2939 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2940 (void) REG_READ(ah, AR_IER);
2941 if (!AR_SREV_9100(ah)) {
2942 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2943 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2945 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2946 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2950 mask = ints & ATH9K_INT_COMMON;
2953 if (ints & ATH9K_INT_TX) {
2954 if (ah->txok_interrupt_mask)
2955 mask |= AR_IMR_TXOK;
2956 if (ah->txdesc_interrupt_mask)
2957 mask |= AR_IMR_TXDESC;
2958 if (ah->txerr_interrupt_mask)
2959 mask |= AR_IMR_TXERR;
2960 if (ah->txeol_interrupt_mask)
2961 mask |= AR_IMR_TXEOL;
2963 if (ints & ATH9K_INT_RX) {
2964 mask |= AR_IMR_RXERR;
2965 if (ah->intr_mitigation)
2966 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2968 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2969 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2970 mask |= AR_IMR_GENTMR;
2973 if (ints & (ATH9K_INT_BMISC)) {
2974 mask |= AR_IMR_BCNMISC;
2975 if (ints & ATH9K_INT_TIM)
2976 mask2 |= AR_IMR_S2_TIM;
2977 if (ints & ATH9K_INT_DTIM)
2978 mask2 |= AR_IMR_S2_DTIM;
2979 if (ints & ATH9K_INT_DTIMSYNC)
2980 mask2 |= AR_IMR_S2_DTIMSYNC;
2981 if (ints & ATH9K_INT_CABEND)
2982 mask2 |= AR_IMR_S2_CABEND;
2983 if (ints & ATH9K_INT_TSFOOR)
2984 mask2 |= AR_IMR_S2_TSFOOR;
2987 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2988 mask |= AR_IMR_BCNMISC;
2989 if (ints & ATH9K_INT_GTT)
2990 mask2 |= AR_IMR_S2_GTT;
2991 if (ints & ATH9K_INT_CST)
2992 mask2 |= AR_IMR_S2_CST;
2995 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2996 REG_WRITE(ah, AR_IMR, mask);
2997 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2999 AR_IMR_S2_DTIMSYNC |
3003 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3004 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3005 ah->mask_reg = ints;
3007 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3008 if (ints & ATH9K_INT_TIM_TIMER)
3009 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3011 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3014 if (ints & ATH9K_INT_GLOBAL) {
3015 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3016 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3017 if (!AR_SREV_9100(ah)) {
3018 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3020 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3023 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3024 AR_INTR_SYNC_DEFAULT);
3025 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3026 AR_INTR_SYNC_DEFAULT);
3028 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3029 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3035 /*******************/
3036 /* Beacon Handling */
3037 /*******************/
3039 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3043 ah->beacon_interval = beacon_period;
3045 switch (ah->opmode) {
3046 case NL80211_IFTYPE_STATION:
3047 case NL80211_IFTYPE_MONITOR:
3048 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3049 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3050 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3051 flags |= AR_TBTT_TIMER_EN;
3053 case NL80211_IFTYPE_ADHOC:
3054 REG_SET_BIT(ah, AR_TXCFG,
3055 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3056 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3057 TU_TO_USEC(next_beacon +
3058 (ah->atim_window ? ah->
3060 flags |= AR_NDP_TIMER_EN;
3061 case NL80211_IFTYPE_AP:
3062 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3063 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3064 TU_TO_USEC(next_beacon -
3066 dma_beacon_response_time));
3067 REG_WRITE(ah, AR_NEXT_SWBA,
3068 TU_TO_USEC(next_beacon -
3070 sw_beacon_response_time));
3072 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3075 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3076 "%s: unsupported opmode: %d\n",
3077 __func__, ah->opmode);
3082 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3083 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3084 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3085 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3087 beacon_period &= ~ATH9K_BEACON_ENA;
3088 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3089 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3090 ath9k_hw_reset_tsf(ah);
3093 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3096 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3097 const struct ath9k_beacon_state *bs)
3099 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3100 struct ath9k_hw_capabilities *pCap = &ah->caps;
3102 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3104 REG_WRITE(ah, AR_BEACON_PERIOD,
3105 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3106 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3107 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3109 REG_RMW_FIELD(ah, AR_RSSI_THR,
3110 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3112 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3114 if (bs->bs_sleepduration > beaconintval)
3115 beaconintval = bs->bs_sleepduration;
3117 dtimperiod = bs->bs_dtimperiod;
3118 if (bs->bs_sleepduration > dtimperiod)
3119 dtimperiod = bs->bs_sleepduration;
3121 if (beaconintval == dtimperiod)
3122 nextTbtt = bs->bs_nextdtim;
3124 nextTbtt = bs->bs_nexttbtt;
3126 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3127 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3128 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3129 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3131 REG_WRITE(ah, AR_NEXT_DTIM,
3132 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3133 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3135 REG_WRITE(ah, AR_SLEEP1,
3136 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3137 | AR_SLEEP1_ASSUME_DTIM);
3139 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3140 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3142 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3144 REG_WRITE(ah, AR_SLEEP2,
3145 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3147 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3148 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3150 REG_SET_BIT(ah, AR_TIMER_MODE,
3151 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3154 /* TSF Out of Range Threshold */
3155 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3158 /*******************/
3159 /* HW Capabilities */
3160 /*******************/
3162 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3164 struct ath9k_hw_capabilities *pCap = &ah->caps;
3165 u16 capField = 0, eeval;
3167 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3168 ah->regulatory.current_rd = eeval;
3170 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3171 if (AR_SREV_9285_10_OR_LATER(ah))
3172 eeval |= AR9285_RDEXT_DEFAULT;
3173 ah->regulatory.current_rd_ext = eeval;
3175 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3177 if (ah->opmode != NL80211_IFTYPE_AP &&
3178 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3179 if (ah->regulatory.current_rd == 0x64 ||
3180 ah->regulatory.current_rd == 0x65)
3181 ah->regulatory.current_rd += 5;
3182 else if (ah->regulatory.current_rd == 0x41)
3183 ah->regulatory.current_rd = 0x43;
3184 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3185 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3188 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3189 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3191 if (eeval & AR5416_OPFLAGS_11A) {
3192 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3193 if (ah->config.ht_enable) {
3194 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3195 set_bit(ATH9K_MODE_11NA_HT20,
3196 pCap->wireless_modes);
3197 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3198 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3199 pCap->wireless_modes);
3200 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3201 pCap->wireless_modes);
3206 if (eeval & AR5416_OPFLAGS_11G) {
3207 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3208 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3209 if (ah->config.ht_enable) {
3210 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3211 set_bit(ATH9K_MODE_11NG_HT20,
3212 pCap->wireless_modes);
3213 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3214 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3215 pCap->wireless_modes);
3216 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3217 pCap->wireless_modes);
3222 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3223 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3224 !(eeval & AR5416_OPFLAGS_11A))
3225 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3227 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3229 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3230 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3232 pCap->low_2ghz_chan = 2312;
3233 pCap->high_2ghz_chan = 2732;
3235 pCap->low_5ghz_chan = 4920;
3236 pCap->high_5ghz_chan = 6100;
3238 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3239 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3240 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3242 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3243 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3244 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3246 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3248 if (ah->config.ht_enable)
3249 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3251 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3253 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3254 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3255 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3256 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3258 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3259 pCap->total_queues =
3260 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3262 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3264 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3265 pCap->keycache_size =
3266 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3268 pCap->keycache_size = AR_KEYTABLE_SIZE;
3270 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3271 pCap->num_mr_retries = 4;
3272 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3274 if (AR_SREV_9285_10_OR_LATER(ah))
3275 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3276 else if (AR_SREV_9280_10_OR_LATER(ah))
3277 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3279 pCap->num_gpio_pins = AR_NUM_GPIO;
3281 if (AR_SREV_9280_10_OR_LATER(ah)) {
3282 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3283 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3285 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3286 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3289 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3290 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3291 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3293 pCap->rts_aggr_limit = (8 * 1024);
3296 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3298 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3299 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3300 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3302 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3303 ah->rfkill_polarity =
3304 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3306 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3310 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3311 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3312 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3313 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3314 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3315 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3317 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3319 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3320 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3322 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3324 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3326 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3327 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3328 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3329 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3332 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3333 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3336 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3338 pCap->num_antcfg_5ghz =
3339 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3340 pCap->num_antcfg_2ghz =
3341 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3343 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3344 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3345 ah->btactive_gpio = 6;
3346 ah->wlanactive_gpio = 5;
3352 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3353 u32 capability, u32 *result)
3356 case ATH9K_CAP_CIPHER:
3357 switch (capability) {
3358 case ATH9K_CIPHER_AES_CCM:
3359 case ATH9K_CIPHER_AES_OCB:
3360 case ATH9K_CIPHER_TKIP:
3361 case ATH9K_CIPHER_WEP:
3362 case ATH9K_CIPHER_MIC:
3363 case ATH9K_CIPHER_CLR:
3368 case ATH9K_CAP_TKIP_MIC:
3369 switch (capability) {
3373 return (ah->sta_id1_defaults &
3374 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3377 case ATH9K_CAP_TKIP_SPLIT:
3378 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3380 case ATH9K_CAP_DIVERSITY:
3381 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3382 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3384 case ATH9K_CAP_MCAST_KEYSRCH:
3385 switch (capability) {
3389 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3392 return (ah->sta_id1_defaults &
3393 AR_STA_ID1_MCAST_KSRCH) ? true :
3398 case ATH9K_CAP_TXPOW:
3399 switch (capability) {
3403 *result = ah->regulatory.power_limit;
3406 *result = ah->regulatory.max_power_level;
3409 *result = ah->regulatory.tp_scale;
3414 return (AR_SREV_9280_20_OR_LATER(ah) &&
3415 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3422 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3423 u32 capability, u32 setting, int *status)
3428 case ATH9K_CAP_TKIP_MIC:
3430 ah->sta_id1_defaults |=
3431 AR_STA_ID1_CRPT_MIC_ENABLE;
3433 ah->sta_id1_defaults &=
3434 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3436 case ATH9K_CAP_DIVERSITY:
3437 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3439 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3441 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3442 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3444 case ATH9K_CAP_MCAST_KEYSRCH:
3446 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3448 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3455 /****************************/
3456 /* GPIO / RFKILL / Antennae */
3457 /****************************/
3459 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3463 u32 gpio_shift, tmp;
3466 addr = AR_GPIO_OUTPUT_MUX3;
3468 addr = AR_GPIO_OUTPUT_MUX2;
3470 addr = AR_GPIO_OUTPUT_MUX1;
3472 gpio_shift = (gpio % 6) * 5;
3474 if (AR_SREV_9280_20_OR_LATER(ah)
3475 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3476 REG_RMW(ah, addr, (type << gpio_shift),
3477 (0x1f << gpio_shift));
3479 tmp = REG_READ(ah, addr);
3480 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3481 tmp &= ~(0x1f << gpio_shift);
3482 tmp |= (type << gpio_shift);
3483 REG_WRITE(ah, addr, tmp);
3487 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3491 ASSERT(gpio < ah->caps.num_gpio_pins);
3493 gpio_shift = gpio << 1;
3497 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3498 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3501 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3503 #define MS_REG_READ(x, y) \
3504 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3506 if (gpio >= ah->caps.num_gpio_pins)
3509 if (AR_SREV_9285_10_OR_LATER(ah))
3510 return MS_REG_READ(AR9285, gpio) != 0;
3511 else if (AR_SREV_9280_10_OR_LATER(ah))
3512 return MS_REG_READ(AR928X, gpio) != 0;
3514 return MS_REG_READ(AR, gpio) != 0;
3517 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3522 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3524 gpio_shift = 2 * gpio;
3528 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3529 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3532 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3534 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3538 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3539 void ath9k_enable_rfkill(struct ath_hw *ah)
3541 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3542 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3544 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3545 AR_GPIO_INPUT_MUX2_RFSILENT);
3547 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3548 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3552 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3554 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3557 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3559 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3562 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3563 enum ath9k_ant_setting settings,
3564 struct ath9k_channel *chan,
3569 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3571 if (AR_SREV_9280(ah)) {
3572 if (!tx_chainmask_cfg) {
3574 tx_chainmask_cfg = *tx_chainmask;
3575 rx_chainmask_cfg = *rx_chainmask;
3579 case ATH9K_ANT_FIXED_A:
3580 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3581 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3582 *antenna_cfgd = true;
3584 case ATH9K_ANT_FIXED_B:
3585 if (ah->caps.tx_chainmask >
3586 ATH9K_ANTENNA1_CHAINMASK) {
3587 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3589 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3590 *antenna_cfgd = true;
3592 case ATH9K_ANT_VARIABLE:
3593 *tx_chainmask = tx_chainmask_cfg;
3594 *rx_chainmask = rx_chainmask_cfg;
3595 *antenna_cfgd = true;
3601 ah->diversity_control = settings;
3607 /*********************/
3608 /* General Operation */
3609 /*********************/
3611 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3613 u32 bits = REG_READ(ah, AR_RX_FILTER);
3614 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3616 if (phybits & AR_PHY_ERR_RADAR)
3617 bits |= ATH9K_RX_FILTER_PHYRADAR;
3618 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3619 bits |= ATH9K_RX_FILTER_PHYERR;
3624 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3628 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3630 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3631 phybits |= AR_PHY_ERR_RADAR;
3632 if (bits & ATH9K_RX_FILTER_PHYERR)
3633 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3634 REG_WRITE(ah, AR_PHY_ERR, phybits);
3637 REG_WRITE(ah, AR_RXCFG,
3638 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3640 REG_WRITE(ah, AR_RXCFG,
3641 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3644 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3646 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3649 bool ath9k_hw_disable(struct ath_hw *ah)
3651 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3654 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3657 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3659 struct ath9k_channel *chan = ah->curchan;
3660 struct ieee80211_channel *channel = chan->chan;
3662 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3664 if (ah->eep_ops->set_txpower(ah, chan,
3665 ath9k_regd_get_ctl(ah, chan),
3666 channel->max_antenna_gain * 2,
3667 channel->max_power * 2,
3668 min((u32) MAX_RATE_POWER,
3669 (u32) ah->regulatory.power_limit)) != 0)
3675 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3677 memcpy(ah->macaddr, mac, ETH_ALEN);
3680 void ath9k_hw_setopmode(struct ath_hw *ah)
3682 ath9k_hw_set_operating_mode(ah, ah->opmode);
3685 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3687 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3688 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3691 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3693 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3694 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3697 void ath9k_hw_write_associd(struct ath_softc *sc)
3699 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3700 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3701 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3704 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3708 tsf = REG_READ(ah, AR_TSF_U32);
3709 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3714 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3716 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3717 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3718 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3721 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3726 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3729 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3730 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3735 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3738 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3741 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3743 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3748 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3750 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3751 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3752 ah->slottime = (u32) -1;
3755 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3761 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3765 if (mode == ATH9K_HT_MACMODE_2040 &&
3766 !ah->config.cwm_ignore_extcca)
3767 macmode = AR_2040_JOINED_RX_CLEAR;
3771 REG_WRITE(ah, AR_2040_MODE, macmode);
3774 /***************************/
3775 /* Bluetooth Coexistence */
3776 /***************************/
3778 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3780 /* connect bt_active to baseband */
3781 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3782 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3783 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3785 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3786 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3788 /* Set input mux for bt_active to gpio pin */
3789 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3790 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3793 /* Configure the desired gpio port for input */
3794 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3796 /* Configure the desired GPIO port for TX_FRAME output */
3797 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3798 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);