drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63 static int modparam_nohwcrypt;
  64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  66
  67
  68 /******************\
  69 * Internal defines *
  70 \******************/
  71
  72 /* Module info */
  73 MODULE_AUTHOR("Jiri Slaby");
  74 MODULE_AUTHOR("Nick Kossifidis");
  75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  79
  80
  81 /* Known PCI ids */
  82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  83         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  84         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  85         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  86         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  87         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  88         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  89         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  90         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  91         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  95         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  96         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  97         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  98         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  99         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
 100         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
 101         { 0 }
 102 };
 103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 104
 105 /* Known SREVs */
 106 static struct ath5k_srev_name srev_names[] = {
 107         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 108         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 109         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 110         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 111         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 112         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 113         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 114         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 115         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 116         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 117         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 118         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 119         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 120         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 121         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 122         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 123         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 124         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 125         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 126         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 127         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 128         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 129         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 130         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 131         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 132         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 133         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 134         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 135         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 136         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 137         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 138         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 139         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 140         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 141         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 142         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 143 };
 144
 145 static struct ieee80211_rate ath5k_rates[] = {
 146         { .bitrate = 10,
 147           .hw_value = ATH5K_RATE_CODE_1M, },
 148         { .bitrate = 20,
 149           .hw_value = ATH5K_RATE_CODE_2M,
 150           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 151           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 152         { .bitrate = 55,
 153           .hw_value = ATH5K_RATE_CODE_5_5M,
 154           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 155           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 156         { .bitrate = 110,
 157           .hw_value = ATH5K_RATE_CODE_11M,
 158           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 159           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 160         { .bitrate = 60,
 161           .hw_value = ATH5K_RATE_CODE_6M,
 162           .flags = 0 },
 163         { .bitrate = 90,
 164           .hw_value = ATH5K_RATE_CODE_9M,
 165           .flags = 0 },
 166         { .bitrate = 120,
 167           .hw_value = ATH5K_RATE_CODE_12M,
 168           .flags = 0 },
 169         { .bitrate = 180,
 170           .hw_value = ATH5K_RATE_CODE_18M,
 171           .flags = 0 },
 172         { .bitrate = 240,
 173           .hw_value = ATH5K_RATE_CODE_24M,
 174           .flags = 0 },
 175         { .bitrate = 360,
 176           .hw_value = ATH5K_RATE_CODE_36M,
 177           .flags = 0 },
 178         { .bitrate = 480,
 179           .hw_value = ATH5K_RATE_CODE_48M,
 180           .flags = 0 },
 181         { .bitrate = 540,
 182           .hw_value = ATH5K_RATE_CODE_54M,
 183           .flags = 0 },
 184         /* XR missing */
 185 };
 186
 187 /*
 188  * Prototypes - PCI stack related functions
 189  */
 190 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 191                                 const struct pci_device_id *id);
 192 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 193 #ifdef CONFIG_PM
 194 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 195                                         pm_message_t state);
 196 static int              ath5k_pci_resume(struct pci_dev *pdev);
 197 #else
 198 #define ath5k_pci_suspend NULL
 199 #define ath5k_pci_resume NULL
 200 #endif /* CONFIG_PM */
 201
 202 static struct pci_driver ath5k_pci_driver = {
 203         .name           = KBUILD_MODNAME,
 204         .id_table       = ath5k_pci_id_table,
 205         .probe          = ath5k_pci_probe,
 206         .remove         = __devexit_p(ath5k_pci_remove),
 207         .suspend        = ath5k_pci_suspend,
 208         .resume         = ath5k_pci_resume,
 209 };
 210
 211
 212
 213 /*
 214  * Prototypes - MAC 802.11 stack related functions
 215  */
 216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 218 static int ath5k_reset_wake(struct ath5k_softc *sc);
 219 static int ath5k_start(struct ieee80211_hw *hw);
 220 static void ath5k_stop(struct ieee80211_hw *hw);
 221 static int ath5k_add_interface(struct ieee80211_hw *hw,
 222                 struct ieee80211_if_init_conf *conf);
 223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 224                 struct ieee80211_if_init_conf *conf);
 225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
 226 static int ath5k_config_interface(struct ieee80211_hw *hw,
 227                 struct ieee80211_vif *vif,
 228                 struct ieee80211_if_conf *conf);
 229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 230                 unsigned int changed_flags,
 231                 unsigned int *new_flags,
 232                 int mc_count, struct dev_mc_list *mclist);
 233 static int ath5k_set_key(struct ieee80211_hw *hw,
 234                 enum set_key_cmd cmd,
 235                 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
 236                 struct ieee80211_key_conf *key);
 237 static int ath5k_get_stats(struct ieee80211_hw *hw,
 238                 struct ieee80211_low_level_stats *stats);
 239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 240                 struct ieee80211_tx_queue_stats *stats);
 241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 242 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
 243 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 244 static int ath5k_beacon_update(struct ath5k_softc *sc,
 245                 struct sk_buff *skb);
 246 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
 247                 struct ieee80211_vif *vif,
 248                 struct ieee80211_bss_conf *bss_conf,
 249                 u32 changes);
 250
 251 static struct ieee80211_ops ath5k_hw_ops = {
 252         .tx             = ath5k_tx,
 253         .start          = ath5k_start,
 254         .stop           = ath5k_stop,
 255         .add_interface  = ath5k_add_interface,
 256         .remove_interface = ath5k_remove_interface,
 257         .config         = ath5k_config,
 258         .config_interface = ath5k_config_interface,
 259         .configure_filter = ath5k_configure_filter,
 260         .set_key        = ath5k_set_key,
 261         .get_stats      = ath5k_get_stats,
 262         .conf_tx        = NULL,
 263         .get_tx_stats   = ath5k_get_tx_stats,
 264         .get_tsf        = ath5k_get_tsf,
 265         .set_tsf        = ath5k_set_tsf,
 266         .reset_tsf      = ath5k_reset_tsf,
 267         .bss_info_changed = ath5k_bss_info_changed,
 268 };
 269
 270 /*
 271  * Prototypes - Internal functions
 272  */
 273 /* Attach detach */
 274 static int      ath5k_attach(struct pci_dev *pdev,
 275                         struct ieee80211_hw *hw);
 276 static void     ath5k_detach(struct pci_dev *pdev,
 277                         struct ieee80211_hw *hw);
 278 /* Channel/mode setup */
 279 static inline short ath5k_ieee2mhz(short chan);
 280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 281                                 struct ieee80211_channel *channels,
 282                                 unsigned int mode,
 283                                 unsigned int max);
 284 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 285 static int      ath5k_chan_set(struct ath5k_softc *sc,
 286                                 struct ieee80211_channel *chan);
 287 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 288                                 unsigned int mode);
 289 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 290
 291 /* Descriptor setup */
 292 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 293                                 struct pci_dev *pdev);
 294 static void     ath5k_desc_free(struct ath5k_softc *sc,
 295                                 struct pci_dev *pdev);
 296 /* Buffers setup */
 297 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 298                                 struct ath5k_buf *bf);
 299 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 300                                 struct ath5k_buf *bf);
 301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 302                                 struct ath5k_buf *bf)
 303 {
 304         BUG_ON(!bf);
 305         if (!bf->skb)
 306                 return;
 307         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 308                         PCI_DMA_TODEVICE);
 309         dev_kfree_skb_any(bf->skb);
 310         bf->skb = NULL;
 311 }
 312
 313 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
 314                                 struct ath5k_buf *bf)
 315 {
 316         BUG_ON(!bf);
 317         if (!bf->skb)
 318                 return;
 319         pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
 320                         PCI_DMA_FROMDEVICE);
 321         dev_kfree_skb_any(bf->skb);
 322         bf->skb = NULL;
 323 }
 324
 325
 326 /* Queues setup */
 327 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 328                                 int qtype, int subtype);
 329 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 330 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 331 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 332                                 struct ath5k_txq *txq);
 333 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 334 static void     ath5k_txq_release(struct ath5k_softc *sc);
 335 /* Rx handling */
 336 static int      ath5k_rx_start(struct ath5k_softc *sc);
 337 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 339                                         struct ath5k_desc *ds,
 340                                         struct sk_buff *skb,
 341                                         struct ath5k_rx_status *rs);
 342 static void     ath5k_tasklet_rx(unsigned long data);
 343 /* Tx handling */
 344 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 345                                 struct ath5k_txq *txq);
 346 static void     ath5k_tasklet_tx(unsigned long data);
 347 /* Beacon handling */
 348 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 349                                         struct ath5k_buf *bf);
 350 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 351 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 352 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 353
 354 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 355 {
 356         u64 tsf = ath5k_hw_get_tsf64(ah);
 357
 358         if ((tsf & 0x7fff) < rstamp)
 359                 tsf -= 0x8000;
 360
 361         return (tsf & ~0x7fff) | rstamp;
 362 }
 363
 364 /* Interrupt handling */
 365 static int      ath5k_init(struct ath5k_softc *sc);
 366 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 367 static int      ath5k_stop_hw(struct ath5k_softc *sc);
 368 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 369 static void     ath5k_tasklet_reset(unsigned long data);
 370
 371 static void     ath5k_calibrate(unsigned long data);
 372 /* LED functions */
 373 static int      ath5k_init_leds(struct ath5k_softc *sc);
 374 static void     ath5k_led_enable(struct ath5k_softc *sc);
 375 static void     ath5k_led_off(struct ath5k_softc *sc);
 376 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 377
 378 /*
 379  * Module init/exit functions
 380  */
 381 static int __init
 382 init_ath5k_pci(void)
 383 {
 384         int ret;
 385
 386         ath5k_debug_init();
 387
 388         ret = pci_register_driver(&ath5k_pci_driver);
 389         if (ret) {
 390                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 391                 return ret;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static void __exit
 398 exit_ath5k_pci(void)
 399 {
 400         pci_unregister_driver(&ath5k_pci_driver);
 401
 402         ath5k_debug_finish();
 403 }
 404
 405 module_init(init_ath5k_pci);
 406 module_exit(exit_ath5k_pci);
 407
 408
 409 /********************\
 410 * PCI Initialization *
 411 \********************/
 412
 413 static const char *
 414 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 415 {
 416         const char *name = "xxxxx";
 417         unsigned int i;
 418
 419         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 420                 if (srev_names[i].sr_type != type)
 421                         continue;
 422
 423                 if ((val & 0xf0) == srev_names[i].sr_val)
 424                         name = srev_names[i].sr_name;
 425
 426                 if ((val & 0xff) == srev_names[i].sr_val) {
 427                         name = srev_names[i].sr_name;
 428                         break;
 429                 }
 430         }
 431
 432         return name;
 433 }
 434
 435 static int __devinit
 436 ath5k_pci_probe(struct pci_dev *pdev,
 437                 const struct pci_device_id *id)
 438 {
 439         void __iomem *mem;
 440         struct ath5k_softc *sc;
 441         struct ieee80211_hw *hw;
 442         int ret;
 443         u8 csz;
 444
 445         ret = pci_enable_device(pdev);
 446         if (ret) {
 447                 dev_err(&pdev->dev, "can't enable device\n");
 448                 goto err;
 449         }
 450
 451         /* XXX 32-bit addressing only */
 452         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 453         if (ret) {
 454                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 455                 goto err_dis;
 456         }
 457
 458         /*
 459          * Cache line size is used to size and align various
 460          * structures used to communicate with the hardware.
 461          */
 462         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 463         if (csz == 0) {
 464                 /*
 465                  * Linux 2.4.18 (at least) writes the cache line size
 466                  * register as a 16-bit wide register which is wrong.
 467                  * We must have this setup properly for rx buffer
 468                  * DMA to work so force a reasonable value here if it
 469                  * comes up zero.
 470                  */
 471                 csz = L1_CACHE_BYTES / sizeof(u32);
 472                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 473         }
 474         /*
 475          * The default setting of latency timer yields poor results,
 476          * set it to the value used by other systems.  It may be worth
 477          * tweaking this setting more.
 478          */
 479         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 480
 481         /* Enable bus mastering */
 482         pci_set_master(pdev);
 483
 484         /*
 485          * Disable the RETRY_TIMEOUT register (0x41) to keep
 486          * PCI Tx retries from interfering with C3 CPU state.
 487          */
 488         pci_write_config_byte(pdev, 0x41, 0);
 489
 490         ret = pci_request_region(pdev, 0, "ath5k");
 491         if (ret) {
 492                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 493                 goto err_dis;
 494         }
 495
 496         mem = pci_iomap(pdev, 0, 0);
 497         if (!mem) {
 498                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 499                 ret = -EIO;
 500                 goto err_reg;
 501         }
 502
 503         /*
 504          * Allocate hw (mac80211 main struct)
 505          * and hw->priv (driver private data)
 506          */
 507         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 508         if (hw == NULL) {
 509                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 510                 ret = -ENOMEM;
 511                 goto err_map;
 512         }
 513
 514         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 515
 516         /* Initialize driver private data */
 517         SET_IEEE80211_DEV(hw, &pdev->dev);
 518         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 519                     IEEE80211_HW_SIGNAL_DBM |
 520                     IEEE80211_HW_NOISE_DBM;
 521
 522         hw->wiphy->interface_modes =
 523                 BIT(NL80211_IFTYPE_STATION) |
 524                 BIT(NL80211_IFTYPE_ADHOC) |
 525                 BIT(NL80211_IFTYPE_MESH_POINT);
 526
 527         hw->extra_tx_headroom = 2;
 528         hw->channel_change_time = 5000;
 529         sc = hw->priv;
 530         sc->hw = hw;
 531         sc->pdev = pdev;
 532
 533         ath5k_debug_init_device(sc);
 534
 535         /*
 536          * Mark the device as detached to avoid processing
 537          * interrupts until setup is complete.
 538          */
 539         __set_bit(ATH_STAT_INVALID, sc->status);
 540
 541         sc->iobase = mem; /* So we can unmap it on detach */
 542         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 543         sc->opmode = NL80211_IFTYPE_STATION;
 544         mutex_init(&sc->lock);
 545         spin_lock_init(&sc->rxbuflock);
 546         spin_lock_init(&sc->txbuflock);
 547         spin_lock_init(&sc->block);
 548
 549         /* Set private data */
 550         pci_set_drvdata(pdev, hw);
 551
 552         /* Setup interrupt handler */
 553         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 554         if (ret) {
 555                 ATH5K_ERR(sc, "request_irq failed\n");
 556                 goto err_free;
 557         }
 558
 559         /* Initialize device */
 560         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 561         if (IS_ERR(sc->ah)) {
 562                 ret = PTR_ERR(sc->ah);
 563                 goto err_irq;
 564         }
 565
 566         /* set up multi-rate retry capabilities */
 567         if (sc->ah->ah_version == AR5K_AR5212) {
 568                 hw->max_rates = 4;
 569                 hw->max_rate_tries = 11;
 570         }
 571
 572         /* Finish private driver data initialization */
 573         ret = ath5k_attach(pdev, hw);
 574         if (ret)
 575                 goto err_ah;
 576
 577         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 578                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
 579                                         sc->ah->ah_mac_srev,
 580                                         sc->ah->ah_phy_revision);
 581
 582         if (!sc->ah->ah_single_chip) {
 583                 /* Single chip radio (!RF5111) */
 584                 if (sc->ah->ah_radio_5ghz_revision &&
 585                         !sc->ah->ah_radio_2ghz_revision) {
 586                         /* No 5GHz support -> report 2GHz radio */
 587                         if (!test_bit(AR5K_MODE_11A,
 588                                 sc->ah->ah_capabilities.cap_mode)) {
 589                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 590                                         ath5k_chip_name(AR5K_VERSION_RAD,
 591                                                 sc->ah->ah_radio_5ghz_revision),
 592                                                 sc->ah->ah_radio_5ghz_revision);
 593                         /* No 2GHz support (5110 and some
 594                          * 5Ghz only cards) -> report 5Ghz radio */
 595                         } else if (!test_bit(AR5K_MODE_11B,
 596                                 sc->ah->ah_capabilities.cap_mode)) {
 597                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 598                                         ath5k_chip_name(AR5K_VERSION_RAD,
 599                                                 sc->ah->ah_radio_5ghz_revision),
 600                                                 sc->ah->ah_radio_5ghz_revision);
 601                         /* Multiband radio */
 602                         } else {
 603                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 604                                         " (0x%x)\n",
 605                                         ath5k_chip_name(AR5K_VERSION_RAD,
 606                                                 sc->ah->ah_radio_5ghz_revision),
 607                                                 sc->ah->ah_radio_5ghz_revision);
 608                         }
 609                 }
 610                 /* Multi chip radio (RF5111 - RF2111) ->
 611                  * report both 2GHz/5GHz radios */
 612                 else if (sc->ah->ah_radio_5ghz_revision &&
 613                                 sc->ah->ah_radio_2ghz_revision){
 614                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 615                                 ath5k_chip_name(AR5K_VERSION_RAD,
 616                                         sc->ah->ah_radio_5ghz_revision),
 617                                         sc->ah->ah_radio_5ghz_revision);
 618                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 619                                 ath5k_chip_name(AR5K_VERSION_RAD,
 620                                         sc->ah->ah_radio_2ghz_revision),
 621                                         sc->ah->ah_radio_2ghz_revision);
 622                 }
 623         }
 624
 625
 626         /* ready to process interrupts */
 627         __clear_bit(ATH_STAT_INVALID, sc->status);
 628
 629         return 0;
 630 err_ah:
 631         ath5k_hw_detach(sc->ah);
 632 err_irq:
 633         free_irq(pdev->irq, sc);
 634 err_free:
 635         ieee80211_free_hw(hw);
 636 err_map:
 637         pci_iounmap(pdev, mem);
 638 err_reg:
 639         pci_release_region(pdev, 0);
 640 err_dis:
 641         pci_disable_device(pdev);
 642 err:
 643         return ret;
 644 }
 645
 646 static void __devexit
 647 ath5k_pci_remove(struct pci_dev *pdev)
 648 {
 649         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 650         struct ath5k_softc *sc = hw->priv;
 651
 652         ath5k_debug_finish_device(sc);
 653         ath5k_detach(pdev, hw);
 654         ath5k_hw_detach(sc->ah);
 655         free_irq(pdev->irq, sc);
 656         pci_iounmap(pdev, sc->iobase);
 657         pci_release_region(pdev, 0);
 658         pci_disable_device(pdev);
 659         ieee80211_free_hw(hw);
 660 }
 661
 662 #ifdef CONFIG_PM
 663 static int
 664 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 665 {
 666         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 667         struct ath5k_softc *sc = hw->priv;
 668
 669         ath5k_led_off(sc);
 670
 671         free_irq(pdev->irq, sc);
 672         pci_save_state(pdev);
 673         pci_disable_device(pdev);
 674         pci_set_power_state(pdev, PCI_D3hot);
 675
 676         return 0;
 677 }
 678
 679 static int
 680 ath5k_pci_resume(struct pci_dev *pdev)
 681 {
 682         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 683         struct ath5k_softc *sc = hw->priv;
 684         int err;
 685
 686         pci_restore_state(pdev);
 687
 688         err = pci_enable_device(pdev);
 689         if (err)
 690                 return err;
 691
 692         /*
 693          * Suspend/Resume resets the PCI configuration space, so we have to
 694          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 695          * PCI Tx retries from interfering with C3 CPU state
 696          */
 697         pci_write_config_byte(pdev, 0x41, 0);
 698
 699         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 700         if (err) {
 701                 ATH5K_ERR(sc, "request_irq failed\n");
 702                 goto err_no_irq;
 703         }
 704
 705         ath5k_led_enable(sc);
 706         return 0;
 707
 708 err_no_irq:
 709         pci_disable_device(pdev);
 710         return err;
 711 }
 712 #endif /* CONFIG_PM */
 713
 714
 715 /***********************\
 716 * Driver Initialization *
 717 \***********************/
 718
 719 static int
 720 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 721 {
 722         struct ath5k_softc *sc = hw->priv;
 723         struct ath5k_hw *ah = sc->ah;
 724         u8 mac[ETH_ALEN] = {};
 725         int ret;
 726
 727         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 728
 729         /*
 730          * Check if the MAC has multi-rate retry support.
 731          * We do this by trying to setup a fake extended
 732          * descriptor.  MAC's that don't have support will
 733          * return false w/o doing anything.  MAC's that do
 734          * support it will return true w/o doing anything.
 735          */
 736         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 737         if (ret < 0)
 738                 goto err;
 739         if (ret > 0)
 740                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 741
 742         /*
 743          * Collect the channel list.  The 802.11 layer
 744          * is resposible for filtering this list based
 745          * on settings like the phy mode and regulatory
 746          * domain restrictions.
 747          */
 748         ret = ath5k_setup_bands(hw);
 749         if (ret) {
 750                 ATH5K_ERR(sc, "can't get channels\n");
 751                 goto err;
 752         }
 753
 754         /* NB: setup here so ath5k_rate_update is happy */
 755         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 756                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 757         else
 758                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 759
 760         /*
 761          * Allocate tx+rx descriptors and populate the lists.
 762          */
 763         ret = ath5k_desc_alloc(sc, pdev);
 764         if (ret) {
 765                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 766                 goto err;
 767         }
 768
 769         /*
 770          * Allocate hardware transmit queues: one queue for
 771          * beacon frames and one data queue for each QoS
 772          * priority.  Note that hw functions handle reseting
 773          * these queues at the needed time.
 774          */
 775         ret = ath5k_beaconq_setup(ah);
 776         if (ret < 0) {
 777                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 778                 goto err_desc;
 779         }
 780         sc->bhalq = ret;
 781
 782         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 783         if (IS_ERR(sc->txq)) {
 784                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 785                 ret = PTR_ERR(sc->txq);
 786                 goto err_bhal;
 787         }
 788
 789         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 790         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 791         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 792         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 793
 794         ret = ath5k_eeprom_read_mac(ah, mac);
 795         if (ret) {
 796                 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
 797                         sc->pdev->device);
 798                 goto err_queues;
 799         }
 800
 801         SET_IEEE80211_PERM_ADDR(hw, mac);
 802         /* All MAC address bits matter for ACKs */
 803         memset(sc->bssidmask, 0xff, ETH_ALEN);
 804         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 805
 806         ret = ieee80211_register_hw(hw);
 807         if (ret) {
 808                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 809                 goto err_queues;
 810         }
 811
 812         ath5k_init_leds(sc);
 813
 814         return 0;
 815 err_queues:
 816         ath5k_txq_release(sc);
 817 err_bhal:
 818         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 819 err_desc:
 820         ath5k_desc_free(sc, pdev);
 821 err:
 822         return ret;
 823 }
 824
 825 static void
 826 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 827 {
 828         struct ath5k_softc *sc = hw->priv;
 829
 830         /*
 831          * NB: the order of these is important:
 832          * o call the 802.11 layer before detaching ath5k_hw to
 833          *   insure callbacks into the driver to delete global
 834          *   key cache entries can be handled
 835          * o reclaim the tx queue data structures after calling
 836          *   the 802.11 layer as we'll get called back to reclaim
 837          *   node state and potentially want to use them
 838          * o to cleanup the tx queues the hal is called, so detach
 839          *   it last
 840          * XXX: ??? detach ath5k_hw ???
 841          * Other than that, it's straightforward...
 842          */
 843         ieee80211_unregister_hw(hw);
 844         ath5k_desc_free(sc, pdev);
 845         ath5k_txq_release(sc);
 846         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 847         ath5k_unregister_leds(sc);
 848
 849         /*
 850          * NB: can't reclaim these until after ieee80211_ifdetach
 851          * returns because we'll get called back to reclaim node
 852          * state and potentially want to use them.
 853          */
 854 }
 855
 856
 857
 858
 859 /********************\
 860 * Channel/mode setup *
 861 \********************/
 862
 863 /*
 864  * Convert IEEE channel number to MHz frequency.
 865  */
 866 static inline short
 867 ath5k_ieee2mhz(short chan)
 868 {
 869         if (chan <= 14 || chan >= 27)
 870                 return ieee80211chan2mhz(chan);
 871         else
 872                 return 2212 + chan * 20;
 873 }
 874
 875 static unsigned int
 876 ath5k_copy_channels(struct ath5k_hw *ah,
 877                 struct ieee80211_channel *channels,
 878                 unsigned int mode,
 879                 unsigned int max)
 880 {
 881         unsigned int i, count, size, chfreq, freq, ch;
 882
 883         if (!test_bit(mode, ah->ah_modes))
 884                 return 0;
 885
 886         switch (mode) {
 887         case AR5K_MODE_11A:
 888         case AR5K_MODE_11A_TURBO:
 889                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 890                 size = 220 ;
 891                 chfreq = CHANNEL_5GHZ;
 892                 break;
 893         case AR5K_MODE_11B:
 894         case AR5K_MODE_11G:
 895         case AR5K_MODE_11G_TURBO:
 896                 size = 26;
 897                 chfreq = CHANNEL_2GHZ;
 898                 break;
 899         default:
 900                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 901                 return 0;
 902         }
 903
 904         for (i = 0, count = 0; i < size && max > 0; i++) {
 905                 ch = i + 1 ;
 906                 freq = ath5k_ieee2mhz(ch);
 907
 908                 /* Check if channel is supported by the chipset */
 909                 if (!ath5k_channel_ok(ah, freq, chfreq))
 910                         continue;
 911
 912                 /* Write channel info and increment counter */
 913                 channels[count].center_freq = freq;
 914                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 915                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 916                 switch (mode) {
 917                 case AR5K_MODE_11A:
 918                 case AR5K_MODE_11G:
 919                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 920                         break;
 921                 case AR5K_MODE_11A_TURBO:
 922                 case AR5K_MODE_11G_TURBO:
 923                         channels[count].hw_value = chfreq |
 924                                 CHANNEL_OFDM | CHANNEL_TURBO;
 925                         break;
 926                 case AR5K_MODE_11B:
 927                         channels[count].hw_value = CHANNEL_B;
 928                 }
 929
 930                 count++;
 931                 max--;
 932         }
 933
 934         return count;
 935 }
 936
 937 static void
 938 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 939 {
 940         u8 i;
 941
 942         for (i = 0; i < AR5K_MAX_RATES; i++)
 943                 sc->rate_idx[b->band][i] = -1;
 944
 945         for (i = 0; i < b->n_bitrates; i++) {
 946                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 947                 if (b->bitrates[i].hw_value_short)
 948                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 949         }
 950 }
 951
 952 static int
 953 ath5k_setup_bands(struct ieee80211_hw *hw)
 954 {
 955         struct ath5k_softc *sc = hw->priv;
 956         struct ath5k_hw *ah = sc->ah;
 957         struct ieee80211_supported_band *sband;
 958         int max_c, count_c = 0;
 959         int i;
 960
 961         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 962         max_c = ARRAY_SIZE(sc->channels);
 963
 964         /* 2GHz band */
 965         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 966         sband->band = IEEE80211_BAND_2GHZ;
 967         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 968
 969         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 970                 /* G mode */
 971                 memcpy(sband->bitrates, &ath5k_rates[0],
 972                        sizeof(struct ieee80211_rate) * 12);
 973                 sband->n_bitrates = 12;
 974
 975                 sband->channels = sc->channels;
 976                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 977                                         AR5K_MODE_11G, max_c);
 978
 979                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 980                 count_c = sband->n_channels;
 981                 max_c -= count_c;
 982         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 983                 /* B mode */
 984                 memcpy(sband->bitrates, &ath5k_rates[0],
 985                        sizeof(struct ieee80211_rate) * 4);
 986                 sband->n_bitrates = 4;
 987
 988                 /* 5211 only supports B rates and uses 4bit rate codes
 989                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 990                  * fix them up here:
 991                  */
 992                 if (ah->ah_version == AR5K_AR5211) {
 993                         for (i = 0; i < 4; i++) {
 994                                 sband->bitrates[i].hw_value =
 995                                         sband->bitrates[i].hw_value & 0xF;
 996                                 sband->bitrates[i].hw_value_short =
 997                                         sband->bitrates[i].hw_value_short & 0xF;
 998                         }
 999                 }
1000
1001                 sband->channels = sc->channels;
1002                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1003                                         AR5K_MODE_11B, max_c);
1004
1005                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1006                 count_c = sband->n_channels;
1007                 max_c -= count_c;
1008         }
1009         ath5k_setup_rate_idx(sc, sband);
1010
1011         /* 5GHz band, A mode */
1012         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1013                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1014                 sband->band = IEEE80211_BAND_5GHZ;
1015                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1016
1017                 memcpy(sband->bitrates, &ath5k_rates[4],
1018                        sizeof(struct ieee80211_rate) * 8);
1019                 sband->n_bitrates = 8;
1020
1021                 sband->channels = &sc->channels[count_c];
1022                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1023                                         AR5K_MODE_11A, max_c);
1024
1025                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1026         }
1027         ath5k_setup_rate_idx(sc, sband);
1028
1029         ath5k_debug_dump_bands(sc);
1030
1031         return 0;
1032 }
1033
1034 /*
1035  * Set/change channels.  If the channel is really being changed,
1036  * it's done by reseting the chip.  To accomplish this we must
1037  * first cleanup any pending DMA, then restart stuff after a la
1038  * ath5k_init.
1039  *
1040  * Called with sc->lock.
1041  */
1042 static int
1043 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1044 {
1045         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1046                 sc->curchan->center_freq, chan->center_freq);
1047
1048         if (chan->center_freq != sc->curchan->center_freq ||
1049                 chan->hw_value != sc->curchan->hw_value) {
1050
1051                 sc->curchan = chan;
1052                 sc->curband = &sc->sbands[chan->band];
1053
1054                 /*
1055                  * To switch channels clear any pending DMA operations;
1056                  * wait long enough for the RX fifo to drain, reset the
1057                  * hardware at the new frequency, and then re-enable
1058                  * the relevant bits of the h/w.
1059                  */
1060                 return ath5k_reset(sc, true, true);
1061         }
1062
1063         return 0;
1064 }
1065
1066 static void
1067 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1068 {
1069         sc->curmode = mode;
1070
1071         if (mode == AR5K_MODE_11A) {
1072                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1073         } else {
1074                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1075         }
1076 }
1077
1078 static void
1079 ath5k_mode_setup(struct ath5k_softc *sc)
1080 {
1081         struct ath5k_hw *ah = sc->ah;
1082         u32 rfilt;
1083
1084         /* configure rx filter */
1085         rfilt = sc->filter_flags;
1086         ath5k_hw_set_rx_filter(ah, rfilt);
1087
1088         if (ath5k_hw_hasbssidmask(ah))
1089                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1090
1091         /* configure operational mode */
1092         ath5k_hw_set_opmode(ah);
1093
1094         ath5k_hw_set_mcast_filter(ah, 0, 0);
1095         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1096 }
1097
1098 static inline int
1099 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1100 {
1101         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1102         return sc->rate_idx[sc->curband->band][hw_rix];
1103 }
1104
1105 /***************\
1106 * Buffers setup *
1107 \***************/
1108
1109 static
1110 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1111 {
1112         struct sk_buff *skb;
1113         unsigned int off;
1114
1115         /*
1116          * Allocate buffer with headroom_needed space for the
1117          * fake physical layer header at the start.
1118          */
1119         skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1120
1121         if (!skb) {
1122                 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1123                                 sc->rxbufsize + sc->cachelsz - 1);
1124                 return NULL;
1125         }
1126         /*
1127          * Cache-line-align.  This is important (for the
1128          * 5210 at least) as not doing so causes bogus data
1129          * in rx'd frames.
1130          */
1131         off = ((unsigned long)skb->data) % sc->cachelsz;
1132         if (off != 0)
1133                 skb_reserve(skb, sc->cachelsz - off);
1134
1135         *skb_addr = pci_map_single(sc->pdev,
1136                 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1137         if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1138                 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1139                 dev_kfree_skb(skb);
1140                 return NULL;
1141         }
1142         return skb;
1143 }
1144
1145 static int
1146 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1147 {
1148         struct ath5k_hw *ah = sc->ah;
1149         struct sk_buff *skb = bf->skb;
1150         struct ath5k_desc *ds;
1151
1152         if (!skb) {
1153                 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1154                 if (!skb)
1155                         return -ENOMEM;
1156                 bf->skb = skb;
1157         }
1158
1159         /*
1160          * Setup descriptors.  For receive we always terminate
1161          * the descriptor list with a self-linked entry so we'll
1162          * not get overrun under high load (as can happen with a
1163          * 5212 when ANI processing enables PHY error frames).
1164          *
1165          * To insure the last descriptor is self-linked we create
1166          * each descriptor as self-linked and add it to the end.  As
1167          * each additional descriptor is added the previous self-linked
1168          * entry is ``fixed'' naturally.  This should be safe even
1169          * if DMA is happening.  When processing RX interrupts we
1170          * never remove/process the last, self-linked, entry on the
1171          * descriptor list.  This insures the hardware always has
1172          * someplace to write a new frame.
1173          */
1174         ds = bf->desc;
1175         ds->ds_link = bf->daddr;        /* link to self */
1176         ds->ds_data = bf->skbaddr;
1177         ah->ah_setup_rx_desc(ah, ds,
1178                 skb_tailroom(skb),      /* buffer size */
1179                 0);
1180
1181         if (sc->rxlink != NULL)
1182                 *sc->rxlink = bf->daddr;
1183         sc->rxlink = &ds->ds_link;
1184         return 0;
1185 }
1186
1187 static int
1188 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1189 {
1190         struct ath5k_hw *ah = sc->ah;
1191         struct ath5k_txq *txq = sc->txq;
1192         struct ath5k_desc *ds = bf->desc;
1193         struct sk_buff *skb = bf->skb;
1194         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1195         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1196         struct ieee80211_rate *rate;
1197         unsigned int mrr_rate[3], mrr_tries[3];
1198         int i, ret;
1199         u16 hw_rate;
1200         u16 cts_rate = 0;
1201         u16 duration = 0;
1202         u8 rc_flags;
1203
1204         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1205
1206         /* XXX endianness */
1207         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1208                         PCI_DMA_TODEVICE);
1209
1210         rate = ieee80211_get_tx_rate(sc->hw, info);
1211
1212         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1213                 flags |= AR5K_TXDESC_NOACK;
1214
1215         rc_flags = info->control.rates[0].flags;
1216         hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1217                 rate->hw_value_short : rate->hw_value;
1218
1219         pktlen = skb->len;
1220
1221         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1222                 flags |= AR5K_TXDESC_RTSENA;
1223                 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1224                 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1225                         sc->vif, pktlen, info));
1226         }
1227         if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1228                 flags |= AR5K_TXDESC_CTSENA;
1229                 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1230                 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1231                         sc->vif, pktlen, info));
1232         }
1233
1234         if (info->control.hw_key) {
1235                 keyidx = info->control.hw_key->hw_key_idx;
1236                 pktlen += info->control.hw_key->icv_len;
1237         }
1238         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1239                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1240                 (sc->power_level * 2),
1241                 hw_rate,
1242                 info->control.rates[0].count, keyidx, 0, flags,
1243                 cts_rate, duration);
1244         if (ret)
1245                 goto err_unmap;
1246
1247         memset(mrr_rate, 0, sizeof(mrr_rate));
1248         memset(mrr_tries, 0, sizeof(mrr_tries));
1249         for (i = 0; i < 3; i++) {
1250                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1251                 if (!rate)
1252                         break;
1253
1254                 mrr_rate[i] = rate->hw_value;
1255                 mrr_tries[i] = info->control.rates[i + 1].count;
1256         }
1257
1258         ah->ah_setup_mrr_tx_desc(ah, ds,
1259                 mrr_rate[0], mrr_tries[0],
1260                 mrr_rate[1], mrr_tries[1],
1261                 mrr_rate[2], mrr_tries[2]);
1262
1263         ds->ds_link = 0;
1264         ds->ds_data = bf->skbaddr;
1265
1266         spin_lock_bh(&txq->lock);
1267         list_add_tail(&bf->list, &txq->q);
1268         sc->tx_stats[txq->qnum].len++;
1269         if (txq->link == NULL) /* is this first packet? */
1270                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1271         else /* no, so only link it */
1272                 *txq->link = bf->daddr;
1273
1274         txq->link = &ds->ds_link;
1275         ath5k_hw_start_tx_dma(ah, txq->qnum);
1276         mmiowb();
1277         spin_unlock_bh(&txq->lock);
1278
1279         return 0;
1280 err_unmap:
1281         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1282         return ret;
1283 }
1284
1285 /*******************\
1286 * Descriptors setup *
1287 \*******************/
1288
1289 static int
1290 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1291 {
1292         struct ath5k_desc *ds;
1293         struct ath5k_buf *bf;
1294         dma_addr_t da;
1295         unsigned int i;
1296         int ret;
1297
1298         /* allocate descriptors */
1299         sc->desc_len = sizeof(struct ath5k_desc) *
1300                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1301         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1302         if (sc->desc == NULL) {
1303                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1304                 ret = -ENOMEM;
1305                 goto err;
1306         }
1307         ds = sc->desc;
1308         da = sc->desc_daddr;
1309         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1310                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1311
1312         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1313                         sizeof(struct ath5k_buf), GFP_KERNEL);
1314         if (bf == NULL) {
1315                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1316                 ret = -ENOMEM;
1317                 goto err_free;
1318         }
1319         sc->bufptr = bf;
1320
1321         INIT_LIST_HEAD(&sc->rxbuf);
1322         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1323                 bf->desc = ds;
1324                 bf->daddr = da;
1325                 list_add_tail(&bf->list, &sc->rxbuf);
1326         }
1327
1328         INIT_LIST_HEAD(&sc->txbuf);
1329         sc->txbuf_len = ATH_TXBUF;
1330         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1331                         da += sizeof(*ds)) {
1332                 bf->desc = ds;
1333                 bf->daddr = da;
1334                 list_add_tail(&bf->list, &sc->txbuf);
1335         }
1336
1337         /* beacon buffer */
1338         bf->desc = ds;
1339         bf->daddr = da;
1340         sc->bbuf = bf;
1341
1342         return 0;
1343 err_free:
1344         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1345 err:
1346         sc->desc = NULL;
1347         return ret;
1348 }
1349
1350 static void
1351 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1352 {
1353         struct ath5k_buf *bf;
1354
1355         ath5k_txbuf_free(sc, sc->bbuf);
1356         list_for_each_entry(bf, &sc->txbuf, list)
1357                 ath5k_txbuf_free(sc, bf);
1358         list_for_each_entry(bf, &sc->rxbuf, list)
1359                 ath5k_rxbuf_free(sc, bf);
1360
1361         /* Free memory associated with all descriptors */
1362         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1363
1364         kfree(sc->bufptr);
1365         sc->bufptr = NULL;
1366 }
1367
1368
1369
1370
1371
1372 /**************\
1373 * Queues setup *
1374 \**************/
1375
1376 static struct ath5k_txq *
1377 ath5k_txq_setup(struct ath5k_softc *sc,
1378                 int qtype, int subtype)
1379 {
1380         struct ath5k_hw *ah = sc->ah;
1381         struct ath5k_txq *txq;
1382         struct ath5k_txq_info qi = {
1383                 .tqi_subtype = subtype,
1384                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1385                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1386                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1387         };
1388         int qnum;
1389
1390         /*
1391          * Enable interrupts only for EOL and DESC conditions.
1392          * We mark tx descriptors to receive a DESC interrupt
1393          * when a tx queue gets deep; otherwise waiting for the
1394          * EOL to reap descriptors.  Note that this is done to
1395          * reduce interrupt load and this only defers reaping
1396          * descriptors, never transmitting frames.  Aside from
1397          * reducing interrupts this also permits more concurrency.
1398          * The only potential downside is if the tx queue backs
1399          * up in which case the top half of the kernel may backup
1400          * due to a lack of tx descriptors.
1401          */
1402         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1403                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1404         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1405         if (qnum < 0) {
1406                 /*
1407                  * NB: don't print a message, this happens
1408                  * normally on parts with too few tx queues
1409                  */
1410                 return ERR_PTR(qnum);
1411         }
1412         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1413                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1414                         qnum, ARRAY_SIZE(sc->txqs));
1415                 ath5k_hw_release_tx_queue(ah, qnum);
1416                 return ERR_PTR(-EINVAL);
1417         }
1418         txq = &sc->txqs[qnum];
1419         if (!txq->setup) {
1420                 txq->qnum = qnum;
1421                 txq->link = NULL;
1422                 INIT_LIST_HEAD(&txq->q);
1423                 spin_lock_init(&txq->lock);
1424                 txq->setup = true;
1425         }
1426         return &sc->txqs[qnum];
1427 }
1428
1429 static int
1430 ath5k_beaconq_setup(struct ath5k_hw *ah)
1431 {
1432         struct ath5k_txq_info qi = {
1433                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1434                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1435                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1436                 /* NB: for dynamic turbo, don't enable any other interrupts */
1437                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1438         };
1439
1440         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1441 }
1442
1443 static int
1444 ath5k_beaconq_config(struct ath5k_softc *sc)
1445 {
1446         struct ath5k_hw *ah = sc->ah;
1447         struct ath5k_txq_info qi;
1448         int ret;
1449
1450         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1451         if (ret)
1452                 return ret;
1453         if (sc->opmode == NL80211_IFTYPE_AP ||
1454                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1455                 /*
1456                  * Always burst out beacon and CAB traffic
1457                  * (aifs = cwmin = cwmax = 0)
1458                  */
1459                 qi.tqi_aifs = 0;
1460                 qi.tqi_cw_min = 0;
1461                 qi.tqi_cw_max = 0;
1462         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1463                 /*
1464                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1465                  */
1466                 qi.tqi_aifs = 0;
1467                 qi.tqi_cw_min = 0;
1468                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1469         }
1470
1471         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1472                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1473                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1474
1475         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1476         if (ret) {
1477                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1478                         "hardware queue!\n", __func__);
1479                 return ret;
1480         }
1481
1482         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1483 }
1484
1485 static void
1486 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1487 {
1488         struct ath5k_buf *bf, *bf0;
1489
1490         /*
1491          * NB: this assumes output has been stopped and
1492          *     we do not need to block ath5k_tx_tasklet
1493          */
1494         spin_lock_bh(&txq->lock);
1495         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1496                 ath5k_debug_printtxbuf(sc, bf);
1497
1498                 ath5k_txbuf_free(sc, bf);
1499
1500                 spin_lock_bh(&sc->txbuflock);
1501                 sc->tx_stats[txq->qnum].len--;
1502                 list_move_tail(&bf->list, &sc->txbuf);
1503                 sc->txbuf_len++;
1504                 spin_unlock_bh(&sc->txbuflock);
1505         }
1506         txq->link = NULL;
1507         spin_unlock_bh(&txq->lock);
1508 }
1509
1510 /*
1511  * Drain the transmit queues and reclaim resources.
1512  */
1513 static void
1514 ath5k_txq_cleanup(struct ath5k_softc *sc)
1515 {
1516         struct ath5k_hw *ah = sc->ah;
1517         unsigned int i;
1518
1519         /* XXX return value */
1520         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1521                 /* don't touch the hardware if marked invalid */
1522                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1523                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1524                         ath5k_hw_get_txdp(ah, sc->bhalq));
1525                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1526                         if (sc->txqs[i].setup) {
1527                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1528                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1529                                         "link %p\n",
1530                                         sc->txqs[i].qnum,
1531                                         ath5k_hw_get_txdp(ah,
1532                                                         sc->txqs[i].qnum),
1533                                         sc->txqs[i].link);
1534                         }
1535         }
1536         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1537
1538         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1539                 if (sc->txqs[i].setup)
1540                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1541 }
1542
1543 static void
1544 ath5k_txq_release(struct ath5k_softc *sc)
1545 {
1546         struct ath5k_txq *txq = sc->txqs;
1547         unsigned int i;
1548
1549         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1550                 if (txq->setup) {
1551                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1552                         txq->setup = false;
1553                 }
1554 }
1555
1556
1557
1558
1559 /*************\
1560 * RX Handling *
1561 \*************/
1562
1563 /*
1564  * Enable the receive h/w following a reset.
1565  */
1566 static int
1567 ath5k_rx_start(struct ath5k_softc *sc)
1568 {
1569         struct ath5k_hw *ah = sc->ah;
1570         struct ath5k_buf *bf;
1571         int ret;
1572
1573         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1574
1575         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1576                 sc->cachelsz, sc->rxbufsize);
1577
1578         sc->rxlink = NULL;
1579
1580         spin_lock_bh(&sc->rxbuflock);
1581         list_for_each_entry(bf, &sc->rxbuf, list) {
1582                 ret = ath5k_rxbuf_setup(sc, bf);
1583                 if (ret != 0) {
1584                         spin_unlock_bh(&sc->rxbuflock);
1585                         goto err;
1586                 }
1587         }
1588         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1589         spin_unlock_bh(&sc->rxbuflock);
1590
1591         ath5k_hw_set_rxdp(ah, bf->daddr);
1592         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1593         ath5k_mode_setup(sc);           /* set filters, etc. */
1594         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1595
1596         return 0;
1597 err:
1598         return ret;
1599 }
1600
1601 /*
1602  * Disable the receive h/w in preparation for a reset.
1603  */
1604 static void
1605 ath5k_rx_stop(struct ath5k_softc *sc)
1606 {
1607         struct ath5k_hw *ah = sc->ah;
1608
1609         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1610         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1611         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1612
1613         ath5k_debug_printrxbuffs(sc, ah);
1614
1615         sc->rxlink = NULL;              /* just in case */
1616 }
1617
1618 static unsigned int
1619 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1620                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1621 {
1622         struct ieee80211_hdr *hdr = (void *)skb->data;
1623         unsigned int keyix, hlen;
1624
1625         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1626                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1627                 return RX_FLAG_DECRYPTED;
1628
1629         /* Apparently when a default key is used to decrypt the packet
1630            the hw does not set the index used to decrypt.  In such cases
1631            get the index from the packet. */
1632         hlen = ieee80211_hdrlen(hdr->frame_control);
1633         if (ieee80211_has_protected(hdr->frame_control) &&
1634             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1635             skb->len >= hlen + 4) {
1636                 keyix = skb->data[hlen + 3] >> 6;
1637
1638                 if (test_bit(keyix, sc->keymap))
1639                         return RX_FLAG_DECRYPTED;
1640         }
1641
1642         return 0;
1643 }
1644
1645
1646 static void
1647 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1648                      struct ieee80211_rx_status *rxs)
1649 {
1650         u64 tsf, bc_tstamp;
1651         u32 hw_tu;
1652         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1653
1654         if (ieee80211_is_beacon(mgmt->frame_control) &&
1655             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1656             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1657                 /*
1658                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1659                  * have updated the local TSF. We have to work around various
1660                  * hardware bugs, though...
1661                  */
1662                 tsf = ath5k_hw_get_tsf64(sc->ah);
1663                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1664                 hw_tu = TSF_TO_TU(tsf);
1665
1666                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1667                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1668                         (unsigned long long)bc_tstamp,
1669                         (unsigned long long)rxs->mactime,
1670                         (unsigned long long)(rxs->mactime - bc_tstamp),
1671                         (unsigned long long)tsf);
1672
1673                 /*
1674                  * Sometimes the HW will give us a wrong tstamp in the rx
1675                  * status, causing the timestamp extension to go wrong.
1676                  * (This seems to happen especially with beacon frames bigger
1677                  * than 78 byte (incl. FCS))
1678                  * But we know that the receive timestamp must be later than the
1679                  * timestamp of the beacon since HW must have synced to that.
1680                  *
1681                  * NOTE: here we assume mactime to be after the frame was
1682                  * received, not like mac80211 which defines it at the start.
1683                  */
1684                 if (bc_tstamp > rxs->mactime) {
1685                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1686                                 "fixing mactime from %llx to %llx\n",
1687                                 (unsigned long long)rxs->mactime,
1688                                 (unsigned long long)tsf);
1689                         rxs->mactime = tsf;
1690                 }
1691
1692                 /*
1693                  * Local TSF might have moved higher than our beacon timers,
1694                  * in that case we have to update them to continue sending
1695                  * beacons. This also takes care of synchronizing beacon sending
1696                  * times with other stations.
1697                  */
1698                 if (hw_tu >= sc->nexttbtt)
1699                         ath5k_beacon_update_timers(sc, bc_tstamp);
1700         }
1701 }
1702
1703 static void
1704 ath5k_tasklet_rx(unsigned long data)
1705 {
1706         struct ieee80211_rx_status rxs = {};
1707         struct ath5k_rx_status rs = {};
1708         struct sk_buff *skb, *next_skb;
1709         dma_addr_t next_skb_addr;
1710         struct ath5k_softc *sc = (void *)data;
1711         struct ath5k_buf *bf, *bf_last;
1712         struct ath5k_desc *ds;
1713         int ret;
1714         int hdrlen;
1715         int padsize;
1716
1717         spin_lock(&sc->rxbuflock);
1718         if (list_empty(&sc->rxbuf)) {
1719                 ATH5K_WARN(sc, "empty rx buf pool\n");
1720                 goto unlock;
1721         }
1722         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1723         do {
1724                 rxs.flag = 0;
1725
1726                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1727                 BUG_ON(bf->skb == NULL);
1728                 skb = bf->skb;
1729                 ds = bf->desc;
1730
1731                 /*
1732                  * last buffer must not be freed to ensure proper hardware
1733                  * function. When the hardware finishes also a packet next to
1734                  * it, we are sure, it doesn't use it anymore and we can go on.
1735                  */
1736                 if (bf_last == bf)
1737                         bf->flags |= 1;
1738                 if (bf->flags) {
1739                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1740                                         struct ath5k_buf, list);
1741                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1742                                         &rs);
1743                         if (ret)
1744                                 break;
1745                         bf->flags &= ~1;
1746                         /* skip the overwritten one (even status is martian) */
1747                         goto next;
1748                 }
1749
1750                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1751                 if (unlikely(ret == -EINPROGRESS))
1752                         break;
1753                 else if (unlikely(ret)) {
1754                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1755                         spin_unlock(&sc->rxbuflock);
1756                         return;
1757                 }
1758
1759                 if (unlikely(rs.rs_more)) {
1760                         ATH5K_WARN(sc, "unsupported jumbo\n");
1761                         goto next;
1762                 }
1763
1764                 if (unlikely(rs.rs_status)) {
1765                         if (rs.rs_status & AR5K_RXERR_PHY)
1766                                 goto next;
1767                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1768                                 /*
1769                                  * Decrypt error.  If the error occurred
1770                                  * because there was no hardware key, then
1771                                  * let the frame through so the upper layers
1772                                  * can process it.  This is necessary for 5210
1773                                  * parts which have no way to setup a ``clear''
1774                                  * key cache entry.
1775                                  *
1776                                  * XXX do key cache faulting
1777                                  */
1778                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1779                                     !(rs.rs_status & AR5K_RXERR_CRC))
1780                                         goto accept;
1781                         }
1782                         if (rs.rs_status & AR5K_RXERR_MIC) {
1783                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1784                                 goto accept;
1785                         }
1786
1787                         /* let crypto-error packets fall through in MNTR */
1788                         if ((rs.rs_status &
1789                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1790                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1791                                 goto next;
1792                 }
1793 accept:
1794                 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1795
1796                 /*
1797                  * If we can't replace bf->skb with a new skb under memory
1798                  * pressure, just skip this packet
1799                  */
1800                 if (!next_skb)
1801                         goto next;
1802
1803                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1804                                 PCI_DMA_FROMDEVICE);
1805                 skb_put(skb, rs.rs_datalen);
1806
1807                 /* The MAC header is padded to have 32-bit boundary if the
1808                  * packet payload is non-zero. The general calculation for
1809                  * padsize would take into account odd header lengths:
1810                  * padsize = (4 - hdrlen % 4) % 4; However, since only
1811                  * even-length headers are used, padding can only be 0 or 2
1812                  * bytes and we can optimize this a bit. In addition, we must
1813                  * not try to remove padding from short control frames that do
1814                  * not have payload. */
1815                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1816                 padsize = ath5k_pad_size(hdrlen);
1817                 if (padsize) {
1818                         memmove(skb->data + padsize, skb->data, hdrlen);
1819                         skb_pull(skb, padsize);
1820                 }
1821
1822                 /*
1823                  * always extend the mac timestamp, since this information is
1824                  * also needed for proper IBSS merging.
1825                  *
1826                  * XXX: it might be too late to do it here, since rs_tstamp is
1827                  * 15bit only. that means TSF extension has to be done within
1828                  * 32768usec (about 32ms). it might be necessary to move this to
1829                  * the interrupt handler, like it is done in madwifi.
1830                  *
1831                  * Unfortunately we don't know when the hardware takes the rx
1832                  * timestamp (beginning of phy frame, data frame, end of rx?).
1833                  * The only thing we know is that it is hardware specific...
1834                  * On AR5213 it seems the rx timestamp is at the end of the
1835                  * frame, but i'm not sure.
1836                  *
1837                  * NOTE: mac80211 defines mactime at the beginning of the first
1838                  * data symbol. Since we don't have any time references it's
1839                  * impossible to comply to that. This affects IBSS merge only
1840                  * right now, so it's not too bad...
1841                  */
1842                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1843                 rxs.flag |= RX_FLAG_TSFT;
1844
1845                 rxs.freq = sc->curchan->center_freq;
1846                 rxs.band = sc->curband->band;
1847
1848                 rxs.noise = sc->ah->ah_noise_floor;
1849                 rxs.signal = rxs.noise + rs.rs_rssi;
1850
1851                 /* An rssi of 35 indicates you should be able use
1852                  * 54 Mbps reliably. A more elaborate scheme can be used
1853                  * here but it requires a map of SNR/throughput for each
1854                  * possible mode used */
1855                 rxs.qual = rs.rs_rssi * 100 / 35;
1856
1857                 /* rssi can be more than 35 though, anything above that
1858                  * should be considered at 100% */
1859                 if (rxs.qual > 100)
1860                         rxs.qual = 100;
1861
1862                 rxs.antenna = rs.rs_antenna;
1863                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1864                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1865
1866                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1867                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1868                         rxs.flag |= RX_FLAG_SHORTPRE;
1869
1870                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1871
1872                 /* check beacons in IBSS mode */
1873                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1874                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1875
1876                 __ieee80211_rx(sc->hw, skb, &rxs);
1877
1878                 bf->skb = next_skb;
1879                 bf->skbaddr = next_skb_addr;
1880 next:
1881                 list_move_tail(&bf->list, &sc->rxbuf);
1882         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1883 unlock:
1884         spin_unlock(&sc->rxbuflock);
1885 }
1886
1887
1888
1889
1890 /*************\
1891 * TX Handling *
1892 \*************/
1893
1894 static void
1895 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1896 {
1897         struct ath5k_tx_status ts = {};
1898         struct ath5k_buf *bf, *bf0;
1899         struct ath5k_desc *ds;
1900         struct sk_buff *skb;
1901         struct ieee80211_tx_info *info;
1902         int i, ret;
1903
1904         spin_lock(&txq->lock);
1905         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1906                 ds = bf->desc;
1907
1908                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1909                 if (unlikely(ret == -EINPROGRESS))
1910                         break;
1911                 else if (unlikely(ret)) {
1912                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1913                                 ret, txq->qnum);
1914                         break;
1915                 }
1916
1917                 skb = bf->skb;
1918                 info = IEEE80211_SKB_CB(skb);
1919                 bf->skb = NULL;
1920
1921                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1922                                 PCI_DMA_TODEVICE);
1923
1924                 ieee80211_tx_info_clear_status(info);
1925                 for (i = 0; i < 4; i++) {
1926                         struct ieee80211_tx_rate *r =
1927                                 &info->status.rates[i];
1928
1929                         if (ts.ts_rate[i]) {
1930                                 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1931                                 r->count = ts.ts_retry[i];
1932                         } else {
1933                                 r->idx = -1;
1934                                 r->count = 0;
1935                         }
1936                 }
1937
1938                 /* count the successful attempt as well */
1939                 info->status.rates[ts.ts_final_idx].count++;
1940
1941                 if (unlikely(ts.ts_status)) {
1942                         sc->ll_stats.dot11ACKFailureCount++;
1943                         if (ts.ts_status & AR5K_TXERR_FILT)
1944                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1945                 } else {
1946                         info->flags |= IEEE80211_TX_STAT_ACK;
1947                         info->status.ack_signal = ts.ts_rssi;
1948                 }
1949
1950                 ieee80211_tx_status(sc->hw, skb);
1951                 sc->tx_stats[txq->qnum].count++;
1952
1953                 spin_lock(&sc->txbuflock);
1954                 sc->tx_stats[txq->qnum].len--;
1955                 list_move_tail(&bf->list, &sc->txbuf);
1956                 sc->txbuf_len++;
1957                 spin_unlock(&sc->txbuflock);
1958         }
1959         if (likely(list_empty(&txq->q)))
1960                 txq->link = NULL;
1961         spin_unlock(&txq->lock);
1962         if (sc->txbuf_len > ATH_TXBUF / 5)
1963                 ieee80211_wake_queues(sc->hw);
1964 }
1965
1966 static void
1967 ath5k_tasklet_tx(unsigned long data)
1968 {
1969         struct ath5k_softc *sc = (void *)data;
1970
1971         ath5k_tx_processq(sc, sc->txq);
1972 }
1973
1974
1975 /*****************\
1976 * Beacon handling *
1977 \*****************/
1978
1979 /*
1980  * Setup the beacon frame for transmit.
1981  */
1982 static int
1983 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1984 {
1985         struct sk_buff *skb = bf->skb;
1986         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1987         struct ath5k_hw *ah = sc->ah;
1988         struct ath5k_desc *ds;
1989         int ret, antenna = 0;
1990         u32 flags;
1991
1992         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1993                         PCI_DMA_TODEVICE);
1994         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1995                         "skbaddr %llx\n", skb, skb->data, skb->len,
1996                         (unsigned long long)bf->skbaddr);
1997         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1998                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1999                 return -EIO;
2000         }
2001
2002         ds = bf->desc;
2003
2004         flags = AR5K_TXDESC_NOACK;
2005         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2006                 ds->ds_link = bf->daddr;        /* self-linked */
2007                 flags |= AR5K_TXDESC_VEOL;
2008                 /*
2009                  * Let hardware handle antenna switching if txantenna is not set
2010                  */
2011         } else {
2012                 ds->ds_link = 0;
2013                 /*
2014                  * Switch antenna every 4 beacons if txantenna is not set
2015                  * XXX assumes two antennas
2016                  */
2017                 if (antenna == 0)
2018                         antenna = sc->bsent & 4 ? 2 : 1;
2019         }
2020
2021         ds->ds_data = bf->skbaddr;
2022         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2023                         ieee80211_get_hdrlen_from_skb(skb),
2024                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2025                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2026                         1, AR5K_TXKEYIX_INVALID,
2027                         antenna, flags, 0, 0);
2028         if (ret)
2029                 goto err_unmap;
2030
2031         return 0;
2032 err_unmap:
2033         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2034         return ret;
2035 }
2036
2037 /*
2038  * Transmit a beacon frame at SWBA.  Dynamic updates to the
2039  * frame contents are done as needed and the slot time is
2040  * also adjusted based on current state.
2041  *
2042  * this is usually called from interrupt context (ath5k_intr())
2043  * but also from ath5k_beacon_config() in IBSS mode which in turn
2044  * can be called from a tasklet and user context
2045  */
2046 static void
2047 ath5k_beacon_send(struct ath5k_softc *sc)
2048 {
2049         struct ath5k_buf *bf = sc->bbuf;
2050         struct ath5k_hw *ah = sc->ah;
2051
2052         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2053
2054         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2055                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
2056                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2057                 return;
2058         }
2059         /*
2060          * Check if the previous beacon has gone out.  If
2061          * not don't don't try to post another, skip this
2062          * period and wait for the next.  Missed beacons
2063          * indicate a problem and should not occur.  If we
2064          * miss too many consecutive beacons reset the device.
2065          */
2066         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2067                 sc->bmisscount++;
2068                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2069                         "missed %u consecutive beacons\n", sc->bmisscount);
2070                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
2071                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2072                                 "stuck beacon time (%u missed)\n",
2073                                 sc->bmisscount);
2074                         tasklet_schedule(&sc->restq);
2075                 }
2076                 return;
2077         }
2078         if (unlikely(sc->bmisscount != 0)) {
2079                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2080                         "resume beacon xmit after %u misses\n",
2081                         sc->bmisscount);
2082                 sc->bmisscount = 0;
2083         }
2084
2085         /*
2086          * Stop any current dma and put the new frame on the queue.
2087          * This should never fail since we check above that no frames
2088          * are still pending on the queue.
2089          */
2090         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2091                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2092                 /* NB: hw still stops DMA, so proceed */
2093         }
2094
2095         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2096         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2097         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2098                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2099
2100         sc->bsent++;
2101 }
2102
2103
2104 /**
2105  * ath5k_beacon_update_timers - update beacon timers
2106  *
2107  * @sc: struct ath5k_softc pointer we are operating on
2108  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2109  *          beacon timer update based on the current HW TSF.
2110  *
2111  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2112  * of a received beacon or the current local hardware TSF and write it to the
2113  * beacon timer registers.
2114  *
2115  * This is called in a variety of situations, e.g. when a beacon is received,
2116  * when a TSF update has been detected, but also when an new IBSS is created or
2117  * when we otherwise know we have to update the timers, but we keep it in this
2118  * function to have it all together in one place.
2119  */
2120 static void
2121 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2122 {
2123         struct ath5k_hw *ah = sc->ah;
2124         u32 nexttbtt, intval, hw_tu, bc_tu;
2125         u64 hw_tsf;
2126
2127         intval = sc->bintval & AR5K_BEACON_PERIOD;
2128         if (WARN_ON(!intval))
2129                 return;
2130
2131         /* beacon TSF converted to TU */
2132         bc_tu = TSF_TO_TU(bc_tsf);
2133
2134         /* current TSF converted to TU */
2135         hw_tsf = ath5k_hw_get_tsf64(ah);
2136         hw_tu = TSF_TO_TU(hw_tsf);
2137
2138 #define FUDGE 3
2139         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2140         if (bc_tsf == -1) {
2141                 /*
2142                  * no beacons received, called internally.
2143                  * just need to refresh timers based on HW TSF.
2144                  */
2145                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2146         } else if (bc_tsf == 0) {
2147                 /*
2148                  * no beacon received, probably called by ath5k_reset_tsf().
2149                  * reset TSF to start with 0.
2150                  */
2151                 nexttbtt = intval;
2152                 intval |= AR5K_BEACON_RESET_TSF;
2153         } else if (bc_tsf > hw_tsf) {
2154                 /*
2155                  * beacon received, SW merge happend but HW TSF not yet updated.
2156                  * not possible to reconfigure timers yet, but next time we
2157                  * receive a beacon with the same BSSID, the hardware will
2158                  * automatically update the TSF and then we need to reconfigure
2159                  * the timers.
2160                  */
2161                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2162                         "need to wait for HW TSF sync\n");
2163                 return;
2164         } else {
2165                 /*
2166                  * most important case for beacon synchronization between STA.
2167                  *
2168                  * beacon received and HW TSF has been already updated by HW.
2169                  * update next TBTT based on the TSF of the beacon, but make
2170                  * sure it is ahead of our local TSF timer.
2171                  */
2172                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2173         }
2174 #undef FUDGE
2175
2176         sc->nexttbtt = nexttbtt;
2177
2178         intval |= AR5K_BEACON_ENA;
2179         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2180
2181         /*
2182          * debugging output last in order to preserve the time critical aspect
2183          * of this function
2184          */
2185         if (bc_tsf == -1)
2186                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2187                         "reconfigured timers based on HW TSF\n");
2188         else if (bc_tsf == 0)
2189                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2190                         "reset HW TSF and timers\n");
2191         else
2192                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2193                         "updated timers based on beacon TSF\n");
2194
2195         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2196                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2197                           (unsigned long long) bc_tsf,
2198                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2199         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2200                 intval & AR5K_BEACON_PERIOD,
2201                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2202                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2203 }
2204
2205
2206 /**
2207  * ath5k_beacon_config - Configure the beacon queues and interrupts
2208  *
2209  * @sc: struct ath5k_softc pointer we are operating on
2210  *
2211  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2212  * interrupts to detect TSF updates only.
2213  */
2214 static void
2215 ath5k_beacon_config(struct ath5k_softc *sc)
2216 {
2217         struct ath5k_hw *ah = sc->ah;
2218         unsigned long flags;
2219
2220         ath5k_hw_set_imr(ah, 0);
2221         sc->bmisscount = 0;
2222         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2223
2224         if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2225                         sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2226                         sc->opmode == NL80211_IFTYPE_AP) {
2227                 /*
2228                  * In IBSS mode we use a self-linked tx descriptor and let the
2229                  * hardware send the beacons automatically. We have to load it
2230                  * only once here.
2231                  * We use the SWBA interrupt only to keep track of the beacon
2232                  * timers in order to detect automatic TSF updates.
2233                  */
2234                 ath5k_beaconq_config(sc);
2235
2236                 sc->imask |= AR5K_INT_SWBA;
2237
2238                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2239                         if (ath5k_hw_hasveol(ah)) {
2240                                 spin_lock_irqsave(&sc->block, flags);
2241                                 ath5k_beacon_send(sc);
2242                                 spin_unlock_irqrestore(&sc->block, flags);
2243                         }
2244                 } else
2245                         ath5k_beacon_update_timers(sc, -1);
2246         }
2247
2248         ath5k_hw_set_imr(ah, sc->imask);
2249 }
2250
2251
2252 /********************\
2253 * Interrupt handling *
2254 \********************/
2255
2256 static int
2257 ath5k_init(struct ath5k_softc *sc)
2258 {
2259         struct ath5k_hw *ah = sc->ah;
2260         int ret, i;
2261
2262         mutex_lock(&sc->lock);
2263
2264         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2265
2266         /*
2267          * Stop anything previously setup.  This is safe
2268          * no matter this is the first time through or not.
2269          */
2270         ath5k_stop_locked(sc);
2271
2272         /*
2273          * The basic interface to setting the hardware in a good
2274          * state is ``reset''.  On return the hardware is known to
2275          * be powered up and with interrupts disabled.  This must
2276          * be followed by initialization of the appropriate bits
2277          * and then setup of the interrupt mask.
2278          */
2279         sc->curchan = sc->hw->conf.channel;
2280         sc->curband = &sc->sbands[sc->curchan->band];
2281         sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2282                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2283                 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2284         ret = ath5k_reset(sc, false, false);
2285         if (ret)
2286                 goto done;
2287
2288         /*
2289          * Reset the key cache since some parts do not reset the
2290          * contents on initial power up or resume from suspend.
2291          */
2292         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2293                 ath5k_hw_reset_key(ah, i);
2294
2295         /* Set ack to be sent at low bit-rates */
2296         ath5k_hw_set_ack_bitrate_high(ah, false);
2297
2298         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2299                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2300
2301         ret = 0;
2302 done:
2303         mmiowb();
2304         mutex_unlock(&sc->lock);
2305         return ret;
2306 }
2307
2308 static int
2309 ath5k_stop_locked(struct ath5k_softc *sc)
2310 {
2311         struct ath5k_hw *ah = sc->ah;
2312
2313         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2314                         test_bit(ATH_STAT_INVALID, sc->status));
2315
2316         /*
2317          * Shutdown the hardware and driver:
2318          *    stop output from above
2319          *    disable interrupts
2320          *    turn off timers
2321          *    turn off the radio
2322          *    clear transmit machinery
2323          *    clear receive machinery
2324          *    drain and release tx queues
2325          *    reclaim beacon resources
2326          *    power down hardware
2327          *
2328          * Note that some of this work is not possible if the
2329          * hardware is gone (invalid).
2330          */
2331         ieee80211_stop_queues(sc->hw);
2332
2333         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2334                 ath5k_led_off(sc);
2335                 ath5k_hw_set_imr(ah, 0);
2336                 synchronize_irq(sc->pdev->irq);
2337         }
2338         ath5k_txq_cleanup(sc);
2339         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2340                 ath5k_rx_stop(sc);
2341                 ath5k_hw_phy_disable(ah);
2342         } else
2343                 sc->rxlink = NULL;
2344
2345         return 0;
2346 }
2347
2348 /*
2349  * Stop the device, grabbing the top-level lock to protect
2350  * against concurrent entry through ath5k_init (which can happen
2351  * if another thread does a system call and the thread doing the
2352  * stop is preempted).
2353  */
2354 static int
2355 ath5k_stop_hw(struct ath5k_softc *sc)
2356 {
2357         int ret;
2358
2359         mutex_lock(&sc->lock);
2360         ret = ath5k_stop_locked(sc);
2361         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2362                 /*
2363                  * Set the chip in full sleep mode.  Note that we are
2364                  * careful to do this only when bringing the interface
2365                  * completely to a stop.  When the chip is in this state
2366                  * it must be carefully woken up or references to
2367                  * registers in the PCI clock domain may freeze the bus
2368                  * (and system).  This varies by chip and is mostly an
2369                  * issue with newer parts that go to sleep more quickly.
2370                  */
2371                 if (sc->ah->ah_mac_srev >= 0x78) {
2372                         /*
2373                          * XXX
2374                          * don't put newer MAC revisions > 7.8 to sleep because
2375                          * of the above mentioned problems
2376                          */
2377                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2378                                 "not putting device to sleep\n");
2379                 } else {
2380                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2381                                 "putting device to full sleep\n");
2382                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2383                 }
2384         }
2385         ath5k_txbuf_free(sc, sc->bbuf);
2386
2387         mmiowb();
2388         mutex_unlock(&sc->lock);
2389
2390         del_timer_sync(&sc->calib_tim);
2391         tasklet_kill(&sc->rxtq);
2392         tasklet_kill(&sc->txtq);
2393         tasklet_kill(&sc->restq);
2394
2395         return ret;
2396 }
2397
2398 static irqreturn_t
2399 ath5k_intr(int irq, void *dev_id)
2400 {
2401         struct ath5k_softc *sc = dev_id;
2402         struct ath5k_hw *ah = sc->ah;
2403         enum ath5k_int status;
2404         unsigned int counter = 1000;
2405
2406         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2407                                 !ath5k_hw_is_intr_pending(ah)))
2408                 return IRQ_NONE;
2409
2410         do {
2411                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2412                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2413                                 status, sc->imask);
2414                 if (unlikely(status & AR5K_INT_FATAL)) {
2415                         /*
2416                          * Fatal errors are unrecoverable.
2417                          * Typically these are caused by DMA errors.
2418                          */
2419                         tasklet_schedule(&sc->restq);
2420                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2421                         tasklet_schedule(&sc->restq);
2422                 } else {
2423                         if (status & AR5K_INT_SWBA) {
2424                                 /*
2425                                 * Software beacon alert--time to send a beacon.
2426                                 * Handle beacon transmission directly; deferring
2427                                 * this is too slow to meet timing constraints
2428                                 * under load.
2429                                 *
2430                                 * In IBSS mode we use this interrupt just to
2431                                 * keep track of the next TBTT (target beacon
2432                                 * transmission time) in order to detect wether
2433                                 * automatic TSF updates happened.
2434                                 */
2435                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2436                                          /* XXX: only if VEOL suppported */
2437                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2438                                         sc->nexttbtt += sc->bintval;
2439                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2440                                                   "SWBA nexttbtt: %x hw_tu: %x "
2441                                                   "TSF: %llx\n",
2442                                                   sc->nexttbtt,
2443                                                   TSF_TO_TU(tsf),
2444                                                   (unsigned long long) tsf);
2445                                 } else {
2446                                         spin_lock(&sc->block);
2447                                         ath5k_beacon_send(sc);
2448                                         spin_unlock(&sc->block);
2449                                 }
2450                         }
2451                         if (status & AR5K_INT_RXEOL) {
2452                                 /*
2453                                 * NB: the hardware should re-read the link when
2454                                 *     RXE bit is written, but it doesn't work at
2455                                 *     least on older hardware revs.
2456                                 */
2457                                 sc->rxlink = NULL;
2458                         }
2459                         if (status & AR5K_INT_TXURN) {
2460                                 /* bump tx trigger level */
2461                                 ath5k_hw_update_tx_triglevel(ah, true);
2462                         }
2463                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2464                                 tasklet_schedule(&sc->rxtq);
2465                         if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2466                                         | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2467                                 tasklet_schedule(&sc->txtq);
2468                         if (status & AR5K_INT_BMISS) {
2469                                 /* TODO */
2470                         }
2471                         if (status & AR5K_INT_MIB) {
2472                                 /*
2473                                  * These stats are also used for ANI i think
2474                                  * so how about updating them more often ?
2475                                  */
2476                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2477                         }
2478                 }
2479         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2480
2481         if (unlikely(!counter))
2482                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2483
2484         return IRQ_HANDLED;
2485 }
2486
2487 static void
2488 ath5k_tasklet_reset(unsigned long data)
2489 {
2490         struct ath5k_softc *sc = (void *)data;
2491
2492         ath5k_reset_wake(sc);
2493 }
2494
2495 /*
2496  * Periodically recalibrate the PHY to account
2497  * for temperature/environment changes.
2498  */
2499 static void
2500 ath5k_calibrate(unsigned long data)
2501 {
2502         struct ath5k_softc *sc = (void *)data;
2503         struct ath5k_hw *ah = sc->ah;
2504
2505         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2506                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2507                 sc->curchan->hw_value);
2508
2509         if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2510                 /*
2511                  * Rfgain is out of bounds, reset the chip
2512                  * to load new gain values.
2513                  */
2514                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2515                 ath5k_reset_wake(sc);
2516         }
2517         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2518                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2519                         ieee80211_frequency_to_channel(
2520                                 sc->curchan->center_freq));
2521
2522         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2523                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2524 }
2525
2526
2527
2528 /***************\
2529 * LED functions *
2530 \***************/
2531
2532 static void
2533 ath5k_led_enable(struct ath5k_softc *sc)
2534 {
2535         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2536                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2537                 ath5k_led_off(sc);
2538         }
2539 }
2540
2541 static void
2542 ath5k_led_on(struct ath5k_softc *sc)
2543 {
2544         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2545                 return;
2546         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2547 }
2548
2549 static void
2550 ath5k_led_off(struct ath5k_softc *sc)
2551 {
2552         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2553                 return;
2554         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2555 }
2556
2557 static void
2558 ath5k_led_brightness_set(struct led_classdev *led_dev,
2559         enum led_brightness brightness)
2560 {
2561         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2562                 led_dev);
2563
2564         if (brightness == LED_OFF)
2565                 ath5k_led_off(led->sc);
2566         else
2567                 ath5k_led_on(led->sc);
2568 }
2569
2570 static int
2571 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2572                    const char *name, char *trigger)
2573 {
2574         int err;
2575
2576         led->sc = sc;
2577         strncpy(led->name, name, sizeof(led->name));
2578         led->led_dev.name = led->name;
2579         led->led_dev.default_trigger = trigger;
2580         led->led_dev.brightness_set = ath5k_led_brightness_set;
2581
2582         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2583         if (err) {
2584                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2585                 led->sc = NULL;
2586         }
2587         return err;
2588 }
2589
2590 static void
2591 ath5k_unregister_led(struct ath5k_led *led)
2592 {
2593         if (!led->sc)
2594                 return;
2595         led_classdev_unregister(&led->led_dev);
2596         ath5k_led_off(led->sc);
2597         led->sc = NULL;
2598 }
2599
2600 static void
2601 ath5k_unregister_leds(struct ath5k_softc *sc)
2602 {
2603         ath5k_unregister_led(&sc->rx_led);
2604         ath5k_unregister_led(&sc->tx_led);
2605 }
2606
2607
2608 static int
2609 ath5k_init_leds(struct ath5k_softc *sc)
2610 {
2611         int ret = 0;
2612         struct ieee80211_hw *hw = sc->hw;
2613         struct pci_dev *pdev = sc->pdev;
2614         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2615
2616         /*
2617          * Auto-enable soft led processing for IBM cards and for
2618          * 5211 minipci cards.
2619          */
2620         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2621             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2622                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2623                 sc->led_pin = 0;
2624                 sc->led_on = 0;  /* active low */
2625         }
2626         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2627         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2628                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2629                 sc->led_pin = 1;
2630                 sc->led_on = 1;  /* active high */
2631         }
2632         /*
2633          * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2634          * in emachines notebooks with AMBIT subsystem.
2635          */
2636         if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2637             pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
2638                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2639                 sc->led_pin = 3;
2640                 sc->led_on = 0;  /* active low */
2641         }
2642
2643         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2644                 goto out;
2645
2646         ath5k_led_enable(sc);
2647
2648         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2649         ret = ath5k_register_led(sc, &sc->rx_led, name,
2650                 ieee80211_get_rx_led_name(hw));
2651         if (ret)
2652                 goto out;
2653
2654         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2655         ret = ath5k_register_led(sc, &sc->tx_led, name,
2656                 ieee80211_get_tx_led_name(hw));
2657 out:
2658         return ret;
2659 }
2660
2661
2662 /********************\
2663 * Mac80211 functions *
2664 \********************/
2665
2666 static int
2667 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2668 {
2669         struct ath5k_softc *sc = hw->priv;
2670         struct ath5k_buf *bf;
2671         unsigned long flags;
2672         int hdrlen;
2673         int padsize;
2674
2675         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2676
2677         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2678                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2679
2680         /*
2681          * the hardware expects the header padded to 4 byte boundaries
2682          * if this is not the case we add the padding after the header
2683          */
2684         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2685         padsize = ath5k_pad_size(hdrlen);
2686         if (padsize) {
2687
2688                 if (skb_headroom(skb) < padsize) {
2689                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2690                                   " headroom to pad %d\n", hdrlen, padsize);
2691                         return NETDEV_TX_BUSY;
2692                 }
2693                 skb_push(skb, padsize);
2694                 memmove(skb->data, skb->data+padsize, hdrlen);
2695         }
2696
2697         spin_lock_irqsave(&sc->txbuflock, flags);
2698         if (list_empty(&sc->txbuf)) {
2699                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2700                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2701                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2702                 return NETDEV_TX_BUSY;
2703         }
2704         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2705         list_del(&bf->list);
2706         sc->txbuf_len--;
2707         if (list_empty(&sc->txbuf))
2708                 ieee80211_stop_queues(hw);
2709         spin_unlock_irqrestore(&sc->txbuflock, flags);
2710
2711         bf->skb = skb;
2712
2713         if (ath5k_txbuf_setup(sc, bf)) {
2714                 bf->skb = NULL;
2715                 spin_lock_irqsave(&sc->txbuflock, flags);
2716                 list_add_tail(&bf->list, &sc->txbuf);
2717                 sc->txbuf_len++;
2718                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2719                 dev_kfree_skb_any(skb);
2720                 return NETDEV_TX_OK;
2721         }
2722
2723         return NETDEV_TX_OK;
2724 }
2725
2726 static int
2727 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2728 {
2729         struct ath5k_hw *ah = sc->ah;
2730         int ret;
2731
2732         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2733
2734         if (stop) {
2735                 ath5k_hw_set_imr(ah, 0);
2736                 ath5k_txq_cleanup(sc);
2737                 ath5k_rx_stop(sc);
2738         }
2739         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2740         if (ret) {
2741                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2742                 goto err;
2743         }
2744
2745         /*
2746          * This is needed only to setup initial state
2747          * but it's best done after a reset.
2748          */
2749         ath5k_hw_set_txpower_limit(sc->ah, 0);
2750
2751         ret = ath5k_rx_start(sc);
2752         if (ret) {
2753                 ATH5K_ERR(sc, "can't start recv logic\n");
2754                 goto err;
2755         }
2756
2757         /*
2758          * Change channels and update the h/w rate map if we're switching;
2759          * e.g. 11a to 11b/g.
2760          *
2761          * We may be doing a reset in response to an ioctl that changes the
2762          * channel so update any state that might change as a result.
2763          *
2764          * XXX needed?
2765          */
2766 /*      ath5k_chan_change(sc, c); */
2767
2768         ath5k_beacon_config(sc);
2769         /* intrs are enabled by ath5k_beacon_config */
2770
2771         return 0;
2772 err:
2773         return ret;
2774 }
2775
2776 static int
2777 ath5k_reset_wake(struct ath5k_softc *sc)
2778 {
2779         int ret;
2780
2781         ret = ath5k_reset(sc, true, true);
2782         if (!ret)
2783                 ieee80211_wake_queues(sc->hw);
2784
2785         return ret;
2786 }
2787
2788 static int ath5k_start(struct ieee80211_hw *hw)
2789 {
2790         return ath5k_init(hw->priv);
2791 }
2792
2793 static void ath5k_stop(struct ieee80211_hw *hw)
2794 {
2795         ath5k_stop_hw(hw->priv);
2796 }
2797
2798 static int ath5k_add_interface(struct ieee80211_hw *hw,
2799                 struct ieee80211_if_init_conf *conf)
2800 {
2801         struct ath5k_softc *sc = hw->priv;
2802         int ret;
2803
2804         mutex_lock(&sc->lock);
2805         if (sc->vif) {
2806                 ret = 0;
2807                 goto end;
2808         }
2809
2810         sc->vif = conf->vif;
2811
2812         switch (conf->type) {
2813         case NL80211_IFTYPE_AP:
2814         case NL80211_IFTYPE_STATION:
2815         case NL80211_IFTYPE_ADHOC:
2816         case NL80211_IFTYPE_MESH_POINT:
2817         case NL80211_IFTYPE_MONITOR:
2818                 sc->opmode = conf->type;
2819                 break;
2820         default:
2821                 ret = -EOPNOTSUPP;
2822                 goto end;
2823         }
2824
2825         /* Set to a reasonable value. Note that this will
2826          * be set to mac80211's value at ath5k_config(). */
2827         sc->bintval = 1000;
2828         ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2829
2830         ret = 0;
2831 end:
2832         mutex_unlock(&sc->lock);
2833         return ret;
2834 }
2835
2836 static void
2837 ath5k_remove_interface(struct ieee80211_hw *hw,
2838                         struct ieee80211_if_init_conf *conf)
2839 {
2840         struct ath5k_softc *sc = hw->priv;
2841         u8 mac[ETH_ALEN] = {};
2842
2843         mutex_lock(&sc->lock);
2844         if (sc->vif != conf->vif)
2845                 goto end;
2846
2847         ath5k_hw_set_lladdr(sc->ah, mac);
2848         sc->vif = NULL;
2849 end:
2850         mutex_unlock(&sc->lock);
2851 }
2852
2853 /*
2854  * TODO: Phy disable/diversity etc
2855  */
2856 static int
2857 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2858 {
2859         struct ath5k_softc *sc = hw->priv;
2860         struct ieee80211_conf *conf = &hw->conf;
2861         int ret;
2862
2863         mutex_lock(&sc->lock);
2864
2865         sc->bintval = conf->beacon_int;
2866         sc->power_level = conf->power_level;
2867
2868         ret = ath5k_chan_set(sc, conf->channel);
2869
2870         mutex_unlock(&sc->lock);
2871         return ret;
2872 }
2873
2874 static int
2875 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2876                         struct ieee80211_if_conf *conf)
2877 {
2878         struct ath5k_softc *sc = hw->priv;
2879         struct ath5k_hw *ah = sc->ah;
2880         int ret = 0;
2881
2882         mutex_lock(&sc->lock);
2883         if (sc->vif != vif) {
2884                 ret = -EIO;
2885                 goto unlock;
2886         }
2887         if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2888                 /* Cache for later use during resets */
2889                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2890                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2891                  * a clean way of letting us retrieve this yet. */
2892                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2893                 mmiowb();
2894         }
2895         if (conf->changed & IEEE80211_IFCC_BEACON &&
2896                         (vif->type == NL80211_IFTYPE_ADHOC ||
2897                          vif->type == NL80211_IFTYPE_MESH_POINT ||
2898                          vif->type == NL80211_IFTYPE_AP)) {
2899                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2900                 if (!beacon) {
2901                         ret = -ENOMEM;
2902                         goto unlock;
2903                 }
2904                 ath5k_beacon_update(sc, beacon);
2905         }
2906
2907 unlock:
2908         mutex_unlock(&sc->lock);
2909         return ret;
2910 }
2911
2912 #define SUPPORTED_FIF_FLAGS \
2913         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2914         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2915         FIF_BCN_PRBRESP_PROMISC
2916 /*
2917  * o always accept unicast, broadcast, and multicast traffic
2918  * o multicast traffic for all BSSIDs will be enabled if mac80211
2919  *   says it should be
2920  * o maintain current state of phy ofdm or phy cck error reception.
2921  *   If the hardware detects any of these type of errors then
2922  *   ath5k_hw_get_rx_filter() will pass to us the respective
2923  *   hardware filters to be able to receive these type of frames.
2924  * o probe request frames are accepted only when operating in
2925  *   hostap, adhoc, or monitor modes
2926  * o enable promiscuous mode according to the interface state
2927  * o accept beacons:
2928  *   - when operating in adhoc mode so the 802.11 layer creates
2929  *     node table entries for peers,
2930  *   - when operating in station mode for collecting rssi data when
2931  *     the station is otherwise quiet, or
2932  *   - when scanning
2933  */
2934 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2935                 unsigned int changed_flags,
2936                 unsigned int *new_flags,
2937                 int mc_count, struct dev_mc_list *mclist)
2938 {
2939         struct ath5k_softc *sc = hw->priv;
2940         struct ath5k_hw *ah = sc->ah;
2941         u32 mfilt[2], val, rfilt;
2942         u8 pos;
2943         int i;
2944
2945         mfilt[0] = 0;
2946         mfilt[1] = 0;
2947
2948         /* Only deal with supported flags */
2949         changed_flags &= SUPPORTED_FIF_FLAGS;
2950         *new_flags &= SUPPORTED_FIF_FLAGS;
2951
2952         /* If HW detects any phy or radar errors, leave those filters on.
2953          * Also, always enable Unicast, Broadcasts and Multicast
2954          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2955         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2956                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2957                 AR5K_RX_FILTER_MCAST);
2958
2959         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2960                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2961                         rfilt |= AR5K_RX_FILTER_PROM;
2962                         __set_bit(ATH_STAT_PROMISC, sc->status);
2963                 } else {
2964                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2965                 }
2966         }
2967
2968         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2969         if (*new_flags & FIF_ALLMULTI) {
2970                 mfilt[0] =  ~0;
2971                 mfilt[1] =  ~0;
2972         } else {
2973                 for (i = 0; i < mc_count; i++) {
2974                         if (!mclist)
2975                                 break;
2976                         /* calculate XOR of eight 6-bit values */
2977                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2978                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2979                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2980                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2981                         pos &= 0x3f;
2982                         mfilt[pos / 32] |= (1 << (pos % 32));
2983                         /* XXX: we might be able to just do this instead,
2984                         * but not sure, needs testing, if we do use this we'd
2985                         * neet to inform below to not reset the mcast */
2986                         /* ath5k_hw_set_mcast_filterindex(ah,
2987                          *      mclist->dmi_addr[5]); */
2988                         mclist = mclist->next;
2989                 }
2990         }
2991
2992         /* This is the best we can do */
2993         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2994                 rfilt |= AR5K_RX_FILTER_PHYERR;
2995
2996         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2997         * and probes for any BSSID, this needs testing */
2998         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2999                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3000
3001         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3002          * set we should only pass on control frames for this
3003          * station. This needs testing. I believe right now this
3004          * enables *all* control frames, which is OK.. but
3005          * but we should see if we can improve on granularity */
3006         if (*new_flags & FIF_CONTROL)
3007                 rfilt |= AR5K_RX_FILTER_CONTROL;
3008
3009         /* Additional settings per mode -- this is per ath5k */
3010
3011         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3012
3013         if (sc->opmode == NL80211_IFTYPE_MONITOR)
3014                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3015                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3016         if (sc->opmode != NL80211_IFTYPE_STATION)
3017                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
3018         if (sc->opmode != NL80211_IFTYPE_AP &&
3019                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
3020                 test_bit(ATH_STAT_PROMISC, sc->status))
3021                 rfilt |= AR5K_RX_FILTER_PROM;
3022         if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
3023                 sc->opmode == NL80211_IFTYPE_ADHOC ||
3024                 sc->opmode == NL80211_IFTYPE_AP)
3025                 rfilt |= AR5K_RX_FILTER_BEACON;
3026         if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3027                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3028                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3029
3030         /* Set filters */
3031         ath5k_hw_set_rx_filter(ah, rfilt);
3032
3033         /* Set multicast bits */
3034         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3035         /* Set the cached hw filter flags, this will alter actually
3036          * be set in HW */
3037         sc->filter_flags = rfilt;
3038 }
3039
3040 static int
3041 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3042               struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3043               struct ieee80211_key_conf *key)
3044 {
3045         struct ath5k_softc *sc = hw->priv;
3046         int ret = 0;
3047
3048         if (modparam_nohwcrypt)
3049                 return -EOPNOTSUPP;
3050
3051         switch (key->alg) {
3052         case ALG_WEP:
3053         case ALG_TKIP:
3054                 break;
3055         case ALG_CCMP:
3056                 return -EOPNOTSUPP;
3057         default:
3058                 WARN_ON(1);
3059                 return -EINVAL;
3060         }
3061
3062         mutex_lock(&sc->lock);
3063
3064         switch (cmd) {
3065         case SET_KEY:
3066                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3067                                        sta ? sta->addr : NULL);
3068                 if (ret) {
3069                         ATH5K_ERR(sc, "can't set the key\n");
3070                         goto unlock;
3071                 }
3072                 __set_bit(key->keyidx, sc->keymap);
3073                 key->hw_key_idx = key->keyidx;
3074                 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3075                                IEEE80211_KEY_FLAG_GENERATE_MMIC);
3076                 break;
3077         case DISABLE_KEY:
3078                 ath5k_hw_reset_key(sc->ah, key->keyidx);
3079                 __clear_bit(key->keyidx, sc->keymap);
3080                 break;
3081         default:
3082                 ret = -EINVAL;
3083                 goto unlock;
3084         }
3085
3086 unlock:
3087         mmiowb();
3088         mutex_unlock(&sc->lock);
3089         return ret;
3090 }
3091
3092 static int
3093 ath5k_get_stats(struct ieee80211_hw *hw,
3094                 struct ieee80211_low_level_stats *stats)
3095 {
3096         struct ath5k_softc *sc = hw->priv;
3097         struct ath5k_hw *ah = sc->ah;
3098
3099         /* Force update */
3100         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3101
3102         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3103
3104         return 0;
3105 }
3106
3107 static int
3108 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3109                 struct ieee80211_tx_queue_stats *stats)
3110 {
3111         struct ath5k_softc *sc = hw->priv;
3112
3113         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3114
3115         return 0;
3116 }
3117
3118 static u64
3119 ath5k_get_tsf(struct ieee80211_hw *hw)
3120 {
3121         struct ath5k_softc *sc = hw->priv;
3122
3123         return ath5k_hw_get_tsf64(sc->ah);
3124 }
3125
3126 static void
3127 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3128 {
3129         struct ath5k_softc *sc = hw->priv;
3130
3131         ath5k_hw_set_tsf64(sc->ah, tsf);
3132 }
3133
3134 static void
3135 ath5k_reset_tsf(struct ieee80211_hw *hw)
3136 {
3137         struct ath5k_softc *sc = hw->priv;
3138
3139         /*
3140          * in IBSS mode we need to update the beacon timers too.
3141          * this will also reset the TSF if we call it with 0
3142          */
3143         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3144                 ath5k_beacon_update_timers(sc, 0);
3145         else
3146                 ath5k_hw_reset_tsf(sc->ah);
3147 }
3148
3149 static int
3150 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3151 {
3152         unsigned long flags;
3153         int ret;
3154
3155         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3156
3157         spin_lock_irqsave(&sc->block, flags);
3158         ath5k_txbuf_free(sc, sc->bbuf);
3159         sc->bbuf->skb = skb;
3160         ret = ath5k_beacon_setup(sc, sc->bbuf);
3161         if (ret)
3162                 sc->bbuf->skb = NULL;
3163         spin_unlock_irqrestore(&sc->block, flags);
3164         if (!ret) {
3165                 ath5k_beacon_config(sc);
3166                 mmiowb();
3167         }
3168
3169         return ret;
3170 }
3171 static void
3172 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3173 {
3174         struct ath5k_softc *sc = hw->priv;
3175         struct ath5k_hw *ah = sc->ah;
3176         u32 rfilt;
3177         rfilt = ath5k_hw_get_rx_filter(ah);
3178         if (enable)
3179                 rfilt |= AR5K_RX_FILTER_BEACON;
3180         else
3181                 rfilt &= ~AR5K_RX_FILTER_BEACON;
3182         ath5k_hw_set_rx_filter(ah, rfilt);
3183         sc->filter_flags = rfilt;
3184 }
3185
3186 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3187                                     struct ieee80211_vif *vif,
3188                                     struct ieee80211_bss_conf *bss_conf,
3189                                     u32 changes)
3190 {
3191         struct ath5k_softc *sc = hw->priv;
3192         if (changes & BSS_CHANGED_ASSOC) {
3193                 mutex_lock(&sc->lock);
3194                 sc->assoc = bss_conf->assoc;
3195                 if (sc->opmode == NL80211_IFTYPE_STATION)
3196                         set_beacon_filter(hw, sc->assoc);
3197                 mutex_unlock(&sc->lock);
3198         }
3199 }