2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 struct ath_tx_control *txctl);
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 struct ieee80211_sta *sta = info->status.status_driver_data[0];
89 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 IEEE80211_TX_STATUS_EOSP)) {
91 ieee80211_tx_status(hw, skb);
96 ieee80211_tx_status_noskb(hw, sta, info);
101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 __releases(&txq->axq_lock)
104 struct ieee80211_hw *hw = sc->hw;
105 struct sk_buff_head q;
108 __skb_queue_head_init(&q);
109 skb_queue_splice_init(&txq->complete_q, &q);
110 spin_unlock_bh(&txq->axq_lock);
112 while ((skb = __skb_dequeue(&q)))
113 ath_tx_status(hw, skb);
116 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
118 struct ieee80211_txq *queue =
119 container_of((void *)tid, struct ieee80211_txq, drv_priv);
121 ieee80211_schedule_txq(sc->hw, queue);
124 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
126 struct ath_softc *sc = hw->priv;
127 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
128 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
129 struct ath_txq *txq = tid->txq;
131 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
132 queue->sta ? queue->sta->addr : queue->vif->addr,
135 ath_txq_lock(sc, txq);
136 ath_txq_schedule(sc, txq);
137 ath_txq_unlock(sc, txq);
140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->status.status_driver_data));
145 return (struct ath_frame_info *) &tx_info->status.status_driver_data[0];
148 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
153 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
154 seqno << IEEE80211_SEQ_SEQ_SHIFT);
157 static bool ath_merge_ratetbl(struct ieee80211_sta *sta, struct ath_buf *bf,
158 struct ieee80211_tx_info *tx_info)
160 struct ieee80211_sta_rates *ratetbl;
166 ratetbl = rcu_dereference(sta->rates);
170 if (tx_info->control.rates[0].idx < 0 ||
171 tx_info->control.rates[0].count == 0)
175 bf->rates[0] = tx_info->control.rates[0];
179 for ( ; i < IEEE80211_TX_MAX_RATES; i++) {
180 bf->rates[i].idx = ratetbl->rate[i].idx;
181 bf->rates[i].flags = ratetbl->rate[i].flags;
182 if (tx_info->control.use_rts)
183 bf->rates[i].count = ratetbl->rate[i].count_rts;
184 else if (tx_info->control.use_cts_prot)
185 bf->rates[i].count = ratetbl->rate[i].count_cts;
187 bf->rates[i].count = ratetbl->rate[i].count;
193 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
196 struct ieee80211_tx_info *tx_info;
198 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
200 if (!ath_merge_ratetbl(sta, bf, tx_info))
201 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
202 ARRAY_SIZE(bf->rates));
205 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
208 struct ath_frame_info *fi = get_frame_info(skb);
214 txq = sc->tx.txq_map[q];
215 if (WARN_ON(--txq->pending_frames < 0))
216 txq->pending_frames = 0;
220 static struct ath_atx_tid *
221 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
223 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
224 return ATH_AN_2_TID(an, tidno);
228 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf)
230 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
231 struct ath_softc *sc = tid->an->sc;
232 struct ieee80211_hw *hw = sc->hw;
233 struct ath_tx_control txctl = {
238 struct ath_frame_info *fi;
241 skb = ieee80211_tx_dequeue(hw, txq);
245 ret = ath_tx_prepare(hw, skb, &txctl);
247 ieee80211_free_txskb(hw, skb);
251 q = skb_get_queue_mapping(skb);
252 if (tid->txq == sc->tx.txq_map[q]) {
253 fi = get_frame_info(skb);
255 ++tid->txq->pending_frames;
262 static int ath_tid_dequeue(struct ath_atx_tid *tid,
263 struct sk_buff **skb)
266 *skb = __skb_dequeue(&tid->retry_q);
268 ret = ath_tid_pull(tid, skb);
273 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
275 struct ath_txq *txq = tid->txq;
278 struct list_head bf_head;
279 struct ath_tx_status ts;
280 struct ath_frame_info *fi;
281 bool sendbar = false;
283 INIT_LIST_HEAD(&bf_head);
285 memset(&ts, 0, sizeof(ts));
287 while ((skb = __skb_dequeue(&tid->retry_q))) {
288 fi = get_frame_info(skb);
291 ath_txq_skb_done(sc, txq, skb);
292 ieee80211_free_txskb(sc->hw, skb);
296 if (fi->baw_tracked) {
297 ath_tx_update_baw(sc, tid, bf);
301 list_add_tail(&bf->list, &bf_head);
302 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
306 ath_txq_unlock(sc, txq);
307 ath_send_bar(tid, tid->seq_start);
308 ath_txq_lock(sc, txq);
312 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
315 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
316 u16 seqno = bf->bf_state.seqno;
319 if (!fi->baw_tracked)
322 index = ATH_BA_INDEX(tid->seq_start, seqno);
323 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
325 __clear_bit(cindex, tid->tx_buf);
327 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
328 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
329 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
330 if (tid->bar_index >= 0)
335 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
338 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
339 u16 seqno = bf->bf_state.seqno;
345 index = ATH_BA_INDEX(tid->seq_start, seqno);
346 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
347 __set_bit(cindex, tid->tx_buf);
350 if (index >= ((tid->baw_tail - tid->baw_head) &
351 (ATH_TID_MAX_BUFS - 1))) {
352 tid->baw_tail = cindex;
353 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
357 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
358 struct ath_atx_tid *tid)
363 struct list_head bf_head;
364 struct ath_tx_status ts;
365 struct ath_frame_info *fi;
368 memset(&ts, 0, sizeof(ts));
369 INIT_LIST_HEAD(&bf_head);
371 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) {
372 fi = get_frame_info(skb);
376 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
380 list_add_tail(&bf->list, &bf_head);
381 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
385 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
386 struct sk_buff *skb, int count)
388 struct ath_frame_info *fi = get_frame_info(skb);
389 struct ath_buf *bf = fi->bf;
390 struct ieee80211_hdr *hdr;
391 int prev = fi->retries;
393 TX_STAT_INC(sc, txq->axq_qnum, a_retries);
394 fi->retries += count;
399 hdr = (struct ieee80211_hdr *)skb->data;
400 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
401 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
402 sizeof(*hdr), DMA_TO_DEVICE);
405 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
407 struct ath_buf *bf = NULL;
409 spin_lock_bh(&sc->tx.txbuflock);
411 if (unlikely(list_empty(&sc->tx.txbuf))) {
412 spin_unlock_bh(&sc->tx.txbuflock);
416 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
419 spin_unlock_bh(&sc->tx.txbuflock);
424 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
426 spin_lock_bh(&sc->tx.txbuflock);
427 list_add_tail(&bf->list, &sc->tx.txbuf);
428 spin_unlock_bh(&sc->tx.txbuflock);
431 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
435 tbf = ath_tx_get_buffer(sc);
439 ATH_TXBUF_RESET(tbf);
441 tbf->bf_mpdu = bf->bf_mpdu;
442 tbf->bf_buf_addr = bf->bf_buf_addr;
443 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
444 tbf->bf_state = bf->bf_state;
445 tbf->bf_state.stale = false;
450 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
451 struct ath_tx_status *ts, int txok,
452 int *nframes, int *nbad)
455 u32 ba[WME_BA_BMP_SIZE >> 5];
462 isaggr = bf_isaggr(bf);
464 seq_st = ts->ts_seqnum;
465 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
469 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
472 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
480 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
481 struct ath_buf *bf, struct list_head *bf_q,
482 struct ieee80211_sta *sta,
483 struct ath_atx_tid *tid,
484 struct ath_tx_status *ts, int txok)
486 struct ath_node *an = NULL;
488 struct ieee80211_tx_info *tx_info;
489 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
490 struct list_head bf_head;
491 struct sk_buff_head bf_pending;
492 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
493 u32 ba[WME_BA_BMP_SIZE >> 5];
494 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
495 bool rc_update = true, isba;
496 struct ieee80211_tx_rate rates[4];
497 struct ath_frame_info *fi;
499 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
504 tx_info = IEEE80211_SKB_CB(skb);
506 memcpy(rates, bf->rates, sizeof(rates));
508 retries = ts->ts_longretry + 1;
509 for (i = 0; i < ts->ts_rateindex; i++)
510 retries += rates[i].count;
513 INIT_LIST_HEAD(&bf_head);
515 bf_next = bf->bf_next;
517 if (!bf->bf_state.stale || bf_next != NULL)
518 list_move_tail(&bf->list, &bf_head);
520 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
527 an = (struct ath_node *)sta->drv_priv;
528 seq_first = tid->seq_start;
529 isba = ts->ts_flags & ATH9K_TX_BA;
532 * The hardware occasionally sends a tx status for the wrong TID.
533 * In this case, the BA status cannot be considered valid and all
534 * subframes need to be retransmitted
536 * Only BlockAcks have a TID and therefore normal Acks cannot be
539 if (isba && tid->tidno != ts->tid)
542 isaggr = bf_isaggr(bf);
543 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
545 if (isaggr && txok) {
546 if (ts->ts_flags & ATH9K_TX_BA) {
547 seq_st = ts->ts_seqnum;
548 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
551 * AR5416 can become deaf/mute when BA
552 * issue happens. Chip needs to be reset.
553 * But AP code may have sychronization issues
554 * when perform internal reset in this routine.
555 * Only enable reset in STA mode for now.
557 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
562 __skb_queue_head_init(&bf_pending);
564 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
566 u16 seqno = bf->bf_state.seqno;
568 txfail = txpending = sendbar = 0;
569 bf_next = bf->bf_next;
572 tx_info = IEEE80211_SKB_CB(skb);
573 fi = get_frame_info(skb);
575 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
578 * Outside of the current BlockAck window,
579 * maybe part of a previous session
582 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
583 /* transmit completion, subframe is
584 * acked by block ack */
586 } else if (!isaggr && txok) {
587 /* transmit completion */
591 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
592 if (txok || !an->sleeping)
593 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
600 bar_index = max_t(int, bar_index,
601 ATH_BA_INDEX(seq_first, seqno));
605 * Make sure the last desc is reclaimed if it
606 * not a holding desc.
608 INIT_LIST_HEAD(&bf_head);
609 if (bf_next != NULL || !bf_last->bf_state.stale)
610 list_move_tail(&bf->list, &bf_head);
614 * complete the acked-ones/xretried ones; update
617 ath_tx_update_baw(sc, tid, bf);
619 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
620 memcpy(tx_info->control.rates, rates, sizeof(rates));
621 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
623 if (bf == bf->bf_lastbf)
624 ath_dynack_sample_tx_ts(sc->sc_ah,
629 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
632 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
633 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
634 ieee80211_sta_eosp(sta);
636 /* retry the un-acked ones */
637 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
640 tbf = ath_clone_txbuf(sc, bf_last);
642 * Update tx baw and complete the
643 * frame with failed status if we
647 ath_tx_update_baw(sc, tid, bf);
649 ath_tx_complete_buf(sc, bf, txq,
652 bar_index = max_t(int, bar_index,
653 ATH_BA_INDEX(seq_first, seqno));
661 * Put this buffer to the temporary pending
662 * queue to retain ordering
664 __skb_queue_tail(&bf_pending, skb);
670 /* prepend un-acked frames to the beginning of the pending frame queue */
671 if (!skb_queue_empty(&bf_pending)) {
673 ieee80211_sta_set_buffered(sta, tid->tidno, true);
675 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
677 ath_tx_queue_tid(sc, tid);
678 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
679 tid->clear_ps_filter = true;
683 if (bar_index >= 0) {
684 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
686 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
687 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
689 ath_txq_unlock(sc, txq);
690 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
691 ath_txq_lock(sc, txq);
695 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
698 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
700 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
701 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
704 static void ath_tx_count_airtime(struct ath_softc *sc,
705 struct ieee80211_sta *sta,
707 struct ath_tx_status *ts,
713 airtime += ts->duration * (ts->ts_longretry + 1);
714 for(i = 0; i < ts->ts_rateindex; i++) {
715 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
716 airtime += rate_dur * bf->rates[i].count;
719 ieee80211_sta_register_airtime(sta, tid, airtime, 0);
722 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
723 struct ath_tx_status *ts, struct ath_buf *bf,
724 struct list_head *bf_head)
726 struct ieee80211_hw *hw = sc->hw;
727 struct ieee80211_tx_info *info;
728 struct ieee80211_sta *sta;
729 struct ieee80211_hdr *hdr;
730 struct ath_atx_tid *tid = NULL;
733 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
734 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
735 txq->axq_tx_inprogress = false;
738 if (bf_is_ampdu_not_probing(bf))
739 txq->axq_ampdu_depth--;
741 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
744 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
745 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
747 struct ath_node *an = (struct ath_node *)sta->drv_priv;
748 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
749 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno);
750 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
751 tid->clear_ps_filter = true;
754 if (!bf_isampdu(bf)) {
756 info = IEEE80211_SKB_CB(bf->bf_mpdu);
757 memcpy(info->control.rates, bf->rates,
758 sizeof(info->control.rates));
759 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
760 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
763 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
765 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
768 ath_txq_schedule(sc, txq);
771 static bool ath_lookup_legacy(struct ath_buf *bf)
774 struct ieee80211_tx_info *tx_info;
775 struct ieee80211_tx_rate *rates;
779 tx_info = IEEE80211_SKB_CB(skb);
780 rates = tx_info->control.rates;
782 for (i = 0; i < 4; i++) {
783 if (!rates[i].count || rates[i].idx < 0)
786 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
793 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
794 struct ath_atx_tid *tid)
797 struct ieee80211_tx_info *tx_info;
798 struct ieee80211_tx_rate *rates;
799 u32 max_4ms_framelen, frmlen;
800 u16 aggr_limit, bt_aggr_limit, legacy = 0;
801 int q = tid->txq->mac80211_qnum;
805 tx_info = IEEE80211_SKB_CB(skb);
809 * Find the lowest frame length among the rate series that will have a
810 * 4ms (or TXOP limited) transmit duration.
812 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
814 for (i = 0; i < 4; i++) {
820 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
825 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
830 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
833 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
834 max_4ms_framelen = min(max_4ms_framelen, frmlen);
838 * limit aggregate size by the minimum rate if rate selected is
839 * not a probe rate, if rate selected is a probe rate then
840 * avoid aggregation of this packet.
842 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
845 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
848 * Override the default aggregation limit for BTCOEX.
850 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
852 aggr_limit = bt_aggr_limit;
854 if (tid->an->maxampdu)
855 aggr_limit = min(aggr_limit, tid->an->maxampdu);
861 * Returns the number of delimiters to be added to
862 * meet the minimum required mpdudensity.
864 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
865 struct ath_buf *bf, u16 frmlen,
868 #define FIRST_DESC_NDELIMS 60
869 u32 nsymbits, nsymbols;
872 int width, streams, half_gi, ndelim, mindelim;
873 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
875 /* Select standard number of delimiters based on frame length alone */
876 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
879 * If encryption enabled, hardware requires some more padding between
881 * TODO - this could be improved to be dependent on the rate.
882 * The hardware can keep up at lower rates, but not higher rates
884 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
885 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
886 ndelim += ATH_AGGR_ENCRYPTDELIM;
889 * Add delimiter when using RTS/CTS with aggregation
890 * and non enterprise AR9003 card
892 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
893 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
894 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
897 * Convert desired mpdu density from microeconds to bytes based
898 * on highest rate in rate series (i.e. first rate) to determine
899 * required minimum length for subframe. Take into account
900 * whether high rate is 20 or 40Mhz and half or full GI.
902 * If there is no mpdu density restriction, no further calculation
906 if (tid->an->mpdudensity == 0)
909 rix = bf->rates[0].idx;
910 flags = bf->rates[0].flags;
911 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
912 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
915 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
917 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
922 streams = HT_RC_2_STREAMS(rix);
923 nsymbits = bits_per_symbol[rix % 8][width] * streams;
924 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
926 if (frmlen < minlen) {
927 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
928 ndelim = max(mindelim, ndelim);
935 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
936 struct ath_atx_tid *tid, struct ath_buf **buf)
938 struct ieee80211_tx_info *tx_info;
939 struct ath_frame_info *fi;
941 struct sk_buff *skb, *first_skb = NULL;
946 ret = ath_tid_dequeue(tid, &skb);
950 fi = get_frame_info(skb);
953 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
955 bf->bf_state.stale = false;
958 ath_txq_skb_done(sc, txq, skb);
959 ieee80211_free_txskb(sc->hw, skb);
966 tx_info = IEEE80211_SKB_CB(skb);
967 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
968 IEEE80211_TX_STATUS_EOSP);
971 * No aggregation session is running, but there may be frames
972 * from a previous session or a failed attempt in the queue.
973 * Send them out as normal data frames
976 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
978 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
979 bf->bf_state.bf_type = 0;
983 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
984 seqno = bf->bf_state.seqno;
986 /* do not step over block-ack window */
987 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
988 __skb_queue_tail(&tid->retry_q, skb);
990 /* If there are other skbs in the retry q, they are
991 * probably within the BAW, so loop immediately to get
992 * one of them. Otherwise the queue can get stuck. */
993 if (!skb_queue_is_first(&tid->retry_q, skb) &&
994 !WARN_ON(skb == first_skb)) {
995 if(!first_skb) /* infinite loop prevention */
1002 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1003 struct ath_tx_status ts = {};
1004 struct list_head bf_head;
1006 INIT_LIST_HEAD(&bf_head);
1007 list_add(&bf->list, &bf_head);
1008 ath_tx_update_baw(sc, tid, bf);
1009 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1014 ath_tx_addto_baw(sc, tid, bf);
1024 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1025 struct ath_atx_tid *tid, struct list_head *bf_q,
1026 struct ath_buf *bf_first)
1028 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1029 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1030 int nframes = 0, ndelim, ret;
1031 u16 aggr_limit = 0, al = 0, bpad = 0,
1032 al_delta, h_baw = tid->baw_size / 2;
1033 struct ieee80211_tx_info *tx_info;
1034 struct ath_frame_info *fi;
1035 struct sk_buff *skb;
1039 aggr_limit = ath_lookup_rate(sc, bf, tid);
1044 fi = get_frame_info(skb);
1046 /* do not exceed aggregation limit */
1047 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1049 if (aggr_limit < al + bpad + al_delta ||
1050 ath_lookup_legacy(bf) || nframes >= h_baw)
1053 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1054 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1055 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1059 /* add padding for previous frame to aggregation length */
1060 al += bpad + al_delta;
1063 * Get the delimiters needed to meet the MPDU
1064 * density for this node.
1066 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1068 bpad = PADBYTES(al_delta) + (ndelim << 2);
1073 /* link buffers of this frame to the aggregate */
1074 bf->bf_state.ndelim = ndelim;
1076 list_add_tail(&bf->list, bf_q);
1078 bf_prev->bf_next = bf;
1082 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1088 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1091 bf->bf_lastbf = bf_prev;
1093 if (bf == bf_prev) {
1094 al = get_frame_info(bf->bf_mpdu)->framelen;
1095 bf->bf_state.bf_type = BUF_AMPDU;
1097 TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1106 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1107 * width - 0 for 20 MHz, 1 for 40 MHz
1108 * half_gi - to use 4us v/s 3.6 us for symbol time
1110 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1111 int width, int half_gi, bool shortPreamble)
1113 u32 nbits, nsymbits, duration, nsymbols;
1116 /* find number of symbols: PLCP + data */
1117 streams = HT_RC_2_STREAMS(rix);
1118 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1119 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1120 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1123 duration = SYMBOL_TIME(nsymbols);
1125 duration = SYMBOL_TIME_HALFGI(nsymbols);
1127 /* addup duration for legacy/ht training and signal fields */
1128 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1133 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1135 int streams = HT_RC_2_STREAMS(mcs);
1139 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1140 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1141 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1142 bits -= OFDM_PLCP_BITS;
1150 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1152 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1155 /* 4ms is the default (and maximum) duration */
1156 if (!txop || txop > 4096)
1159 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1160 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1161 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1162 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1163 for (mcs = 0; mcs < 32; mcs++) {
1164 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1165 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1166 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1167 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1171 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1172 u8 rateidx, bool is_40, bool is_cck)
1175 struct sk_buff *skb;
1176 struct ath_frame_info *fi;
1177 struct ieee80211_tx_info *info;
1178 struct ath_hw *ah = sc->sc_ah;
1180 if (sc->tx99_state || !ah->tpc_enabled)
1181 return MAX_RATE_POWER;
1184 fi = get_frame_info(skb);
1185 info = IEEE80211_SKB_CB(skb);
1187 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1188 int txpower = fi->tx_power;
1192 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1193 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1195 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1197 struct modal_eep_header *pmodal;
1199 is_2ghz = info->band == NL80211_BAND_2GHZ;
1200 pmodal = &eep->modalHeader[is_2ghz];
1201 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1203 power_ht40delta = 2;
1205 txpower += power_ht40delta;
1208 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1210 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1211 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1214 power_offset = ah->eep_ops->get_eeprom(ah,
1215 EEP_PWR_TABLE_OFFSET);
1216 txpower -= 2 * power_offset;
1219 if (OLC_FOR_AR9280_20_LATER && is_cck)
1222 txpower = max(txpower, 0);
1223 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1225 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1226 * max_power is set to 0, frames are transmitted at max
1229 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1231 } else if (!bf->bf_state.bfs_paprd) {
1232 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1233 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1236 max_power = min_t(u8, ah->tx_power[rateidx],
1239 max_power = ah->paprd_training_power;
1245 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1246 struct ath_tx_info *info, int len, bool rts)
1248 struct ath_hw *ah = sc->sc_ah;
1249 struct ath_common *common = ath9k_hw_common(ah);
1250 struct sk_buff *skb;
1251 struct ieee80211_tx_info *tx_info;
1252 struct ieee80211_tx_rate *rates;
1253 const struct ieee80211_rate *rate;
1254 struct ieee80211_hdr *hdr;
1255 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1256 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1261 tx_info = IEEE80211_SKB_CB(skb);
1263 hdr = (struct ieee80211_hdr *)skb->data;
1265 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1266 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1267 info->rtscts_rate = fi->rtscts_rate;
1269 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1270 bool is_40, is_sgi, is_sp, is_cck;
1273 if (!rates[i].count || (rates[i].idx < 0))
1277 info->rates[i].Tries = rates[i].count;
1280 * Handle RTS threshold for unaggregated HT frames.
1282 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1283 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1284 unlikely(rts_thresh != (u32) -1)) {
1285 if (!rts_thresh || (len > rts_thresh))
1289 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1290 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1291 info->flags |= ATH9K_TXDESC_RTSENA;
1292 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1293 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1294 info->flags |= ATH9K_TXDESC_CTSENA;
1297 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1298 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1299 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1300 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1302 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1303 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1304 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1306 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1308 info->rates[i].Rate = rix | 0x80;
1309 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1310 ah->txchainmask, info->rates[i].Rate);
1311 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1312 is_40, is_sgi, is_sp);
1313 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1314 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1315 if (rix >= 8 && fi->dyn_smps) {
1316 info->rates[i].RateFlags |=
1317 ATH9K_RATESERIES_RTS_CTS;
1318 info->flags |= ATH9K_TXDESC_CTSENA;
1321 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1327 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1328 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1329 !(rate->flags & IEEE80211_RATE_ERP_G))
1330 phy = WLAN_RC_PHY_CCK;
1332 phy = WLAN_RC_PHY_OFDM;
1334 info->rates[i].Rate = rate->hw_value;
1335 if (rate->hw_value_short) {
1336 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1337 info->rates[i].Rate |= rate->hw_value_short;
1342 if (bf->bf_state.bfs_paprd)
1343 info->rates[i].ChSel = ah->txchainmask;
1345 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1346 ah->txchainmask, info->rates[i].Rate);
1348 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1349 phy, rate->bitrate * 100, len, rix, is_sp);
1351 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1352 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1356 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1357 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1358 info->flags &= ~ATH9K_TXDESC_RTSENA;
1360 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1361 if (info->flags & ATH9K_TXDESC_RTSENA)
1362 info->flags &= ~ATH9K_TXDESC_CTSENA;
1365 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1367 struct ieee80211_hdr *hdr;
1368 enum ath9k_pkt_type htype;
1371 hdr = (struct ieee80211_hdr *)skb->data;
1372 fc = hdr->frame_control;
1374 if (ieee80211_is_beacon(fc))
1375 htype = ATH9K_PKT_TYPE_BEACON;
1376 else if (ieee80211_is_probe_resp(fc))
1377 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1378 else if (ieee80211_is_atim(fc))
1379 htype = ATH9K_PKT_TYPE_ATIM;
1380 else if (ieee80211_is_pspoll(fc))
1381 htype = ATH9K_PKT_TYPE_PSPOLL;
1383 htype = ATH9K_PKT_TYPE_NORMAL;
1388 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1389 struct ath_txq *txq, int len)
1391 struct ath_hw *ah = sc->sc_ah;
1392 struct ath_buf *bf_first = NULL;
1393 struct ath_tx_info info;
1394 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1397 memset(&info, 0, sizeof(info));
1398 info.is_first = true;
1399 info.is_last = true;
1400 info.qcu = txq->axq_qnum;
1403 struct sk_buff *skb = bf->bf_mpdu;
1404 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1405 struct ath_frame_info *fi = get_frame_info(skb);
1406 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1408 info.type = get_hw_packet_type(skb);
1410 info.link = bf->bf_next->bf_daddr;
1412 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1417 if (!sc->tx99_state)
1418 info.flags = ATH9K_TXDESC_INTREQ;
1419 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1420 txq == sc->tx.uapsdq)
1421 info.flags |= ATH9K_TXDESC_CLRDMASK;
1423 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1424 info.flags |= ATH9K_TXDESC_NOACK;
1425 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1426 info.flags |= ATH9K_TXDESC_LDPC;
1428 if (bf->bf_state.bfs_paprd)
1429 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1430 ATH9K_TXDESC_PAPRD_S;
1433 * mac80211 doesn't handle RTS threshold for HT because
1434 * the decision has to be taken based on AMPDU length
1435 * and aggregation is done entirely inside ath9k.
1436 * Set the RTS/CTS flag for the first subframe based
1439 if (aggr && (bf == bf_first) &&
1440 unlikely(rts_thresh != (u32) -1)) {
1442 * "len" is the size of the entire AMPDU.
1444 if (!rts_thresh || (len > rts_thresh))
1451 ath_buf_set_rate(sc, bf, &info, len, rts);
1454 info.buf_addr[0] = bf->bf_buf_addr;
1455 info.buf_len[0] = skb->len;
1456 info.pkt_len = fi->framelen;
1457 info.keyix = fi->keyix;
1458 info.keytype = fi->keytype;
1462 info.aggr = AGGR_BUF_FIRST;
1463 else if (bf == bf_first->bf_lastbf)
1464 info.aggr = AGGR_BUF_LAST;
1466 info.aggr = AGGR_BUF_MIDDLE;
1468 info.ndelim = bf->bf_state.ndelim;
1469 info.aggr_len = len;
1472 if (bf == bf_first->bf_lastbf)
1475 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1481 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1482 struct ath_atx_tid *tid, struct list_head *bf_q,
1483 struct ath_buf *bf_first)
1485 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1486 int nframes = 0, ret;
1489 struct ieee80211_tx_info *tx_info;
1492 list_add_tail(&bf->list, bf_q);
1494 bf_prev->bf_next = bf;
1500 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1504 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1505 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1506 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1510 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1514 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1515 struct ath_atx_tid *tid)
1517 struct ath_buf *bf = NULL;
1518 struct ieee80211_tx_info *tx_info;
1519 struct list_head bf_q;
1520 int aggr_len = 0, ret;
1523 INIT_LIST_HEAD(&bf_q);
1525 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1529 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1530 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1531 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1532 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1533 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1537 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1539 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1541 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1543 if (list_empty(&bf_q))
1546 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1547 tid->clear_ps_filter = false;
1548 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1551 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1552 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1556 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1559 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1560 struct ath_atx_tid *txtid;
1561 struct ath_txq *txq;
1562 struct ath_node *an;
1565 ath_dbg(common, XMIT, "%s called\n", __func__);
1567 an = (struct ath_node *)sta->drv_priv;
1568 txtid = ATH_AN_2_TID(an, tid);
1571 ath_txq_lock(sc, txq);
1573 /* update ampdu factor/density, they may have changed. This may happen
1574 * in HT IBSS when a beacon with HT-info is received after the station
1575 * has already been added.
1577 if (sta->ht_cap.ht_supported) {
1578 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1579 sta->ht_cap.ampdu_factor)) - 1;
1580 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1581 an->mpdudensity = density;
1584 txtid->active = true;
1585 *ssn = txtid->seq_start = txtid->seq_next;
1586 txtid->bar_index = -1;
1588 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1589 txtid->baw_head = txtid->baw_tail = 0;
1591 ath_txq_unlock_complete(sc, txq);
1596 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1598 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1599 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1600 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1601 struct ath_txq *txq = txtid->txq;
1603 ath_dbg(common, XMIT, "%s called\n", __func__);
1605 ath_txq_lock(sc, txq);
1606 txtid->active = false;
1607 ath_tx_flush_tid(sc, txtid);
1608 ath_txq_unlock_complete(sc, txq);
1611 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1612 struct ath_node *an)
1614 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1615 struct ath_atx_tid *tid;
1618 ath_dbg(common, XMIT, "%s called\n", __func__);
1620 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1621 tid = ath_node_to_tid(an, tidno);
1623 if (!skb_queue_empty(&tid->retry_q))
1624 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1629 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1631 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1632 struct ath_atx_tid *tid;
1633 struct ath_txq *txq;
1636 ath_dbg(common, XMIT, "%s called\n", __func__);
1638 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1639 tid = ath_node_to_tid(an, tidno);
1642 ath_txq_lock(sc, txq);
1643 tid->clear_ps_filter = true;
1644 if (!skb_queue_empty(&tid->retry_q)) {
1645 ath_tx_queue_tid(sc, tid);
1646 ath_txq_schedule(sc, txq);
1648 ath_txq_unlock_complete(sc, txq);
1655 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1657 struct ieee80211_hdr *hdr;
1658 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1659 u16 mask_val = mask * val;
1661 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1662 if ((hdr->frame_control & mask) != mask_val) {
1663 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1664 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1665 sizeof(*hdr), DMA_TO_DEVICE);
1669 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1670 struct ieee80211_sta *sta,
1671 u16 tids, int nframes,
1672 enum ieee80211_frame_release_type reason,
1675 struct ath_softc *sc = hw->priv;
1676 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1677 struct ath_txq *txq = sc->tx.uapsdq;
1678 struct ieee80211_tx_info *info;
1679 struct list_head bf_q;
1680 struct ath_buf *bf_tail = NULL, *bf = NULL;
1684 INIT_LIST_HEAD(&bf_q);
1685 for (i = 0; tids && nframes; i++, tids >>= 1) {
1686 struct ath_atx_tid *tid;
1691 tid = ATH_AN_2_TID(an, i);
1693 ath_txq_lock(sc, tid->txq);
1694 while (nframes > 0) {
1695 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq,
1700 ath9k_set_moredata(sc, bf, true);
1701 list_add_tail(&bf->list, &bf_q);
1702 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1704 bf->bf_state.bf_type &= ~BUF_AGGR;
1706 bf_tail->bf_next = bf;
1711 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1713 if (an->sta && skb_queue_empty(&tid->retry_q))
1714 ieee80211_sta_set_buffered(an->sta, i, false);
1716 ath_txq_unlock_complete(sc, tid->txq);
1719 if (list_empty(&bf_q))
1723 ath9k_set_moredata(sc, bf_tail, false);
1725 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1726 info->flags |= IEEE80211_TX_STATUS_EOSP;
1728 bf = list_first_entry(&bf_q, struct ath_buf, list);
1729 ath_txq_lock(sc, txq);
1730 ath_tx_fill_desc(sc, bf, txq, 0);
1731 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1732 ath_txq_unlock(sc, txq);
1735 /********************/
1736 /* Queue Management */
1737 /********************/
1739 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1741 struct ath_hw *ah = sc->sc_ah;
1742 struct ath9k_tx_queue_info qi;
1743 static const int subtype_txq_to_hwq[] = {
1744 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1745 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1746 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1747 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1751 memset(&qi, 0, sizeof(qi));
1752 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1753 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1754 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1755 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1756 qi.tqi_physCompBuf = 0;
1759 * Enable interrupts only for EOL and DESC conditions.
1760 * We mark tx descriptors to receive a DESC interrupt
1761 * when a tx queue gets deep; otherwise waiting for the
1762 * EOL to reap descriptors. Note that this is done to
1763 * reduce interrupt load and this only defers reaping
1764 * descriptors, never transmitting frames. Aside from
1765 * reducing interrupts this also permits more concurrency.
1766 * The only potential downside is if the tx queue backs
1767 * up in which case the top half of the kernel may backup
1768 * due to a lack of tx descriptors.
1770 * The UAPSD queue is an exception, since we take a desc-
1771 * based intr on the EOSP frames.
1773 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1774 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1776 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1777 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1779 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1780 TXQ_FLAG_TXDESCINT_ENABLE;
1782 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1783 if (axq_qnum == -1) {
1785 * NB: don't print a message, this happens
1786 * normally on parts with too few tx queues
1790 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1791 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1793 txq->axq_qnum = axq_qnum;
1794 txq->mac80211_qnum = -1;
1795 txq->axq_link = NULL;
1796 __skb_queue_head_init(&txq->complete_q);
1797 INIT_LIST_HEAD(&txq->axq_q);
1798 spin_lock_init(&txq->axq_lock);
1800 txq->axq_ampdu_depth = 0;
1801 txq->axq_tx_inprogress = false;
1802 sc->tx.txqsetup |= 1<<axq_qnum;
1804 txq->txq_headidx = txq->txq_tailidx = 0;
1805 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1806 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1808 return &sc->tx.txq[axq_qnum];
1811 int ath_txq_update(struct ath_softc *sc, int qnum,
1812 struct ath9k_tx_queue_info *qinfo)
1814 struct ath_hw *ah = sc->sc_ah;
1816 struct ath9k_tx_queue_info qi;
1818 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1820 ath9k_hw_get_txq_props(ah, qnum, &qi);
1821 qi.tqi_aifs = qinfo->tqi_aifs;
1822 qi.tqi_cwmin = qinfo->tqi_cwmin;
1823 qi.tqi_cwmax = qinfo->tqi_cwmax;
1824 qi.tqi_burstTime = qinfo->tqi_burstTime;
1825 qi.tqi_readyTime = qinfo->tqi_readyTime;
1827 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1828 ath_err(ath9k_hw_common(sc->sc_ah),
1829 "Unable to update hardware queue %u!\n", qnum);
1832 ath9k_hw_resettxqueue(ah, qnum);
1838 int ath_cabq_update(struct ath_softc *sc)
1840 struct ath9k_tx_queue_info qi;
1841 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1842 int qnum = sc->beacon.cabq->axq_qnum;
1844 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1846 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1847 ATH_CABQ_READY_TIME) / 100;
1848 ath_txq_update(sc, qnum, &qi);
1853 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1854 struct list_head *list)
1856 struct ath_buf *bf, *lastbf;
1857 struct list_head bf_head;
1858 struct ath_tx_status ts;
1860 memset(&ts, 0, sizeof(ts));
1861 ts.ts_status = ATH9K_TX_FLUSH;
1862 INIT_LIST_HEAD(&bf_head);
1864 while (!list_empty(list)) {
1865 bf = list_first_entry(list, struct ath_buf, list);
1867 if (bf->bf_state.stale) {
1868 list_del(&bf->list);
1870 ath_tx_return_buffer(sc, bf);
1874 lastbf = bf->bf_lastbf;
1875 list_cut_position(&bf_head, list, &lastbf->list);
1876 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1881 * Drain a given TX queue (could be Beacon or Data)
1883 * This assumes output has been stopped and
1884 * we do not need to block ath_tx_tasklet.
1886 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1889 ath_txq_lock(sc, txq);
1891 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1892 int idx = txq->txq_tailidx;
1894 while (!list_empty(&txq->txq_fifo[idx])) {
1895 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1897 INCR(idx, ATH_TXFIFO_DEPTH);
1899 txq->txq_tailidx = idx;
1902 txq->axq_link = NULL;
1903 txq->axq_tx_inprogress = false;
1904 ath_drain_txq_list(sc, txq, &txq->axq_q);
1906 ath_txq_unlock_complete(sc, txq);
1910 bool ath_drain_all_txq(struct ath_softc *sc)
1912 struct ath_hw *ah = sc->sc_ah;
1913 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1914 struct ath_txq *txq;
1918 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1921 ath9k_hw_abort_tx_dma(ah);
1923 /* Check if any queue remains active */
1924 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1925 if (!ATH_TXQ_SETUP(sc, i))
1928 if (!sc->tx.txq[i].axq_depth)
1931 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1936 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1937 ath_dbg(common, RESET,
1938 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1941 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1942 if (!ATH_TXQ_SETUP(sc, i))
1945 txq = &sc->tx.txq[i];
1946 ath_draintxq(sc, txq);
1952 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1954 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1955 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1958 /* For each acq entry, for each tid, try to schedule packets
1959 * for transmit until ampdu_depth has reached min Q depth.
1961 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1963 struct ieee80211_hw *hw = sc->hw;
1964 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1965 struct ieee80211_txq *queue;
1966 struct ath_atx_tid *tid;
1969 if (txq->mac80211_qnum < 0)
1972 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1975 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum);
1976 spin_lock_bh(&sc->chan_lock);
1979 if (sc->cur_chan->stopped)
1982 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) {
1985 tid = (struct ath_atx_tid *)queue->drv_priv;
1987 ret = ath_tx_sched_aggr(sc, txq, tid);
1988 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret);
1990 force = !skb_queue_empty(&tid->retry_q);
1991 ieee80211_return_txq(hw, queue, force);
1996 spin_unlock_bh(&sc->chan_lock);
1997 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum);
2000 void ath_txq_schedule_all(struct ath_softc *sc)
2002 struct ath_txq *txq;
2005 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2006 txq = sc->tx.txq_map[i];
2008 spin_lock_bh(&txq->axq_lock);
2009 ath_txq_schedule(sc, txq);
2010 spin_unlock_bh(&txq->axq_lock);
2019 * Insert a chain of ath_buf (descriptors) on a txq and
2020 * assume the descriptors are already chained together by caller.
2022 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2023 struct list_head *head, bool internal)
2025 struct ath_hw *ah = sc->sc_ah;
2026 struct ath_common *common = ath9k_hw_common(ah);
2027 struct ath_buf *bf, *bf_last;
2028 bool puttxbuf = false;
2032 * Insert the frame on the outbound list and
2033 * pass it on to the hardware.
2036 if (list_empty(head))
2039 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2040 bf = list_first_entry(head, struct ath_buf, list);
2041 bf_last = list_entry(head->prev, struct ath_buf, list);
2043 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2044 txq->axq_qnum, txq->axq_depth);
2046 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2047 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2048 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2051 list_splice_tail_init(head, &txq->axq_q);
2053 if (txq->axq_link) {
2054 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2055 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2056 txq->axq_qnum, txq->axq_link,
2057 ito64(bf->bf_daddr), bf->bf_desc);
2061 txq->axq_link = bf_last->bf_desc;
2065 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2066 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2067 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2068 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2071 if (!edma || sc->tx99_state) {
2072 TX_STAT_INC(sc, txq->axq_qnum, txstart);
2073 ath9k_hw_txstart(ah, txq->axq_qnum);
2079 if (bf_is_ampdu_not_probing(bf))
2080 txq->axq_ampdu_depth++;
2082 bf_last = bf->bf_lastbf;
2083 bf = bf_last->bf_next;
2084 bf_last->bf_next = NULL;
2089 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2090 struct ath_atx_tid *tid, struct sk_buff *skb)
2092 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2093 struct ath_frame_info *fi = get_frame_info(skb);
2094 struct list_head bf_head;
2095 struct ath_buf *bf = fi->bf;
2097 INIT_LIST_HEAD(&bf_head);
2098 list_add_tail(&bf->list, &bf_head);
2099 bf->bf_state.bf_type = 0;
2100 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2101 bf->bf_state.bf_type = BUF_AMPDU;
2102 ath_tx_addto_baw(sc, tid, bf);
2107 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2108 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2109 TX_STAT_INC(sc, txq->axq_qnum, queued);
2112 static void setup_frame_info(struct ieee80211_hw *hw,
2113 struct ieee80211_sta *sta,
2114 struct sk_buff *skb,
2117 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2118 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2119 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2120 const struct ieee80211_rate *rate;
2121 struct ath_frame_info *fi = get_frame_info(skb);
2122 struct ath_node *an = NULL;
2123 enum ath9k_key_type keytype;
2124 bool short_preamble = false;
2128 * We check if Short Preamble is needed for the CTS rate by
2129 * checking the BSS's global flag.
2130 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2132 if (tx_info->control.vif &&
2133 tx_info->control.vif->bss_conf.use_short_preamble)
2134 short_preamble = true;
2136 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2137 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2140 an = (struct ath_node *) sta->drv_priv;
2142 if (tx_info->control.vif) {
2143 struct ieee80211_vif *vif = tx_info->control.vif;
2144 if (vif->bss_conf.txpower == INT_MIN)
2146 txpower = 2 * vif->bss_conf.txpower;
2148 struct ath_softc *sc;
2152 txpower = sc->cur_chan->cur_txpower;
2155 memset(fi, 0, sizeof(*fi));
2158 fi->keyix = hw_key->hw_key_idx;
2159 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2160 fi->keyix = an->ps_key;
2162 fi->keyix = ATH9K_TXKEYIX_INVALID;
2163 fi->dyn_smps = sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC;
2164 fi->keytype = keytype;
2165 fi->framelen = framelen;
2166 fi->tx_power = txpower;
2170 fi->rtscts_rate = rate->hw_value;
2172 fi->rtscts_rate |= rate->hw_value_short;
2175 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2177 struct ath_hw *ah = sc->sc_ah;
2178 struct ath9k_channel *curchan = ah->curchan;
2180 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2181 (chainmask == 0x7) && (rate < 0x90))
2183 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2191 * Assign a descriptor (and sequence number if necessary,
2192 * and map buffer for DMA. Frees skb on error
2194 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2195 struct ath_txq *txq,
2196 struct ath_atx_tid *tid,
2197 struct sk_buff *skb)
2199 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2200 struct ath_frame_info *fi = get_frame_info(skb);
2201 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2206 bf = ath_tx_get_buffer(sc);
2208 ath_dbg(common, XMIT, "TX buffers are full\n");
2212 ATH_TXBUF_RESET(bf);
2214 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2215 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2216 seqno = tid->seq_next;
2217 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2220 hdr->seq_ctrl |= cpu_to_le16(fragno);
2222 if (!ieee80211_has_morefrags(hdr->frame_control))
2223 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2225 bf->bf_state.seqno = seqno;
2230 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2231 skb->len, DMA_TO_DEVICE);
2232 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2234 bf->bf_buf_addr = 0;
2235 ath_err(ath9k_hw_common(sc->sc_ah),
2236 "dma_mapping_error() on TX\n");
2237 ath_tx_return_buffer(sc, bf);
2246 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2248 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2249 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2250 struct ieee80211_vif *vif = info->control.vif;
2251 struct ath_vif *avp;
2253 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2259 avp = (struct ath_vif *)vif->drv_priv;
2261 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2262 avp->seq_no += 0x10;
2264 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2265 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2268 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2269 struct ath_tx_control *txctl)
2271 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2272 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2273 struct ieee80211_sta *sta = txctl->sta;
2274 struct ieee80211_vif *vif = info->control.vif;
2275 struct ath_vif *avp;
2276 struct ath_softc *sc = hw->priv;
2277 int frmlen = skb->len + FCS_LEN;
2278 int padpos, padsize;
2280 /* NOTE: sta can be NULL according to net/mac80211.h */
2282 txctl->an = (struct ath_node *)sta->drv_priv;
2283 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2284 avp = (void *)vif->drv_priv;
2285 txctl->an = &avp->mcast_node;
2288 if (info->control.hw_key)
2289 frmlen += info->control.hw_key->icv_len;
2291 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2293 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2294 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2295 !ieee80211_is_data(hdr->frame_control))
2296 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2298 /* Add the padding after the header if this is not already done */
2299 padpos = ieee80211_hdrlen(hdr->frame_control);
2300 padsize = padpos & 3;
2301 if (padsize && skb->len > padpos) {
2302 if (skb_headroom(skb) < padsize)
2305 skb_push(skb, padsize);
2306 memmove(skb->data, skb->data + padsize, padpos);
2309 setup_frame_info(hw, sta, skb, frmlen);
2314 /* Upon failure caller should free skb */
2315 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2316 struct ath_tx_control *txctl)
2318 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2319 struct ieee80211_sta *sta = txctl->sta;
2320 struct ieee80211_vif *vif = info->control.vif;
2321 struct ath_frame_info *fi = get_frame_info(skb);
2322 struct ath_softc *sc = hw->priv;
2323 struct ath_txq *txq = txctl->txq;
2324 struct ath_atx_tid *tid = NULL;
2325 struct ath_node *an = NULL;
2330 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2332 ret = ath_tx_prepare(hw, skb, txctl);
2337 * At this point, the vif, hw_key and sta pointers in the tx control
2338 * info are no longer valid (overwritten by the ath_frame_info data.
2341 q = skb_get_queue_mapping(skb);
2344 txq = sc->tx.uapsdq;
2347 an = (struct ath_node *) sta->drv_priv;
2348 tid = ath_get_skb_tid(sc, an, skb);
2351 ath_txq_lock(sc, txq);
2352 if (txq == sc->tx.txq_map[q]) {
2354 ++txq->pending_frames;
2357 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2359 ath_txq_skb_done(sc, txq, skb);
2361 dev_kfree_skb_any(skb);
2363 ieee80211_free_txskb(sc->hw, skb);
2367 bf->bf_state.bfs_paprd = txctl->paprd;
2370 bf->bf_state.bfs_paprd_timestamp = jiffies;
2372 ath_set_rates(vif, sta, bf);
2373 ath_tx_send_normal(sc, txq, tid, skb);
2376 ath_txq_unlock(sc, txq);
2381 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2382 struct sk_buff *skb)
2384 struct ath_softc *sc = hw->priv;
2385 struct ath_tx_control txctl = {
2386 .txq = sc->beacon.cabq
2388 struct ath_tx_info info = {};
2389 struct ath_buf *bf_tail = NULL;
2396 sc->cur_chan->beacon.beacon_interval * 1000 *
2397 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2400 struct ath_frame_info *fi = get_frame_info(skb);
2402 if (ath_tx_prepare(hw, skb, &txctl))
2405 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2410 ath_set_rates(vif, NULL, bf);
2411 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2412 duration += info.rates[0].PktDuration;
2414 bf_tail->bf_next = bf;
2416 list_add_tail(&bf->list, &bf_q);
2420 if (duration > max_duration)
2423 skb = ieee80211_get_buffered_bc(hw, vif);
2427 ieee80211_free_txskb(hw, skb);
2429 if (list_empty(&bf_q))
2432 bf = list_last_entry(&bf_q, struct ath_buf, list);
2433 ath9k_set_moredata(sc, bf, false);
2435 bf = list_first_entry(&bf_q, struct ath_buf, list);
2436 ath_txq_lock(sc, txctl.txq);
2437 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2438 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2439 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2440 ath_txq_unlock(sc, txctl.txq);
2447 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2448 int tx_flags, struct ath_txq *txq,
2449 struct ieee80211_sta *sta)
2451 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2452 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2453 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2454 int padpos, padsize;
2455 unsigned long flags;
2457 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2459 if (sc->sc_ah->caldata)
2460 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2462 if (!(tx_flags & ATH_TX_ERROR)) {
2463 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2464 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2466 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2469 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2470 padpos = ieee80211_hdrlen(hdr->frame_control);
2471 padsize = padpos & 3;
2472 if (padsize && skb->len>padpos+padsize) {
2474 * Remove MAC header padding before giving the frame back to
2477 memmove(skb->data + padsize, skb->data, padpos);
2478 skb_pull(skb, padsize);
2482 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2483 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2484 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2486 "Going back to sleep after having received TX status (0x%lx)\n",
2487 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2489 PS_WAIT_FOR_PSPOLL_DATA |
2490 PS_WAIT_FOR_TX_ACK));
2492 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2494 ath_txq_skb_done(sc, txq, skb);
2495 tx_info->status.status_driver_data[0] = sta;
2496 __skb_queue_tail(&txq->complete_q, skb);
2499 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2500 struct ath_txq *txq, struct list_head *bf_q,
2501 struct ieee80211_sta *sta,
2502 struct ath_tx_status *ts, int txok)
2504 struct sk_buff *skb = bf->bf_mpdu;
2505 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2506 unsigned long flags;
2510 tx_flags |= ATH_TX_ERROR;
2512 if (ts->ts_status & ATH9K_TXERR_FILT)
2513 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2515 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2516 bf->bf_buf_addr = 0;
2518 goto skip_tx_complete;
2520 if (bf->bf_state.bfs_paprd) {
2521 if (time_after(jiffies,
2522 bf->bf_state.bfs_paprd_timestamp +
2523 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2524 dev_kfree_skb_any(skb);
2526 complete(&sc->paprd_complete);
2528 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2529 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2532 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2533 * accidentally reference it later.
2538 * Return the list of ath_buf of this mpdu to free queue
2540 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2541 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2542 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2545 static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info)
2547 void *ptr = &tx_info->status;
2549 memset(ptr + sizeof(tx_info->status.rates), 0,
2550 sizeof(tx_info->status) -
2551 sizeof(tx_info->status.rates) -
2552 sizeof(tx_info->status.status_driver_data));
2555 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2556 struct ath_tx_status *ts, int nframes, int nbad,
2559 struct sk_buff *skb = bf->bf_mpdu;
2560 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2561 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2562 struct ieee80211_hw *hw = sc->hw;
2563 struct ath_hw *ah = sc->sc_ah;
2566 ath_clear_tx_status(tx_info);
2569 tx_info->status.ack_signal = ts->ts_rssi;
2571 tx_rateindex = ts->ts_rateindex;
2572 WARN_ON(tx_rateindex >= hw->max_rates);
2574 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2575 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2577 BUG_ON(nbad > nframes);
2579 tx_info->status.ampdu_len = nframes;
2580 tx_info->status.ampdu_ack_len = nframes - nbad;
2582 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2584 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2585 tx_info->status.rates[i].count = 0;
2586 tx_info->status.rates[i].idx = -1;
2589 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2590 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2592 * If an underrun error is seen assume it as an excessive
2593 * retry only if max frame trigger level has been reached
2594 * (2 KB for single stream, and 4 KB for dual stream).
2595 * Adjust the long retry as if the frame was tried
2596 * hw->max_rate_tries times to affect how rate control updates
2597 * PER for the failed rate.
2598 * In case of congestion on the bus penalizing this type of
2599 * underruns should help hardware actually transmit new frames
2600 * successfully by eventually preferring slower rates.
2601 * This itself should also alleviate congestion on the bus.
2603 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2604 ATH9K_TX_DELIM_UNDERRUN)) &&
2605 ieee80211_is_data(hdr->frame_control) &&
2606 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2607 tx_info->status.rates[tx_rateindex].count =
2612 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2614 struct ath_hw *ah = sc->sc_ah;
2615 struct ath_common *common = ath9k_hw_common(ah);
2616 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2617 struct list_head bf_head;
2618 struct ath_desc *ds;
2619 struct ath_tx_status ts;
2622 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2623 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2626 ath_txq_lock(sc, txq);
2628 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2631 if (list_empty(&txq->axq_q)) {
2632 txq->axq_link = NULL;
2633 ath_txq_schedule(sc, txq);
2636 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2639 * There is a race condition that a BH gets scheduled
2640 * after sw writes TxE and before hw re-load the last
2641 * descriptor to get the newly chained one.
2642 * Software must keep the last DONE descriptor as a
2643 * holding descriptor - software does so by marking
2644 * it with the STALE flag.
2647 if (bf->bf_state.stale) {
2649 if (list_is_last(&bf_held->list, &txq->axq_q))
2652 bf = list_entry(bf_held->list.next, struct ath_buf,
2656 lastbf = bf->bf_lastbf;
2657 ds = lastbf->bf_desc;
2659 memset(&ts, 0, sizeof(ts));
2660 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2661 if (status == -EINPROGRESS)
2664 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2667 * Remove ath_buf's of the same transmit unit from txq,
2668 * however leave the last descriptor back as the holding
2669 * descriptor for hw.
2671 lastbf->bf_state.stale = true;
2672 INIT_LIST_HEAD(&bf_head);
2673 if (!list_is_singular(&lastbf->list))
2674 list_cut_position(&bf_head,
2675 &txq->axq_q, lastbf->list.prev);
2678 list_del(&bf_held->list);
2679 ath_tx_return_buffer(sc, bf_held);
2682 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2684 ath_txq_unlock_complete(sc, txq);
2687 void ath_tx_tasklet(struct ath_softc *sc)
2689 struct ath_hw *ah = sc->sc_ah;
2690 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2694 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2695 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2696 ath_tx_processq(sc, &sc->tx.txq[i]);
2701 void ath_tx_edma_tasklet(struct ath_softc *sc)
2703 struct ath_tx_status ts;
2704 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2705 struct ath_hw *ah = sc->sc_ah;
2706 struct ath_txq *txq;
2707 struct ath_buf *bf, *lastbf;
2708 struct list_head bf_head;
2709 struct list_head *fifo_list;
2714 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2717 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2718 if (status == -EINPROGRESS)
2720 if (status == -EIO) {
2721 ath_dbg(common, XMIT, "Error processing tx status\n");
2725 /* Process beacon completions separately */
2726 if (ts.qid == sc->beacon.beaconq) {
2727 sc->beacon.tx_processed = true;
2728 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2730 if (ath9k_is_chanctx_enabled()) {
2731 ath_chanctx_event(sc, NULL,
2732 ATH_CHANCTX_EVENT_BEACON_SENT);
2735 ath9k_csa_update(sc);
2739 txq = &sc->tx.txq[ts.qid];
2741 ath_txq_lock(sc, txq);
2743 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2745 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2746 if (list_empty(fifo_list)) {
2747 ath_txq_unlock(sc, txq);
2751 bf = list_first_entry(fifo_list, struct ath_buf, list);
2752 if (bf->bf_state.stale) {
2753 list_del(&bf->list);
2754 ath_tx_return_buffer(sc, bf);
2755 bf = list_first_entry(fifo_list, struct ath_buf, list);
2758 lastbf = bf->bf_lastbf;
2760 INIT_LIST_HEAD(&bf_head);
2761 if (list_is_last(&lastbf->list, fifo_list)) {
2762 list_splice_tail_init(fifo_list, &bf_head);
2763 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2765 if (!list_empty(&txq->axq_q)) {
2766 struct list_head bf_q;
2768 INIT_LIST_HEAD(&bf_q);
2769 txq->axq_link = NULL;
2770 list_splice_tail_init(&txq->axq_q, &bf_q);
2771 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2774 lastbf->bf_state.stale = true;
2776 list_cut_position(&bf_head, fifo_list,
2780 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2781 ath_txq_unlock_complete(sc, txq);
2790 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2792 struct ath_descdma *dd = &sc->txsdma;
2793 u8 txs_len = sc->sc_ah->caps.txs_len;
2795 dd->dd_desc_len = size * txs_len;
2796 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2797 &dd->dd_desc_paddr, GFP_KERNEL);
2804 static int ath_tx_edma_init(struct ath_softc *sc)
2808 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2810 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2811 sc->txsdma.dd_desc_paddr,
2812 ATH_TXSTATUS_RING_SIZE);
2817 int ath_tx_init(struct ath_softc *sc, int nbufs)
2819 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2822 spin_lock_init(&sc->tx.txbuflock);
2824 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2828 "Failed to allocate tx descriptors: %d\n", error);
2832 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2833 "beacon", ATH_BCBUF, 1, 1);
2836 "Failed to allocate beacon descriptors: %d\n", error);
2840 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2841 error = ath_tx_edma_init(sc);
2846 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2848 struct ath_atx_tid *tid;
2851 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2852 tid = ath_node_to_tid(an, tidno);
2855 tid->seq_start = tid->seq_next = 0;
2856 tid->baw_size = WME_MAX_BA;
2857 tid->baw_head = tid->baw_tail = 0;
2858 tid->active = false;
2859 tid->clear_ps_filter = true;
2860 __skb_queue_head_init(&tid->retry_q);
2861 INIT_LIST_HEAD(&tid->list);
2862 acno = TID_TO_WME_AC(tidno);
2863 tid->txq = sc->tx.txq_map[acno];
2866 break; /* just one multicast ath_atx_tid */
2870 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2872 struct ath_atx_tid *tid;
2873 struct ath_txq *txq;
2878 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2879 tid = ath_node_to_tid(an, tidno);
2882 ath_txq_lock(sc, txq);
2884 if (!list_empty(&tid->list))
2885 list_del_init(&tid->list);
2887 ath_tid_drain(sc, txq, tid);
2888 tid->active = false;
2890 ath_txq_unlock(sc, txq);
2893 break; /* just one multicast ath_atx_tid */
2899 #ifdef CONFIG_ATH9K_TX99
2901 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2902 struct ath_tx_control *txctl)
2904 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2905 struct ath_frame_info *fi = get_frame_info(skb);
2906 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2908 int padpos, padsize;
2910 padpos = ieee80211_hdrlen(hdr->frame_control);
2911 padsize = padpos & 3;
2913 if (padsize && skb->len > padpos) {
2914 if (skb_headroom(skb) < padsize) {
2915 ath_dbg(common, XMIT,
2916 "tx99 padding failed\n");
2920 skb_push(skb, padsize);
2921 memmove(skb->data, skb->data + padsize, padpos);
2924 fi->keyix = ATH9K_TXKEYIX_INVALID;
2925 fi->framelen = skb->len + FCS_LEN;
2926 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2928 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2930 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2934 ath_set_rates(sc->tx99_vif, NULL, bf);
2936 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2937 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2939 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2944 #endif /* CONFIG_ATH9K_TX99 */