2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include "ar9002_phy.h"
21 /* We can tune this as we go by monitoring really low values */
22 #define ATH9K_NF_TOO_LOW -60
23 #define AR9285_CLCAL_REDO_THRESH 1
25 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
26 * is incorrect and we should use the static NF value. Later we can try to
27 * find out why they are reporting these values */
29 static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
31 if (nf > ATH9K_NF_TOO_LOW) {
32 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
33 "noise floor value detected (%d) is "
34 "lower than what we think is a "
35 "reasonable value (%d)\n",
36 nf, ATH9K_NF_TOO_LOW);
42 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
45 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
48 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
49 sort[i] = nfCalBuffer[i];
51 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
52 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
53 if (sort[j] > sort[j - 1]) {
55 sort[j] = sort[j - 1];
60 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
65 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
70 for (i = 0; i < NUM_NF_READINGS; i++) {
71 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
73 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
76 if (h[i].invalidNFcount > 0) {
77 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
78 nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
79 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
81 h[i].invalidNFcount--;
82 h[i].privNF = nfarray[i];
86 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
92 static bool getNoiseFloorThresh(struct ath_hw *ah,
93 enum ieee80211_band band,
97 case IEEE80211_BAND_5GHZ:
98 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
100 case IEEE80211_BAND_2GHZ:
101 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
111 static void ath9k_hw_setup_calibration(struct ath_hw *ah,
112 struct ath9k_cal_list *currCal)
114 struct ath_common *common = ath9k_hw_common(ah);
116 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
117 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
118 currCal->calData->calCountMax);
120 switch (currCal->calData->calType) {
121 case IQ_MISMATCH_CAL:
122 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
123 ath_print(common, ATH_DBG_CALIBRATE,
124 "starting IQ Mismatch Calibration\n");
127 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
128 ath_print(common, ATH_DBG_CALIBRATE,
129 "starting ADC Gain Calibration\n");
132 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
133 ath_print(common, ATH_DBG_CALIBRATE,
134 "starting ADC DC Calibration\n");
136 case ADC_DC_INIT_CAL:
137 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
138 ath_print(common, ATH_DBG_CALIBRATE,
139 "starting Init ADC DC Calibration\n");
143 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
144 AR_PHY_TIMING_CTRL4_DO_CAL);
147 static void ath9k_hw_reset_calibration(struct ath_hw *ah,
148 struct ath9k_cal_list *currCal)
152 ath9k_hw_setup_calibration(ah, currCal);
154 currCal->calState = CAL_RUNNING;
156 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
157 ah->meas0.sign[i] = 0;
158 ah->meas1.sign[i] = 0;
159 ah->meas2.sign[i] = 0;
160 ah->meas3.sign[i] = 0;
166 static bool ath9k_hw_per_calibration(struct ath_hw *ah,
167 struct ath9k_channel *ichan,
169 struct ath9k_cal_list *currCal)
171 bool iscaldone = false;
173 if (currCal->calState == CAL_RUNNING) {
174 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
175 AR_PHY_TIMING_CTRL4_DO_CAL)) {
177 currCal->calData->calCollect(ah);
180 if (ah->cal_samples >= currCal->calData->calNumSamples) {
181 int i, numChains = 0;
182 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
183 if (rxchainmask & (1 << i))
187 currCal->calData->calPostProc(ah, numChains);
188 ichan->CalValid |= currCal->calData->calType;
189 currCal->calState = CAL_DONE;
192 ath9k_hw_setup_calibration(ah, currCal);
195 } else if (!(ichan->CalValid & currCal->calData->calType)) {
196 ath9k_hw_reset_calibration(ah, currCal);
202 /* Assumes you are talking about the currently configured channel */
203 static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
204 enum ath9k_cal_types calType)
206 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
208 switch (calType & ah->supp_cals) {
209 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
213 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
221 static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
225 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
226 ah->totalPowerMeasI[i] +=
227 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
228 ah->totalPowerMeasQ[i] +=
229 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
230 ah->totalIqCorrMeas[i] +=
231 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
232 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
233 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
234 ah->cal_samples, i, ah->totalPowerMeasI[i],
235 ah->totalPowerMeasQ[i],
236 ah->totalIqCorrMeas[i]);
240 static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
244 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
245 ah->totalAdcIOddPhase[i] +=
246 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
247 ah->totalAdcIEvenPhase[i] +=
248 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
249 ah->totalAdcQOddPhase[i] +=
250 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
251 ah->totalAdcQEvenPhase[i] +=
252 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
254 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
255 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
256 "oddq=0x%08x; evenq=0x%08x;\n",
258 ah->totalAdcIOddPhase[i],
259 ah->totalAdcIEvenPhase[i],
260 ah->totalAdcQOddPhase[i],
261 ah->totalAdcQEvenPhase[i]);
265 static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
269 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
270 ah->totalAdcDcOffsetIOddPhase[i] +=
271 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
272 ah->totalAdcDcOffsetIEvenPhase[i] +=
273 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
274 ah->totalAdcDcOffsetQOddPhase[i] +=
275 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
276 ah->totalAdcDcOffsetQEvenPhase[i] +=
277 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
279 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
280 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
281 "oddq=0x%08x; evenq=0x%08x;\n",
283 ah->totalAdcDcOffsetIOddPhase[i],
284 ah->totalAdcDcOffsetIEvenPhase[i],
285 ah->totalAdcDcOffsetQOddPhase[i],
286 ah->totalAdcDcOffsetQEvenPhase[i]);
290 static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
292 struct ath_common *common = ath9k_hw_common(ah);
293 u32 powerMeasQ, powerMeasI, iqCorrMeas;
294 u32 qCoffDenom, iCoffDenom;
295 int32_t qCoff, iCoff;
298 for (i = 0; i < numChains; i++) {
299 powerMeasI = ah->totalPowerMeasI[i];
300 powerMeasQ = ah->totalPowerMeasQ[i];
301 iqCorrMeas = ah->totalIqCorrMeas[i];
303 ath_print(common, ATH_DBG_CALIBRATE,
304 "Starting IQ Cal and Correction for Chain %d\n",
307 ath_print(common, ATH_DBG_CALIBRATE,
308 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
309 i, ah->totalIqCorrMeas[i]);
313 if (iqCorrMeas > 0x80000000) {
314 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
318 ath_print(common, ATH_DBG_CALIBRATE,
319 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
320 ath_print(common, ATH_DBG_CALIBRATE,
321 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
322 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
325 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
326 qCoffDenom = powerMeasQ / 64;
328 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
330 iCoff = iqCorrMeas / iCoffDenom;
331 qCoff = powerMeasI / qCoffDenom - 64;
332 ath_print(common, ATH_DBG_CALIBRATE,
333 "Chn %d iCoff = 0x%08x\n", i, iCoff);
334 ath_print(common, ATH_DBG_CALIBRATE,
335 "Chn %d qCoff = 0x%08x\n", i, qCoff);
337 iCoff = iCoff & 0x3f;
338 ath_print(common, ATH_DBG_CALIBRATE,
339 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
340 if (iqCorrNeg == 0x0)
341 iCoff = 0x40 - iCoff;
345 else if (qCoff <= -16)
348 ath_print(common, ATH_DBG_CALIBRATE,
349 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
352 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
353 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
355 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
356 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
358 ath_print(common, ATH_DBG_CALIBRATE,
359 "IQ Cal and Correction done for Chain %d\n",
364 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
365 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
368 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
370 struct ath_common *common = ath9k_hw_common(ah);
371 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
372 u32 qGainMismatch, iGainMismatch, val, i;
374 for (i = 0; i < numChains; i++) {
375 iOddMeasOffset = ah->totalAdcIOddPhase[i];
376 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
377 qOddMeasOffset = ah->totalAdcQOddPhase[i];
378 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
380 ath_print(common, ATH_DBG_CALIBRATE,
381 "Starting ADC Gain Cal for Chain %d\n", i);
383 ath_print(common, ATH_DBG_CALIBRATE,
384 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
386 ath_print(common, ATH_DBG_CALIBRATE,
387 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
389 ath_print(common, ATH_DBG_CALIBRATE,
390 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
392 ath_print(common, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
396 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
398 ((iEvenMeasOffset * 32) /
399 iOddMeasOffset) & 0x3f;
401 ((qOddMeasOffset * 32) /
402 qEvenMeasOffset) & 0x3f;
404 ath_print(common, ATH_DBG_CALIBRATE,
405 "Chn %d gain_mismatch_i = 0x%08x\n", i,
407 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d gain_mismatch_q = 0x%08x\n", i,
411 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
413 val |= (qGainMismatch) | (iGainMismatch << 6);
414 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
416 ath_print(common, ATH_DBG_CALIBRATE,
417 "ADC Gain Cal done for Chain %d\n", i);
421 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
422 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
423 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
426 static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
428 struct ath_common *common = ath9k_hw_common(ah);
429 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
430 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
431 const struct ath9k_percal_data *calData =
432 ah->cal_list_curr->calData;
434 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
436 for (i = 0; i < numChains; i++) {
437 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
438 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
439 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
440 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
442 ath_print(common, ATH_DBG_CALIBRATE,
443 "Starting ADC DC Offset Cal for Chain %d\n", i);
445 ath_print(common, ATH_DBG_CALIBRATE,
446 "Chn %d pwr_meas_odd_i = %d\n", i,
448 ath_print(common, ATH_DBG_CALIBRATE,
449 "Chn %d pwr_meas_even_i = %d\n", i,
451 ath_print(common, ATH_DBG_CALIBRATE,
452 "Chn %d pwr_meas_odd_q = %d\n", i,
454 ath_print(common, ATH_DBG_CALIBRATE,
455 "Chn %d pwr_meas_even_q = %d\n", i,
458 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
460 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
463 ath_print(common, ATH_DBG_CALIBRATE,
464 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
466 ath_print(common, ATH_DBG_CALIBRATE,
467 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
470 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
472 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
473 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
475 ath_print(common, ATH_DBG_CALIBRATE,
476 "ADC DC Offset Cal done for Chain %d\n", i);
479 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
480 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
481 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
484 /* This is done for the currently configured channel */
485 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
487 struct ath_common *common = ath9k_hw_common(ah);
488 struct ieee80211_conf *conf = &common->hw->conf;
489 struct ath9k_cal_list *currCal = ah->cal_list_curr;
494 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
500 if (currCal->calState != CAL_DONE) {
501 ath_print(common, ATH_DBG_CALIBRATE,
502 "Calibration state incorrect, %d\n",
507 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
510 ath_print(common, ATH_DBG_CALIBRATE,
511 "Resetting Cal %d state for channel %u\n",
512 currCal->calData->calType, conf->channel->center_freq);
514 ah->curchan->CalValid &= ~currCal->calData->calType;
515 currCal->calState = CAL_WAITING;
519 EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
521 void ath9k_hw_start_nfcal(struct ath_hw *ah)
523 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
524 AR_PHY_AGC_CONTROL_ENABLE_NF);
525 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
526 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
527 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
530 void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
532 struct ath9k_nfcal_hist *h;
535 const u32 ar5416_cca_regs[6] = {
543 u8 chainmask, rx_chain_status;
545 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
546 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
548 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
549 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
554 if (rx_chain_status & 0x4)
556 else if (rx_chain_status & 0x2)
564 for (i = 0; i < NUM_NF_READINGS; i++) {
565 if (chainmask & (1 << i)) {
566 val = REG_READ(ah, ar5416_cca_regs[i]);
568 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
569 REG_WRITE(ah, ar5416_cca_regs[i], val);
573 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
574 AR_PHY_AGC_CONTROL_ENABLE_NF);
575 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
576 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
577 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
579 for (j = 0; j < 5; j++) {
580 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
581 AR_PHY_AGC_CONTROL_NF) == 0)
586 for (i = 0; i < NUM_NF_READINGS; i++) {
587 if (chainmask & (1 << i)) {
588 val = REG_READ(ah, ar5416_cca_regs[i]);
590 val |= (((u32) (-50) << 1) & 0x1ff);
591 REG_WRITE(ah, ar5416_cca_regs[i], val);
596 int16_t ath9k_hw_getnf(struct ath_hw *ah,
597 struct ath9k_channel *chan)
599 struct ath_common *common = ath9k_hw_common(ah);
600 int16_t nf, nfThresh;
601 int16_t nfarray[NUM_NF_READINGS] = { 0 };
602 struct ath9k_nfcal_hist *h;
603 struct ieee80211_channel *c = chan->chan;
605 chan->channelFlags &= (~CHANNEL_CW_INT);
606 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
607 ath_print(common, ATH_DBG_CALIBRATE,
608 "NF did not complete in calibration window\n");
610 chan->rawNoiseFloor = nf;
611 return chan->rawNoiseFloor;
613 ath9k_hw_do_getnf(ah, nfarray);
615 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
617 ath_print(common, ATH_DBG_CALIBRATE,
618 "noise floor failed detected; "
619 "detected %d, threshold %d\n",
621 chan->channelFlags |= CHANNEL_CW_INT;
627 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
628 chan->rawNoiseFloor = h[0].privNF;
630 return chan->rawNoiseFloor;
633 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
638 if (AR_SREV_9280(ah))
639 noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;
640 else if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
641 noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;
642 else if (AR_SREV_9287(ah))
643 noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;
645 noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
647 for (i = 0; i < NUM_NF_READINGS; i++) {
648 ah->nfCalHist[i].currIndex = 0;
649 ah->nfCalHist[i].privNF = noise_floor;
650 ah->nfCalHist[i].invalidNFcount =
651 AR_PHY_CCA_FILTERWINDOW_LENGTH;
652 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
653 ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;
658 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
662 if (chan->rawNoiseFloor == 0)
665 nf = chan->rawNoiseFloor;
667 if (!ath9k_hw_nf_in_range(ah, nf))
668 nf = ATH_DEFAULT_NOISE_FLOOR;
672 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
674 static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
677 int32_t delta, currPDADC, slope;
679 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
680 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
682 if (ah->initPDADC == 0 || currPDADC == 0) {
684 * Zero value indicates that no frames have been transmitted yet,
685 * can't do temperature compensation until frames are transmitted.
689 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
691 if (slope == 0) { /* to avoid divide by zero case */
694 delta = ((currPDADC - ah->initPDADC)*4) / slope;
696 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
697 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
698 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
699 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
703 static void ath9k_olc_temp_compensation(struct ath_hw *ah)
706 int delta, currPDADC, regval;
708 if (OLC_FOR_AR9287_10_LATER) {
709 ath9k_olc_temp_compensation_9287(ah);
711 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
712 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
714 if (ah->initPDADC == 0 || currPDADC == 0) {
717 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
718 delta = (currPDADC - ah->initPDADC + 4) / 8;
720 delta = (currPDADC - ah->initPDADC + 5) / 10;
722 if (delta != ah->PDADCdelta) {
723 ah->PDADCdelta = delta;
724 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
725 regval = ah->originalGain[i] - delta;
730 AR_PHY_TX_GAIN_TBL1 + i * 4,
731 AR_PHY_TX_GAIN, regval);
738 static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
742 u32 regList [][2] = {
753 for (i = 0; i < ARRAY_SIZE(regList); i++)
754 regList[i][1] = REG_READ(ah, regList[i][0]);
756 regVal = REG_READ(ah, 0x7834);
758 REG_WRITE(ah, 0x7834, regVal);
759 regVal = REG_READ(ah, 0x9808);
760 regVal |= (0x1 << 27);
761 REG_WRITE(ah, 0x9808, regVal);
763 /* 786c,b23,1, pwddac=1 */
764 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
765 /* 7854, b5,1, pdrxtxbb=1 */
766 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
767 /* 7854, b7,1, pdv2i=1 */
768 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
769 /* 7854, b8,1, pddacinterface=1 */
770 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
771 /* 7824,b12,0, offcal=0 */
772 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
773 /* 7838, b1,0, pwddb=0 */
774 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
775 /* 7820,b11,0, enpacal=0 */
776 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
777 /* 7820,b25,1, pdpadrv1=0 */
778 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
779 /* 7820,b24,0, pdpadrv2=0 */
780 REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
781 /* 7820,b23,0, pdpaout=0 */
782 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
783 /* 783c,b14-16,7, padrvgn2tab_0=7 */
784 REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
786 * 7838,b29-31,0, padrvgn1tab_0=0
787 * does not matter since we turn it off
789 REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
791 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
794 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
795 * txon=1,paon=1,oscon=1,synthon_force=1
797 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
799 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
802 for (i = 6; i > 0; i--) {
803 regVal = REG_READ(ah, 0x7834);
804 regVal |= (1 << (20 + i));
805 REG_WRITE(ah, 0x7834, regVal);
807 //regVal = REG_READ(ah, 0x7834);
808 regVal &= (~(0x1 << (20 + i)));
809 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
811 REG_WRITE(ah, 0x7834, regVal);
814 regVal = (regVal >>20) & 0x7f;
816 /* Update PA cal info */
817 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
818 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
819 ah->pacal_info.max_skipcount =
820 2 * ah->pacal_info.max_skipcount;
821 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
823 ah->pacal_info.max_skipcount = 1;
824 ah->pacal_info.skipcount = 0;
825 ah->pacal_info.prev_offset = regVal;
828 regVal = REG_READ(ah, 0x7834);
830 REG_WRITE(ah, 0x7834, regVal);
831 regVal = REG_READ(ah, 0x9808);
832 regVal &= (~(0x1 << 27));
833 REG_WRITE(ah, 0x9808, regVal);
835 for (i = 0; i < ARRAY_SIZE(regList); i++)
836 REG_WRITE(ah, regList[i][0], regList[i][1]);
839 static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
841 struct ath_common *common = ath9k_hw_common(ah);
843 int i, offset, offs_6_1, offs_0;
844 u32 ccomp_org, reg_field;
855 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
857 /* PA CAL is not needed for high power solution */
858 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
859 AR5416_EEP_TXGAIN_HIGH_POWER)
862 if (AR_SREV_9285_11(ah)) {
863 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
867 for (i = 0; i < ARRAY_SIZE(regList); i++)
868 regList[i][1] = REG_READ(ah, regList[i][0]);
870 regVal = REG_READ(ah, 0x7834);
872 REG_WRITE(ah, 0x7834, regVal);
873 regVal = REG_READ(ah, 0x9808);
874 regVal |= (0x1 << 27);
875 REG_WRITE(ah, 0x9808, regVal);
877 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
878 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
879 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
880 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
881 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
882 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
883 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
884 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
885 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
886 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
887 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
888 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
889 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
890 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
892 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
894 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
895 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
897 for (i = 6; i > 0; i--) {
898 regVal = REG_READ(ah, 0x7834);
899 regVal |= (1 << (19 + i));
900 REG_WRITE(ah, 0x7834, regVal);
902 regVal = REG_READ(ah, 0x7834);
903 regVal &= (~(0x1 << (19 + i)));
904 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
905 regVal |= (reg_field << (19 + i));
906 REG_WRITE(ah, 0x7834, regVal);
909 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
911 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
912 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
913 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
914 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
916 offset = (offs_6_1<<1) | offs_0;
918 offs_6_1 = offset>>1;
921 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
922 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
923 ah->pacal_info.max_skipcount =
924 2 * ah->pacal_info.max_skipcount;
925 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
927 ah->pacal_info.max_skipcount = 1;
928 ah->pacal_info.skipcount = 0;
929 ah->pacal_info.prev_offset = offset;
932 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
933 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
935 regVal = REG_READ(ah, 0x7834);
937 REG_WRITE(ah, 0x7834, regVal);
938 regVal = REG_READ(ah, 0x9808);
939 regVal &= (~(0x1 << 27));
940 REG_WRITE(ah, 0x9808, regVal);
942 for (i = 0; i < ARRAY_SIZE(regList); i++)
943 REG_WRITE(ah, regList[i][0], regList[i][1]);
945 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
947 if (AR_SREV_9285_11(ah))
948 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
952 bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
953 u8 rxchainmask, bool longcal)
955 bool iscaldone = true;
956 struct ath9k_cal_list *currCal = ah->cal_list_curr;
959 (currCal->calState == CAL_RUNNING ||
960 currCal->calState == CAL_WAITING)) {
961 iscaldone = ath9k_hw_per_calibration(ah, chan,
962 rxchainmask, currCal);
964 ah->cal_list_curr = currCal = currCal->calNext;
966 if (currCal->calState == CAL_WAITING) {
968 ath9k_hw_reset_calibration(ah, currCal);
973 /* Do NF cal only at longer intervals */
975 /* Do periodic PAOffset Cal */
976 if (AR_SREV_9271(ah)) {
977 if (!ah->pacal_info.skipcount)
978 ath9k_hw_9271_pa_cal(ah, false);
980 ah->pacal_info.skipcount--;
981 } else if (AR_SREV_9285_11_OR_LATER(ah)) {
982 if (!ah->pacal_info.skipcount)
983 ath9k_hw_9285_pa_cal(ah, false);
985 ah->pacal_info.skipcount--;
988 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
989 ath9k_olc_temp_compensation(ah);
991 /* Get the value from the previous NF cal and update history buffer */
992 ath9k_hw_getnf(ah, chan);
995 * Load the NF from history buffer of the current channel.
996 * NF is slow time-variant, so it is OK to use a historical value.
998 ath9k_hw_loadnf(ah, ah->curchan);
1000 ath9k_hw_start_nfcal(ah);
1005 EXPORT_SYMBOL(ath9k_hw_calibrate);
1007 /* Carrier leakage Calibration fix */
1008 static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1010 struct ath_common *common = ath9k_hw_common(ah);
1012 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1013 if (IS_CHAN_HT20(chan)) {
1014 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1015 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1016 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1017 AR_PHY_AGC_CONTROL_FLTR_CAL);
1018 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1019 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1020 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1021 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1022 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1023 "calibration failed to complete in "
1027 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1028 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1029 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1031 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1032 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1033 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1034 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1035 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1036 0, AH_WAIT_TIMEOUT)) {
1037 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1038 "failed to complete in 1ms; noisy ??\n");
1042 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1043 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1044 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1049 static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1052 u_int32_t txgain_max;
1053 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
1054 u_int32_t reg_clc_I0, reg_clc_Q0;
1055 u_int32_t i0_num = 0;
1056 u_int32_t q0_num = 0;
1057 u_int32_t total_num = 0;
1058 u_int32_t reg_rf2g5_org;
1061 if (!(ar9285_cl_cal(ah, chan)))
1064 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
1065 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
1067 for (i = 0; i < (txgain_max+1); i++) {
1068 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
1069 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
1070 if (!(gain_mask & (1 << clc_gain))) {
1071 gain_mask |= (1 << clc_gain);
1076 for (i = 0; i < clc_num; i++) {
1077 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1078 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
1079 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1080 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
1081 if (reg_clc_I0 == 0)
1084 if (reg_clc_Q0 == 0)
1087 total_num = i0_num + q0_num;
1088 if (total_num > AR9285_CLCAL_REDO_THRESH) {
1089 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
1090 if (AR_SREV_9285E_20(ah)) {
1091 REG_WRITE(ah, AR9285_RF2G5,
1092 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1093 AR9285_RF2G5_IC50TX_XE_SET);
1095 REG_WRITE(ah, AR9285_RF2G5,
1096 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1097 AR9285_RF2G5_IC50TX_SET);
1099 retv = ar9285_cl_cal(ah, chan);
1100 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
1105 bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1107 struct ath_common *common = ath9k_hw_common(ah);
1109 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
1110 if (!ar9285_clc(ah, chan))
1113 if (AR_SREV_9280_10_OR_LATER(ah)) {
1114 if (!AR_SREV_9287_10_OR_LATER(ah))
1115 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
1116 AR_PHY_ADC_CTL_OFF_PWDADC);
1117 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1118 AR_PHY_AGC_CONTROL_FLTR_CAL);
1121 /* Calibrate the AGC */
1122 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1123 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1124 AR_PHY_AGC_CONTROL_CAL);
1126 /* Poll for offset calibration complete */
1127 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1128 0, AH_WAIT_TIMEOUT)) {
1129 ath_print(common, ATH_DBG_CALIBRATE,
1130 "offset calibration failed to "
1131 "complete in 1ms; noisy environment?\n");
1135 if (AR_SREV_9280_10_OR_LATER(ah)) {
1136 if (!AR_SREV_9287_10_OR_LATER(ah))
1137 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
1138 AR_PHY_ADC_CTL_OFF_PWDADC);
1139 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1140 AR_PHY_AGC_CONTROL_FLTR_CAL);
1144 /* Do PA Calibration */
1145 if (AR_SREV_9271(ah))
1146 ath9k_hw_9271_pa_cal(ah, true);
1147 else if (AR_SREV_9285_11_OR_LATER(ah))
1148 ath9k_hw_9285_pa_cal(ah, true);
1150 /* Do NF Calibration after DC offset and other calibrations */
1151 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1152 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
1154 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1156 /* Enable IQ, ADC Gain and ADC DC offset CALs */
1157 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
1158 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1159 INIT_CAL(&ah->adcgain_caldata);
1160 INSERT_CAL(ah, &ah->adcgain_caldata);
1161 ath_print(common, ATH_DBG_CALIBRATE,
1162 "enabling ADC Gain Calibration.\n");
1164 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1165 INIT_CAL(&ah->adcdc_caldata);
1166 INSERT_CAL(ah, &ah->adcdc_caldata);
1167 ath_print(common, ATH_DBG_CALIBRATE,
1168 "enabling ADC DC Calibration.\n");
1170 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1171 INIT_CAL(&ah->iq_caldata);
1172 INSERT_CAL(ah, &ah->iq_caldata);
1173 ath_print(common, ATH_DBG_CALIBRATE,
1174 "enabling IQ Calibration.\n");
1177 ah->cal_list_curr = ah->cal_list;
1179 if (ah->cal_list_curr)
1180 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1188 const struct ath9k_percal_data iq_cal_multi_sample = {
1192 ath9k_hw_iqcal_collect,
1193 ath9k_hw_iqcalibrate
1195 const struct ath9k_percal_data iq_cal_single_sample = {
1199 ath9k_hw_iqcal_collect,
1200 ath9k_hw_iqcalibrate
1202 const struct ath9k_percal_data adc_gain_cal_multi_sample = {
1206 ath9k_hw_adc_gaincal_collect,
1207 ath9k_hw_adc_gaincal_calibrate
1209 const struct ath9k_percal_data adc_gain_cal_single_sample = {
1213 ath9k_hw_adc_gaincal_collect,
1214 ath9k_hw_adc_gaincal_calibrate
1216 const struct ath9k_percal_data adc_dc_cal_multi_sample = {
1220 ath9k_hw_adc_dccal_collect,
1221 ath9k_hw_adc_dccal_calibrate
1223 const struct ath9k_percal_data adc_dc_cal_single_sample = {
1227 ath9k_hw_adc_dccal_collect,
1228 ath9k_hw_adc_dccal_calibrate
1230 const struct ath9k_percal_data adc_init_dc_cal = {
1234 ath9k_hw_adc_dccal_collect,
1235 ath9k_hw_adc_dccal_calibrate