2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/hardirq.h>
51 #include <linux/netdevice.h>
52 #include <linux/cache.h>
53 #include <linux/ethtool.h>
54 #include <linux/uaccess.h>
55 #include <linux/slab.h>
56 #include <linux/etherdevice.h>
57 #include <linux/nl80211.h>
59 #include <net/ieee80211_radiotap.h>
61 #include <asm/unaligned.h>
70 #define CREATE_TRACE_POINTS
73 bool ath5k_modparam_nohwcrypt;
74 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
75 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77 static bool modparam_fastchanswitch;
78 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
79 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
81 static bool ath5k_modparam_no_hw_rfkill_switch;
82 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
84 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
88 MODULE_AUTHOR("Jiri Slaby");
89 MODULE_AUTHOR("Nick Kossifidis");
90 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
91 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
92 MODULE_LICENSE("Dual BSD/GPL");
94 static int ath5k_init(struct ieee80211_hw *hw);
95 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
99 static const struct ath5k_srev_name srev_names[] = {
100 #ifdef CONFIG_ATHEROS_AR231X
101 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
103 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
104 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
106 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
109 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
110 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
111 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
112 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
113 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
114 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
115 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
116 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
117 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
118 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
119 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
120 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
121 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
122 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
123 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
124 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
125 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
126 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
128 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
129 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
130 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
131 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
135 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
136 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
137 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
138 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
139 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
140 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
141 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
142 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
143 #ifdef CONFIG_ATHEROS_AR231X
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150 static const struct ieee80211_rate ath5k_rates[] = {
152 .hw_value = ATH5K_RATE_CODE_1M, },
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 .hw_value = ATH5K_RATE_CODE_6M,
169 .hw_value = ATH5K_RATE_CODE_9M,
172 .hw_value = ATH5K_RATE_CODE_12M,
175 .hw_value = ATH5K_RATE_CODE_18M,
178 .hw_value = ATH5K_RATE_CODE_24M,
181 .hw_value = ATH5K_RATE_CODE_36M,
184 .hw_value = ATH5K_RATE_CODE_48M,
187 .hw_value = ATH5K_RATE_CODE_54M,
191 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
193 u64 tsf = ath5k_hw_get_tsf64(ah);
195 if ((tsf & 0x7fff) < rstamp)
198 return (tsf & ~0x7fff) | rstamp;
202 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
204 const char *name = "xxxxx";
207 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
208 if (srev_names[i].sr_type != type)
211 if ((val & 0xf0) == srev_names[i].sr_val)
212 name = srev_names[i].sr_name;
214 if ((val & 0xff) == srev_names[i].sr_val) {
215 name = srev_names[i].sr_name;
222 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 return ath5k_hw_reg_read(ah, reg_offset);
228 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
230 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
231 ath5k_hw_reg_write(ah, val, reg_offset);
234 static const struct ath_ops ath5k_common_ops = {
235 .read = ath5k_ioread32,
236 .write = ath5k_iowrite32,
239 /***********************\
240 * Driver Initialization *
241 \***********************/
243 static void ath5k_reg_notifier(struct wiphy *wiphy,
244 struct regulatory_request *request)
246 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
247 struct ath5k_hw *ah = hw->priv;
248 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
250 ath_reg_notifier_apply(wiphy, request, regulatory);
253 /********************\
254 * Channel/mode setup *
255 \********************/
258 * Returns true for the channel numbers used.
260 #ifdef CONFIG_ATH5K_TEST_CHANNELS
261 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
267 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
269 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
272 return /* UNII 1,2 */
273 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
275 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
277 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
278 /* 802.11j 5.030-5.080 GHz (20MHz) */
279 (chan == 8 || chan == 12 || chan == 16) ||
280 /* 802.11j 4.9GHz (20MHz) */
281 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
286 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
287 unsigned int mode, unsigned int max)
289 unsigned int count, size, freq, ch;
290 enum ieee80211_band band;
294 /* 1..220, but 2GHz frequencies are filtered by check_channel */
296 band = IEEE80211_BAND_5GHZ;
301 band = IEEE80211_BAND_2GHZ;
304 ATH5K_WARN(ah, "bad mode, not copying channels\n");
309 for (ch = 1; ch <= size && count < max; ch++) {
310 freq = ieee80211_channel_to_frequency(ch, band);
312 if (freq == 0) /* mapping failed - not a standard channel */
315 /* Write channel info, needed for ath5k_channel_ok() */
316 channels[count].center_freq = freq;
317 channels[count].band = band;
318 channels[count].hw_value = mode;
320 /* Check if channel is supported by the chipset */
321 if (!ath5k_channel_ok(ah, &channels[count]))
324 if (!ath5k_is_standard_channel(ch, band))
334 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
338 for (i = 0; i < AR5K_MAX_RATES; i++)
339 ah->rate_idx[b->band][i] = -1;
341 for (i = 0; i < b->n_bitrates; i++) {
342 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
343 if (b->bitrates[i].hw_value_short)
344 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
349 ath5k_setup_bands(struct ieee80211_hw *hw)
351 struct ath5k_hw *ah = hw->priv;
352 struct ieee80211_supported_band *sband;
353 int max_c, count_c = 0;
356 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
357 max_c = ARRAY_SIZE(ah->channels);
360 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
361 sband->band = IEEE80211_BAND_2GHZ;
362 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
364 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
366 memcpy(sband->bitrates, &ath5k_rates[0],
367 sizeof(struct ieee80211_rate) * 12);
368 sband->n_bitrates = 12;
370 sband->channels = ah->channels;
371 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
372 AR5K_MODE_11G, max_c);
374 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
375 count_c = sband->n_channels;
377 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
379 memcpy(sband->bitrates, &ath5k_rates[0],
380 sizeof(struct ieee80211_rate) * 4);
381 sband->n_bitrates = 4;
383 /* 5211 only supports B rates and uses 4bit rate codes
384 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
387 if (ah->ah_version == AR5K_AR5211) {
388 for (i = 0; i < 4; i++) {
389 sband->bitrates[i].hw_value =
390 sband->bitrates[i].hw_value & 0xF;
391 sband->bitrates[i].hw_value_short =
392 sband->bitrates[i].hw_value_short & 0xF;
396 sband->channels = ah->channels;
397 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
398 AR5K_MODE_11B, max_c);
400 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
401 count_c = sband->n_channels;
404 ath5k_setup_rate_idx(ah, sband);
406 /* 5GHz band, A mode */
407 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
408 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
409 sband->band = IEEE80211_BAND_5GHZ;
410 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
412 memcpy(sband->bitrates, &ath5k_rates[4],
413 sizeof(struct ieee80211_rate) * 8);
414 sband->n_bitrates = 8;
416 sband->channels = &ah->channels[count_c];
417 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
418 AR5K_MODE_11A, max_c);
420 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
422 ath5k_setup_rate_idx(ah, sband);
424 ath5k_debug_dump_bands(ah);
430 * Set/change channels. We always reset the chip.
431 * To accomplish this we must first cleanup any pending DMA,
432 * then restart stuff after a la ath5k_init.
434 * Called with ah->lock.
437 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
439 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
440 "channel set, resetting (%u -> %u MHz)\n",
441 ah->curchan->center_freq, chan->center_freq);
444 * To switch channels clear any pending DMA operations;
445 * wait long enough for the RX fifo to drain, reset the
446 * hardware at the new frequency, and then re-enable
447 * the relevant bits of the h/w.
449 return ath5k_reset(ah, chan, true);
452 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
454 struct ath5k_vif_iter_data *iter_data = data;
456 struct ath5k_vif *avf = (void *)vif->drv_priv;
458 if (iter_data->hw_macaddr)
459 for (i = 0; i < ETH_ALEN; i++)
460 iter_data->mask[i] &=
461 ~(iter_data->hw_macaddr[i] ^ mac[i]);
463 if (!iter_data->found_active) {
464 iter_data->found_active = true;
465 memcpy(iter_data->active_mac, mac, ETH_ALEN);
468 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
469 if (ether_addr_equal(iter_data->hw_macaddr, mac))
470 iter_data->need_set_hw_addr = false;
472 if (!iter_data->any_assoc) {
474 iter_data->any_assoc = true;
477 /* Calculate combined mode - when APs are active, operate in AP mode.
478 * Otherwise use the mode of the new interface. This can currently
479 * only deal with combinations of APs and STAs. Only one ad-hoc
480 * interfaces is allowed.
482 if (avf->opmode == NL80211_IFTYPE_AP)
483 iter_data->opmode = NL80211_IFTYPE_AP;
485 if (avf->opmode == NL80211_IFTYPE_STATION)
487 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
488 iter_data->opmode = avf->opmode;
493 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
494 struct ieee80211_vif *vif)
496 struct ath_common *common = ath5k_hw_common(ah);
497 struct ath5k_vif_iter_data iter_data;
501 * Use the hardware MAC address as reference, the hardware uses it
502 * together with the BSSID mask when matching addresses.
504 iter_data.hw_macaddr = common->macaddr;
505 memset(&iter_data.mask, 0xff, ETH_ALEN);
506 iter_data.found_active = false;
507 iter_data.need_set_hw_addr = true;
508 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
509 iter_data.n_stas = 0;
512 ath5k_vif_iter(&iter_data, vif->addr, vif);
514 /* Get list of all active MAC addresses */
515 ieee80211_iterate_active_interfaces_atomic(
516 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
517 ath5k_vif_iter, &iter_data);
518 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
520 ah->opmode = iter_data.opmode;
521 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
522 /* Nothing active, default to station mode */
523 ah->opmode = NL80211_IFTYPE_STATION;
525 ath5k_hw_set_opmode(ah, ah->opmode);
526 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
527 ah->opmode, ath_opmode_to_string(ah->opmode));
529 if (iter_data.need_set_hw_addr && iter_data.found_active)
530 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
532 if (ath5k_hw_hasbssidmask(ah))
533 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
535 /* Set up RX Filter */
536 if (iter_data.n_stas > 1) {
537 /* If you have multiple STA interfaces connected to
538 * different APs, ARPs are not received (most of the time?)
539 * Enabling PROMISC appears to fix that problem.
541 ah->filter_flags |= AR5K_RX_FILTER_PROM;
544 rfilt = ah->filter_flags;
545 ath5k_hw_set_rx_filter(ah, rfilt);
546 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
550 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
554 /* return base rate on errors */
555 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
556 "hw_rix out of bounds: %x\n", hw_rix))
559 rix = ah->rate_idx[ah->curchan->band][hw_rix];
560 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
571 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
573 struct ath_common *common = ath5k_hw_common(ah);
577 * Allocate buffer with headroom_needed space for the
578 * fake physical layer header at the start.
580 skb = ath_rxbuf_alloc(common,
585 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
590 *skb_addr = dma_map_single(ah->dev,
591 skb->data, common->rx_bufsize,
594 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
595 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
603 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
605 struct sk_buff *skb = bf->skb;
606 struct ath5k_desc *ds;
610 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
617 * Setup descriptors. For receive we always terminate
618 * the descriptor list with a self-linked entry so we'll
619 * not get overrun under high load (as can happen with a
620 * 5212 when ANI processing enables PHY error frames).
622 * To ensure the last descriptor is self-linked we create
623 * each descriptor as self-linked and add it to the end. As
624 * each additional descriptor is added the previous self-linked
625 * entry is "fixed" naturally. This should be safe even
626 * if DMA is happening. When processing RX interrupts we
627 * never remove/process the last, self-linked, entry on the
628 * descriptor list. This ensures the hardware always has
629 * someplace to write a new frame.
632 ds->ds_link = bf->daddr; /* link to self */
633 ds->ds_data = bf->skbaddr;
634 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
636 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
640 if (ah->rxlink != NULL)
641 *ah->rxlink = bf->daddr;
642 ah->rxlink = &ds->ds_link;
646 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
648 struct ieee80211_hdr *hdr;
649 enum ath5k_pkt_type htype;
652 hdr = (struct ieee80211_hdr *)skb->data;
653 fc = hdr->frame_control;
655 if (ieee80211_is_beacon(fc))
656 htype = AR5K_PKT_TYPE_BEACON;
657 else if (ieee80211_is_probe_resp(fc))
658 htype = AR5K_PKT_TYPE_PROBE_RESP;
659 else if (ieee80211_is_atim(fc))
660 htype = AR5K_PKT_TYPE_ATIM;
661 else if (ieee80211_is_pspoll(fc))
662 htype = AR5K_PKT_TYPE_PSPOLL;
664 htype = AR5K_PKT_TYPE_NORMAL;
670 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
671 struct ath5k_txq *txq, int padsize)
673 struct ath5k_desc *ds = bf->desc;
674 struct sk_buff *skb = bf->skb;
675 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
676 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
677 struct ieee80211_rate *rate;
678 unsigned int mrr_rate[3], mrr_tries[3];
685 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
688 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
691 rate = ieee80211_get_tx_rate(ah->hw, info);
697 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
698 flags |= AR5K_TXDESC_NOACK;
700 rc_flags = info->control.rates[0].flags;
701 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
702 rate->hw_value_short : rate->hw_value;
706 /* FIXME: If we are in g mode and rate is a CCK rate
707 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
708 * from tx power (value is in dB units already) */
709 if (info->control.hw_key) {
710 keyidx = info->control.hw_key->hw_key_idx;
711 pktlen += info->control.hw_key->icv_len;
713 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
714 flags |= AR5K_TXDESC_RTSENA;
715 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
716 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
717 info->control.vif, pktlen, info));
719 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
720 flags |= AR5K_TXDESC_CTSENA;
721 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
722 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
723 info->control.vif, pktlen, info));
725 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
726 ieee80211_get_hdrlen_from_skb(skb), padsize,
727 get_hw_packet_type(skb),
728 (ah->ah_txpower.txp_requested * 2),
730 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
735 /* Set up MRR descriptor */
736 if (ah->ah_capabilities.cap_has_mrr_support) {
737 memset(mrr_rate, 0, sizeof(mrr_rate));
738 memset(mrr_tries, 0, sizeof(mrr_tries));
739 for (i = 0; i < 3; i++) {
740 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
744 mrr_rate[i] = rate->hw_value;
745 mrr_tries[i] = info->control.rates[i + 1].count;
748 ath5k_hw_setup_mrr_tx_desc(ah, ds,
749 mrr_rate[0], mrr_tries[0],
750 mrr_rate[1], mrr_tries[1],
751 mrr_rate[2], mrr_tries[2]);
755 ds->ds_data = bf->skbaddr;
757 spin_lock_bh(&txq->lock);
758 list_add_tail(&bf->list, &txq->q);
760 if (txq->link == NULL) /* is this first packet? */
761 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
762 else /* no, so only link it */
763 *txq->link = bf->daddr;
765 txq->link = &ds->ds_link;
766 ath5k_hw_start_tx_dma(ah, txq->qnum);
768 spin_unlock_bh(&txq->lock);
772 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
776 /*******************\
777 * Descriptors setup *
778 \*******************/
781 ath5k_desc_alloc(struct ath5k_hw *ah)
783 struct ath5k_desc *ds;
784 struct ath5k_buf *bf;
789 /* allocate descriptors */
790 ah->desc_len = sizeof(struct ath5k_desc) *
791 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
793 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
794 &ah->desc_daddr, GFP_KERNEL);
795 if (ah->desc == NULL) {
796 ATH5K_ERR(ah, "can't allocate descriptors\n");
802 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
803 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
805 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
806 sizeof(struct ath5k_buf), GFP_KERNEL);
808 ATH5K_ERR(ah, "can't allocate bufptr\n");
814 INIT_LIST_HEAD(&ah->rxbuf);
815 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
818 list_add_tail(&bf->list, &ah->rxbuf);
821 INIT_LIST_HEAD(&ah->txbuf);
822 ah->txbuf_len = ATH_TXBUF;
823 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
826 list_add_tail(&bf->list, &ah->txbuf);
830 INIT_LIST_HEAD(&ah->bcbuf);
831 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
834 list_add_tail(&bf->list, &ah->bcbuf);
839 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
846 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
851 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
853 ieee80211_free_txskb(ah->hw, bf->skb);
856 bf->desc->ds_data = 0;
860 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
862 struct ath_common *common = ath5k_hw_common(ah);
867 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
869 dev_kfree_skb_any(bf->skb);
872 bf->desc->ds_data = 0;
876 ath5k_desc_free(struct ath5k_hw *ah)
878 struct ath5k_buf *bf;
880 list_for_each_entry(bf, &ah->txbuf, list)
881 ath5k_txbuf_free_skb(ah, bf);
882 list_for_each_entry(bf, &ah->rxbuf, list)
883 ath5k_rxbuf_free_skb(ah, bf);
884 list_for_each_entry(bf, &ah->bcbuf, list)
885 ath5k_txbuf_free_skb(ah, bf);
887 /* Free memory associated with all descriptors */
888 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
901 static struct ath5k_txq *
902 ath5k_txq_setup(struct ath5k_hw *ah,
903 int qtype, int subtype)
905 struct ath5k_txq *txq;
906 struct ath5k_txq_info qi = {
907 .tqi_subtype = subtype,
908 /* XXX: default values not correct for B and XR channels,
910 .tqi_aifs = AR5K_TUNE_AIFS,
911 .tqi_cw_min = AR5K_TUNE_CWMIN,
912 .tqi_cw_max = AR5K_TUNE_CWMAX
917 * Enable interrupts only for EOL and DESC conditions.
918 * We mark tx descriptors to receive a DESC interrupt
919 * when a tx queue gets deep; otherwise we wait for the
920 * EOL to reap descriptors. Note that this is done to
921 * reduce interrupt load and this only defers reaping
922 * descriptors, never transmitting frames. Aside from
923 * reducing interrupts this also permits more concurrency.
924 * The only potential downside is if the tx queue backs
925 * up in which case the top half of the kernel may backup
926 * due to a lack of tx descriptors.
928 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
929 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
930 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
933 * NB: don't print a message, this happens
934 * normally on parts with too few tx queues
936 return ERR_PTR(qnum);
938 txq = &ah->txqs[qnum];
942 INIT_LIST_HEAD(&txq->q);
943 spin_lock_init(&txq->lock);
946 txq->txq_max = ATH5K_TXQ_LEN_MAX;
947 txq->txq_poll_mark = false;
950 return &ah->txqs[qnum];
954 ath5k_beaconq_setup(struct ath5k_hw *ah)
956 struct ath5k_txq_info qi = {
957 /* XXX: default values not correct for B and XR channels,
959 .tqi_aifs = AR5K_TUNE_AIFS,
960 .tqi_cw_min = AR5K_TUNE_CWMIN,
961 .tqi_cw_max = AR5K_TUNE_CWMAX,
962 /* NB: for dynamic turbo, don't enable any other interrupts */
963 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
966 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
970 ath5k_beaconq_config(struct ath5k_hw *ah)
972 struct ath5k_txq_info qi;
975 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
979 if (ah->opmode == NL80211_IFTYPE_AP ||
980 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
982 * Always burst out beacon and CAB traffic
983 * (aifs = cwmin = cwmax = 0)
988 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
990 * Adhoc mode; backoff between 0 and (2 * cw_min).
994 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
997 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
998 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
999 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1001 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1003 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1004 "hardware queue!\n", __func__);
1007 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1011 /* reconfigure cabq with ready time to 80% of beacon_interval */
1012 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1017 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1021 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1027 * ath5k_drain_tx_buffs - Empty tx buffers
1029 * @ah The &struct ath5k_hw
1031 * Empty tx buffers from all queues in preparation
1032 * of a reset or during shutdown.
1034 * NB: this assumes output has been stopped and
1035 * we do not need to block ath5k_tx_tasklet
1038 ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1040 struct ath5k_txq *txq;
1041 struct ath5k_buf *bf, *bf0;
1044 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1045 if (ah->txqs[i].setup) {
1047 spin_lock_bh(&txq->lock);
1048 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1049 ath5k_debug_printtxbuf(ah, bf);
1051 ath5k_txbuf_free_skb(ah, bf);
1053 spin_lock(&ah->txbuflock);
1054 list_move_tail(&bf->list, &ah->txbuf);
1057 spin_unlock(&ah->txbuflock);
1060 txq->txq_poll_mark = false;
1061 spin_unlock_bh(&txq->lock);
1067 ath5k_txq_release(struct ath5k_hw *ah)
1069 struct ath5k_txq *txq = ah->txqs;
1072 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1074 ath5k_hw_release_tx_queue(ah, txq->qnum);
1085 * Enable the receive h/w following a reset.
1088 ath5k_rx_start(struct ath5k_hw *ah)
1090 struct ath_common *common = ath5k_hw_common(ah);
1091 struct ath5k_buf *bf;
1094 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1096 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1097 common->cachelsz, common->rx_bufsize);
1099 spin_lock_bh(&ah->rxbuflock);
1101 list_for_each_entry(bf, &ah->rxbuf, list) {
1102 ret = ath5k_rxbuf_setup(ah, bf);
1104 spin_unlock_bh(&ah->rxbuflock);
1108 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1109 ath5k_hw_set_rxdp(ah, bf->daddr);
1110 spin_unlock_bh(&ah->rxbuflock);
1112 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1113 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1114 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1122 * Disable the receive logic on PCU (DRU)
1123 * In preparation for a shutdown.
1125 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1129 ath5k_rx_stop(struct ath5k_hw *ah)
1132 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1133 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1135 ath5k_debug_printrxbuffs(ah);
1139 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1140 struct ath5k_rx_status *rs)
1142 struct ath_common *common = ath5k_hw_common(ah);
1143 struct ieee80211_hdr *hdr = (void *)skb->data;
1144 unsigned int keyix, hlen;
1146 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1147 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1148 return RX_FLAG_DECRYPTED;
1150 /* Apparently when a default key is used to decrypt the packet
1151 the hw does not set the index used to decrypt. In such cases
1152 get the index from the packet. */
1153 hlen = ieee80211_hdrlen(hdr->frame_control);
1154 if (ieee80211_has_protected(hdr->frame_control) &&
1155 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1156 skb->len >= hlen + 4) {
1157 keyix = skb->data[hlen + 3] >> 6;
1159 if (test_bit(keyix, common->keymap))
1160 return RX_FLAG_DECRYPTED;
1168 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1169 struct ieee80211_rx_status *rxs)
1171 struct ath_common *common = ath5k_hw_common(ah);
1174 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1176 if (ieee80211_is_beacon(mgmt->frame_control) &&
1177 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1178 ether_addr_equal(mgmt->bssid, common->curbssid)) {
1180 * Received an IBSS beacon with the same BSSID. Hardware *must*
1181 * have updated the local TSF. We have to work around various
1182 * hardware bugs, though...
1184 tsf = ath5k_hw_get_tsf64(ah);
1185 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1186 hw_tu = TSF_TO_TU(tsf);
1188 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1189 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1190 (unsigned long long)bc_tstamp,
1191 (unsigned long long)rxs->mactime,
1192 (unsigned long long)(rxs->mactime - bc_tstamp),
1193 (unsigned long long)tsf);
1196 * Sometimes the HW will give us a wrong tstamp in the rx
1197 * status, causing the timestamp extension to go wrong.
1198 * (This seems to happen especially with beacon frames bigger
1199 * than 78 byte (incl. FCS))
1200 * But we know that the receive timestamp must be later than the
1201 * timestamp of the beacon since HW must have synced to that.
1203 * NOTE: here we assume mactime to be after the frame was
1204 * received, not like mac80211 which defines it at the start.
1206 if (bc_tstamp > rxs->mactime) {
1207 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1208 "fixing mactime from %llx to %llx\n",
1209 (unsigned long long)rxs->mactime,
1210 (unsigned long long)tsf);
1215 * Local TSF might have moved higher than our beacon timers,
1216 * in that case we have to update them to continue sending
1217 * beacons. This also takes care of synchronizing beacon sending
1218 * times with other stations.
1220 if (hw_tu >= ah->nexttbtt)
1221 ath5k_beacon_update_timers(ah, bc_tstamp);
1223 /* Check if the beacon timers are still correct, because a TSF
1224 * update might have created a window between them - for a
1225 * longer description see the comment of this function: */
1226 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1227 ath5k_beacon_update_timers(ah, bc_tstamp);
1228 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1229 "fixed beacon timers after beacon receive\n");
1235 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1237 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1238 struct ath_common *common = ath5k_hw_common(ah);
1240 /* only beacons from our BSSID */
1241 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1242 !ether_addr_equal(mgmt->bssid, common->curbssid))
1245 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1247 /* in IBSS mode we should keep RSSI statistics per neighbour */
1248 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1252 * Compute padding position. skb must contain an IEEE 802.11 frame
1254 static int ath5k_common_padpos(struct sk_buff *skb)
1256 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1257 __le16 frame_control = hdr->frame_control;
1260 if (ieee80211_has_a4(frame_control))
1263 if (ieee80211_is_data_qos(frame_control))
1264 padpos += IEEE80211_QOS_CTL_LEN;
1270 * This function expects an 802.11 frame and returns the number of
1271 * bytes added, or -1 if we don't have enough header room.
1273 static int ath5k_add_padding(struct sk_buff *skb)
1275 int padpos = ath5k_common_padpos(skb);
1276 int padsize = padpos & 3;
1278 if (padsize && skb->len > padpos) {
1280 if (skb_headroom(skb) < padsize)
1283 skb_push(skb, padsize);
1284 memmove(skb->data, skb->data + padsize, padpos);
1292 * The MAC header is padded to have 32-bit boundary if the
1293 * packet payload is non-zero. The general calculation for
1294 * padsize would take into account odd header lengths:
1295 * padsize = 4 - (hdrlen & 3); however, since only
1296 * even-length headers are used, padding can only be 0 or 2
1297 * bytes and we can optimize this a bit. We must not try to
1298 * remove padding from short control frames that do not have a
1301 * This function expects an 802.11 frame and returns the number of
1304 static int ath5k_remove_padding(struct sk_buff *skb)
1306 int padpos = ath5k_common_padpos(skb);
1307 int padsize = padpos & 3;
1309 if (padsize && skb->len >= padpos + padsize) {
1310 memmove(skb->data + padsize, skb->data, padpos);
1311 skb_pull(skb, padsize);
1319 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1320 struct ath5k_rx_status *rs)
1322 struct ieee80211_rx_status *rxs;
1324 ath5k_remove_padding(skb);
1326 rxs = IEEE80211_SKB_RXCB(skb);
1329 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1330 rxs->flag |= RX_FLAG_MMIC_ERROR;
1333 * always extend the mac timestamp, since this information is
1334 * also needed for proper IBSS merging.
1336 * XXX: it might be too late to do it here, since rs_tstamp is
1337 * 15bit only. that means TSF extension has to be done within
1338 * 32768usec (about 32ms). it might be necessary to move this to
1339 * the interrupt handler, like it is done in madwifi.
1341 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1342 rxs->flag |= RX_FLAG_MACTIME_END;
1344 rxs->freq = ah->curchan->center_freq;
1345 rxs->band = ah->curchan->band;
1347 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1349 rxs->antenna = rs->rs_antenna;
1351 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1352 ah->stats.antenna_rx[rs->rs_antenna]++;
1354 ah->stats.antenna_rx[0]++; /* invalid */
1356 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1357 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1359 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1360 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1361 rxs->flag |= RX_FLAG_SHORTPRE;
1363 trace_ath5k_rx(ah, skb);
1365 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1367 /* check beacons in IBSS mode */
1368 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1369 ath5k_check_ibss_tsf(ah, skb, rxs);
1371 ieee80211_rx(ah->hw, skb);
1374 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1376 * Check if we want to further process this frame or not. Also update
1377 * statistics. Return true if we want this frame, false if not.
1380 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1382 ah->stats.rx_all_count++;
1383 ah->stats.rx_bytes_count += rs->rs_datalen;
1385 if (unlikely(rs->rs_status)) {
1386 if (rs->rs_status & AR5K_RXERR_CRC)
1387 ah->stats.rxerr_crc++;
1388 if (rs->rs_status & AR5K_RXERR_FIFO)
1389 ah->stats.rxerr_fifo++;
1390 if (rs->rs_status & AR5K_RXERR_PHY) {
1391 ah->stats.rxerr_phy++;
1392 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1393 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1396 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1398 * Decrypt error. If the error occurred
1399 * because there was no hardware key, then
1400 * let the frame through so the upper layers
1401 * can process it. This is necessary for 5210
1402 * parts which have no way to setup a ``clear''
1405 * XXX do key cache faulting
1407 ah->stats.rxerr_decrypt++;
1408 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1409 !(rs->rs_status & AR5K_RXERR_CRC))
1412 if (rs->rs_status & AR5K_RXERR_MIC) {
1413 ah->stats.rxerr_mic++;
1417 /* reject any frames with non-crypto errors */
1418 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1422 if (unlikely(rs->rs_more)) {
1423 ah->stats.rxerr_jumbo++;
1430 ath5k_set_current_imask(struct ath5k_hw *ah)
1432 enum ath5k_int imask;
1433 unsigned long flags;
1435 spin_lock_irqsave(&ah->irqlock, flags);
1438 imask &= ~AR5K_INT_RX_ALL;
1440 imask &= ~AR5K_INT_TX_ALL;
1441 ath5k_hw_set_imr(ah, imask);
1442 spin_unlock_irqrestore(&ah->irqlock, flags);
1446 ath5k_tasklet_rx(unsigned long data)
1448 struct ath5k_rx_status rs = {};
1449 struct sk_buff *skb, *next_skb;
1450 dma_addr_t next_skb_addr;
1451 struct ath5k_hw *ah = (void *)data;
1452 struct ath_common *common = ath5k_hw_common(ah);
1453 struct ath5k_buf *bf;
1454 struct ath5k_desc *ds;
1457 spin_lock(&ah->rxbuflock);
1458 if (list_empty(&ah->rxbuf)) {
1459 ATH5K_WARN(ah, "empty rx buf pool\n");
1463 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1464 BUG_ON(bf->skb == NULL);
1468 /* bail if HW is still using self-linked descriptor */
1469 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1472 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1473 if (unlikely(ret == -EINPROGRESS))
1475 else if (unlikely(ret)) {
1476 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1477 ah->stats.rxerr_proc++;
1481 if (ath5k_receive_frame_ok(ah, &rs)) {
1482 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1485 * If we can't replace bf->skb with a new skb under
1486 * memory pressure, just skip this packet
1491 dma_unmap_single(ah->dev, bf->skbaddr,
1495 skb_put(skb, rs.rs_datalen);
1497 ath5k_receive_frame(ah, skb, &rs);
1500 bf->skbaddr = next_skb_addr;
1503 list_move_tail(&bf->list, &ah->rxbuf);
1504 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1506 spin_unlock(&ah->rxbuflock);
1507 ah->rx_pending = false;
1508 ath5k_set_current_imask(ah);
1517 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1518 struct ath5k_txq *txq)
1520 struct ath5k_hw *ah = hw->priv;
1521 struct ath5k_buf *bf;
1522 unsigned long flags;
1525 trace_ath5k_tx(ah, skb, txq);
1528 * The hardware expects the header padded to 4 byte boundaries.
1529 * If this is not the case, we add the padding after the header.
1531 padsize = ath5k_add_padding(skb);
1533 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1534 " headroom to pad");
1538 if (txq->txq_len >= txq->txq_max &&
1539 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1540 ieee80211_stop_queue(hw, txq->qnum);
1542 spin_lock_irqsave(&ah->txbuflock, flags);
1543 if (list_empty(&ah->txbuf)) {
1544 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1545 spin_unlock_irqrestore(&ah->txbuflock, flags);
1546 ieee80211_stop_queues(hw);
1549 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1550 list_del(&bf->list);
1552 if (list_empty(&ah->txbuf))
1553 ieee80211_stop_queues(hw);
1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
1558 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
1560 spin_lock_irqsave(&ah->txbuflock, flags);
1561 list_add_tail(&bf->list, &ah->txbuf);
1563 spin_unlock_irqrestore(&ah->txbuflock, flags);
1569 ieee80211_free_txskb(hw, skb);
1573 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1574 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1576 struct ieee80211_tx_info *info;
1580 ah->stats.tx_all_count++;
1581 ah->stats.tx_bytes_count += skb->len;
1582 info = IEEE80211_SKB_CB(skb);
1584 tries[0] = info->status.rates[0].count;
1585 tries[1] = info->status.rates[1].count;
1586 tries[2] = info->status.rates[2].count;
1588 ieee80211_tx_info_clear_status(info);
1590 for (i = 0; i < ts->ts_final_idx; i++) {
1591 struct ieee80211_tx_rate *r =
1592 &info->status.rates[i];
1594 r->count = tries[i];
1597 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1598 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1600 if (unlikely(ts->ts_status)) {
1601 ah->stats.ack_fail++;
1602 if (ts->ts_status & AR5K_TXERR_FILT) {
1603 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1604 ah->stats.txerr_filt++;
1606 if (ts->ts_status & AR5K_TXERR_XRETRY)
1607 ah->stats.txerr_retry++;
1608 if (ts->ts_status & AR5K_TXERR_FIFO)
1609 ah->stats.txerr_fifo++;
1611 info->flags |= IEEE80211_TX_STAT_ACK;
1612 info->status.ack_signal = ts->ts_rssi;
1614 /* count the successful attempt as well */
1615 info->status.rates[ts->ts_final_idx].count++;
1619 * Remove MAC header padding before giving the frame
1622 ath5k_remove_padding(skb);
1624 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1625 ah->stats.antenna_tx[ts->ts_antenna]++;
1627 ah->stats.antenna_tx[0]++; /* invalid */
1629 trace_ath5k_tx_complete(ah, skb, txq, ts);
1630 ieee80211_tx_status(ah->hw, skb);
1634 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1636 struct ath5k_tx_status ts = {};
1637 struct ath5k_buf *bf, *bf0;
1638 struct ath5k_desc *ds;
1639 struct sk_buff *skb;
1642 spin_lock(&txq->lock);
1643 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1645 txq->txq_poll_mark = false;
1647 /* skb might already have been processed last time. */
1648 if (bf->skb != NULL) {
1651 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1652 if (unlikely(ret == -EINPROGRESS))
1654 else if (unlikely(ret)) {
1656 "error %d while processing "
1657 "queue %u\n", ret, txq->qnum);
1664 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1666 ath5k_tx_frame_completed(ah, skb, txq, &ts);
1670 * It's possible that the hardware can say the buffer is
1671 * completed when it hasn't yet loaded the ds_link from
1672 * host memory and moved on.
1673 * Always keep the last descriptor to avoid HW races...
1675 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1676 spin_lock(&ah->txbuflock);
1677 list_move_tail(&bf->list, &ah->txbuf);
1680 spin_unlock(&ah->txbuflock);
1683 spin_unlock(&txq->lock);
1684 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1685 ieee80211_wake_queue(ah->hw, txq->qnum);
1689 ath5k_tasklet_tx(unsigned long data)
1692 struct ath5k_hw *ah = (void *)data;
1694 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1695 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1696 ath5k_tx_processq(ah, &ah->txqs[i]);
1698 ah->tx_pending = false;
1699 ath5k_set_current_imask(ah);
1708 * Setup the beacon frame for transmit.
1711 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1713 struct sk_buff *skb = bf->skb;
1714 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1715 struct ath5k_desc *ds;
1719 const int padsize = 0;
1721 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1723 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1724 "skbaddr %llx\n", skb, skb->data, skb->len,
1725 (unsigned long long)bf->skbaddr);
1727 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1728 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1729 dev_kfree_skb_any(skb);
1735 antenna = ah->ah_tx_ant;
1737 flags = AR5K_TXDESC_NOACK;
1738 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1739 ds->ds_link = bf->daddr; /* self-linked */
1740 flags |= AR5K_TXDESC_VEOL;
1745 * If we use multiple antennas on AP and use
1746 * the Sectored AP scenario, switch antenna every
1747 * 4 beacons to make sure everybody hears our AP.
1748 * When a client tries to associate, hw will keep
1749 * track of the tx antenna to be used for this client
1750 * automatically, based on ACKed packets.
1752 * Note: AP still listens and transmits RTS on the
1753 * default antenna which is supposed to be an omni.
1755 * Note2: On sectored scenarios it's possible to have
1756 * multiple antennas (1 omni -- the default -- and 14
1757 * sectors), so if we choose to actually support this
1758 * mode, we need to allow the user to set how many antennas
1759 * we have and tweak the code below to send beacons
1762 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1763 antenna = ah->bsent & 4 ? 2 : 1;
1766 /* FIXME: If we are in g mode and rate is a CCK rate
1767 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1768 * from tx power (value is in dB units already) */
1769 ds->ds_data = bf->skbaddr;
1770 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1771 ieee80211_get_hdrlen_from_skb(skb), padsize,
1772 AR5K_PKT_TYPE_BEACON,
1773 (ah->ah_txpower.txp_requested * 2),
1774 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1775 1, AR5K_TXKEYIX_INVALID,
1776 antenna, flags, 0, 0);
1782 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1787 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1788 * this is called only once at config_bss time, for AP we do it every
1789 * SWBA interrupt so that the TIM will reflect buffered frames.
1791 * Called with the beacon lock.
1794 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1797 struct ath5k_hw *ah = hw->priv;
1798 struct ath5k_vif *avf;
1799 struct sk_buff *skb;
1801 if (WARN_ON(!vif)) {
1806 skb = ieee80211_beacon_get(hw, vif);
1813 avf = (void *)vif->drv_priv;
1814 ath5k_txbuf_free_skb(ah, avf->bbuf);
1815 avf->bbuf->skb = skb;
1816 ret = ath5k_beacon_setup(ah, avf->bbuf);
1822 * Transmit a beacon frame at SWBA. Dynamic updates to the
1823 * frame contents are done as needed and the slot time is
1824 * also adjusted based on current state.
1826 * This is called from software irq context (beacontq tasklets)
1827 * or user context from ath5k_beacon_config.
1830 ath5k_beacon_send(struct ath5k_hw *ah)
1832 struct ieee80211_vif *vif;
1833 struct ath5k_vif *avf;
1834 struct ath5k_buf *bf;
1835 struct sk_buff *skb;
1838 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1841 * Check if the previous beacon has gone out. If
1842 * not, don't don't try to post another: skip this
1843 * period and wait for the next. Missed beacons
1844 * indicate a problem and should not occur. If we
1845 * miss too many consecutive beacons reset the device.
1847 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1849 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1850 "missed %u consecutive beacons\n", ah->bmisscount);
1851 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1852 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1853 "stuck beacon time (%u missed)\n",
1855 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1856 "stuck beacon, resetting\n");
1857 ieee80211_queue_work(ah->hw, &ah->reset_work);
1861 if (unlikely(ah->bmisscount != 0)) {
1862 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1863 "resume beacon xmit after %u misses\n",
1868 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1869 ah->num_mesh_vifs > 1) ||
1870 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1871 u64 tsf = ath5k_hw_get_tsf64(ah);
1872 u32 tsftu = TSF_TO_TU(tsf);
1873 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1874 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1875 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1876 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1877 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1878 } else /* only one interface */
1884 avf = (void *)vif->drv_priv;
1888 * Stop any current dma and put the new frame on the queue.
1889 * This should never fail since we check above that no frames
1890 * are still pending on the queue.
1892 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1893 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1894 /* NB: hw still stops DMA, so proceed */
1897 /* refresh the beacon for AP or MESH mode */
1898 if (ah->opmode == NL80211_IFTYPE_AP ||
1899 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1900 err = ath5k_beacon_update(ah->hw, vif);
1905 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1906 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1907 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1911 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1913 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1914 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1915 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1916 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1918 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1920 ath5k_tx_queue(ah->hw, skb, ah->cabq);
1922 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1925 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1932 * ath5k_beacon_update_timers - update beacon timers
1934 * @ah: struct ath5k_hw pointer we are operating on
1935 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1936 * beacon timer update based on the current HW TSF.
1938 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1939 * of a received beacon or the current local hardware TSF and write it to the
1940 * beacon timer registers.
1942 * This is called in a variety of situations, e.g. when a beacon is received,
1943 * when a TSF update has been detected, but also when an new IBSS is created or
1944 * when we otherwise know we have to update the timers, but we keep it in this
1945 * function to have it all together in one place.
1948 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
1950 u32 nexttbtt, intval, hw_tu, bc_tu;
1953 intval = ah->bintval & AR5K_BEACON_PERIOD;
1954 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
1955 + ah->num_mesh_vifs > 1) {
1956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
1961 if (WARN_ON(!intval))
1964 /* beacon TSF converted to TU */
1965 bc_tu = TSF_TO_TU(bc_tsf);
1967 /* current TSF converted to TU */
1968 hw_tsf = ath5k_hw_get_tsf64(ah);
1969 hw_tu = TSF_TO_TU(hw_tsf);
1971 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1972 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1973 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1974 * configuration we need to make sure it is bigger than that. */
1978 * no beacons received, called internally.
1979 * just need to refresh timers based on HW TSF.
1981 nexttbtt = roundup(hw_tu + FUDGE, intval);
1982 } else if (bc_tsf == 0) {
1984 * no beacon received, probably called by ath5k_reset_tsf().
1985 * reset TSF to start with 0.
1988 intval |= AR5K_BEACON_RESET_TSF;
1989 } else if (bc_tsf > hw_tsf) {
1991 * beacon received, SW merge happened but HW TSF not yet updated.
1992 * not possible to reconfigure timers yet, but next time we
1993 * receive a beacon with the same BSSID, the hardware will
1994 * automatically update the TSF and then we need to reconfigure
1997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1998 "need to wait for HW TSF sync\n");
2002 * most important case for beacon synchronization between STA.
2004 * beacon received and HW TSF has been already updated by HW.
2005 * update next TBTT based on the TSF of the beacon, but make
2006 * sure it is ahead of our local TSF timer.
2008 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2012 ah->nexttbtt = nexttbtt;
2014 intval |= AR5K_BEACON_ENA;
2015 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2018 * debugging output last in order to preserve the time critical aspect
2022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2023 "reconfigured timers based on HW TSF\n");
2024 else if (bc_tsf == 0)
2025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2026 "reset HW TSF and timers\n");
2028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2029 "updated timers based on beacon TSF\n");
2031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2033 (unsigned long long) bc_tsf,
2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2036 intval & AR5K_BEACON_PERIOD,
2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2044 * @ah: struct ath5k_hw pointer we are operating on
2046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2047 * interrupts to detect TSF updates only.
2050 ath5k_beacon_config(struct ath5k_hw *ah)
2052 spin_lock_bh(&ah->block);
2054 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2056 if (ah->enable_beacon) {
2058 * In IBSS mode we use a self-linked tx descriptor and let the
2059 * hardware send the beacons automatically. We have to load it
2061 * We use the SWBA interrupt only to keep track of the beacon
2062 * timers in order to detect automatic TSF updates.
2064 ath5k_beaconq_config(ah);
2066 ah->imask |= AR5K_INT_SWBA;
2068 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2069 if (ath5k_hw_hasveol(ah))
2070 ath5k_beacon_send(ah);
2072 ath5k_beacon_update_timers(ah, -1);
2074 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2077 ath5k_hw_set_imr(ah, ah->imask);
2079 spin_unlock_bh(&ah->block);
2082 static void ath5k_tasklet_beacon(unsigned long data)
2084 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2087 * Software beacon alert--time to send a beacon.
2089 * In IBSS mode we use this interrupt just to
2090 * keep track of the next TBTT (target beacon
2091 * transmission time) in order to detect whether
2092 * automatic TSF updates happened.
2094 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2095 /* XXX: only if VEOL supported */
2096 u64 tsf = ath5k_hw_get_tsf64(ah);
2097 ah->nexttbtt += ah->bintval;
2098 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2099 "SWBA nexttbtt: %x hw_tu: %x "
2103 (unsigned long long) tsf);
2105 spin_lock(&ah->block);
2106 ath5k_beacon_send(ah);
2107 spin_unlock(&ah->block);
2112 /********************\
2113 * Interrupt handling *
2114 \********************/
2117 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2119 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2120 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2121 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2123 /* Run ANI only when calibration is not active */
2125 ah->ah_cal_next_ani = jiffies +
2126 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2127 tasklet_schedule(&ah->ani_tasklet);
2129 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2130 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2131 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2133 /* Run calibration only when another calibration
2136 * Note: This is for both full/short calibration,
2137 * if it's time for a full one, ath5k_calibrate_work will deal
2140 ah->ah_cal_next_short = jiffies +
2141 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2142 ieee80211_queue_work(ah->hw, &ah->calib_work);
2144 /* we could use SWI to generate enough interrupts to meet our
2145 * calibration interval requirements, if necessary:
2146 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2150 ath5k_schedule_rx(struct ath5k_hw *ah)
2152 ah->rx_pending = true;
2153 tasklet_schedule(&ah->rxtq);
2157 ath5k_schedule_tx(struct ath5k_hw *ah)
2159 ah->tx_pending = true;
2160 tasklet_schedule(&ah->txtq);
2164 ath5k_intr(int irq, void *dev_id)
2166 struct ath5k_hw *ah = dev_id;
2167 enum ath5k_int status;
2168 unsigned int counter = 1000;
2172 * If hw is not ready (or detached) and we get an
2173 * interrupt, or if we have no interrupts pending
2174 * (that means it's not for us) skip it.
2176 * NOTE: Group 0/1 PCI interface registers are not
2177 * supported on WiSOCs, so we can't check for pending
2178 * interrupts (ISR belongs to another register group
2181 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2182 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2183 !ath5k_hw_is_intr_pending(ah))))
2188 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2190 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2194 * Fatal hw error -> Log and reset
2196 * Fatal errors are unrecoverable so we have to
2197 * reset the card. These errors include bus and
2200 if (unlikely(status & AR5K_INT_FATAL)) {
2202 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2203 "fatal int, resetting\n");
2204 ieee80211_queue_work(ah->hw, &ah->reset_work);
2207 * RX Overrun -> Count and reset if needed
2209 * Receive buffers are full. Either the bus is busy or
2210 * the CPU is not fast enough to process all received
2213 } else if (unlikely(status & AR5K_INT_RXORN)) {
2216 * Older chipsets need a reset to come out of this
2217 * condition, but we treat it as RX for newer chips.
2218 * We don't know exactly which versions need a reset
2219 * this guess is copied from the HAL.
2221 ah->stats.rxorn_intr++;
2223 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2224 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2225 "rx overrun, resetting\n");
2226 ieee80211_queue_work(ah->hw, &ah->reset_work);
2228 ath5k_schedule_rx(ah);
2232 /* Software Beacon Alert -> Schedule beacon tasklet */
2233 if (status & AR5K_INT_SWBA)
2234 tasklet_hi_schedule(&ah->beacontq);
2237 * No more RX descriptors -> Just count
2239 * NB: the hardware should re-read the link when
2240 * RXE bit is written, but it doesn't work at
2241 * least on older hardware revs.
2243 if (status & AR5K_INT_RXEOL)
2244 ah->stats.rxeol_intr++;
2247 /* TX Underrun -> Bump tx trigger level */
2248 if (status & AR5K_INT_TXURN)
2249 ath5k_hw_update_tx_triglevel(ah, true);
2251 /* RX -> Schedule rx tasklet */
2252 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2253 ath5k_schedule_rx(ah);
2255 /* TX -> Schedule tx tasklet */
2256 if (status & (AR5K_INT_TXOK
2260 ath5k_schedule_tx(ah);
2262 /* Missed beacon -> TODO
2263 if (status & AR5K_INT_BMISS)
2266 /* MIB event -> Update counters and notify ANI */
2267 if (status & AR5K_INT_MIB) {
2268 ah->stats.mib_intr++;
2269 ath5k_hw_update_mib_counters(ah);
2270 ath5k_ani_mib_intr(ah);
2273 /* GPIO -> Notify RFKill layer */
2274 if (status & AR5K_INT_GPIO)
2275 tasklet_schedule(&ah->rf_kill.toggleq);
2279 if (ath5k_get_bus_type(ah) == ATH_AHB)
2282 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2285 * Until we handle rx/tx interrupts mask them on IMR
2287 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2288 * and unset after we 've handled the interrupts.
2290 if (ah->rx_pending || ah->tx_pending)
2291 ath5k_set_current_imask(ah);
2293 if (unlikely(!counter))
2294 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2296 /* Fire up calibration poll */
2297 ath5k_intr_calibration_poll(ah);
2303 * Periodically recalibrate the PHY to account
2304 * for temperature/environment changes.
2307 ath5k_calibrate_work(struct work_struct *work)
2309 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2312 /* Should we run a full calibration ? */
2313 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2315 ah->ah_cal_next_full = jiffies +
2316 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2317 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2319 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2320 "running full calibration\n");
2322 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2324 * Rfgain is out of bounds, reset the chip
2325 * to load new gain values.
2327 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2328 "got new rfgain, resetting\n");
2329 ieee80211_queue_work(ah->hw, &ah->reset_work);
2332 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2335 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2336 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2337 ah->curchan->hw_value);
2339 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2340 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2341 ieee80211_frequency_to_channel(
2342 ah->curchan->center_freq));
2344 /* Clear calibration flags */
2345 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2346 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2347 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2348 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2353 ath5k_tasklet_ani(unsigned long data)
2355 struct ath5k_hw *ah = (void *)data;
2357 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2358 ath5k_ani_calibration(ah);
2359 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2364 ath5k_tx_complete_poll_work(struct work_struct *work)
2366 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2367 tx_complete_work.work);
2368 struct ath5k_txq *txq;
2370 bool needreset = false;
2372 mutex_lock(&ah->lock);
2374 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2375 if (ah->txqs[i].setup) {
2377 spin_lock_bh(&txq->lock);
2378 if (txq->txq_len > 1) {
2379 if (txq->txq_poll_mark) {
2380 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2381 "TX queue stuck %d\n",
2385 spin_unlock_bh(&txq->lock);
2388 txq->txq_poll_mark = true;
2391 spin_unlock_bh(&txq->lock);
2396 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2397 "TX queues stuck, resetting\n");
2398 ath5k_reset(ah, NULL, true);
2401 mutex_unlock(&ah->lock);
2403 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2404 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2408 /*************************\
2409 * Initialization routines *
2410 \*************************/
2412 static const struct ieee80211_iface_limit if_limits[] = {
2413 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2414 { .max = 4, .types =
2415 #ifdef CONFIG_MAC80211_MESH
2416 BIT(NL80211_IFTYPE_MESH_POINT) |
2418 BIT(NL80211_IFTYPE_AP) },
2421 static const struct ieee80211_iface_combination if_comb = {
2422 .limits = if_limits,
2423 .n_limits = ARRAY_SIZE(if_limits),
2424 .max_interfaces = 2048,
2425 .num_different_channels = 1,
2429 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2431 struct ieee80211_hw *hw = ah->hw;
2432 struct ath_common *common;
2436 /* Initialize driver private data */
2437 SET_IEEE80211_DEV(hw, ah->dev);
2438 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2439 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2440 IEEE80211_HW_SIGNAL_DBM |
2441 IEEE80211_HW_MFP_CAPABLE |
2442 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2444 hw->wiphy->interface_modes =
2445 BIT(NL80211_IFTYPE_AP) |
2446 BIT(NL80211_IFTYPE_STATION) |
2447 BIT(NL80211_IFTYPE_ADHOC) |
2448 BIT(NL80211_IFTYPE_MESH_POINT);
2450 hw->wiphy->iface_combinations = &if_comb;
2451 hw->wiphy->n_iface_combinations = 1;
2453 /* SW support for IBSS_RSN is provided by mac80211 */
2454 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2456 /* both antennas can be configured as RX or TX */
2457 hw->wiphy->available_antennas_tx = 0x3;
2458 hw->wiphy->available_antennas_rx = 0x3;
2460 hw->extra_tx_headroom = 2;
2461 hw->channel_change_time = 5000;
2464 * Mark the device as detached to avoid processing
2465 * interrupts until setup is complete.
2467 __set_bit(ATH_STAT_INVALID, ah->status);
2469 ah->opmode = NL80211_IFTYPE_STATION;
2471 mutex_init(&ah->lock);
2472 spin_lock_init(&ah->rxbuflock);
2473 spin_lock_init(&ah->txbuflock);
2474 spin_lock_init(&ah->block);
2475 spin_lock_init(&ah->irqlock);
2477 /* Setup interrupt handler */
2478 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2480 ATH5K_ERR(ah, "request_irq failed\n");
2484 common = ath5k_hw_common(ah);
2485 common->ops = &ath5k_common_ops;
2486 common->bus_ops = bus_ops;
2490 common->clockrate = 40;
2493 * Cache line size is used to size and align various
2494 * structures used to communicate with the hardware.
2496 ath5k_read_cachesize(common, &csz);
2497 common->cachelsz = csz << 2; /* convert to bytes */
2499 spin_lock_init(&common->cc_lock);
2501 /* Initialize device */
2502 ret = ath5k_hw_init(ah);
2506 /* Set up multi-rate retry capabilities */
2507 if (ah->ah_capabilities.cap_has_mrr_support) {
2509 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2510 AR5K_INIT_RETRY_LONG);
2513 hw->vif_data_size = sizeof(struct ath5k_vif);
2515 /* Finish private driver data initialization */
2516 ret = ath5k_init(hw);
2520 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2521 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2523 ah->ah_phy_revision);
2525 if (!ah->ah_single_chip) {
2526 /* Single chip radio (!RF5111) */
2527 if (ah->ah_radio_5ghz_revision &&
2528 !ah->ah_radio_2ghz_revision) {
2529 /* No 5GHz support -> report 2GHz radio */
2530 if (!test_bit(AR5K_MODE_11A,
2531 ah->ah_capabilities.cap_mode)) {
2532 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2533 ath5k_chip_name(AR5K_VERSION_RAD,
2534 ah->ah_radio_5ghz_revision),
2535 ah->ah_radio_5ghz_revision);
2536 /* No 2GHz support (5110 and some
2537 * 5GHz only cards) -> report 5GHz radio */
2538 } else if (!test_bit(AR5K_MODE_11B,
2539 ah->ah_capabilities.cap_mode)) {
2540 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2541 ath5k_chip_name(AR5K_VERSION_RAD,
2542 ah->ah_radio_5ghz_revision),
2543 ah->ah_radio_5ghz_revision);
2544 /* Multiband radio */
2546 ATH5K_INFO(ah, "RF%s multiband radio found"
2548 ath5k_chip_name(AR5K_VERSION_RAD,
2549 ah->ah_radio_5ghz_revision),
2550 ah->ah_radio_5ghz_revision);
2553 /* Multi chip radio (RF5111 - RF2111) ->
2554 * report both 2GHz/5GHz radios */
2555 else if (ah->ah_radio_5ghz_revision &&
2556 ah->ah_radio_2ghz_revision) {
2557 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2558 ath5k_chip_name(AR5K_VERSION_RAD,
2559 ah->ah_radio_5ghz_revision),
2560 ah->ah_radio_5ghz_revision);
2561 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2562 ath5k_chip_name(AR5K_VERSION_RAD,
2563 ah->ah_radio_2ghz_revision),
2564 ah->ah_radio_2ghz_revision);
2568 ath5k_debug_init_device(ah);
2570 /* ready to process interrupts */
2571 __clear_bit(ATH_STAT_INVALID, ah->status);
2575 ath5k_hw_deinit(ah);
2577 free_irq(ah->irq, ah);
2583 ath5k_stop_locked(struct ath5k_hw *ah)
2586 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2587 test_bit(ATH_STAT_INVALID, ah->status));
2590 * Shutdown the hardware and driver:
2591 * stop output from above
2592 * disable interrupts
2594 * turn off the radio
2595 * clear transmit machinery
2596 * clear receive machinery
2597 * drain and release tx queues
2598 * reclaim beacon resources
2599 * power down hardware
2601 * Note that some of this work is not possible if the
2602 * hardware is gone (invalid).
2604 ieee80211_stop_queues(ah->hw);
2606 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2608 ath5k_hw_set_imr(ah, 0);
2609 synchronize_irq(ah->irq);
2611 ath5k_hw_dma_stop(ah);
2612 ath5k_drain_tx_buffs(ah);
2613 ath5k_hw_phy_disable(ah);
2619 int ath5k_start(struct ieee80211_hw *hw)
2621 struct ath5k_hw *ah = hw->priv;
2622 struct ath_common *common = ath5k_hw_common(ah);
2625 mutex_lock(&ah->lock);
2627 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2630 * Stop anything previously setup. This is safe
2631 * no matter this is the first time through or not.
2633 ath5k_stop_locked(ah);
2636 * The basic interface to setting the hardware in a good
2637 * state is ``reset''. On return the hardware is known to
2638 * be powered up and with interrupts disabled. This must
2639 * be followed by initialization of the appropriate bits
2640 * and then setup of the interrupt mask.
2642 ah->curchan = ah->hw->conf.chandef.chan;
2643 ah->imask = AR5K_INT_RXOK
2653 ret = ath5k_reset(ah, NULL, false);
2657 if (!ath5k_modparam_no_hw_rfkill_switch)
2658 ath5k_rfkill_hw_start(ah);
2661 * Reset the key cache since some parts do not reset the
2662 * contents on initial power up or resume from suspend.
2664 for (i = 0; i < common->keymax; i++)
2665 ath_hw_keyreset(common, (u16) i);
2667 /* Use higher rates for acks instead of base
2669 ah->ah_ack_bitrate_high = true;
2671 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2672 ah->bslot[i] = NULL;
2677 mutex_unlock(&ah->lock);
2679 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2680 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2685 static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2687 ah->rx_pending = false;
2688 ah->tx_pending = false;
2689 tasklet_kill(&ah->rxtq);
2690 tasklet_kill(&ah->txtq);
2691 tasklet_kill(&ah->beacontq);
2692 tasklet_kill(&ah->ani_tasklet);
2696 * Stop the device, grabbing the top-level lock to protect
2697 * against concurrent entry through ath5k_init (which can happen
2698 * if another thread does a system call and the thread doing the
2699 * stop is preempted).
2701 void ath5k_stop(struct ieee80211_hw *hw)
2703 struct ath5k_hw *ah = hw->priv;
2706 mutex_lock(&ah->lock);
2707 ret = ath5k_stop_locked(ah);
2708 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2710 * Don't set the card in full sleep mode!
2712 * a) When the device is in this state it must be carefully
2713 * woken up or references to registers in the PCI clock
2714 * domain may freeze the bus (and system). This varies
2715 * by chip and is mostly an issue with newer parts
2716 * (madwifi sources mentioned srev >= 0x78) that go to
2717 * sleep more quickly.
2719 * b) On older chips full sleep results a weird behaviour
2720 * during wakeup. I tested various cards with srev < 0x78
2721 * and they don't wake up after module reload, a second
2722 * module reload is needed to bring the card up again.
2724 * Until we figure out what's going on don't enable
2725 * full chip reset on any chip (this is what Legacy HAL
2726 * and Sam's HAL do anyway). Instead Perform a full reset
2727 * on the device (same as initial state after attach) and
2728 * leave it idle (keep MAC/BB on warm reset) */
2729 ret = ath5k_hw_on_hold(ah);
2731 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2732 "putting device to sleep\n");
2736 mutex_unlock(&ah->lock);
2738 ath5k_stop_tasklets(ah);
2740 cancel_delayed_work_sync(&ah->tx_complete_work);
2742 if (!ath5k_modparam_no_hw_rfkill_switch)
2743 ath5k_rfkill_hw_stop(ah);
2747 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2748 * and change to the given channel.
2750 * This should be called with ah->lock.
2753 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2756 struct ath_common *common = ath5k_hw_common(ah);
2760 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2762 ath5k_hw_set_imr(ah, 0);
2763 synchronize_irq(ah->irq);
2764 ath5k_stop_tasklets(ah);
2766 /* Save ani mode and disable ANI during
2767 * reset. If we don't we might get false
2768 * PHY error interrupts. */
2769 ani_mode = ah->ani_state.ani_mode;
2770 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2772 /* We are going to empty hw queues
2773 * so we should also free any remaining
2775 ath5k_drain_tx_buffs(ah);
2779 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2781 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2783 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2787 ret = ath5k_rx_start(ah);
2789 ATH5K_ERR(ah, "can't start recv logic\n");
2793 ath5k_ani_init(ah, ani_mode);
2796 * Set calibration intervals
2798 * Note: We don't need to run calibration imediately
2799 * since some initial calibration is done on reset
2800 * even for fast channel switching. Also on scanning
2801 * this will get set again and again and it won't get
2802 * executed unless we connect somewhere and spend some
2803 * time on the channel (that's what calibration needs
2804 * anyway to be accurate).
2806 ah->ah_cal_next_full = jiffies +
2807 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2808 ah->ah_cal_next_ani = jiffies +
2809 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2810 ah->ah_cal_next_short = jiffies +
2811 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2813 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2815 /* clear survey data and cycle counters */
2816 memset(&ah->survey, 0, sizeof(ah->survey));
2817 spin_lock_bh(&common->cc_lock);
2818 ath_hw_cycle_counters_update(common);
2819 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2820 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2821 spin_unlock_bh(&common->cc_lock);
2824 * Change channels and update the h/w rate map if we're switching;
2825 * e.g. 11a to 11b/g.
2827 * We may be doing a reset in response to an ioctl that changes the
2828 * channel so update any state that might change as a result.
2832 /* ath5k_chan_change(ah, c); */
2834 ath5k_beacon_config(ah);
2835 /* intrs are enabled by ath5k_beacon_config */
2837 ieee80211_wake_queues(ah->hw);
2844 static void ath5k_reset_work(struct work_struct *work)
2846 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2849 mutex_lock(&ah->lock);
2850 ath5k_reset(ah, NULL, true);
2851 mutex_unlock(&ah->lock);
2855 ath5k_init(struct ieee80211_hw *hw)
2858 struct ath5k_hw *ah = hw->priv;
2859 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2860 struct ath5k_txq *txq;
2861 u8 mac[ETH_ALEN] = {};
2866 * Collect the channel list. The 802.11 layer
2867 * is responsible for filtering this list based
2868 * on settings like the phy mode and regulatory
2869 * domain restrictions.
2871 ret = ath5k_setup_bands(hw);
2873 ATH5K_ERR(ah, "can't get channels\n");
2878 * Allocate tx+rx descriptors and populate the lists.
2880 ret = ath5k_desc_alloc(ah);
2882 ATH5K_ERR(ah, "can't allocate descriptors\n");
2887 * Allocate hardware transmit queues: one queue for
2888 * beacon frames and one data queue for each QoS
2889 * priority. Note that hw functions handle resetting
2890 * these queues at the needed time.
2892 ret = ath5k_beaconq_setup(ah);
2894 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2898 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2899 if (IS_ERR(ah->cabq)) {
2900 ATH5K_ERR(ah, "can't setup cab queue\n");
2901 ret = PTR_ERR(ah->cabq);
2905 /* 5211 and 5212 usually support 10 queues but we better rely on the
2906 * capability information */
2907 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2908 /* This order matches mac80211's queue priority, so we can
2909 * directly use the mac80211 queue number without any mapping */
2910 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2912 ATH5K_ERR(ah, "can't setup xmit queue\n");
2916 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2918 ATH5K_ERR(ah, "can't setup xmit queue\n");
2922 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2924 ATH5K_ERR(ah, "can't setup xmit queue\n");
2928 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2930 ATH5K_ERR(ah, "can't setup xmit queue\n");
2936 /* older hardware (5210) can only support one data queue */
2937 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2939 ATH5K_ERR(ah, "can't setup xmit queue\n");
2946 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2947 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2948 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2949 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
2951 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2952 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
2953 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
2955 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2957 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
2961 SET_IEEE80211_PERM_ADDR(hw, mac);
2962 /* All MAC address bits matter for ACKs */
2963 ath5k_update_bssid_mask_and_opmode(ah, NULL);
2965 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2966 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2968 ATH5K_ERR(ah, "can't initialize regulatory system\n");
2972 ret = ieee80211_register_hw(hw);
2974 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
2978 if (!ath_is_world_regd(regulatory))
2979 regulatory_hint(hw->wiphy, regulatory->alpha2);
2981 ath5k_init_leds(ah);
2983 ath5k_sysfs_register(ah);
2987 ath5k_txq_release(ah);
2989 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2991 ath5k_desc_free(ah);
2997 ath5k_deinit_ah(struct ath5k_hw *ah)
2999 struct ieee80211_hw *hw = ah->hw;
3002 * NB: the order of these is important:
3003 * o call the 802.11 layer before detaching ath5k_hw to
3004 * ensure callbacks into the driver to delete global
3005 * key cache entries can be handled
3006 * o reclaim the tx queue data structures after calling
3007 * the 802.11 layer as we'll get called back to reclaim
3008 * node state and potentially want to use them
3009 * o to cleanup the tx queues the hal is called, so detach
3011 * XXX: ??? detach ath5k_hw ???
3012 * Other than that, it's straightforward...
3014 ieee80211_unregister_hw(hw);
3015 ath5k_desc_free(ah);
3016 ath5k_txq_release(ah);
3017 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3018 ath5k_unregister_leds(ah);
3020 ath5k_sysfs_unregister(ah);
3022 * NB: can't reclaim these until after ieee80211_ifdetach
3023 * returns because we'll get called back to reclaim node
3024 * state and potentially want to use them.
3026 ath5k_hw_deinit(ah);
3027 free_irq(ah->irq, ah);
3031 ath5k_any_vif_assoc(struct ath5k_hw *ah)
3033 struct ath5k_vif_iter_data iter_data;
3034 iter_data.hw_macaddr = NULL;
3035 iter_data.any_assoc = false;
3036 iter_data.need_set_hw_addr = false;
3037 iter_data.found_active = true;
3039 ieee80211_iterate_active_interfaces_atomic(
3040 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3041 ath5k_vif_iter, &iter_data);
3042 return iter_data.any_assoc;
3046 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3048 struct ath5k_hw *ah = hw->priv;
3050 rfilt = ath5k_hw_get_rx_filter(ah);
3052 rfilt |= AR5K_RX_FILTER_BEACON;
3054 rfilt &= ~AR5K_RX_FILTER_BEACON;
3055 ath5k_hw_set_rx_filter(ah, rfilt);
3056 ah->filter_flags = rfilt;
3059 void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3060 const char *fmt, ...)
3062 struct va_format vaf;
3065 va_start(args, fmt);
3071 printk("%s" pr_fmt("%s: %pV"),
3072 level, wiphy_name(ah->hw->wiphy), &vaf);
3074 printk("%s" pr_fmt("%pV"), level, &vaf);