2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 enum rx_attention_flags {
22 RX_ATTENTION_FLAGS_FIRST_MPDU = 1 << 0,
23 RX_ATTENTION_FLAGS_LAST_MPDU = 1 << 1,
24 RX_ATTENTION_FLAGS_MCAST_BCAST = 1 << 2,
25 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = 1 << 3,
26 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = 1 << 4,
27 RX_ATTENTION_FLAGS_POWER_MGMT = 1 << 5,
28 RX_ATTENTION_FLAGS_NON_QOS = 1 << 6,
29 RX_ATTENTION_FLAGS_NULL_DATA = 1 << 7,
30 RX_ATTENTION_FLAGS_MGMT_TYPE = 1 << 8,
31 RX_ATTENTION_FLAGS_CTRL_TYPE = 1 << 9,
32 RX_ATTENTION_FLAGS_MORE_DATA = 1 << 10,
33 RX_ATTENTION_FLAGS_EOSP = 1 << 11,
34 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = 1 << 12,
35 RX_ATTENTION_FLAGS_FRAGMENT = 1 << 13,
36 RX_ATTENTION_FLAGS_ORDER = 1 << 14,
37 RX_ATTENTION_FLAGS_CLASSIFICATION = 1 << 15,
38 RX_ATTENTION_FLAGS_OVERFLOW_ERR = 1 << 16,
39 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = 1 << 17,
40 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = 1 << 18,
41 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = 1 << 19,
42 RX_ATTENTION_FLAGS_SA_IDX_INVALID = 1 << 20,
43 RX_ATTENTION_FLAGS_DA_IDX_INVALID = 1 << 21,
44 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = 1 << 22,
45 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = 1 << 23,
46 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = 1 << 24,
47 RX_ATTENTION_FLAGS_DIRECTED = 1 << 25,
48 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = 1 << 26,
49 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = 1 << 27,
50 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = 1 << 28,
51 RX_ATTENTION_FLAGS_DECRYPT_ERR = 1 << 29,
52 RX_ATTENTION_FLAGS_FCS_ERR = 1 << 30,
53 RX_ATTENTION_FLAGS_MSDU_DONE = 1 << 31,
57 __le32 flags; /* %RX_ATTENTION_FLAGS_ */
62 * Indicates the first MSDU of the PPDU. If both first_mpdu
63 * and last_mpdu are set in the MSDU then this is a not an
64 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
65 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
66 * 0. The PPDU start status will only be valid when this bit
70 * Indicates the last MSDU of the last MPDU of the PPDU. The
71 * PPDU end status will only be valid when this bit is set.
74 * Multicast / broadcast indicator. Only set when the MAC
75 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
76 * matches one of the 4 BSSID registers. Only set when
80 * Indicates no matching entries within the the max search
81 * count. Only set when first_msdu is set.
84 * Indicates an unsuccessful search for the peer index due to
85 * timeout. Only set when first_msdu is set.
88 * Power management bit set in the 802.11 header. Only set
89 * when first_msdu is set.
92 * Set if packet is not a non-QoS data frame. Only set when
96 * Set if frame type indicates either null data or QoS null
97 * data format. Only set when first_msdu is set.
100 * Set if packet is a management packet. Only set when
104 * Set if packet is a control packet. Only set when first_msdu
108 * Set if more bit in frame control is set. Only set when
112 * Set if the EOSP (end of service period) bit in the QoS
113 * control field is set. Only set when first_msdu is set.
116 * Set if packet is U-APSD trigger. Key table will have bits
117 * per TID to indicate U-APSD trigger.
120 * Indicates that this is an 802.11 fragment frame. This is
121 * set when either the more_frag bit is set in the frame
122 * control or the fragment number is not zero. Only set when
126 * Set if the order bit in the frame control is set. Only set
127 * when first_msdu is set.
130 * Indicates that this status has a corresponding MSDU that
131 * requires FW processing. The OLE will have classification
132 * ring mask registers which will indicate the ring(s) for
133 * packets and descriptors which need FW attention.
136 * PCU Receive FIFO does not have enough space to store the
137 * full receive packet. Enough space is reserved in the
138 * receive FIFO for the status is written. This MPDU remaining
139 * packets in the PPDU will be filtered and no Ack response
140 * will be transmitted.
143 * Indicates that the MSDU length from the 802.3 encapsulated
144 * length field extends beyond the MPDU boundary.
146 * tcp_udp_chksum_fail
147 * Indicates that the computed checksum (tcp_udp_chksum) did
148 * not match the checksum in the TCP/UDP header.
151 * Indicates that the computed checksum did not match the
152 * checksum in the IP header.
155 * Indicates no matching entry was found in the address search
156 * table for the source MAC address.
159 * Indicates no matching entry was found in the address search
160 * table for the destination MAC address.
163 * Indicates an unsuccessful search for the source MAC address
164 * due to the expiring of the search timer.
167 * Indicates an unsuccessful search for the destination MAC
168 * address due to the expiring of the search timer.
171 * Indicates that this data type frame is not encrypted even if
172 * the policy for this MPDU requires encryption as indicated in
173 * the peer table key type.
176 * MPDU is a directed packet which means that the RA matched
177 * our STA addresses. In proxySTA it means that the TA matched
178 * an entry in our address search table with the corresponding
179 * 'no_ack' bit is the address search entry cleared.
182 * Indicates that at least one of the rx buffers has been
183 * fragmented. If set the FW should look at the rx_frag_info
184 * descriptor described below.
187 * Indicates that the MPDU was pre-maturely terminated
188 * resulting in a truncated MPDU. Don't trust the MPDU length
192 * Indicates that the MPDU Michael integrity check failed
195 * Indicates that the MPDU decrypt integrity check failed
198 * Indicates that the MPDU FCS check failed
201 * If set indicates that the RX packet data, RX header data, RX
202 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
203 * start/end descriptors and RX Attention descriptor are all
204 * valid. This bit must be in the last octet of the
208 struct rx_frag_info {
217 * Indicates the number of more buffers associated with RX DMA
218 * ring 0. Field is filled in by the RX_DMA.
221 * Indicates the number of more buffers associated with RX DMA
222 * ring 1. Field is filled in by the RX_DMA.
225 * Indicates the number of more buffers associated with RX DMA
226 * ring 2. Field is filled in by the RX_DMA.
229 * Indicates the number of more buffers associated with RX DMA
230 * ring 3. Field is filled in by the RX_DMA.
233 enum htt_rx_mpdu_encrypt_type {
234 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
235 HTT_RX_MPDU_ENCRYPT_WEP104 = 1,
236 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2,
237 HTT_RX_MPDU_ENCRYPT_WEP128 = 3,
238 HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4,
239 HTT_RX_MPDU_ENCRYPT_WAPI = 5,
240 HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6,
241 HTT_RX_MPDU_ENCRYPT_NONE = 7,
244 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
245 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
246 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
247 #define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16
248 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
249 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28
250 #define RX_MPDU_START_INFO0_FROM_DS (1 << 11)
251 #define RX_MPDU_START_INFO0_TO_DS (1 << 12)
252 #define RX_MPDU_START_INFO0_ENCRYPTED (1 << 13)
253 #define RX_MPDU_START_INFO0_RETRY (1 << 14)
254 #define RX_MPDU_START_INFO0_TXBF_H_INFO (1 << 15)
256 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
257 #define RX_MPDU_START_INFO1_TID_LSB 28
258 #define RX_MPDU_START_INFO1_DIRECTED (1 << 16)
260 struct rx_mpdu_start {
265 __le32 info1; /* %RX_MPDU_START_INFO1_ */
275 * The index of the address search table which associated with
276 * the peer table entry corresponding to this MPDU. Only valid
277 * when first_msdu is set.
280 * Set if the from DS bit is set in the frame control. Only
281 * valid when first_msdu is set.
284 * Set if the to DS bit is set in the frame control. Only
285 * valid when first_msdu is set.
288 * Protected bit from the frame control. Only valid when
292 * Retry bit from the frame control. Only valid when
296 * The MPDU data will contain H information. Primarily used
300 * The sequence number from the 802.11 header. Only valid when
304 * Indicates type of decrypt cipher used (as defined in the
308 * 2: TKIP without MIC
314 * Only valid when first_msdu_is set
317 * Bits [31:0] of the PN number extracted from the IV field
318 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is
320 * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
321 * WEPSeed[1], pn1}. Only pn[47:0] is valid.
322 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
323 * pn0}. Only pn[47:0] is valid.
324 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
325 * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}.
326 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and
327 * pn[47:0] are valid.
328 * Only valid when first_msdu is set.
331 * Bits [47:32] of the PN number. See description for
332 * pn_31_0. The remaining PN fields are in the rx_msdu_end
336 * Use this field to access the pn without worrying about
337 * byte-order and bitmasking/bitshifting.
340 * See definition in RX attention descriptor
343 * Reserved: HW should fill with zero. FW should ignore.
346 * The TID field in the QoS control field
349 #define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff
350 #define RX_MPDU_END_INFO0_RESERVED_0_LSB 0
351 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
352 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16
353 #define RX_MPDU_END_INFO0_OVERFLOW_ERR (1 << 13)
354 #define RX_MPDU_END_INFO0_LAST_MPDU (1 << 14)
355 #define RX_MPDU_END_INFO0_POST_DELIM_ERR (1 << 15)
356 #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR (1 << 28)
357 #define RX_MPDU_END_INFO0_TKIP_MIC_ERR (1 << 29)
358 #define RX_MPDU_END_INFO0_DECRYPT_ERR (1 << 30)
359 #define RX_MPDU_END_INFO0_FCS_ERR (1 << 31)
370 * PCU Receive FIFO does not have enough space to store the
371 * full receive packet. Enough space is reserved in the
372 * receive FIFO for the status is written. This MPDU remaining
373 * packets in the PPDU will be filtered and no Ack response
374 * will be transmitted.
377 * Indicates that this is the last MPDU of a PPDU.
380 * Indicates that a delimiter FCS error occurred after this
381 * MPDU before the next MPDU. Only valid when last_msdu is
385 * Count of the delimiters after this MPDU. This requires the
386 * last MPDU to be held until all the EOF descriptors have been
387 * received. This may be inefficient in the future when
388 * ML-MIMO is used. Only valid when last_mpdu is set.
391 * See definition in RX attention descriptor
394 * See definition in RX attention descriptor
397 * See definition in RX attention descriptor
400 * See definition in RX attention descriptor
403 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff
404 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0
405 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000
406 #define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14
407 #define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000
408 #define RX_MSDU_START_INFO0_RING_MASK_LSB 20
409 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
410 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24
412 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff
413 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0
414 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300
415 #define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8
416 #define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000
417 #define RX_MSDU_START_INFO1_SA_IDX_LSB 16
418 #define RX_MSDU_START_INFO1_IPV4_PROTO (1 << 10)
419 #define RX_MSDU_START_INFO1_IPV6_PROTO (1 << 11)
420 #define RX_MSDU_START_INFO1_TCP_PROTO (1 << 12)
421 #define RX_MSDU_START_INFO1_UDP_PROTO (1 << 13)
422 #define RX_MSDU_START_INFO1_IP_FRAG (1 << 14)
423 #define RX_MSDU_START_INFO1_TCP_ONLY_ACK (1 << 15)
425 /* The decapped header (rx_hdr_status) contains the following:
427 * [padding to 4 bytes]
428 * b) HW crypto parameter
429 * - 0 bytes for no security
431 * - 8 bytes for TKIP, AES
432 * [padding to 4 bytes]
433 * c) A-MSDU subframe header (14 bytes) if appliable
434 * d) LLC/SNAP (RFC1042, 8 bytes)
436 * In case of A-MSDU only first frame in sequence contains (a) and (b). */
437 enum rx_msdu_decap_format {
438 RX_MSDU_DECAP_RAW = 0,
440 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in
441 * htt_rx_desc contains the original decapped 802.11 header. */
442 RX_MSDU_DECAP_NATIVE_WIFI = 1,
444 /* Payload contains an ethernet header (struct ethhdr). */
445 RX_MSDU_DECAP_ETHERNET2_DIX = 2,
447 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes
448 * total), followed by an RFC1042 header (8 bytes). */
449 RX_MSDU_DECAP_8023_SNAP_LLC = 3
452 struct rx_msdu_start {
453 __le32 info0; /* %RX_MSDU_START_INFO0_ */
455 __le32 info1; /* %RX_MSDU_START_INFO1_ */
460 * MSDU length in bytes after decapsulation. This field is
461 * still valid for MPDU frames without A-MSDU. It still
462 * represents MSDU length after decapsulation
465 * Indicates the IP offset in bytes from the start of the
466 * packet after decapsulation. Only valid if ipv4_proto or
470 * Indicates the destination RX rings for this MSDU.
473 * Indicates the offset in bytes to the start of TCP or UDP
474 * header from the start of the IP header after decapsulation.
475 * Only valid if tcp_prot or udp_prot is set. The value 0
476 * indicates that the offset is longer than 127 bytes.
479 * Reserved: HW should fill with zero. FW should ignore.
482 * The flow_id_crc runs CRC32 on the following information:
483 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
485 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
487 * UDP case: sort_port[15:0], dest_port[15:0]
488 * TCP case: sort_port[15:0], dest_port[15:0],
489 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
490 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit
494 * Indicates the MSDU number within a MPDU. This value is
495 * reset to zero at the start of each MPDU. If the number of
496 * MSDU exceeds 255 this number will wrap using modulo 256.
499 * Indicates the format after decapsulation:
500 * 0: RAW: No decapsulation
502 * 2: Ethernet 2 (DIX)
503 * 3: 802.3 (SNAP/LLC)
506 * Set if L2 layer indicates IPv4 protocol.
509 * Set if L2 layer indicates IPv6 protocol.
512 * Set if the ipv4_proto or ipv6_proto are set and the IP
513 * protocol indicates TCP.
516 * Set if the ipv4_proto or ipv6_proto are set and the IP
517 * protocol indicates UDP.
520 * Indicates that either the IP More frag bit is set or IP frag
521 * number is non-zero. If set indicates that this is a
522 * fragmented IP packet.
525 * Set if only the TCP Ack bit is set in the TCP flags and if
526 * the TCP payload is 0.
529 * The offset in the address table which matches the MAC source
533 * Reserved: HW should fill with zero. FW should ignore.
536 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
537 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0
538 #define RX_MSDU_END_INFO0_FIRST_MSDU (1 << 14)
539 #define RX_MSDU_END_INFO0_LAST_MSDU (1 << 15)
540 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR (1 << 30)
541 #define RX_MSDU_END_INFO0_RESERVED_3B (1 << 31)
545 __le16 tcp_hdr_cksum;
547 u8 classification_filter;
554 * This can include the IP header checksum or the pseudo header
555 * checksum used by TCP/UDP checksum.
558 * The value of the computed TCP/UDP checksum. A mode bit
559 * selects whether this checksum is the full checksum or the
560 * partial checksum which does not include the pseudo header.
563 * The key ID octet from the IV. Only valid when first_msdu is
566 *classification_filter
567 * Indicates the number classification filter rule
570 * Extension PN (packet number) which is only used by WAPI.
571 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The
572 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
576 * Extension PN (packet number) which is only used by WAPI.
577 * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and
581 * Extension PN (packet number) which is only used by WAPI.
582 * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14,
585 *reported_mpdu_length
586 * MPDU length before decapsulation. Only valid when
587 * first_msdu is set. This field is taken directly from the
588 * length field of the A-MPDU delimiter or the preamble length
589 * field for non-A-MPDU frames.
592 * Indicates the first MSDU of A-MSDU. If both first_msdu and
593 * last_msdu are set in the MSDU then this is a non-aggregated
594 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall
595 * have both first_mpdu and last_mpdu bits set to 0.
598 * Indicates the last MSDU of the A-MSDU. MPDU end status is
599 * only valid when last_msdu is set.
602 * Reserved: HW should fill with zero. FW should ignore.
605 * Indicates that the first delimiter had a FCS failure. Only
606 * valid when first_mpdu and first_msdu are set.
609 * Reserved: HW should fill with zero. FW should ignore.
612 #define RX_PPDU_START_SIG_RATE_SELECT_OFDM 0
613 #define RX_PPDU_START_SIG_RATE_SELECT_CCK 1
615 #define RX_PPDU_START_SIG_RATE_OFDM_48 0
616 #define RX_PPDU_START_SIG_RATE_OFDM_24 1
617 #define RX_PPDU_START_SIG_RATE_OFDM_12 2
618 #define RX_PPDU_START_SIG_RATE_OFDM_6 3
619 #define RX_PPDU_START_SIG_RATE_OFDM_54 4
620 #define RX_PPDU_START_SIG_RATE_OFDM_36 5
621 #define RX_PPDU_START_SIG_RATE_OFDM_18 6
622 #define RX_PPDU_START_SIG_RATE_OFDM_9 7
624 #define RX_PPDU_START_SIG_RATE_CCK_LP_11 0
625 #define RX_PPDU_START_SIG_RATE_CCK_LP_5_5 1
626 #define RX_PPDU_START_SIG_RATE_CCK_LP_2 2
627 #define RX_PPDU_START_SIG_RATE_CCK_LP_1 3
628 #define RX_PPDU_START_SIG_RATE_CCK_SP_11 4
629 #define RX_PPDU_START_SIG_RATE_CCK_SP_5_5 5
630 #define RX_PPDU_START_SIG_RATE_CCK_SP_2 6
632 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04
633 #define HTT_RX_PPDU_START_PREAMBLE_HT 0x08
634 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09
635 #define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C
636 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
638 #define RX_PPDU_START_INFO0_IS_GREENFIELD (1 << 0)
640 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f
641 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0
642 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0
643 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5
644 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000
645 #define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18
646 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
647 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24
648 #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT (1 << 4)
649 #define RX_PPDU_START_INFO1_L_SIG_PARITY (1 << 17)
651 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
652 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0
654 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
655 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0
656 #define RX_PPDU_START_INFO3_TXBF_H_INFO (1 << 24)
658 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
659 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0
661 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
662 #define RX_PPDU_START_INFO5_SERVICE_LSB 0
664 /* No idea what this flag means. It seems to be always set in rate. */
665 #define RX_PPDU_START_RATE_FLAG BIT(3)
667 enum rx_ppdu_start_rate {
668 RX_PPDU_START_RATE_OFDM_48M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_48M,
669 RX_PPDU_START_RATE_OFDM_24M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_24M,
670 RX_PPDU_START_RATE_OFDM_12M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_12M,
671 RX_PPDU_START_RATE_OFDM_6M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_6M,
672 RX_PPDU_START_RATE_OFDM_54M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_54M,
673 RX_PPDU_START_RATE_OFDM_36M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_36M,
674 RX_PPDU_START_RATE_OFDM_18M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_18M,
675 RX_PPDU_START_RATE_OFDM_9M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_9M,
677 RX_PPDU_START_RATE_CCK_LP_11M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_11M,
678 RX_PPDU_START_RATE_CCK_LP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_5_5M,
679 RX_PPDU_START_RATE_CCK_LP_2M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_2M,
680 RX_PPDU_START_RATE_CCK_LP_1M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_1M,
681 RX_PPDU_START_RATE_CCK_SP_11M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_11M,
682 RX_PPDU_START_RATE_CCK_SP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_5_5M,
683 RX_PPDU_START_RATE_CCK_SP_2M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_2M,
686 struct rx_ppdu_start {
695 u8 info0; /* %RX_PPDU_START_INFO0_ */
696 __le32 info1; /* %RX_PPDU_START_INFO1_ */
697 __le32 info2; /* %RX_PPDU_START_INFO2_ */
698 __le32 info3; /* %RX_PPDU_START_INFO3_ */
699 __le32 info4; /* %RX_PPDU_START_INFO4_ */
700 __le32 info5; /* %RX_PPDU_START_INFO5_ */
705 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
706 * Value of 0x80 indicates invalid.
709 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
710 * Value of 0x80 indicates invalid.
713 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
714 * Value of 0x80 indicates invalid.
717 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
718 * Value of 0x80 indicates invalid.
721 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
722 * Value of 0x80 indicates invalid.
725 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
726 * Value of 0x80 indicates invalid.
729 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
730 * Value of 0x80 indicates invalid.
733 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
734 * Value of 0x80 indicates invalid.
737 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
738 * Value of 0x80 indicates invalid.
741 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth.
742 * Value of 0x80 indicates invalid.
745 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth.
746 * Value of 0x80 indicates invalid.
749 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth.
750 * Value of 0x80 indicates invalid.
753 * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
754 * Value of 0x80 indicates invalid.
757 * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth.
758 * Value of 0x80 indicates invalid.
761 * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth.
762 * Value of 0x80 indicates invalid.
765 * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth.
766 * Value of 0x80 indicates invalid.
769 * The combined RSSI of RX PPDU of all active chains and
770 * bandwidths. Value of 0x80 indicates invalid.
773 * Reserved: HW should fill with 0, FW should ignore.
776 * Do we really support this?
779 * Reserved: HW should fill with 0, FW should ignore.
782 * If l_sig_rate_select is 0:
791 * If l_sig_rate_select is 1:
792 * 0x8: CCK 11 Mbps long preamble
793 * 0x9: CCK 5.5 Mbps long preamble
794 * 0xA: CCK 2 Mbps long preamble
795 * 0xB: CCK 1 Mbps long preamble
796 * 0xC: CCK 11 Mbps short preamble
797 * 0xD: CCK 5.5 Mbps short preamble
798 * 0xE: CCK 2 Mbps short preamble
801 * Legacy signal rate select. If set then l_sig_rate indicates
802 * CCK rates. If clear then l_sig_rate indicates OFDM rates.
805 * Length of legacy frame in octets.
808 * Odd parity over l_sig_rate and l_sig_length
811 * Tail bits for Viterbi decoder
814 * Indicates the type of preamble ahead:
815 * 0x4: Legacy (OFDM/CCK)
820 * 0x80 - 0xFF: Reserved for special baseband data types such
821 * as radar and spectral scan.
824 * If preamble_type == 0x8 or 0x9
825 * HT-SIG (first 24 bits)
826 * If preamble_type == 0xC or 0xD
827 * VHT-SIG A (first 24 bits)
832 * Reserved: HW should fill with 0, FW should ignore.
835 * If preamble_type == 0x8 or 0x9
836 * HT-SIG (last 24 bits)
837 * If preamble_type == 0xC or 0xD
838 * VHT-SIG A (last 24 bits)
843 * Indicates that the packet data carries H information which
844 * is used for TxBF debug.
847 * Reserved: HW should fill with 0, FW should ignore.
850 * WiFi 1.0 and WiFi 2.0 will likely have this field to be all
851 * 0s since the BB does not plan on decoding VHT SIG-B.
854 * Reserved: HW should fill with 0, FW should ignore.
857 * Service field from BB for OFDM, HT and VHT packets. CCK
858 * packets will have service field of 0.
861 * Reserved: HW should fill with 0, FW should ignore.
864 #define RX_PPDU_END_FLAGS_PHY_ERR (1 << 0)
865 #define RX_PPDU_END_FLAGS_RX_LOCATION (1 << 1)
866 #define RX_PPDU_END_FLAGS_TXBF_H_INFO (1 << 2)
868 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff
869 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0
870 #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK (1 << 24)
871 #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL (1 << 25)
873 #define RX_PPDU_END_INFO1_PPDU_DONE (1 << 15)
875 struct rx_ppdu_end_common {
892 __le32 tsf_timestamp;
894 u8 locationing_timestamp;
896 __le16 flags; /* %RX_PPDU_END_FLAGS_ */
897 __le32 info0; /* %RX_PPDU_END_INFO0_ */
900 struct rx_ppdu_end_qca988x {
902 __le16 info1; /* %RX_PPDU_END_INFO1_ */
905 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff
906 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0
907 #define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000
908 #define RX_PPDU_END_RTT_UNUSED_LSB 24
909 #define RX_PPDU_END_RTT_NORMAL_MODE BIT(31)
911 struct rx_ppdu_end_qca6174 {
912 __le32 rtt; /* %RX_PPDU_END_RTT_ */
914 __le16 info1; /* %RX_PPDU_END_INFO1_ */
918 struct rx_ppdu_end_common common;
920 struct rx_ppdu_end_qca988x qca988x;
921 struct rx_ppdu_end_qca6174 qca6174;
927 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3.
930 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3.
933 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3.
936 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3.
939 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3.
942 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3.
945 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3.
948 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3.
951 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3.
954 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3.
957 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3.
960 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3.
963 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3.
966 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3.
969 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3.
972 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3.
975 * Receive TSF timestamp sampled on the rising edge of
976 * rx_clear. For PHY errors this may be the current TSF when
977 * phy_error is asserted if the rx_clear does not assert before
978 * the end of the PHY error.
981 * WLAN/BT timestamp is a 1 usec resolution timestamp which
982 * does not get updated based on receive beacon like TSF. The
983 * same rules for capturing tsf_timestamp are used to capture
986 * locationing_timestamp
987 * Timestamp used for locationing. This timestamp is used to
988 * indicate fractions of usec. For example if the MAC clock is
989 * running at 80 MHz, the timestamp will increment every 12.5
990 * nsec. The value starts at 0 and increments to 79 and
991 * returns to 0 and repeats. This information is valid for
992 * every PPDU. This information can be used in conjunction
993 * with wb_timestamp to capture large delta times.
996 * See the 1.10.8.1.2 for the list of the PHY error codes.
999 * Indicates a PHY error was detected for this PPDU.
1002 * Indicates that location information was requested.
1005 * Indicates that the packet data carries H information which
1006 * is used for TxBF debug.
1009 * Reserved: HW should fill with 0, FW should ignore.
1012 * Receive antenna value
1015 * Indicates that a HT or VHT Ack/BA frame was transmitted in
1016 * response to this receive packet.
1018 * bb_captured_channel
1019 * Indicates that the BB has captured a channel dump. FW can
1020 * then read the channel dump memory. This may indicate that
1021 * the channel was captured either based on PCU setting the
1022 * capture_channel bit BB descriptor or FW setting the
1023 * capture_channel mode bit.
1026 * Reserved: HW should fill with 0, FW should ignore.
1029 * Indicates the number of bytes of baseband information for
1030 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
1031 * which indicates that this is not a normal PPDU but rather
1032 * contains baseband debug information.
1035 * Reserved: HW should fill with 0, FW should ignore.
1038 * PPDU end status is only valid when ppdu_done bit is set.
1039 * Every time HW sets this bit in memory FW/SW must clear this
1040 * bit in memory. FW will initialize all the ppdu_done dword
1044 #define FW_RX_DESC_INFO0_DISCARD (1 << 0)
1045 #define FW_RX_DESC_INFO0_FORWARD (1 << 1)
1046 #define FW_RX_DESC_INFO0_INSPECT (1 << 5)
1047 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0
1048 #define FW_RX_DESC_INFO0_EXT_LSB 6
1050 struct fw_rx_desc_base {
1054 #endif /* _RX_DESC_H_ */