2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
28 #include "targaddrs.h"
37 enum ath10k_pci_reset_mode {
38 ATH10K_PCI_RESET_AUTO = 0,
39 ATH10K_PCI_RESET_WARM_ONLY = 1,
42 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
43 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
45 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
46 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
48 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
49 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
51 /* how long wait to wait for target to initialise, in ms */
52 #define ATH10K_PCI_TARGET_WAIT 3000
53 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
55 /* Maximum number of bytes that can be handled atomically by
56 * diag read and write.
58 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000
60 #define QCA99X0_PCIE_BAR0_START_REG 0x81030
61 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c
62 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010
64 static const struct pci_device_id ath10k_pci_id_table[] = {
65 /* PCI-E QCA988X V2 (Ubiquiti branded) */
66 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) },
68 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
69 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
70 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
71 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
72 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
73 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
74 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
75 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
79 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
80 /* QCA988X pre 2.0 chips are not supported because they need some nasty
81 * hacks. ath10k doesn't have them and these devices crash horribly
84 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV },
85 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
88 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
89 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
90 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
91 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
94 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
95 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
96 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
97 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
99 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
101 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
103 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
105 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
106 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
108 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
111 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
112 static int ath10k_pci_cold_reset(struct ath10k *ar);
113 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
114 static int ath10k_pci_init_irq(struct ath10k *ar);
115 static int ath10k_pci_deinit_irq(struct ath10k *ar);
116 static int ath10k_pci_request_irq(struct ath10k *ar);
117 static void ath10k_pci_free_irq(struct ath10k *ar);
118 static int ath10k_pci_bmi_wait(struct ath10k *ar,
119 struct ath10k_ce_pipe *tx_pipe,
120 struct ath10k_ce_pipe *rx_pipe,
121 struct bmi_xfer *xfer);
122 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
123 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
124 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
125 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
126 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
127 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
128 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
130 static struct ce_attr host_ce_config_wlan[] = {
131 /* CE0: host->target HTC control and raw streams */
133 .flags = CE_ATTR_FLAGS,
137 .send_cb = ath10k_pci_htc_tx_cb,
140 /* CE1: target->host HTT + HTC control */
142 .flags = CE_ATTR_FLAGS,
145 .dest_nentries = 512,
146 .recv_cb = ath10k_pci_htt_htc_rx_cb,
149 /* CE2: target->host WMI */
151 .flags = CE_ATTR_FLAGS,
154 .dest_nentries = 128,
155 .recv_cb = ath10k_pci_htc_rx_cb,
158 /* CE3: host->target WMI */
160 .flags = CE_ATTR_FLAGS,
164 .send_cb = ath10k_pci_htc_tx_cb,
167 /* CE4: host->target HTT */
169 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
170 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
173 .send_cb = ath10k_pci_htt_tx_cb,
176 /* CE5: target->host HTT (HIF->HTT) */
178 .flags = CE_ATTR_FLAGS,
181 .dest_nentries = 512,
182 .recv_cb = ath10k_pci_htt_rx_cb,
185 /* CE6: target autonomous hif_memcpy */
187 .flags = CE_ATTR_FLAGS,
193 /* CE7: ce_diag, the Diagnostic Window */
195 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL,
197 .src_sz_max = DIAG_TRANSFER_LIMIT,
201 /* CE8: target->host pktlog */
203 .flags = CE_ATTR_FLAGS,
206 .dest_nentries = 128,
207 .recv_cb = ath10k_pci_pktlog_rx_cb,
210 /* CE9 target autonomous qcache memcpy */
212 .flags = CE_ATTR_FLAGS,
218 /* CE10: target autonomous hif memcpy */
220 .flags = CE_ATTR_FLAGS,
226 /* CE11: target autonomous hif memcpy */
228 .flags = CE_ATTR_FLAGS,
235 /* Target firmware's Copy Engine configuration. */
236 static struct ce_pipe_config target_ce_config_wlan[] = {
237 /* CE0: host->target HTC control and raw streams */
239 .pipenum = __cpu_to_le32(0),
240 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
241 .nentries = __cpu_to_le32(32),
242 .nbytes_max = __cpu_to_le32(256),
243 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
244 .reserved = __cpu_to_le32(0),
247 /* CE1: target->host HTT + HTC control */
249 .pipenum = __cpu_to_le32(1),
250 .pipedir = __cpu_to_le32(PIPEDIR_IN),
251 .nentries = __cpu_to_le32(32),
252 .nbytes_max = __cpu_to_le32(2048),
253 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
254 .reserved = __cpu_to_le32(0),
257 /* CE2: target->host WMI */
259 .pipenum = __cpu_to_le32(2),
260 .pipedir = __cpu_to_le32(PIPEDIR_IN),
261 .nentries = __cpu_to_le32(64),
262 .nbytes_max = __cpu_to_le32(2048),
263 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
264 .reserved = __cpu_to_le32(0),
267 /* CE3: host->target WMI */
269 .pipenum = __cpu_to_le32(3),
270 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
271 .nentries = __cpu_to_le32(32),
272 .nbytes_max = __cpu_to_le32(2048),
273 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
274 .reserved = __cpu_to_le32(0),
277 /* CE4: host->target HTT */
279 .pipenum = __cpu_to_le32(4),
280 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
281 .nentries = __cpu_to_le32(256),
282 .nbytes_max = __cpu_to_le32(256),
283 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
284 .reserved = __cpu_to_le32(0),
287 /* NB: 50% of src nentries, since tx has 2 frags */
289 /* CE5: target->host HTT (HIF->HTT) */
291 .pipenum = __cpu_to_le32(5),
292 .pipedir = __cpu_to_le32(PIPEDIR_IN),
293 .nentries = __cpu_to_le32(32),
294 .nbytes_max = __cpu_to_le32(512),
295 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
296 .reserved = __cpu_to_le32(0),
299 /* CE6: Reserved for target autonomous hif_memcpy */
301 .pipenum = __cpu_to_le32(6),
302 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
303 .nentries = __cpu_to_le32(32),
304 .nbytes_max = __cpu_to_le32(4096),
305 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
306 .reserved = __cpu_to_le32(0),
309 /* CE7 used only by Host */
311 .pipenum = __cpu_to_le32(7),
312 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
313 .nentries = __cpu_to_le32(0),
314 .nbytes_max = __cpu_to_le32(0),
315 .flags = __cpu_to_le32(0),
316 .reserved = __cpu_to_le32(0),
319 /* CE8 target->host packtlog */
321 .pipenum = __cpu_to_le32(8),
322 .pipedir = __cpu_to_le32(PIPEDIR_IN),
323 .nentries = __cpu_to_le32(64),
324 .nbytes_max = __cpu_to_le32(2048),
325 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
326 .reserved = __cpu_to_le32(0),
329 /* CE9 target autonomous qcache memcpy */
331 .pipenum = __cpu_to_le32(9),
332 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
333 .nentries = __cpu_to_le32(32),
334 .nbytes_max = __cpu_to_le32(2048),
335 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
336 .reserved = __cpu_to_le32(0),
339 /* It not necessary to send target wlan configuration for CE10 & CE11
340 * as these CEs are not actively used in target.
345 * Map from service/endpoint to Copy Engine.
346 * This table is derived from the CE_PCI TABLE, above.
347 * It is passed to the Target at startup for use by firmware.
349 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
351 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
352 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
356 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
357 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
362 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
367 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
372 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
377 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
382 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
387 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
391 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
392 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
396 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
397 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
401 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
402 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
406 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
407 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
411 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
412 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
416 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
417 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
421 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
422 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
426 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
427 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
431 /* (Additions here) */
440 static bool ath10k_pci_is_awake(struct ath10k *ar)
442 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
443 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
446 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
449 static void __ath10k_pci_wake(struct ath10k *ar)
451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
453 lockdep_assert_held(&ar_pci->ps_lock);
455 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
456 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
458 iowrite32(PCIE_SOC_WAKE_V_MASK,
459 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
460 PCIE_SOC_WAKE_ADDRESS);
463 static void __ath10k_pci_sleep(struct ath10k *ar)
465 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
467 lockdep_assert_held(&ar_pci->ps_lock);
469 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
470 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
472 iowrite32(PCIE_SOC_WAKE_RESET,
473 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
474 PCIE_SOC_WAKE_ADDRESS);
475 ar_pci->ps_awake = false;
478 static int ath10k_pci_wake_wait(struct ath10k *ar)
483 while (tot_delay < PCIE_WAKE_TIMEOUT) {
484 if (ath10k_pci_is_awake(ar)) {
485 if (tot_delay > PCIE_WAKE_LATE_US)
486 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
492 tot_delay += curr_delay;
501 static int ath10k_pci_force_wake(struct ath10k *ar)
503 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
510 spin_lock_irqsave(&ar_pci->ps_lock, flags);
512 if (!ar_pci->ps_awake) {
513 iowrite32(PCIE_SOC_WAKE_V_MASK,
514 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
515 PCIE_SOC_WAKE_ADDRESS);
517 ret = ath10k_pci_wake_wait(ar);
519 ar_pci->ps_awake = true;
522 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
527 static void ath10k_pci_force_sleep(struct ath10k *ar)
529 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
532 spin_lock_irqsave(&ar_pci->ps_lock, flags);
534 iowrite32(PCIE_SOC_WAKE_RESET,
535 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
536 PCIE_SOC_WAKE_ADDRESS);
537 ar_pci->ps_awake = false;
539 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
542 static int ath10k_pci_wake(struct ath10k *ar)
544 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
548 if (ar_pci->pci_ps == 0)
551 spin_lock_irqsave(&ar_pci->ps_lock, flags);
553 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
554 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
556 /* This function can be called very frequently. To avoid excessive
557 * CPU stalls for MMIO reads use a cache var to hold the device state.
559 if (!ar_pci->ps_awake) {
560 __ath10k_pci_wake(ar);
562 ret = ath10k_pci_wake_wait(ar);
564 ar_pci->ps_awake = true;
568 ar_pci->ps_wake_refcount++;
569 WARN_ON(ar_pci->ps_wake_refcount == 0);
572 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
577 static void ath10k_pci_sleep(struct ath10k *ar)
579 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
582 if (ar_pci->pci_ps == 0)
585 spin_lock_irqsave(&ar_pci->ps_lock, flags);
587 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
588 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
590 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
593 ar_pci->ps_wake_refcount--;
595 mod_timer(&ar_pci->ps_timer, jiffies +
596 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
599 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
602 static void ath10k_pci_ps_timer(struct timer_list *t)
604 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer);
605 struct ath10k *ar = ar_pci->ar;
608 spin_lock_irqsave(&ar_pci->ps_lock, flags);
610 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
611 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
613 if (ar_pci->ps_wake_refcount > 0)
616 __ath10k_pci_sleep(ar);
619 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
622 static void ath10k_pci_sleep_sync(struct ath10k *ar)
624 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
627 if (ar_pci->pci_ps == 0) {
628 ath10k_pci_force_sleep(ar);
632 del_timer_sync(&ar_pci->ps_timer);
634 spin_lock_irqsave(&ar_pci->ps_lock, flags);
635 WARN_ON(ar_pci->ps_wake_refcount > 0);
636 __ath10k_pci_sleep(ar);
637 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
640 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
642 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
645 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
646 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
647 offset, offset + sizeof(value), ar_pci->mem_len);
651 ret = ath10k_pci_wake(ar);
653 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
658 iowrite32(value, ar_pci->mem + offset);
659 ath10k_pci_sleep(ar);
662 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
664 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
668 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
669 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
670 offset, offset + sizeof(val), ar_pci->mem_len);
674 ret = ath10k_pci_wake(ar);
676 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
681 val = ioread32(ar_pci->mem + offset);
682 ath10k_pci_sleep(ar);
687 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
689 struct ath10k_ce *ce = ath10k_ce_priv(ar);
691 ce->bus_ops->write32(ar, offset, value);
694 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
696 struct ath10k_ce *ce = ath10k_ce_priv(ar);
698 return ce->bus_ops->read32(ar, offset);
701 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
703 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
706 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
708 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
711 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
713 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
716 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
718 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
721 bool ath10k_pci_irq_pending(struct ath10k *ar)
725 /* Check if the shared legacy irq is for us */
726 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
727 PCIE_INTR_CAUSE_ADDRESS);
728 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
734 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
736 /* IMPORTANT: INTR_CLR register has to be set after
737 * INTR_ENABLE is set to 0, otherwise interrupt can not be
740 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
742 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
743 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
745 /* IMPORTANT: this extra read transaction is required to
746 * flush the posted write buffer.
748 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
749 PCIE_INTR_ENABLE_ADDRESS);
752 void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
754 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
755 PCIE_INTR_ENABLE_ADDRESS,
756 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
758 /* IMPORTANT: this extra read transaction is required to
759 * flush the posted write buffer.
761 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
762 PCIE_INTR_ENABLE_ADDRESS);
765 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
767 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
769 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
775 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
777 struct ath10k *ar = pipe->hif_ce_state;
778 struct ath10k_ce *ce = ath10k_ce_priv(ar);
779 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
784 skb = dev_alloc_skb(pipe->buf_sz);
788 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
790 paddr = dma_map_single(ar->dev, skb->data,
791 skb->len + skb_tailroom(skb),
793 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
794 ath10k_warn(ar, "failed to dma map pci rx buf\n");
795 dev_kfree_skb_any(skb);
799 ATH10K_SKB_RXCB(skb)->paddr = paddr;
801 spin_lock_bh(&ce->ce_lock);
802 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
803 spin_unlock_bh(&ce->ce_lock);
805 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
807 dev_kfree_skb_any(skb);
814 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
816 struct ath10k *ar = pipe->hif_ce_state;
817 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
818 struct ath10k_ce *ce = ath10k_ce_priv(ar);
819 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
822 if (pipe->buf_sz == 0)
825 if (!ce_pipe->dest_ring)
828 spin_lock_bh(&ce->ce_lock);
829 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
830 spin_unlock_bh(&ce->ce_lock);
833 ret = __ath10k_pci_rx_post_buf(pipe);
837 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
838 mod_timer(&ar_pci->rx_post_retry, jiffies +
839 ATH10K_PCI_RX_POST_RETRY_MS);
846 void ath10k_pci_rx_post(struct ath10k *ar)
848 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
851 for (i = 0; i < CE_COUNT; i++)
852 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
855 void ath10k_pci_rx_replenish_retry(struct timer_list *t)
857 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry);
858 struct ath10k *ar = ar_pci->ar;
860 ath10k_pci_rx_post(ar);
863 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
865 u32 val = 0, region = addr & 0xfffff;
867 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
869 val |= 0x100000 | region;
873 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr.
874 * Support to access target space below 1M for qca6174 and qca9377.
875 * If target space is below 1M, the bit[20] of converted CE addr is 0.
876 * Otherwise bit[20] of converted CE addr is 1.
878 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
880 u32 val = 0, region = addr & 0xfffff;
882 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
884 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region;
888 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
890 u32 val = 0, region = addr & 0xfffff;
892 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
893 val |= 0x100000 | region;
897 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
899 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
901 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
904 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
908 * Diagnostic read/write access is provided for startup/config/debug usage.
909 * Caller must guarantee proper alignment, when applicable, and single user
912 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
915 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
916 struct ath10k_ce *ce = ath10k_ce_priv(ar);
919 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
920 struct ath10k_ce_pipe *ce_diag;
921 /* Host buffer address in CE space */
923 dma_addr_t ce_data_base = 0;
924 void *data_buf = NULL;
927 spin_lock_bh(&ce->ce_lock);
929 ce_diag = ar_pci->ce_diag;
932 * Allocate a temporary bounce buffer to hold caller's data
933 * to be DMA'ed from Target. This guarantees
934 * 1) 4-byte alignment
935 * 2) Buffer in DMA-able space
937 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
939 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, alloc_nbytes,
948 /* The address supplied by the caller is in the
949 * Target CPU virtual address space.
951 * In order to use this address with the diagnostic CE,
952 * convert it from Target CPU virtual address space
953 * to CE address space
955 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
957 remaining_bytes = nbytes;
958 ce_data = ce_data_base;
959 while (remaining_bytes) {
960 nbytes = min_t(unsigned int, remaining_bytes,
961 DIAG_TRANSFER_LIMIT);
963 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &ce_data, ce_data);
967 /* Request CE to send from Target(!) address to Host buffer */
968 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
974 while (ath10k_ce_completed_send_next_nolock(ce_diag,
976 udelay(DIAG_ACCESS_CE_WAIT_US);
977 i += DIAG_ACCESS_CE_WAIT_US;
979 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
986 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
990 udelay(DIAG_ACCESS_CE_WAIT_US);
991 i += DIAG_ACCESS_CE_WAIT_US;
993 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
999 if (nbytes != completed_nbytes) {
1004 if (*buf != ce_data) {
1009 remaining_bytes -= nbytes;
1010 memcpy(data, data_buf, nbytes);
1019 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1022 spin_unlock_bh(&ce->ce_lock);
1027 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1032 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1033 *value = __le32_to_cpu(val);
1038 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1041 u32 host_addr, addr;
1044 host_addr = host_interest_item_address(src);
1046 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1048 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1053 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1055 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1063 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1064 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1066 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1067 const void *data, int nbytes)
1069 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1070 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1073 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
1074 struct ath10k_ce_pipe *ce_diag;
1075 void *data_buf = NULL;
1076 dma_addr_t ce_data_base = 0;
1079 spin_lock_bh(&ce->ce_lock);
1081 ce_diag = ar_pci->ce_diag;
1084 * Allocate a temporary bounce buffer to hold caller's data
1085 * to be DMA'ed to Target. This guarantees
1086 * 1) 4-byte alignment
1087 * 2) Buffer in DMA-able space
1089 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
1091 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1101 * The address supplied by the caller is in the
1102 * Target CPU virtual address space.
1104 * In order to use this address with the diagnostic CE,
1106 * Target CPU virtual address space
1110 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1112 remaining_bytes = nbytes;
1113 while (remaining_bytes) {
1114 /* FIXME: check cast */
1115 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1117 /* Copy caller's data to allocated DMA buf */
1118 memcpy(data_buf, data, nbytes);
1120 /* Set up to receive directly into Target(!) address */
1121 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &address, address);
1126 * Request CE to send caller-supplied data that
1127 * was copied to bounce buffer to Target(!) address.
1129 ret = ath10k_ce_send_nolock(ce_diag, NULL, ce_data_base,
1135 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1137 udelay(DIAG_ACCESS_CE_WAIT_US);
1138 i += DIAG_ACCESS_CE_WAIT_US;
1140 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1147 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
1151 udelay(DIAG_ACCESS_CE_WAIT_US);
1152 i += DIAG_ACCESS_CE_WAIT_US;
1154 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1160 if (nbytes != completed_nbytes) {
1165 if (*buf != address) {
1170 remaining_bytes -= nbytes;
1177 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1182 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1185 spin_unlock_bh(&ce->ce_lock);
1190 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1192 __le32 val = __cpu_to_le32(value);
1194 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1197 /* Called by lower (CE) layer when a send to Target completes. */
1198 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1200 struct ath10k *ar = ce_state->ar;
1201 struct sk_buff_head list;
1202 struct sk_buff *skb;
1204 __skb_queue_head_init(&list);
1205 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1206 /* no need to call tx completion for NULL pointers */
1210 __skb_queue_tail(&list, skb);
1213 while ((skb = __skb_dequeue(&list)))
1214 ath10k_htc_tx_completion_handler(ar, skb);
1217 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1218 void (*callback)(struct ath10k *ar,
1219 struct sk_buff *skb))
1221 struct ath10k *ar = ce_state->ar;
1222 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1223 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1224 struct sk_buff *skb;
1225 struct sk_buff_head list;
1226 void *transfer_context;
1227 unsigned int nbytes, max_nbytes;
1229 __skb_queue_head_init(&list);
1230 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1232 skb = transfer_context;
1233 max_nbytes = skb->len + skb_tailroom(skb);
1234 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1235 max_nbytes, DMA_FROM_DEVICE);
1237 if (unlikely(max_nbytes < nbytes)) {
1238 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1239 nbytes, max_nbytes);
1240 dev_kfree_skb_any(skb);
1244 skb_put(skb, nbytes);
1245 __skb_queue_tail(&list, skb);
1248 while ((skb = __skb_dequeue(&list))) {
1249 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1250 ce_state->id, skb->len);
1251 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1252 skb->data, skb->len);
1257 ath10k_pci_rx_post_pipe(pipe_info);
1260 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1261 void (*callback)(struct ath10k *ar,
1262 struct sk_buff *skb))
1264 struct ath10k *ar = ce_state->ar;
1265 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1266 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1267 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1268 struct sk_buff *skb;
1269 struct sk_buff_head list;
1270 void *transfer_context;
1271 unsigned int nbytes, max_nbytes, nentries;
1274 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1275 * is processed other than init and deinit. Before releasing CE5
1276 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1278 __skb_queue_head_init(&list);
1279 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1281 skb = transfer_context;
1282 max_nbytes = skb->len + skb_tailroom(skb);
1284 if (unlikely(max_nbytes < nbytes)) {
1285 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1286 nbytes, max_nbytes);
1290 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1291 max_nbytes, DMA_FROM_DEVICE);
1292 skb_put(skb, nbytes);
1293 __skb_queue_tail(&list, skb);
1296 nentries = skb_queue_len(&list);
1297 while ((skb = __skb_dequeue(&list))) {
1298 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1299 ce_state->id, skb->len);
1300 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1301 skb->data, skb->len);
1303 orig_len = skb->len;
1305 skb_push(skb, orig_len - skb->len);
1306 skb_reset_tail_pointer(skb);
1309 /*let device gain the buffer again*/
1310 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1311 skb->len + skb_tailroom(skb),
1314 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1317 /* Called by lower (CE) layer when data is received from the Target. */
1318 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1320 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1323 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1325 /* CE4 polling needs to be done whenever CE pipe which transports
1326 * HTT Rx (target->host) is processed.
1328 ath10k_ce_per_engine_service(ce_state->ar, 4);
1330 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1333 /* Called by lower (CE) layer when data is received from the Target.
1334 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1336 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1338 ath10k_pci_process_rx_cb(ce_state,
1339 ath10k_htt_rx_pktlog_completion_handler);
1342 /* Called by lower (CE) layer when a send to HTT Target completes. */
1343 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1345 struct ath10k *ar = ce_state->ar;
1346 struct sk_buff *skb;
1348 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1349 /* no need to call tx completion for NULL pointers */
1353 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1354 skb->len, DMA_TO_DEVICE);
1355 ath10k_htt_hif_tx_complete(ar, skb);
1359 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1361 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1362 ath10k_htt_t2h_msg_handler(ar, skb);
1365 /* Called by lower (CE) layer when HTT data is received from the Target. */
1366 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1368 /* CE4 polling needs to be done whenever CE pipe which transports
1369 * HTT Rx (target->host) is processed.
1371 ath10k_ce_per_engine_service(ce_state->ar, 4);
1373 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1376 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1377 struct ath10k_hif_sg_item *items, int n_items)
1379 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1380 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1381 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1382 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1383 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1384 unsigned int nentries_mask;
1385 unsigned int sw_index;
1386 unsigned int write_index;
1389 spin_lock_bh(&ce->ce_lock);
1391 nentries_mask = src_ring->nentries_mask;
1392 sw_index = src_ring->sw_index;
1393 write_index = src_ring->write_index;
1395 if (unlikely(CE_RING_DELTA(nentries_mask,
1396 write_index, sw_index - 1) < n_items)) {
1401 for (i = 0; i < n_items - 1; i++) {
1402 ath10k_dbg(ar, ATH10K_DBG_PCI,
1403 "pci tx item %d paddr %pad len %d n_items %d\n",
1404 i, &items[i].paddr, items[i].len, n_items);
1405 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1406 items[i].vaddr, items[i].len);
1408 err = ath10k_ce_send_nolock(ce_pipe,
1409 items[i].transfer_context,
1412 items[i].transfer_id,
1413 CE_SEND_FLAG_GATHER);
1418 /* `i` is equal to `n_items -1` after for() */
1420 ath10k_dbg(ar, ATH10K_DBG_PCI,
1421 "pci tx item %d paddr %pad len %d n_items %d\n",
1422 i, &items[i].paddr, items[i].len, n_items);
1423 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1424 items[i].vaddr, items[i].len);
1426 err = ath10k_ce_send_nolock(ce_pipe,
1427 items[i].transfer_context,
1430 items[i].transfer_id,
1435 spin_unlock_bh(&ce->ce_lock);
1440 __ath10k_ce_send_revert(ce_pipe);
1442 spin_unlock_bh(&ce->ce_lock);
1446 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1449 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1452 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1454 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1456 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1458 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1461 static void ath10k_pci_dump_registers(struct ath10k *ar,
1462 struct ath10k_fw_crash_data *crash_data)
1464 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1467 lockdep_assert_held(&ar->data_lock);
1469 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1471 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1473 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1477 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1479 ath10k_err(ar, "firmware register dump:\n");
1480 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1481 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1483 __le32_to_cpu(reg_dump_values[i]),
1484 __le32_to_cpu(reg_dump_values[i + 1]),
1485 __le32_to_cpu(reg_dump_values[i + 2]),
1486 __le32_to_cpu(reg_dump_values[i + 3]));
1491 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1492 crash_data->registers[i] = reg_dump_values[i];
1495 static int ath10k_pci_dump_memory_section(struct ath10k *ar,
1496 const struct ath10k_mem_region *mem_region,
1497 u8 *buf, size_t buf_len)
1499 const struct ath10k_mem_section *cur_section, *next_section;
1500 unsigned int count, section_size, skip_size;
1503 if (!mem_region || !buf)
1506 cur_section = &mem_region->section_table.sections[0];
1508 if (mem_region->start > cur_section->start) {
1509 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
1510 mem_region->start, cur_section->start);
1514 skip_size = cur_section->start - mem_region->start;
1516 /* fill the gap between the first register section and register
1519 for (i = 0; i < skip_size; i++) {
1520 *buf = ATH10K_MAGIC_NOT_COPIED;
1526 for (i = 0; cur_section != NULL; i++) {
1527 section_size = cur_section->end - cur_section->start;
1529 if (section_size <= 0) {
1530 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
1536 if ((i + 1) == mem_region->section_table.size) {
1538 next_section = NULL;
1541 next_section = cur_section + 1;
1543 if (cur_section->end > next_section->start) {
1544 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
1545 next_section->start,
1550 skip_size = next_section->start - cur_section->end;
1553 if (buf_len < (skip_size + section_size)) {
1554 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len);
1558 buf_len -= skip_size + section_size;
1560 /* read section to dest memory */
1561 ret = ath10k_pci_diag_read_mem(ar, cur_section->start,
1564 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
1565 cur_section->start, ret);
1569 buf += section_size;
1570 count += section_size;
1572 /* fill in the gap between this section and the next */
1573 for (j = 0; j < skip_size; j++) {
1574 *buf = ATH10K_MAGIC_NOT_COPIED;
1581 /* this was the last section */
1584 cur_section = next_section;
1590 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config)
1594 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1595 FW_RAM_CONFIG_ADDRESS, config);
1597 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1598 FW_RAM_CONFIG_ADDRESS);
1599 if (val != config) {
1600 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n",
1608 /* if an error happened returns < 0, otherwise the length */
1609 static int ath10k_pci_dump_memory_sram(struct ath10k *ar,
1610 const struct ath10k_mem_region *region,
1613 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1616 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG);
1617 base_addr += region->start;
1619 for (i = 0; i < region->len; i += 4) {
1620 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG);
1621 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG);
1627 /* if an error happened returns < 0, otherwise the length */
1628 static int ath10k_pci_dump_memory_reg(struct ath10k *ar,
1629 const struct ath10k_mem_region *region,
1632 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1635 for (i = 0; i < region->len; i += 4)
1636 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i);
1641 /* if an error happened returns < 0, otherwise the length */
1642 static int ath10k_pci_dump_memory_generic(struct ath10k *ar,
1643 const struct ath10k_mem_region *current_region,
1648 if (current_region->section_table.size > 0)
1649 /* Copy each section individually. */
1650 return ath10k_pci_dump_memory_section(ar,
1653 current_region->len);
1655 /* No individiual memory sections defined so we can
1656 * copy the entire memory region.
1658 ret = ath10k_pci_diag_read_mem(ar,
1659 current_region->start,
1661 current_region->len);
1663 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
1664 current_region->name, ret);
1668 return current_region->len;
1671 static void ath10k_pci_dump_memory(struct ath10k *ar,
1672 struct ath10k_fw_crash_data *crash_data)
1674 const struct ath10k_hw_mem_layout *mem_layout;
1675 const struct ath10k_mem_region *current_region;
1676 struct ath10k_dump_ram_data_hdr *hdr;
1682 lockdep_assert_held(&ar->data_lock);
1687 mem_layout = ath10k_coredump_get_mem_layout(ar);
1691 current_region = &mem_layout->region_table.regions[0];
1693 buf = crash_data->ramdump_buf;
1694 buf_len = crash_data->ramdump_buf_len;
1696 memset(buf, 0, buf_len);
1698 for (i = 0; i < mem_layout->region_table.size; i++) {
1701 if (current_region->len > buf_len) {
1702 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n",
1703 current_region->name,
1704 current_region->len,
1709 /* To get IRAM dump, the host driver needs to switch target
1710 * ram config from DRAM to IRAM.
1712 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 ||
1713 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) {
1714 shift = current_region->start >> 20;
1716 ret = ath10k_pci_set_ram_config(ar, shift);
1718 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n",
1719 current_region->name, ret);
1724 /* Reserve space for the header. */
1726 buf += sizeof(*hdr);
1727 buf_len -= sizeof(*hdr);
1729 switch (current_region->type) {
1730 case ATH10K_MEM_REGION_TYPE_IOSRAM:
1731 count = ath10k_pci_dump_memory_sram(ar, current_region, buf);
1733 case ATH10K_MEM_REGION_TYPE_IOREG:
1734 count = ath10k_pci_dump_memory_reg(ar, current_region, buf);
1737 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf);
1745 hdr->region_type = cpu_to_le32(current_region->type);
1746 hdr->start = cpu_to_le32(current_region->start);
1747 hdr->length = cpu_to_le32(count);
1750 /* Note: the header remains, just with zero length. */
1760 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1762 struct ath10k_fw_crash_data *crash_data;
1763 char guid[UUID_STRING_LEN + 1];
1765 spin_lock_bh(&ar->data_lock);
1767 ar->stats.fw_crash_counter++;
1769 crash_data = ath10k_coredump_new(ar);
1772 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1774 scnprintf(guid, sizeof(guid), "n/a");
1776 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1777 ath10k_print_driver_info(ar);
1778 ath10k_pci_dump_registers(ar, crash_data);
1779 ath10k_ce_dump_registers(ar, crash_data);
1780 ath10k_pci_dump_memory(ar, crash_data);
1782 spin_unlock_bh(&ar->data_lock);
1784 queue_work(ar->workqueue, &ar->restart_work);
1787 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1790 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1795 * Decide whether to actually poll for completions, or just
1796 * wait for a later chance.
1797 * If there seem to be plenty of resources left, then just wait
1798 * since checking involves reading a CE register, which is a
1799 * relatively expensive operation.
1801 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1804 * If at least 50% of the total resources are still available,
1805 * don't bother checking again yet.
1807 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1810 ath10k_ce_per_engine_service(ar, pipe);
1813 static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1815 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1817 del_timer_sync(&ar_pci->rx_post_retry);
1820 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1821 u8 *ul_pipe, u8 *dl_pipe)
1823 const struct service_to_pipe *entry;
1824 bool ul_set = false, dl_set = false;
1827 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1829 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1830 entry = &target_service_to_ce_map_wlan[i];
1832 if (__le32_to_cpu(entry->service_id) != service_id)
1835 switch (__le32_to_cpu(entry->pipedir)) {
1840 *dl_pipe = __le32_to_cpu(entry->pipenum);
1845 *ul_pipe = __le32_to_cpu(entry->pipenum);
1851 *dl_pipe = __le32_to_cpu(entry->pipenum);
1852 *ul_pipe = __le32_to_cpu(entry->pipenum);
1859 if (!ul_set || !dl_set)
1865 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1866 u8 *ul_pipe, u8 *dl_pipe)
1868 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1870 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1871 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1875 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1879 switch (ar->hw_rev) {
1880 case ATH10K_HW_QCA988X:
1881 case ATH10K_HW_QCA9887:
1882 case ATH10K_HW_QCA6174:
1883 case ATH10K_HW_QCA9377:
1884 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1886 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1887 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1888 CORE_CTRL_ADDRESS, val);
1890 case ATH10K_HW_QCA99X0:
1891 case ATH10K_HW_QCA9984:
1892 case ATH10K_HW_QCA9888:
1893 case ATH10K_HW_QCA4019:
1894 /* TODO: Find appropriate register configuration for QCA99X0
1898 case ATH10K_HW_WCN3990:
1903 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1907 switch (ar->hw_rev) {
1908 case ATH10K_HW_QCA988X:
1909 case ATH10K_HW_QCA9887:
1910 case ATH10K_HW_QCA6174:
1911 case ATH10K_HW_QCA9377:
1912 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1914 val |= CORE_CTRL_PCIE_REG_31_MASK;
1915 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1916 CORE_CTRL_ADDRESS, val);
1918 case ATH10K_HW_QCA99X0:
1919 case ATH10K_HW_QCA9984:
1920 case ATH10K_HW_QCA9888:
1921 case ATH10K_HW_QCA4019:
1922 /* TODO: Find appropriate register configuration for QCA99X0
1923 * to unmask irq/MSI.
1926 case ATH10K_HW_WCN3990:
1931 static void ath10k_pci_irq_disable(struct ath10k *ar)
1933 ath10k_ce_disable_interrupts(ar);
1934 ath10k_pci_disable_and_clear_legacy_irq(ar);
1935 ath10k_pci_irq_msi_fw_mask(ar);
1938 static void ath10k_pci_irq_sync(struct ath10k *ar)
1940 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1942 synchronize_irq(ar_pci->pdev->irq);
1945 static void ath10k_pci_irq_enable(struct ath10k *ar)
1947 ath10k_ce_enable_interrupts(ar);
1948 ath10k_pci_enable_legacy_irq(ar);
1949 ath10k_pci_irq_msi_fw_unmask(ar);
1952 static int ath10k_pci_hif_start(struct ath10k *ar)
1954 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1956 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1958 napi_enable(&ar->napi);
1960 ath10k_pci_irq_enable(ar);
1961 ath10k_pci_rx_post(ar);
1963 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1969 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1972 struct ath10k_ce_pipe *ce_pipe;
1973 struct ath10k_ce_ring *ce_ring;
1974 struct sk_buff *skb;
1977 ar = pci_pipe->hif_ce_state;
1978 ce_pipe = pci_pipe->ce_hdl;
1979 ce_ring = ce_pipe->dest_ring;
1984 if (!pci_pipe->buf_sz)
1987 for (i = 0; i < ce_ring->nentries; i++) {
1988 skb = ce_ring->per_transfer_context[i];
1992 ce_ring->per_transfer_context[i] = NULL;
1994 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1995 skb->len + skb_tailroom(skb),
1997 dev_kfree_skb_any(skb);
2001 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
2004 struct ath10k_ce_pipe *ce_pipe;
2005 struct ath10k_ce_ring *ce_ring;
2006 struct sk_buff *skb;
2009 ar = pci_pipe->hif_ce_state;
2010 ce_pipe = pci_pipe->ce_hdl;
2011 ce_ring = ce_pipe->src_ring;
2016 if (!pci_pipe->buf_sz)
2019 for (i = 0; i < ce_ring->nentries; i++) {
2020 skb = ce_ring->per_transfer_context[i];
2024 ce_ring->per_transfer_context[i] = NULL;
2026 ath10k_htc_tx_completion_handler(ar, skb);
2031 * Cleanup residual buffers for device shutdown:
2032 * buffers that were enqueued for receive
2033 * buffers that were to be sent
2034 * Note: Buffers that had completed but which were
2035 * not yet processed are on a completion queue. They
2036 * are handled when the completion thread shuts down.
2038 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
2040 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2043 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
2044 struct ath10k_pci_pipe *pipe_info;
2046 pipe_info = &ar_pci->pipe_info[pipe_num];
2047 ath10k_pci_rx_pipe_cleanup(pipe_info);
2048 ath10k_pci_tx_pipe_cleanup(pipe_info);
2052 void ath10k_pci_ce_deinit(struct ath10k *ar)
2056 for (i = 0; i < CE_COUNT; i++)
2057 ath10k_ce_deinit_pipe(ar, i);
2060 void ath10k_pci_flush(struct ath10k *ar)
2062 ath10k_pci_rx_retry_sync(ar);
2063 ath10k_pci_buffer_cleanup(ar);
2066 static void ath10k_pci_hif_stop(struct ath10k *ar)
2068 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2069 unsigned long flags;
2071 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
2073 /* Most likely the device has HTT Rx ring configured. The only way to
2074 * prevent the device from accessing (and possible corrupting) host
2075 * memory is to reset the chip now.
2077 * There's also no known way of masking MSI interrupts on the device.
2078 * For ranged MSI the CE-related interrupts can be masked. However
2079 * regardless how many MSI interrupts are assigned the first one
2080 * is always used for firmware indications (crashes) and cannot be
2081 * masked. To prevent the device from asserting the interrupt reset it
2082 * before proceeding with cleanup.
2084 ath10k_pci_safe_chip_reset(ar);
2086 ath10k_pci_irq_disable(ar);
2087 ath10k_pci_irq_sync(ar);
2088 napi_synchronize(&ar->napi);
2089 napi_disable(&ar->napi);
2090 ath10k_pci_flush(ar);
2092 spin_lock_irqsave(&ar_pci->ps_lock, flags);
2093 WARN_ON(ar_pci->ps_wake_refcount > 0);
2094 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
2097 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
2098 void *req, u32 req_len,
2099 void *resp, u32 *resp_len)
2101 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2102 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
2103 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
2104 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
2105 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
2106 dma_addr_t req_paddr = 0;
2107 dma_addr_t resp_paddr = 0;
2108 struct bmi_xfer xfer = {};
2109 void *treq, *tresp = NULL;
2114 if (resp && !resp_len)
2117 if (resp && resp_len && *resp_len == 0)
2120 treq = kmemdup(req, req_len, GFP_KERNEL);
2124 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
2125 ret = dma_mapping_error(ar->dev, req_paddr);
2131 if (resp && resp_len) {
2132 tresp = kzalloc(*resp_len, GFP_KERNEL);
2138 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
2140 ret = dma_mapping_error(ar->dev, resp_paddr);
2146 xfer.wait_for_resp = true;
2149 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
2152 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
2156 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
2158 dma_addr_t unused_buffer;
2159 unsigned int unused_nbytes;
2160 unsigned int unused_id;
2162 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
2163 &unused_nbytes, &unused_id);
2165 /* non-zero means we did not time out */
2171 dma_addr_t unused_buffer;
2173 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
2174 dma_unmap_single(ar->dev, resp_paddr,
2175 *resp_len, DMA_FROM_DEVICE);
2178 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
2180 if (ret == 0 && resp_len) {
2181 *resp_len = min(*resp_len, xfer.resp_len);
2182 memcpy(resp, tresp, xfer.resp_len);
2191 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
2193 struct bmi_xfer *xfer;
2195 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
2198 xfer->tx_done = true;
2201 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
2203 struct ath10k *ar = ce_state->ar;
2204 struct bmi_xfer *xfer;
2205 unsigned int nbytes;
2207 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
2211 if (WARN_ON_ONCE(!xfer))
2214 if (!xfer->wait_for_resp) {
2215 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
2219 xfer->resp_len = nbytes;
2220 xfer->rx_done = true;
2223 static int ath10k_pci_bmi_wait(struct ath10k *ar,
2224 struct ath10k_ce_pipe *tx_pipe,
2225 struct ath10k_ce_pipe *rx_pipe,
2226 struct bmi_xfer *xfer)
2228 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
2229 unsigned long started = jiffies;
2233 while (time_before_eq(jiffies, timeout)) {
2234 ath10k_pci_bmi_send_done(tx_pipe);
2235 ath10k_pci_bmi_recv_data(rx_pipe);
2237 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
2248 dur = jiffies - started;
2250 ath10k_dbg(ar, ATH10K_DBG_BMI,
2251 "bmi cmd took %lu jiffies hz %d ret %d\n",
2257 * Send an interrupt to the device to wake up the Target CPU
2258 * so it has an opportunity to notice any changed state.
2260 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
2264 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
2265 val = ath10k_pci_read32(ar, addr);
2266 val |= CORE_CTRL_CPU_INTR_MASK;
2267 ath10k_pci_write32(ar, addr, val);
2272 static int ath10k_pci_get_num_banks(struct ath10k *ar)
2274 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2276 switch (ar_pci->pdev->device) {
2277 case QCA988X_2_0_DEVICE_ID_UBNT:
2278 case QCA988X_2_0_DEVICE_ID:
2279 case QCA99X0_2_0_DEVICE_ID:
2280 case QCA9888_2_0_DEVICE_ID:
2281 case QCA9984_1_0_DEVICE_ID:
2282 case QCA9887_1_0_DEVICE_ID:
2284 case QCA6164_2_1_DEVICE_ID:
2285 case QCA6174_2_1_DEVICE_ID:
2286 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
2287 case QCA6174_HW_1_0_CHIP_ID_REV:
2288 case QCA6174_HW_1_1_CHIP_ID_REV:
2289 case QCA6174_HW_2_1_CHIP_ID_REV:
2290 case QCA6174_HW_2_2_CHIP_ID_REV:
2292 case QCA6174_HW_1_3_CHIP_ID_REV:
2294 case QCA6174_HW_3_0_CHIP_ID_REV:
2295 case QCA6174_HW_3_1_CHIP_ID_REV:
2296 case QCA6174_HW_3_2_CHIP_ID_REV:
2300 case QCA9377_1_0_DEVICE_ID:
2304 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2308 static int ath10k_bus_get_num_banks(struct ath10k *ar)
2310 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2312 return ce->bus_ops->get_num_banks(ar);
2315 int ath10k_pci_init_config(struct ath10k *ar)
2317 u32 interconnect_targ_addr;
2318 u32 pcie_state_targ_addr = 0;
2319 u32 pipe_cfg_targ_addr = 0;
2320 u32 svc_to_pipe_map = 0;
2321 u32 pcie_config_flags = 0;
2323 u32 ealloc_targ_addr;
2325 u32 flag2_targ_addr;
2328 /* Download to Target the CE Config and the service-to-CE map */
2329 interconnect_targ_addr =
2330 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2332 /* Supply Target-side CE configuration */
2333 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2334 &pcie_state_targ_addr);
2336 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2340 if (pcie_state_targ_addr == 0) {
2342 ath10k_err(ar, "Invalid pcie state addr\n");
2346 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2347 offsetof(struct pcie_state,
2349 &pipe_cfg_targ_addr);
2351 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2355 if (pipe_cfg_targ_addr == 0) {
2357 ath10k_err(ar, "Invalid pipe cfg addr\n");
2361 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2362 target_ce_config_wlan,
2363 sizeof(struct ce_pipe_config) *
2364 NUM_TARGET_CE_CONFIG_WLAN);
2367 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2371 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2372 offsetof(struct pcie_state,
2376 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2380 if (svc_to_pipe_map == 0) {
2382 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2386 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2387 target_service_to_ce_map_wlan,
2388 sizeof(target_service_to_ce_map_wlan));
2390 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2394 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2395 offsetof(struct pcie_state,
2397 &pcie_config_flags);
2399 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2403 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2405 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2406 offsetof(struct pcie_state,
2410 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2414 /* configure early allocation */
2415 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2417 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2419 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2423 /* first bank is switched to IRAM */
2424 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2425 HI_EARLY_ALLOC_MAGIC_MASK);
2426 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2427 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2428 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2430 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2432 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2436 /* Tell Target to proceed with initialization */
2437 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2439 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2441 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2445 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2447 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2449 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2456 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2458 struct ce_attr *attr;
2459 struct ce_pipe_config *config;
2461 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2462 * since it is currently used for other feature.
2465 /* Override Host's Copy Engine 5 configuration */
2466 attr = &host_ce_config_wlan[5];
2467 attr->src_sz_max = 0;
2468 attr->dest_nentries = 0;
2470 /* Override Target firmware's Copy Engine configuration */
2471 config = &target_ce_config_wlan[5];
2472 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2473 config->nbytes_max = __cpu_to_le32(2048);
2475 /* Map from service/endpoint to Copy Engine */
2476 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2479 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2481 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2482 struct ath10k_pci_pipe *pipe;
2483 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2486 for (i = 0; i < CE_COUNT; i++) {
2487 pipe = &ar_pci->pipe_info[i];
2488 pipe->ce_hdl = &ce->ce_states[i];
2490 pipe->hif_ce_state = ar;
2492 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2494 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2499 /* Last CE is Diagnostic Window */
2500 if (i == CE_DIAG_PIPE) {
2501 ar_pci->ce_diag = pipe->ce_hdl;
2505 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2511 void ath10k_pci_free_pipes(struct ath10k *ar)
2515 for (i = 0; i < CE_COUNT; i++)
2516 ath10k_ce_free_pipe(ar, i);
2519 int ath10k_pci_init_pipes(struct ath10k *ar)
2523 for (i = 0; i < CE_COUNT; i++) {
2524 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2526 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2535 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2537 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2538 FW_IND_EVENT_PENDING;
2541 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2545 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2546 val &= ~FW_IND_EVENT_PENDING;
2547 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2550 static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2554 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2555 return (val == 0xffffffff);
2558 /* this function effectively clears target memory controller assert line */
2559 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2563 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2564 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2565 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2566 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2570 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2571 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2572 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2573 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2578 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2582 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2584 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2585 SOC_RESET_CONTROL_ADDRESS);
2586 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2587 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2590 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2594 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2595 SOC_RESET_CONTROL_ADDRESS);
2597 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2598 val | SOC_RESET_CONTROL_CE_RST_MASK);
2600 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2601 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2604 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2608 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2609 SOC_LF_TIMER_CONTROL0_ADDRESS);
2610 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2611 SOC_LF_TIMER_CONTROL0_ADDRESS,
2612 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2615 static int ath10k_pci_warm_reset(struct ath10k *ar)
2619 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2621 spin_lock_bh(&ar->data_lock);
2622 ar->stats.fw_warm_reset_counter++;
2623 spin_unlock_bh(&ar->data_lock);
2625 ath10k_pci_irq_disable(ar);
2627 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2628 * were to access copy engine while host performs copy engine reset
2629 * then it is possible for the device to confuse pci-e controller to
2630 * the point of bringing host system to a complete stop (i.e. hang).
2632 ath10k_pci_warm_reset_si0(ar);
2633 ath10k_pci_warm_reset_cpu(ar);
2634 ath10k_pci_init_pipes(ar);
2635 ath10k_pci_wait_for_target_init(ar);
2637 ath10k_pci_warm_reset_clear_lf(ar);
2638 ath10k_pci_warm_reset_ce(ar);
2639 ath10k_pci_warm_reset_cpu(ar);
2640 ath10k_pci_init_pipes(ar);
2642 ret = ath10k_pci_wait_for_target_init(ar);
2644 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2648 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2653 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2655 ath10k_pci_irq_disable(ar);
2656 return ath10k_pci_qca99x0_chip_reset(ar);
2659 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2661 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2663 if (!ar_pci->pci_soft_reset)
2666 return ar_pci->pci_soft_reset(ar);
2669 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2674 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2676 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2677 * It is thus preferred to use warm reset which is safer but may not be
2678 * able to recover the device from all possible fail scenarios.
2680 * Warm reset doesn't always work on first try so attempt it a few
2681 * times before giving up.
2683 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2684 ret = ath10k_pci_warm_reset(ar);
2686 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2687 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2692 /* FIXME: Sometimes copy engine doesn't recover after warm
2693 * reset. In most cases this needs cold reset. In some of these
2694 * cases the device is in such a state that a cold reset may
2697 * Reading any host interest register via copy engine is
2698 * sufficient to verify if device is capable of booting
2701 ret = ath10k_pci_init_pipes(ar);
2703 ath10k_warn(ar, "failed to init copy engine: %d\n",
2708 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2711 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2716 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2720 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2721 ath10k_warn(ar, "refusing cold reset as requested\n");
2725 ret = ath10k_pci_cold_reset(ar);
2727 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2731 ret = ath10k_pci_wait_for_target_init(ar);
2733 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2738 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2743 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2747 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2749 /* FIXME: QCA6174 requires cold + warm reset to work. */
2751 ret = ath10k_pci_cold_reset(ar);
2753 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2757 ret = ath10k_pci_wait_for_target_init(ar);
2759 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2764 ret = ath10k_pci_warm_reset(ar);
2766 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2770 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2775 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2779 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2781 ret = ath10k_pci_cold_reset(ar);
2783 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2787 ret = ath10k_pci_wait_for_target_init(ar);
2789 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2794 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2799 static int ath10k_pci_chip_reset(struct ath10k *ar)
2801 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2803 if (WARN_ON(!ar_pci->pci_hard_reset))
2806 return ar_pci->pci_hard_reset(ar);
2809 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2811 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2814 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2816 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2818 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2819 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2822 * Bring the target up cleanly.
2824 * The target may be in an undefined state with an AUX-powered Target
2825 * and a Host in WoW mode. If the Host crashes, loses power, or is
2826 * restarted (without unloading the driver) then the Target is left
2827 * (aux) powered and running. On a subsequent driver load, the Target
2828 * is in an unexpected state. We try to catch that here in order to
2829 * reset the Target and retry the probe.
2831 ret = ath10k_pci_chip_reset(ar);
2833 if (ath10k_pci_has_fw_crashed(ar)) {
2834 ath10k_warn(ar, "firmware crashed during chip reset\n");
2835 ath10k_pci_fw_crashed_clear(ar);
2836 ath10k_pci_fw_crashed_dump(ar);
2839 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2843 ret = ath10k_pci_init_pipes(ar);
2845 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2849 ret = ath10k_pci_init_config(ar);
2851 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2855 ret = ath10k_pci_wake_target_cpu(ar);
2857 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2864 ath10k_pci_ce_deinit(ar);
2870 void ath10k_pci_hif_power_down(struct ath10k *ar)
2872 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2874 /* Currently hif_power_up performs effectively a reset and hif_stop
2875 * resets the chip as well so there's no point in resetting here.
2879 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2881 /* Nothing to do; the important stuff is in the driver suspend. */
2885 static int ath10k_pci_suspend(struct ath10k *ar)
2887 /* The grace timer can still be counting down and ar->ps_awake be true.
2888 * It is known that the device may be asleep after resuming regardless
2889 * of the SoC powersave state before suspending. Hence make sure the
2890 * device is asleep before proceeding.
2892 ath10k_pci_sleep_sync(ar);
2897 static int ath10k_pci_hif_resume(struct ath10k *ar)
2899 /* Nothing to do; the important stuff is in the driver resume. */
2903 static int ath10k_pci_resume(struct ath10k *ar)
2905 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2906 struct pci_dev *pdev = ar_pci->pdev;
2910 ret = ath10k_pci_force_wake(ar);
2912 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2916 /* Suspend/Resume resets the PCI configuration space, so we have to
2917 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2918 * from interfering with C3 CPU state. pci_restore_state won't help
2919 * here since it only restores the first 64 bytes pci config header.
2921 pci_read_config_dword(pdev, 0x40, &val);
2922 if ((val & 0x0000ff00) != 0)
2923 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2928 static bool ath10k_pci_validate_cal(void *data, size_t size)
2930 __le16 *cal_words = data;
2937 for (i = 0; i < size / 2; i++)
2938 checksum ^= le16_to_cpu(cal_words[i]);
2940 return checksum == 0xffff;
2943 static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2945 /* Enable SI clock */
2946 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2948 /* Configure GPIOs for I2C operation */
2949 ath10k_pci_write32(ar,
2950 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2951 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2952 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2954 SM(1, GPIO_PIN0_PAD_PULL));
2956 ath10k_pci_write32(ar,
2957 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2958 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2959 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2960 SM(1, GPIO_PIN0_PAD_PULL));
2962 ath10k_pci_write32(ar,
2964 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2965 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2967 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2968 ath10k_pci_write32(ar,
2969 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2970 SM(1, SI_CONFIG_ERR_INT) |
2971 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2972 SM(1, SI_CONFIG_I2C) |
2973 SM(1, SI_CONFIG_POS_SAMPLE) |
2974 SM(1, SI_CONFIG_INACTIVE_DATA) |
2975 SM(1, SI_CONFIG_INACTIVE_CLK) |
2976 SM(8, SI_CONFIG_DIVIDER));
2979 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2984 /* set device select byte and for the read operation */
2985 reg = QCA9887_EEPROM_SELECT_READ |
2986 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2987 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2988 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2990 /* write transmit data, transfer length, and START bit */
2991 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2992 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2993 SM(4, SI_CS_TX_CNT));
2995 /* wait max 1 sec */
2996 wait_limit = 100000;
2998 /* wait for SI_CS_DONE_INT */
3000 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
3001 if (MS(reg, SI_CS_DONE_INT))
3006 } while (wait_limit > 0);
3008 if (!MS(reg, SI_CS_DONE_INT)) {
3009 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
3014 /* clear SI_CS_DONE_INT */
3015 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
3017 if (MS(reg, SI_CS_DONE_ERR)) {
3018 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
3022 /* extract receive data */
3023 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
3029 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
3036 if (!QCA_REV_9887(ar))
3039 calsize = ar->hw_params.cal_data_len;
3040 caldata = kmalloc(calsize, GFP_KERNEL);
3044 ath10k_pci_enable_eeprom(ar);
3046 for (i = 0; i < calsize; i++) {
3047 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
3052 if (!ath10k_pci_validate_cal(caldata, calsize))
3056 *data_len = calsize;
3066 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
3067 .tx_sg = ath10k_pci_hif_tx_sg,
3068 .diag_read = ath10k_pci_hif_diag_read,
3069 .diag_write = ath10k_pci_diag_write_mem,
3070 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
3071 .start = ath10k_pci_hif_start,
3072 .stop = ath10k_pci_hif_stop,
3073 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
3074 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
3075 .send_complete_check = ath10k_pci_hif_send_complete_check,
3076 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
3077 .power_up = ath10k_pci_hif_power_up,
3078 .power_down = ath10k_pci_hif_power_down,
3079 .read32 = ath10k_pci_read32,
3080 .write32 = ath10k_pci_write32,
3081 .suspend = ath10k_pci_hif_suspend,
3082 .resume = ath10k_pci_hif_resume,
3083 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
3087 * Top-level interrupt handler for all PCI interrupts from a Target.
3088 * When a block of MSI interrupts is allocated, this top-level handler
3089 * is not used; instead, we directly call the correct sub-handler.
3091 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
3093 struct ath10k *ar = arg;
3094 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3097 if (ath10k_pci_has_device_gone(ar))
3100 ret = ath10k_pci_force_wake(ar);
3102 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
3106 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
3107 !ath10k_pci_irq_pending(ar))
3110 ath10k_pci_disable_and_clear_legacy_irq(ar);
3111 ath10k_pci_irq_msi_fw_mask(ar);
3112 napi_schedule(&ar->napi);
3117 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
3119 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
3122 if (ath10k_pci_has_fw_crashed(ar)) {
3123 ath10k_pci_fw_crashed_clear(ar);
3124 ath10k_pci_fw_crashed_dump(ar);
3129 ath10k_ce_per_engine_service_any(ar);
3131 done = ath10k_htt_txrx_compl_task(ar, budget);
3133 if (done < budget) {
3134 napi_complete_done(ctx, done);
3135 /* In case of MSI, it is possible that interrupts are received
3136 * while NAPI poll is inprogress. So pending interrupts that are
3137 * received after processing all copy engine pipes by NAPI poll
3138 * will not be handled again. This is causing failure to
3139 * complete boot sequence in x86 platform. So before enabling
3140 * interrupts safer to check for pending interrupts for
3141 * immediate servicing.
3143 if (ath10k_ce_interrupt_summary(ar)) {
3144 napi_reschedule(ctx);
3147 ath10k_pci_enable_legacy_irq(ar);
3148 ath10k_pci_irq_msi_fw_unmask(ar);
3155 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
3157 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3160 ret = request_irq(ar_pci->pdev->irq,
3161 ath10k_pci_interrupt_handler,
3162 IRQF_SHARED, "ath10k_pci", ar);
3164 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
3165 ar_pci->pdev->irq, ret);
3172 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
3174 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3177 ret = request_irq(ar_pci->pdev->irq,
3178 ath10k_pci_interrupt_handler,
3179 IRQF_SHARED, "ath10k_pci", ar);
3181 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
3182 ar_pci->pdev->irq, ret);
3189 static int ath10k_pci_request_irq(struct ath10k *ar)
3191 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3193 switch (ar_pci->oper_irq_mode) {
3194 case ATH10K_PCI_IRQ_LEGACY:
3195 return ath10k_pci_request_irq_legacy(ar);
3196 case ATH10K_PCI_IRQ_MSI:
3197 return ath10k_pci_request_irq_msi(ar);
3203 static void ath10k_pci_free_irq(struct ath10k *ar)
3205 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3207 free_irq(ar_pci->pdev->irq, ar);
3210 void ath10k_pci_init_napi(struct ath10k *ar)
3212 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
3213 ATH10K_NAPI_BUDGET);
3216 static int ath10k_pci_init_irq(struct ath10k *ar)
3218 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3221 ath10k_pci_init_napi(ar);
3223 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
3224 ath10k_info(ar, "limiting irq mode to: %d\n",
3225 ath10k_pci_irq_mode);
3228 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
3229 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
3230 ret = pci_enable_msi(ar_pci->pdev);
3239 * A potential race occurs here: The CORE_BASE write
3240 * depends on target correctly decoding AXI address but
3241 * host won't know when target writes BAR to CORE_CTRL.
3242 * This write might get lost if target has NOT written BAR.
3243 * For now, fix the race by repeating the write in below
3244 * synchronization checking.
3246 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
3248 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3249 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
3254 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
3256 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3260 static int ath10k_pci_deinit_irq(struct ath10k *ar)
3262 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3264 switch (ar_pci->oper_irq_mode) {
3265 case ATH10K_PCI_IRQ_LEGACY:
3266 ath10k_pci_deinit_irq_legacy(ar);
3269 pci_disable_msi(ar_pci->pdev);
3276 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
3278 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3279 unsigned long timeout;
3282 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
3284 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
3287 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3289 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
3292 /* target should never return this */
3293 if (val == 0xffffffff)
3296 /* the device has crashed so don't bother trying anymore */
3297 if (val & FW_IND_EVENT_PENDING)
3300 if (val & FW_IND_INITIALIZED)
3303 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
3304 /* Fix potential race by repeating CORE_BASE writes */
3305 ath10k_pci_enable_legacy_irq(ar);
3308 } while (time_before(jiffies, timeout));
3310 ath10k_pci_disable_and_clear_legacy_irq(ar);
3311 ath10k_pci_irq_msi_fw_mask(ar);
3313 if (val == 0xffffffff) {
3314 ath10k_err(ar, "failed to read device register, device is gone\n");
3318 if (val & FW_IND_EVENT_PENDING) {
3319 ath10k_warn(ar, "device has crashed during init\n");
3323 if (!(val & FW_IND_INITIALIZED)) {
3324 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3329 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3333 static int ath10k_pci_cold_reset(struct ath10k *ar)
3337 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3339 spin_lock_bh(&ar->data_lock);
3341 ar->stats.fw_cold_reset_counter++;
3343 spin_unlock_bh(&ar->data_lock);
3345 /* Put Target, including PCIe, into RESET. */
3346 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3348 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3350 /* After writing into SOC_GLOBAL_RESET to put device into
3351 * reset and pulling out of reset pcie may not be stable
3352 * for any immediate pcie register access and cause bus error,
3353 * add delay before any pcie access request to fix this issue.
3357 /* Pull Target, including PCIe, out of RESET. */
3359 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3363 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3368 static int ath10k_pci_claim(struct ath10k *ar)
3370 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3371 struct pci_dev *pdev = ar_pci->pdev;
3374 pci_set_drvdata(pdev, ar);
3376 ret = pci_enable_device(pdev);
3378 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3382 ret = pci_request_region(pdev, BAR_NUM, "ath");
3384 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3389 /* Target expects 32 bit DMA. Enforce it. */
3390 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3392 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3396 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3398 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3403 pci_set_master(pdev);
3405 /* Arrange for access to Target SoC registers. */
3406 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3407 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3409 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3414 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3418 pci_clear_master(pdev);
3421 pci_release_region(pdev, BAR_NUM);
3424 pci_disable_device(pdev);
3429 static void ath10k_pci_release(struct ath10k *ar)
3431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3432 struct pci_dev *pdev = ar_pci->pdev;
3434 pci_iounmap(pdev, ar_pci->mem);
3435 pci_release_region(pdev, BAR_NUM);
3436 pci_clear_master(pdev);
3437 pci_disable_device(pdev);
3440 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3442 const struct ath10k_pci_supp_chip *supp_chip;
3444 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3446 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3447 supp_chip = &ath10k_pci_supp_chips[i];
3449 if (supp_chip->dev_id == dev_id &&
3450 supp_chip->rev_id == rev_id)
3457 int ath10k_pci_setup_resource(struct ath10k *ar)
3459 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3460 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3463 spin_lock_init(&ce->ce_lock);
3464 spin_lock_init(&ar_pci->ps_lock);
3466 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3468 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3469 ath10k_pci_override_ce_config(ar);
3471 ret = ath10k_pci_alloc_pipes(ar);
3473 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3481 void ath10k_pci_release_resource(struct ath10k *ar)
3483 ath10k_pci_rx_retry_sync(ar);
3484 netif_napi_del(&ar->napi);
3485 ath10k_pci_ce_deinit(ar);
3486 ath10k_pci_free_pipes(ar);
3489 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3490 .read32 = ath10k_bus_pci_read32,
3491 .write32 = ath10k_bus_pci_write32,
3492 .get_num_banks = ath10k_pci_get_num_banks,
3495 static int ath10k_pci_probe(struct pci_dev *pdev,
3496 const struct pci_device_id *pci_dev)
3500 struct ath10k_pci *ar_pci;
3501 enum ath10k_hw_rev hw_rev;
3502 struct ath10k_bus_params bus_params;
3504 int (*pci_soft_reset)(struct ath10k *ar);
3505 int (*pci_hard_reset)(struct ath10k *ar);
3506 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3508 switch (pci_dev->device) {
3509 case QCA988X_2_0_DEVICE_ID_UBNT:
3510 case QCA988X_2_0_DEVICE_ID:
3511 hw_rev = ATH10K_HW_QCA988X;
3513 pci_soft_reset = ath10k_pci_warm_reset;
3514 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3515 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3517 case QCA9887_1_0_DEVICE_ID:
3518 hw_rev = ATH10K_HW_QCA9887;
3520 pci_soft_reset = ath10k_pci_warm_reset;
3521 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3522 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3524 case QCA6164_2_1_DEVICE_ID:
3525 case QCA6174_2_1_DEVICE_ID:
3526 hw_rev = ATH10K_HW_QCA6174;
3528 pci_soft_reset = ath10k_pci_warm_reset;
3529 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3530 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3532 case QCA99X0_2_0_DEVICE_ID:
3533 hw_rev = ATH10K_HW_QCA99X0;
3535 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3536 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3537 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3539 case QCA9984_1_0_DEVICE_ID:
3540 hw_rev = ATH10K_HW_QCA9984;
3542 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3543 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3544 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3546 case QCA9888_2_0_DEVICE_ID:
3547 hw_rev = ATH10K_HW_QCA9888;
3549 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3550 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3551 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3553 case QCA9377_1_0_DEVICE_ID:
3554 hw_rev = ATH10K_HW_QCA9377;
3556 pci_soft_reset = NULL;
3557 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3558 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3565 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3566 hw_rev, &ath10k_pci_hif_ops);
3568 dev_err(&pdev->dev, "failed to allocate core\n");
3572 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3573 pdev->vendor, pdev->device,
3574 pdev->subsystem_vendor, pdev->subsystem_device);
3576 ar_pci = ath10k_pci_priv(ar);
3577 ar_pci->pdev = pdev;
3578 ar_pci->dev = &pdev->dev;
3580 ar->dev_id = pci_dev->device;
3581 ar_pci->pci_ps = pci_ps;
3582 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3583 ar_pci->pci_soft_reset = pci_soft_reset;
3584 ar_pci->pci_hard_reset = pci_hard_reset;
3585 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3586 ar->ce_priv = &ar_pci->ce;
3588 ar->id.vendor = pdev->vendor;
3589 ar->id.device = pdev->device;
3590 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3591 ar->id.subsystem_device = pdev->subsystem_device;
3593 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0);
3595 ret = ath10k_pci_setup_resource(ar);
3597 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3598 goto err_core_destroy;
3601 ret = ath10k_pci_claim(ar);
3603 ath10k_err(ar, "failed to claim device: %d\n", ret);
3604 goto err_free_pipes;
3607 ret = ath10k_pci_force_wake(ar);
3609 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3613 ath10k_pci_ce_deinit(ar);
3614 ath10k_pci_irq_disable(ar);
3616 ret = ath10k_pci_init_irq(ar);
3618 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3622 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3623 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3624 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3626 ret = ath10k_pci_request_irq(ar);
3628 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3629 goto err_deinit_irq;
3632 ret = ath10k_pci_chip_reset(ar);
3634 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3638 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
3639 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3640 if (bus_params.chip_id == 0xffffffff) {
3641 ath10k_err(ar, "failed to get chip id\n");
3645 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
3646 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3647 pdev->device, bus_params.chip_id);
3651 ret = ath10k_core_register(ar, &bus_params);
3653 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3660 ath10k_pci_free_irq(ar);
3661 ath10k_pci_rx_retry_sync(ar);
3664 ath10k_pci_deinit_irq(ar);
3667 ath10k_pci_sleep_sync(ar);
3668 ath10k_pci_release(ar);
3671 ath10k_pci_free_pipes(ar);
3674 ath10k_core_destroy(ar);
3679 static void ath10k_pci_remove(struct pci_dev *pdev)
3681 struct ath10k *ar = pci_get_drvdata(pdev);
3682 struct ath10k_pci *ar_pci;
3684 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3689 ar_pci = ath10k_pci_priv(ar);
3694 ath10k_core_unregister(ar);
3695 ath10k_pci_free_irq(ar);
3696 ath10k_pci_deinit_irq(ar);
3697 ath10k_pci_release_resource(ar);
3698 ath10k_pci_sleep_sync(ar);
3699 ath10k_pci_release(ar);
3700 ath10k_core_destroy(ar);
3703 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3705 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3707 struct ath10k *ar = dev_get_drvdata(dev);
3710 ret = ath10k_pci_suspend(ar);
3712 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3717 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3719 struct ath10k *ar = dev_get_drvdata(dev);
3722 ret = ath10k_pci_resume(ar);
3724 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3729 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3730 ath10k_pci_pm_suspend,
3731 ath10k_pci_pm_resume);
3733 static struct pci_driver ath10k_pci_driver = {
3734 .name = "ath10k_pci",
3735 .id_table = ath10k_pci_id_table,
3736 .probe = ath10k_pci_probe,
3737 .remove = ath10k_pci_remove,
3739 .driver.pm = &ath10k_pci_pm_ops,
3743 static int __init ath10k_pci_init(void)
3747 ret = pci_register_driver(&ath10k_pci_driver);
3749 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3752 ret = ath10k_ahb_init();
3754 printk(KERN_ERR "ahb init failed: %d\n", ret);
3758 module_init(ath10k_pci_init);
3760 static void __exit ath10k_pci_exit(void)
3762 pci_unregister_driver(&ath10k_pci_driver);
3766 module_exit(ath10k_pci_exit);
3768 MODULE_AUTHOR("Qualcomm Atheros");
3769 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3770 MODULE_LICENSE("Dual BSD/GPL");
3772 /* QCA988x 2.0 firmware files */
3773 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3774 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3775 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3776 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3777 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3778 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3780 /* QCA9887 1.0 firmware files */
3781 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3782 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
3783 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3785 /* QCA6174 2.1 firmware files */
3786 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3787 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3788 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3789 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3791 /* QCA6174 3.1 firmware files */
3792 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3793 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3794 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3795 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3796 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3798 /* QCA9377 1.0 firmware files */
3799 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3800 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3801 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);