1 // SPDX-License-Identifier: GPL-2.0-only
3 * Goramo PCI200SYN synchronous serial card driver for Linux
5 * Copyright (C) 2002-2008 Krzysztof Halasa <khc@pm.waw.pl>
7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
9 * Sources of information:
10 * Hitachi HD64572 SCA-II User's Manual
11 * PLX Technology Inc. PCI9052 Data Book
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/capability.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
23 #include <linux/string.h>
24 #include <linux/errno.h>
25 #include <linux/init.h>
26 #include <linux/ioport.h>
27 #include <linux/netdevice.h>
28 #include <linux/hdlc.h>
29 #include <linux/pci.h>
30 #include <linux/delay.h>
38 #define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */
39 #define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */
40 #define MAX_TX_BUFFERS 10
42 static int pci_clock_freq = 33000000;
43 #define CLOCK_BASE pci_clock_freq
46 * PLX PCI9052 local configuration and shared runtime registers.
47 * This structure can be used to access 9052 registers (memory mapped).
50 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
51 u32 loc_rom_range; /* 10h : Local ROM Range */
52 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
53 u32 loc_rom_base; /* 24h : Local ROM Base */
54 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
55 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
56 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
57 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
58 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
63 typedef struct port_s {
64 struct napi_struct napi;
65 struct net_device *netdev;
67 spinlock_t lock; /* TX lock */
68 sync_serial_settings settings;
69 int rxpart; /* partial frame received, next frame invalid*/
70 unsigned short encoding;
71 unsigned short parity;
72 u16 rxin; /* rx ring buffer 'in' pointer */
73 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
75 u8 rxs, txs, tmc; /* SCA registers */
76 u8 chan; /* physical port # - 0 or 1 */
81 typedef struct card_s {
82 u8 __iomem *rambase; /* buffer memory base (virtual) */
83 u8 __iomem *scabase; /* SCA memory base (virtual) */
84 plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */
85 u16 rx_ring_buffers; /* number of buffers in a ring */
87 u16 buff_offset; /* offset of first buffer of first channel */
88 u8 irq; /* interrupt request level */
94 #define get_port(card, port) (&card->ports[port])
95 #define sca_flush(card) (sca_in(IER0, card))
97 static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
101 len = length > 256 ? 256 : length;
102 memcpy_toio(dest, src, len);
111 #define memcpy_toio new_memcpy_toio
116 static void pci200_set_iface(port_t *port)
118 card_t *card = port->card;
119 u16 msci = get_msci(port);
120 u8 rxs = port->rxs & CLK_BRG_MASK;
121 u8 txs = port->txs & CLK_BRG_MASK;
123 sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
125 switch(port->settings.clock_type) {
127 rxs |= CLK_BRG; /* BRG output */
128 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
132 rxs |= CLK_LINE; /* RXC input */
133 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
137 rxs |= CLK_LINE; /* RXC input */
138 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
141 default: /* EXTernal clock */
142 rxs |= CLK_LINE; /* RXC input */
143 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
149 sca_out(rxs, msci + RXS, card);
150 sca_out(txs, msci + TXS, card);
156 static int pci200_open(struct net_device *dev)
158 port_t *port = dev_to_port(dev);
160 int result = hdlc_open(dev);
165 pci200_set_iface(port);
166 sca_flush(port->card);
172 static int pci200_close(struct net_device *dev)
175 sca_flush(dev_to_port(dev)->card);
182 static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
184 const size_t size = sizeof(sync_serial_settings);
185 sync_serial_settings new_line;
186 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
187 port_t *port = dev_to_port(dev);
190 if (cmd == SIOCDEVPRIVATE) {
195 if (cmd != SIOCWANDEV)
196 return hdlc_ioctl(dev, ifr, cmd);
198 switch(ifr->ifr_settings.type) {
200 ifr->ifr_settings.type = IF_IFACE_V35;
201 if (ifr->ifr_settings.size < size) {
202 ifr->ifr_settings.size = size; /* data size wanted */
205 if (copy_to_user(line, &port->settings, size))
210 case IF_IFACE_SYNC_SERIAL:
211 if (!capable(CAP_NET_ADMIN))
214 if (copy_from_user(&new_line, line, size))
217 if (new_line.clock_type != CLOCK_EXT &&
218 new_line.clock_type != CLOCK_TXFROMRX &&
219 new_line.clock_type != CLOCK_INT &&
220 new_line.clock_type != CLOCK_TXINT)
221 return -EINVAL; /* No such clock setting */
223 if (new_line.loopback != 0 && new_line.loopback != 1)
226 memcpy(&port->settings, &new_line, size); /* Update settings */
227 pci200_set_iface(port);
228 sca_flush(port->card);
232 return hdlc_ioctl(dev, ifr, cmd);
238 static void pci200_pci_remove_one(struct pci_dev *pdev)
241 card_t *card = pci_get_drvdata(pdev);
243 for (i = 0; i < 2; i++)
244 if (card->ports[i].card)
245 unregister_hdlc_device(card->ports[i].netdev);
248 free_irq(card->irq, card);
251 iounmap(card->rambase);
253 iounmap(card->scabase);
255 iounmap(card->plxbase);
257 pci_release_regions(pdev);
258 pci_disable_device(pdev);
259 if (card->ports[0].netdev)
260 free_netdev(card->ports[0].netdev);
261 if (card->ports[1].netdev)
262 free_netdev(card->ports[1].netdev);
266 static const struct net_device_ops pci200_ops = {
267 .ndo_open = pci200_open,
268 .ndo_stop = pci200_close,
269 .ndo_start_xmit = hdlc_start_xmit,
270 .ndo_do_ioctl = pci200_ioctl,
273 static int pci200_pci_init_one(struct pci_dev *pdev,
274 const struct pci_device_id *ent)
280 u32 ramphys; /* buffer memory base */
281 u32 scaphys; /* SCA memory base */
282 u32 plxphys; /* PLX registers memory base */
284 i = pci_enable_device(pdev);
288 i = pci_request_regions(pdev, "PCI200SYN");
290 pci_disable_device(pdev);
294 card = kzalloc(sizeof(card_t), GFP_KERNEL);
296 pci_release_regions(pdev);
297 pci_disable_device(pdev);
300 pci_set_drvdata(pdev, card);
301 card->ports[0].netdev = alloc_hdlcdev(&card->ports[0]);
302 card->ports[1].netdev = alloc_hdlcdev(&card->ports[1]);
303 if (!card->ports[0].netdev || !card->ports[1].netdev) {
304 pr_err("unable to allocate memory\n");
305 pci200_pci_remove_one(pdev);
309 if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
310 pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
311 pci_resource_len(pdev, 3) < 16384) {
312 pr_err("invalid card EEPROM parameters\n");
313 pci200_pci_remove_one(pdev);
317 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
318 card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
320 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
321 card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
323 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
324 card->rambase = pci_ioremap_bar(pdev, 3);
326 if (card->plxbase == NULL ||
327 card->scabase == NULL ||
328 card->rambase == NULL) {
329 pr_err("ioremap() failed\n");
330 pci200_pci_remove_one(pdev);
335 p = &card->plxbase->init_ctrl;
336 writel(readl(p) | 0x40000000, p);
337 readl(p); /* Flush the write - do not use sca_flush */
340 writel(readl(p) & ~0x40000000, p);
341 readl(p); /* Flush the write - do not use sca_flush */
344 ramsize = sca_detect_ram(card, card->rambase,
345 pci_resource_len(pdev, 3));
347 /* number of TX + RX buffers for one port - this is dual port card */
348 i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
349 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
350 card->rx_ring_buffers = i - card->tx_ring_buffers;
352 card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
353 card->rx_ring_buffers);
355 pr_info("%u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
356 ramsize / 1024, ramphys,
357 pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
359 if (card->tx_ring_buffers < 1) {
360 pr_err("RAM test failed\n");
361 pci200_pci_remove_one(pdev);
365 /* Enable interrupts on the PCI bridge */
366 p = &card->plxbase->intr_ctrl_stat;
367 writew(readw(p) | 0x0040, p);
370 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pci200syn", card)) {
371 pr_warn("could not allocate IRQ%d\n", pdev->irq);
372 pci200_pci_remove_one(pdev);
375 card->irq = pdev->irq;
379 for (i = 0; i < 2; i++) {
380 port_t *port = &card->ports[i];
381 struct net_device *dev = port->netdev;
382 hdlc_device *hdlc = dev_to_hdlc(dev);
385 spin_lock_init(&port->lock);
386 dev->irq = card->irq;
387 dev->mem_start = ramphys;
388 dev->mem_end = ramphys + ramsize - 1;
389 dev->tx_queue_len = 50;
390 dev->netdev_ops = &pci200_ops;
391 hdlc->attach = sca_attach;
392 hdlc->xmit = sca_xmit;
393 port->settings.clock_type = CLOCK_EXT;
396 if (register_hdlc_device(dev)) {
397 pr_err("unable to register hdlc device\n");
399 pci200_pci_remove_one(pdev);
403 netdev_info(dev, "PCI200SYN channel %d\n", port->chan);
412 static const struct pci_device_id pci200_pci_tbl[] = {
413 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX,
414 PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 },
419 static struct pci_driver pci200_pci_driver = {
421 .id_table = pci200_pci_tbl,
422 .probe = pci200_pci_init_one,
423 .remove = pci200_pci_remove_one,
427 static int __init pci200_init_module(void)
429 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
430 pr_err("Invalid PCI clock frequency\n");
433 return pci_register_driver(&pci200_pci_driver);
438 static void __exit pci200_cleanup_module(void)
440 pci_unregister_driver(&pci200_pci_driver);
443 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
444 MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
445 MODULE_LICENSE("GPL v2");
446 MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
447 module_param(pci_clock_freq, int, 0444);
448 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
449 module_init(pci200_init_module);
450 module_exit(pci200_cleanup_module);