1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cyclades PC300 synchronous serial card driver for Linux
5 * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>.
9 * Sources of information:
10 * Hitachi HD64572 SCA-II User's Manual
11 * Original Cyclades PC300 Linux driver
13 * This driver currently supports only PC300/RSV (V.24/V.35) and
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/types.h>
24 #include <linux/fcntl.h>
26 #include <linux/string.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/hdlc.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
42 #define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */
43 #define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */
44 #define MAX_TX_BUFFERS 10
46 static int pci_clock_freq = 33000000;
47 static int use_crystal_clock;
48 static unsigned int CLOCK_BASE;
50 /* Masks to access the init_ctrl PLX register */
51 #define PC300_CLKSEL_MASK (0x00000004UL)
52 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
53 #define PC300_CTYPE_MASK (0x00000800UL)
55 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
57 /* PLX PCI9050-1 local configuration and shared runtime registers.
58 * This structure can be used to access 9050 registers (memory mapped).
61 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
62 u32 loc_rom_range; /* 10h : Local ROM Range */
63 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
64 u32 loc_rom_base; /* 24h : Local ROM Base */
65 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
66 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
67 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
68 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
69 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
72 typedef struct port_s {
73 struct napi_struct napi;
74 struct net_device *netdev;
76 spinlock_t lock; /* TX lock */
77 sync_serial_settings settings;
78 int rxpart; /* partial frame received, next frame invalid*/
79 unsigned short encoding;
80 unsigned short parity;
82 u16 rxin; /* rx ring buffer 'in' pointer */
83 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
85 u8 rxs, txs, tmc; /* SCA registers */
86 u8 chan; /* physical port # - 0 or 1 */
89 typedef struct card_s {
90 int type; /* RSV, X21, etc. */
91 int n_ports; /* 1 or 2 ports */
92 u8 __iomem *rambase; /* buffer memory base (virtual) */
93 u8 __iomem *scabase; /* SCA memory base (virtual) */
94 plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
95 u32 init_ctrl_value; /* Saved value - 9050 bug workaround */
96 u16 rx_ring_buffers; /* number of buffers in a ring */
98 u16 buff_offset; /* offset of first buffer of first channel */
99 u8 irq; /* interrupt request level */
104 #define get_port(card, port) ((port) < (card)->n_ports ? \
105 (&(card)->ports[port]) : (NULL))
109 static void pc300_set_iface(port_t *port)
111 card_t *card = port->card;
112 u32 __iomem *init_ctrl = &card->plxbase->init_ctrl;
113 u16 msci = get_msci(port);
114 u8 rxs = port->rxs & CLK_BRG_MASK;
115 u8 txs = port->txs & CLK_BRG_MASK;
117 sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
119 switch (port->settings.clock_type) {
121 rxs |= CLK_BRG; /* BRG output */
122 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
126 rxs |= CLK_LINE; /* RXC input */
127 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
131 rxs |= CLK_LINE; /* RXC input */
132 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
135 default: /* EXTernal clock */
136 rxs |= CLK_LINE; /* RXC input */
137 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
143 sca_out(rxs, msci + RXS, card);
144 sca_out(txs, msci + TXS, card);
147 if (port->card->type == PC300_RSV) {
148 if (port->iface == IF_IFACE_V35)
149 writel(card->init_ctrl_value |
150 PC300_CHMEDIA_MASK(port->chan), init_ctrl);
152 writel(card->init_ctrl_value &
153 ~PC300_CHMEDIA_MASK(port->chan), init_ctrl);
157 static int pc300_open(struct net_device *dev)
159 port_t *port = dev_to_port(dev);
160 int result = hdlc_open(dev);
166 pc300_set_iface(port);
170 static int pc300_close(struct net_device *dev)
177 static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
179 const size_t size = sizeof(sync_serial_settings);
180 sync_serial_settings new_line;
181 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
183 port_t *port = dev_to_port(dev);
186 if (cmd == SIOCDEVPRIVATE) {
191 if (cmd != SIOCWANDEV)
192 return hdlc_ioctl(dev, ifr, cmd);
194 if (ifr->ifr_settings.type == IF_GET_IFACE) {
195 ifr->ifr_settings.type = port->iface;
196 if (ifr->ifr_settings.size < size) {
197 ifr->ifr_settings.size = size; /* data size wanted */
200 if (copy_to_user(line, &port->settings, size))
205 if (port->card->type == PC300_X21 &&
206 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
207 ifr->ifr_settings.type == IF_IFACE_X21))
208 new_type = IF_IFACE_X21;
210 else if (port->card->type == PC300_RSV &&
211 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
212 ifr->ifr_settings.type == IF_IFACE_V35))
213 new_type = IF_IFACE_V35;
215 else if (port->card->type == PC300_RSV &&
216 ifr->ifr_settings.type == IF_IFACE_V24)
217 new_type = IF_IFACE_V24;
220 return hdlc_ioctl(dev, ifr, cmd);
222 if (!capable(CAP_NET_ADMIN))
225 if (copy_from_user(&new_line, line, size))
228 if (new_line.clock_type != CLOCK_EXT &&
229 new_line.clock_type != CLOCK_TXFROMRX &&
230 new_line.clock_type != CLOCK_INT &&
231 new_line.clock_type != CLOCK_TXINT)
232 return -EINVAL; /* No such clock setting */
234 if (new_line.loopback != 0 && new_line.loopback != 1)
237 memcpy(&port->settings, &new_line, size); /* Update settings */
238 port->iface = new_type;
239 pc300_set_iface(port);
243 static void pc300_pci_remove_one(struct pci_dev *pdev)
246 card_t *card = pci_get_drvdata(pdev);
248 for (i = 0; i < 2; i++)
249 if (card->ports[i].card)
250 unregister_hdlc_device(card->ports[i].netdev);
253 free_irq(card->irq, card);
256 iounmap(card->rambase);
258 iounmap(card->scabase);
260 iounmap(card->plxbase);
262 pci_release_regions(pdev);
263 pci_disable_device(pdev);
264 if (card->ports[0].netdev)
265 free_netdev(card->ports[0].netdev);
266 if (card->ports[1].netdev)
267 free_netdev(card->ports[1].netdev);
271 static const struct net_device_ops pc300_ops = {
272 .ndo_open = pc300_open,
273 .ndo_stop = pc300_close,
274 .ndo_start_xmit = hdlc_start_xmit,
275 .ndo_do_ioctl = pc300_ioctl,
278 static int pc300_pci_init_one(struct pci_dev *pdev,
279 const struct pci_device_id *ent)
285 u32 ramphys; /* buffer memory base */
286 u32 scaphys; /* SCA memory base */
287 u32 plxphys; /* PLX registers memory base */
289 i = pci_enable_device(pdev);
293 i = pci_request_regions(pdev, "PC300");
295 pci_disable_device(pdev);
299 card = kzalloc(sizeof(card_t), GFP_KERNEL);
301 pci_release_regions(pdev);
302 pci_disable_device(pdev);
305 pci_set_drvdata(pdev, card);
307 if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
308 pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
309 pci_resource_len(pdev, 3) < 16384) {
310 pr_err("invalid card EEPROM parameters\n");
311 pc300_pci_remove_one(pdev);
315 plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
316 card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
318 scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
319 card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
321 ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
322 card->rambase = pci_ioremap_bar(pdev, 3);
324 if (!card->plxbase || !card->scabase || !card->rambase) {
325 pr_err("ioremap() failed\n");
326 pc300_pci_remove_one(pdev);
330 /* PLX PCI 9050 workaround for local configuration register read bug */
331 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
332 card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
333 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
335 if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
336 pdev->device == PCI_DEVICE_ID_PC300_TE_2)
337 card->type = PC300_TE; /* not fully supported */
338 else if (card->init_ctrl_value & PC300_CTYPE_MASK)
339 card->type = PC300_X21;
341 card->type = PC300_RSV;
343 if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
344 pdev->device == PCI_DEVICE_ID_PC300_TE_1)
349 for (i = 0; i < card->n_ports; i++) {
350 card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]);
351 if (!card->ports[i].netdev) {
352 pr_err("unable to allocate memory\n");
353 pc300_pci_remove_one(pdev);
359 p = &card->plxbase->init_ctrl;
360 writel(card->init_ctrl_value | 0x40000000, p);
361 readl(p); /* Flush the write - do not use sca_flush */
364 writel(card->init_ctrl_value, p);
365 readl(p); /* Flush the write - do not use sca_flush */
368 /* Reload Config. Registers from EEPROM */
369 writel(card->init_ctrl_value | 0x20000000, p);
370 readl(p); /* Flush the write - do not use sca_flush */
373 writel(card->init_ctrl_value, p);
374 readl(p); /* Flush the write - do not use sca_flush */
377 ramsize = sca_detect_ram(card, card->rambase,
378 pci_resource_len(pdev, 3));
380 if (use_crystal_clock)
381 card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
383 card->init_ctrl_value |= PC300_CLKSEL_MASK;
385 writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
386 /* number of TX + RX buffers for one port */
387 i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
388 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
389 card->rx_ring_buffers = i - card->tx_ring_buffers;
391 card->buff_offset = card->n_ports * sizeof(pkt_desc) *
392 (card->tx_ring_buffers + card->rx_ring_buffers);
394 pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
395 card->type == PC300_X21 ? "X21" :
396 card->type == PC300_TE ? "TE" : "RSV",
397 ramsize / 1024, ramphys, pdev->irq,
398 card->tx_ring_buffers, card->rx_ring_buffers);
400 if (card->tx_ring_buffers < 1) {
401 pr_err("RAM test failed\n");
402 pc300_pci_remove_one(pdev);
406 /* Enable interrupts on the PCI bridge, LINTi1 active low */
407 writew(0x0041, &card->plxbase->intr_ctrl_stat);
410 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
411 pr_warn("could not allocate IRQ%d\n", pdev->irq);
412 pc300_pci_remove_one(pdev);
415 card->irq = pdev->irq;
419 // COTE not set - allows better TX DMA settings
420 // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
422 sca_out(0x10, BTCR, card);
424 for (i = 0; i < card->n_ports; i++) {
425 port_t *port = &card->ports[i];
426 struct net_device *dev = port->netdev;
427 hdlc_device *hdlc = dev_to_hdlc(dev);
431 spin_lock_init(&port->lock);
432 dev->irq = card->irq;
433 dev->mem_start = ramphys;
434 dev->mem_end = ramphys + ramsize - 1;
435 dev->tx_queue_len = 50;
436 dev->netdev_ops = &pc300_ops;
437 hdlc->attach = sca_attach;
438 hdlc->xmit = sca_xmit;
439 port->settings.clock_type = CLOCK_EXT;
441 if (card->type == PC300_X21)
442 port->iface = IF_IFACE_X21;
444 port->iface = IF_IFACE_V35;
447 if (register_hdlc_device(dev)) {
448 pr_err("unable to register hdlc device\n");
450 pc300_pci_remove_one(pdev);
454 netdev_info(dev, "PC300 channel %d\n", port->chan);
459 static const struct pci_device_id pc300_pci_tbl[] = {
460 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
461 PCI_ANY_ID, 0, 0, 0 },
462 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
463 PCI_ANY_ID, 0, 0, 0 },
464 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
465 PCI_ANY_ID, 0, 0, 0 },
466 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
467 PCI_ANY_ID, 0, 0, 0 },
471 static struct pci_driver pc300_pci_driver = {
473 .id_table = pc300_pci_tbl,
474 .probe = pc300_pci_init_one,
475 .remove = pc300_pci_remove_one,
478 static int __init pc300_init_module(void)
480 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
481 pr_err("Invalid PCI clock frequency\n");
484 if (use_crystal_clock != 0 && use_crystal_clock != 1) {
485 pr_err("Invalid 'use_crystal_clock' value\n");
489 CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
491 return pci_register_driver(&pc300_pci_driver);
494 static void __exit pc300_cleanup_module(void)
496 pci_unregister_driver(&pc300_pci_driver);
499 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
500 MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
501 MODULE_LICENSE("GPL v2");
502 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
503 module_param(pci_clock_freq, int, 0444);
504 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
505 module_param(use_crystal_clock, int, 0444);
506 MODULE_PARM_DESC(use_crystal_clock,
507 "Use 24.576 MHz clock instead of PCI clock");
508 module_init(pc300_init_module);
509 module_exit(pc300_cleanup_module);