1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
5 * Copyright (C) 2007-2008 Krzysztof HaĆasa <khc@pm.waw.pl>
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/module.h>
11 #include <linux/bitops.h>
12 #include <linux/cdev.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
16 #include <linux/hdlc.h>
18 #include <linux/kernel.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/wan_ixp4xx_hss.h>
21 #include <linux/poll.h>
22 #include <linux/slab.h>
23 #include <linux/soc/ixp4xx/npe.h>
24 #include <linux/soc/ixp4xx/qmgr.h>
25 #include <linux/soc/ixp4xx/cpu.h>
30 #define DEBUG_PKT_BYTES 0
33 #define DRV_NAME "ixp4xx_hss"
35 #define PKT_EXTRA_FLAGS 0 /* orig 1 */
36 #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
37 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
39 #define RX_DESCS 16 /* also length of all RX queues */
40 #define TX_DESCS 16 /* also length of all TX queues */
42 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
43 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
44 #define MAX_CLOSE_WAIT 1000 /* microseconds */
46 #define FRAME_SIZE 256 /* doesn't matter at this point */
47 #define FRAME_OFFSET 0
48 #define MAX_CHANNELS (FRAME_SIZE / 8)
50 #define NAPI_WEIGHT 16
53 #define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
54 #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
55 #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
56 #define HSS0_PKT_TX1_QUEUE 15
57 #define HSS0_PKT_TX2_QUEUE 16
58 #define HSS0_PKT_TX3_QUEUE 17
59 #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
60 #define HSS0_PKT_RXFREE1_QUEUE 19
61 #define HSS0_PKT_RXFREE2_QUEUE 20
62 #define HSS0_PKT_RXFREE3_QUEUE 21
63 #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
65 #define HSS1_CHL_RXTRIG_QUEUE 10
66 #define HSS1_PKT_RX_QUEUE 0
67 #define HSS1_PKT_TX0_QUEUE 5
68 #define HSS1_PKT_TX1_QUEUE 6
69 #define HSS1_PKT_TX2_QUEUE 7
70 #define HSS1_PKT_TX3_QUEUE 8
71 #define HSS1_PKT_RXFREE0_QUEUE 1
72 #define HSS1_PKT_RXFREE1_QUEUE 2
73 #define HSS1_PKT_RXFREE2_QUEUE 3
74 #define HSS1_PKT_RXFREE3_QUEUE 4
75 #define HSS1_PKT_TXDONE_QUEUE 9
77 #define NPE_PKT_MODE_HDLC 0
78 #define NPE_PKT_MODE_RAW 1
79 #define NPE_PKT_MODE_56KMODE 2
80 #define NPE_PKT_MODE_56KENDIAN_MSB 4
82 /* PKT_PIPE_HDLC_CFG_WRITE flags */
83 #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
84 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
85 #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
87 /* hss_config, PCRs */
88 /* Frame sync sampling, default = active low */
89 #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
90 #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
91 #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
93 /* Frame sync pin: input (default) or output generated off a given clk edge */
94 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
95 #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
97 /* Frame and data clock sampling on edge, default = falling */
98 #define PCR_FCLK_EDGE_RISING 0x08000000
99 #define PCR_DCLK_EDGE_RISING 0x04000000
101 /* Clock direction, default = input */
102 #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
104 /* Generate/Receive frame pulses, default = enabled */
105 #define PCR_FRM_PULSE_DISABLED 0x01000000
107 /* Data rate is full (default) or half the configured clk speed */
108 #define PCR_HALF_CLK_RATE 0x00200000
110 /* Invert data between NPE and HSS FIFOs? (default = no) */
111 #define PCR_DATA_POLARITY_INVERT 0x00100000
113 /* TX/RX endianness, default = LSB */
114 #define PCR_MSB_ENDIAN 0x00080000
116 /* Normal (default) / open drain mode (TX only) */
117 #define PCR_TX_PINS_OPEN_DRAIN 0x00040000
119 /* No framing bit transmitted and expected on RX? (default = framing bit) */
120 #define PCR_SOF_NO_FBIT 0x00020000
122 /* Drive data pins? */
123 #define PCR_TX_DATA_ENABLE 0x00010000
125 /* Voice 56k type: drive the data pins low (default), high, high Z */
126 #define PCR_TX_V56K_HIGH 0x00002000
127 #define PCR_TX_V56K_HIGH_IMP 0x00004000
129 /* Unassigned type: drive the data pins low (default), high, high Z */
130 #define PCR_TX_UNASS_HIGH 0x00000800
131 #define PCR_TX_UNASS_HIGH_IMP 0x00001000
133 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
134 #define PCR_TX_FB_HIGH_IMP 0x00000400
136 /* 56k data endiannes - which bit unused: high (default) or low */
137 #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
139 /* 56k data transmission type: 32/8 bit data (default) or 56K data */
140 #define PCR_TX_56KS_56K_DATA 0x00000100
142 /* hss_config, cCR */
143 /* Number of packetized clients, default = 1 */
144 #define CCR_NPE_HFIFO_2_HDLC 0x04000000
145 #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
147 /* default = no loopback */
148 #define CCR_LOOPBACK 0x02000000
150 /* HSS number, default = 0 (first) */
151 #define CCR_SECOND_HSS 0x01000000
153 /* hss_config, clkCR: main:10, num:10, denom:12 */
154 #define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/
156 #define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15)
157 #define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47)
158 #define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192)
159 #define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63)
160 #define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127)
161 #define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255)
163 #define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127)
164 #define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383)
165 #define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385)
166 #define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511)
167 #define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023)
168 #define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047)
170 /* HSS_CONFIG_CLOCK_CR register consists of 3 parts:
171 * A (10 bits), B (10 bits) and C (12 bits).
172 * IXP42x HSS clock generator operation (verified with an oscilloscope):
173 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
174 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
175 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
178 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
179 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
180 * minimum freq = 66.666 MHz / (A + 1)
181 * maximum freq = 66.666 MHz / A
183 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
184 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
185 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
186 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
187 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
188 * The sequence consists of 4 complete clock periods, thus the average
189 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
190 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
193 /* hss_config, LUT entries */
194 #define TDMMAP_UNASSIGNED 0
195 #define TDMMAP_HDLC 1 /* HDLC - packetized */
196 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
197 #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
199 /* offsets into HSS config */
200 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
201 #define HSS_CONFIG_RX_PCR 0x04
202 #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
203 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
204 #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
205 #define HSS_CONFIG_RX_FCR 0x14
206 #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
207 #define HSS_CONFIG_RX_LUT 0x38
209 /* NPE command codes */
210 /* writes the ConfigWord value to the location specified by offset */
211 #define PORT_CONFIG_WRITE 0x40
213 /* triggers the NPE to load the contents of the configuration table */
214 #define PORT_CONFIG_LOAD 0x41
216 /* triggers the NPE to return an HssErrorReadResponse message */
217 #define PORT_ERROR_READ 0x42
219 /* triggers the NPE to reset internal status and enable the HssPacketized
220 * operation for the flow specified by pPipe
222 #define PKT_PIPE_FLOW_ENABLE 0x50
223 #define PKT_PIPE_FLOW_DISABLE 0x51
224 #define PKT_NUM_PIPES_WRITE 0x52
225 #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
226 #define PKT_PIPE_HDLC_CFG_WRITE 0x54
227 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
228 #define PKT_PIPE_RX_SIZE_WRITE 0x56
229 #define PKT_PIPE_MODE_WRITE 0x57
231 /* HDLC packet status values - desc->status */
232 #define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
233 #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
234 #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
235 #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
236 * this packet (if buf_len < pkt_len)
238 #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
239 #define ERR_HDLC_ABORT 6 /* abort sequence received */
240 #define ERR_DISCONNECTING 7 /* disconnect is in progress */
243 typedef struct sk_buff buffer_t;
244 #define free_buffer dev_kfree_skb
245 #define free_buffer_irq dev_consume_skb_irq
247 typedef void buffer_t;
248 #define free_buffer kfree
249 #define free_buffer_irq kfree
255 struct net_device *netdev;
256 struct napi_struct napi;
257 struct hss_plat_info *plat;
258 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
259 struct desc *desc_tab; /* coherent */
260 dma_addr_t desc_tab_phys;
262 unsigned int clock_type, clock_rate, loopback;
263 unsigned int initialized, carrier;
268 /* NPE message structure */
271 u8 cmd, unused, hss_port, index;
273 struct { u8 data8a, data8b, data8c, data8d; };
274 struct { u16 data16a, data16b; };
275 struct { u32 data32; };
278 u8 index, hss_port, unused, cmd;
280 struct { u8 data8d, data8c, data8b, data8a; };
281 struct { u16 data16b, data16a; };
282 struct { u32 data32; };
287 /* HDLC packet descriptor */
289 u32 next; /* pointer to next buffer, unused */
292 u16 buf_len; /* buffer length */
293 u16 pkt_len; /* packet length */
294 u32 data; /* pointer to data buffer in RAM */
299 u16 pkt_len; /* packet length */
300 u16 buf_len; /* buffer length */
301 u32 data; /* pointer to data buffer in RAM */
309 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
310 (n) * sizeof(struct desc))
311 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
313 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
314 ((n) + RX_DESCS) * sizeof(struct desc))
315 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
317 /*****************************************************************************
319 ****************************************************************************/
321 static int ports_open;
322 static struct dma_pool *dma_pool;
323 static DEFINE_SPINLOCK(npe_lock);
325 static const struct {
326 int tx, txdone, rx, rxfree;
327 } queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
328 HSS0_PKT_RXFREE0_QUEUE},
329 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
330 HSS1_PKT_RXFREE0_QUEUE},
333 /*****************************************************************************
335 ****************************************************************************/
337 static inline struct port *dev_to_port(struct net_device *dev)
339 return dev_to_hdlc(dev)->priv;
343 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
347 for (i = 0; i < cnt; i++)
348 dest[i] = swab32(src[i]);
352 /*****************************************************************************
354 ****************************************************************************/
356 static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
358 u32 *val = (u32 *)msg;
360 if (npe_send_message(port->npe, msg, what)) {
361 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
362 port->id, val[0], val[1], npe_name(port->npe));
367 static void hss_config_set_lut(struct port *port)
372 memset(&msg, 0, sizeof(msg));
373 msg.cmd = PORT_CONFIG_WRITE;
374 msg.hss_port = port->id;
376 for (ch = 0; ch < MAX_CHANNELS; ch++) {
378 msg.data32 |= TDMMAP_HDLC << 30;
381 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
382 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
384 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
385 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
390 static void hss_config(struct port *port)
394 memset(&msg, 0, sizeof(msg));
395 msg.cmd = PORT_CONFIG_WRITE;
396 msg.hss_port = port->id;
397 msg.index = HSS_CONFIG_TX_PCR;
398 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
399 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
400 if (port->clock_type == CLOCK_INT)
401 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
402 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
404 msg.index = HSS_CONFIG_RX_PCR;
405 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
406 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
408 memset(&msg, 0, sizeof(msg));
409 msg.cmd = PORT_CONFIG_WRITE;
410 msg.hss_port = port->id;
411 msg.index = HSS_CONFIG_CORE_CR;
412 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
413 (port->id ? CCR_SECOND_HSS : 0);
414 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
416 memset(&msg, 0, sizeof(msg));
417 msg.cmd = PORT_CONFIG_WRITE;
418 msg.hss_port = port->id;
419 msg.index = HSS_CONFIG_CLOCK_CR;
420 msg.data32 = port->clock_reg;
421 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
423 memset(&msg, 0, sizeof(msg));
424 msg.cmd = PORT_CONFIG_WRITE;
425 msg.hss_port = port->id;
426 msg.index = HSS_CONFIG_TX_FCR;
427 msg.data16a = FRAME_OFFSET;
428 msg.data16b = FRAME_SIZE - 1;
429 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
431 memset(&msg, 0, sizeof(msg));
432 msg.cmd = PORT_CONFIG_WRITE;
433 msg.hss_port = port->id;
434 msg.index = HSS_CONFIG_RX_FCR;
435 msg.data16a = FRAME_OFFSET;
436 msg.data16b = FRAME_SIZE - 1;
437 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
439 hss_config_set_lut(port);
441 memset(&msg, 0, sizeof(msg));
442 msg.cmd = PORT_CONFIG_LOAD;
443 msg.hss_port = port->id;
444 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
446 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
447 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
448 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
449 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
453 /* HDLC may stop working without this - check FIXME */
454 npe_recv_message(port->npe, &msg, "FLUSH_IT");
457 static void hss_set_hdlc_cfg(struct port *port)
461 memset(&msg, 0, sizeof(msg));
462 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
463 msg.hss_port = port->id;
464 msg.data8a = port->hdlc_cfg; /* rx_cfg */
465 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
466 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
469 static u32 hss_get_status(struct port *port)
473 memset(&msg, 0, sizeof(msg));
474 msg.cmd = PORT_ERROR_READ;
475 msg.hss_port = port->id;
476 hss_npe_send(port, &msg, "PORT_ERROR_READ");
477 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
478 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
485 static void hss_start_hdlc(struct port *port)
489 memset(&msg, 0, sizeof(msg));
490 msg.cmd = PKT_PIPE_FLOW_ENABLE;
491 msg.hss_port = port->id;
493 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
496 static void hss_stop_hdlc(struct port *port)
500 memset(&msg, 0, sizeof(msg));
501 msg.cmd = PKT_PIPE_FLOW_DISABLE;
502 msg.hss_port = port->id;
503 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
504 hss_get_status(port); /* make sure it's halted */
507 static int hss_load_firmware(struct port *port)
512 if (port->initialized)
515 if (!npe_running(port->npe)) {
516 err = npe_load_firmware(port->npe, npe_name(port->npe),
522 /* HDLC mode configuration */
523 memset(&msg, 0, sizeof(msg));
524 msg.cmd = PKT_NUM_PIPES_WRITE;
525 msg.hss_port = port->id;
526 msg.data8a = PKT_NUM_PIPES;
527 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
529 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
530 msg.data8a = PKT_PIPE_FIFO_SIZEW;
531 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
533 msg.cmd = PKT_PIPE_MODE_WRITE;
534 msg.data8a = NPE_PKT_MODE_HDLC;
535 /* msg.data8b = inv_mask */
536 /* msg.data8c = or_mask */
537 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
539 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
540 msg.data16a = HDLC_MAX_MRU; /* including CRC */
541 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
543 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
544 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
545 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
547 port->initialized = 1;
551 /*****************************************************************************
552 * packetized (HDLC) operation
553 ****************************************************************************/
555 static inline void debug_pkt(struct net_device *dev, const char *func,
561 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
562 for (i = 0; i < len; i++) {
563 if (i >= DEBUG_PKT_BYTES)
565 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
571 static inline void debug_desc(u32 phys, struct desc *desc)
574 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
575 phys, desc->next, desc->buf_len, desc->pkt_len,
576 desc->data, desc->status, desc->error_count);
580 static inline int queue_get_desc(unsigned int queue, struct port *port,
583 u32 phys, tab_phys, n_desc;
586 phys = qmgr_get_entry(queue);
591 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
592 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
593 n_desc = (phys - tab_phys) / sizeof(struct desc);
594 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
595 debug_desc(phys, &tab[n_desc]);
596 BUG_ON(tab[n_desc].next);
600 static inline void queue_put_desc(unsigned int queue, u32 phys,
603 debug_desc(phys, desc);
605 qmgr_put_entry(queue, phys);
606 /* Don't check for queue overflow here, we've allocated sufficient
607 * length and queues >= 32 don't support this check anyway.
611 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
614 dma_unmap_single(&port->netdev->dev, desc->data,
615 desc->buf_len, DMA_TO_DEVICE);
617 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
618 ALIGN((desc->data & 3) + desc->buf_len, 4),
623 static void hss_hdlc_set_carrier(void *pdev, int carrier)
625 struct net_device *netdev = pdev;
626 struct port *port = dev_to_port(netdev);
629 spin_lock_irqsave(&npe_lock, flags);
630 port->carrier = carrier;
631 if (!port->loopback) {
633 netif_carrier_on(netdev);
635 netif_carrier_off(netdev);
637 spin_unlock_irqrestore(&npe_lock, flags);
640 static void hss_hdlc_rx_irq(void *pdev)
642 struct net_device *dev = pdev;
643 struct port *port = dev_to_port(dev);
646 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
648 qmgr_disable_irq(queue_ids[port->id].rx);
649 napi_schedule(&port->napi);
652 static int hss_hdlc_poll(struct napi_struct *napi, int budget)
654 struct port *port = container_of(napi, struct port, napi);
655 struct net_device *dev = port->netdev;
656 unsigned int rxq = queue_ids[port->id].rx;
657 unsigned int rxfreeq = queue_ids[port->id].rxfree;
661 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
664 while (received < budget) {
669 struct sk_buff *temp;
673 n = queue_get_desc(rxq, port, 0);
676 printk(KERN_DEBUG "%s: hss_hdlc_poll"
677 " napi_complete\n", dev->name);
680 qmgr_enable_irq(rxq);
681 if (!qmgr_stat_empty(rxq) &&
682 napi_reschedule(napi)) {
684 printk(KERN_DEBUG "%s: hss_hdlc_poll"
685 " napi_reschedule succeeded\n",
688 qmgr_disable_irq(rxq);
692 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
695 return received; /* all work done */
698 desc = rx_desc_ptr(port, n);
699 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
700 if (desc->error_count)
701 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
702 " errors %u\n", dev->name, desc->status,
706 switch (desc->status) {
709 skb = netdev_alloc_skb(dev, RX_SIZE);
711 phys = dma_map_single(&dev->dev, skb->data,
714 if (dma_mapping_error(&dev->dev, phys)) {
720 skb = netdev_alloc_skb(dev, desc->pkt_len);
723 dev->stats.rx_dropped++;
727 dev->stats.rx_frame_errors++;
728 dev->stats.rx_errors++;
731 dev->stats.rx_crc_errors++;
732 dev->stats.rx_errors++;
734 case ERR_HDLC_TOO_LONG:
735 dev->stats.rx_length_errors++;
736 dev->stats.rx_errors++;
738 default: /* FIXME - remove printk */
739 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
740 desc->status, desc->error_count);
741 dev->stats.rx_errors++;
745 /* put the desc back on RX-ready queue */
746 desc->buf_len = RX_SIZE;
747 desc->pkt_len = desc->status = 0;
748 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
752 /* process received frame */
755 skb = port->rx_buff_tab[n];
756 dma_unmap_single(&dev->dev, desc->data,
757 RX_SIZE, DMA_FROM_DEVICE);
759 dma_sync_single_for_cpu(&dev->dev, desc->data,
760 RX_SIZE, DMA_FROM_DEVICE);
761 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
762 ALIGN(desc->pkt_len, 4) / 4);
764 skb_put(skb, desc->pkt_len);
766 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
768 skb->protocol = hdlc_type_trans(skb, dev);
769 dev->stats.rx_packets++;
770 dev->stats.rx_bytes += skb->len;
771 netif_receive_skb(skb);
773 /* put the new buffer on RX-free queue */
775 port->rx_buff_tab[n] = temp;
778 desc->buf_len = RX_SIZE;
780 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
784 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
786 return received; /* not all work done */
789 static void hss_hdlc_txdone_irq(void *pdev)
791 struct net_device *dev = pdev;
792 struct port *port = dev_to_port(dev);
796 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
798 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
803 desc = tx_desc_ptr(port, n_desc);
805 dev->stats.tx_packets++;
806 dev->stats.tx_bytes += desc->pkt_len;
808 dma_unmap_tx(port, desc);
810 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
811 dev->name, port->tx_buff_tab[n_desc]);
813 free_buffer_irq(port->tx_buff_tab[n_desc]);
814 port->tx_buff_tab[n_desc] = NULL;
816 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
817 queue_put_desc(port->plat->txreadyq,
818 tx_desc_phys(port, n_desc), desc);
819 if (start) { /* TX-ready queue was empty */
821 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
822 " ready\n", dev->name);
824 netif_wake_queue(dev);
829 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
831 struct port *port = dev_to_port(dev);
832 unsigned int txreadyq = port->plat->txreadyq;
833 int len, offset, bytes, n;
839 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
842 if (unlikely(skb->len > HDLC_MAX_MRU)) {
844 dev->stats.tx_errors++;
848 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
852 offset = 0; /* no need to keep alignment */
856 offset = (int)skb->data & 3; /* keep 32-bit alignment */
857 bytes = ALIGN(offset + len, 4);
858 mem = kmalloc(bytes, GFP_ATOMIC);
861 dev->stats.tx_dropped++;
864 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
868 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
869 if (dma_mapping_error(&dev->dev, phys)) {
875 dev->stats.tx_dropped++;
879 n = queue_get_desc(txreadyq, port, 1);
881 desc = tx_desc_ptr(port, n);
884 port->tx_buff_tab[n] = skb;
886 port->tx_buff_tab[n] = mem;
888 desc->data = phys + offset;
889 desc->buf_len = desc->pkt_len = len;
892 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
894 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
896 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
898 netif_stop_queue(dev);
899 /* we could miss TX ready interrupt */
900 if (!qmgr_stat_below_low_watermark(txreadyq)) {
902 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
905 netif_wake_queue(dev);
910 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
915 static int request_hdlc_queues(struct port *port)
919 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
920 "%s:RX-free", port->netdev->name);
924 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
925 "%s:RX", port->netdev->name);
929 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
930 "%s:TX", port->netdev->name);
934 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
935 "%s:TX-ready", port->netdev->name);
939 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
940 "%s:TX-done", port->netdev->name);
946 qmgr_release_queue(port->plat->txreadyq);
948 qmgr_release_queue(queue_ids[port->id].tx);
950 qmgr_release_queue(queue_ids[port->id].rx);
952 qmgr_release_queue(queue_ids[port->id].rxfree);
953 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
958 static void release_hdlc_queues(struct port *port)
960 qmgr_release_queue(queue_ids[port->id].rxfree);
961 qmgr_release_queue(queue_ids[port->id].rx);
962 qmgr_release_queue(queue_ids[port->id].txdone);
963 qmgr_release_queue(queue_ids[port->id].tx);
964 qmgr_release_queue(port->plat->txreadyq);
967 static int init_hdlc_queues(struct port *port)
972 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
973 POOL_ALLOC_SIZE, 32, 0);
978 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL,
979 &port->desc_tab_phys);
982 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
983 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
985 /* Setup RX buffers */
986 for (i = 0; i < RX_DESCS; i++) {
987 struct desc *desc = rx_desc_ptr(port, i);
991 buff = netdev_alloc_skb(port->netdev, RX_SIZE);
996 buff = kmalloc(RX_SIZE, GFP_KERNEL);
1001 desc->buf_len = RX_SIZE;
1002 desc->data = dma_map_single(&port->netdev->dev, data,
1003 RX_SIZE, DMA_FROM_DEVICE);
1004 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1008 port->rx_buff_tab[i] = buff;
1014 static void destroy_hdlc_queues(struct port *port)
1018 if (port->desc_tab) {
1019 for (i = 0; i < RX_DESCS; i++) {
1020 struct desc *desc = rx_desc_ptr(port, i);
1021 buffer_t *buff = port->rx_buff_tab[i];
1024 dma_unmap_single(&port->netdev->dev,
1025 desc->data, RX_SIZE,
1030 for (i = 0; i < TX_DESCS; i++) {
1031 struct desc *desc = tx_desc_ptr(port, i);
1032 buffer_t *buff = port->tx_buff_tab[i];
1035 dma_unmap_tx(port, desc);
1039 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1040 port->desc_tab = NULL;
1043 if (!ports_open && dma_pool) {
1044 dma_pool_destroy(dma_pool);
1049 static int hss_hdlc_open(struct net_device *dev)
1051 struct port *port = dev_to_port(dev);
1052 unsigned long flags;
1055 err = hdlc_open(dev);
1059 err = hss_load_firmware(port);
1061 goto err_hdlc_close;
1063 err = request_hdlc_queues(port);
1065 goto err_hdlc_close;
1067 err = init_hdlc_queues(port);
1069 goto err_destroy_queues;
1071 spin_lock_irqsave(&npe_lock, flags);
1072 if (port->plat->open) {
1073 err = port->plat->open(port->id, dev, hss_hdlc_set_carrier);
1078 spin_unlock_irqrestore(&npe_lock, flags);
1080 /* Populate queues with buffers, no failure after this point */
1081 for (i = 0; i < TX_DESCS; i++)
1082 queue_put_desc(port->plat->txreadyq,
1083 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1085 for (i = 0; i < RX_DESCS; i++)
1086 queue_put_desc(queue_ids[port->id].rxfree,
1087 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1089 napi_enable(&port->napi);
1090 netif_start_queue(dev);
1092 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1093 hss_hdlc_rx_irq, dev);
1095 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1096 hss_hdlc_txdone_irq, dev);
1097 qmgr_enable_irq(queue_ids[port->id].txdone);
1101 hss_set_hdlc_cfg(port);
1104 hss_start_hdlc(port);
1106 /* we may already have RX data, enables IRQ */
1107 napi_schedule(&port->napi);
1111 spin_unlock_irqrestore(&npe_lock, flags);
1113 destroy_hdlc_queues(port);
1114 release_hdlc_queues(port);
1120 static int hss_hdlc_close(struct net_device *dev)
1122 struct port *port = dev_to_port(dev);
1123 unsigned long flags;
1124 int i, buffs = RX_DESCS; /* allocated RX buffers */
1126 spin_lock_irqsave(&npe_lock, flags);
1128 qmgr_disable_irq(queue_ids[port->id].rx);
1129 netif_stop_queue(dev);
1130 napi_disable(&port->napi);
1132 hss_stop_hdlc(port);
1134 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1136 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1140 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1144 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1145 buffs--; /* cancel TX */
1149 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1153 } while (++i < MAX_CLOSE_WAIT);
1156 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1160 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1162 qmgr_disable_irq(queue_ids[port->id].txdone);
1164 if (port->plat->close)
1165 port->plat->close(port->id, dev);
1166 spin_unlock_irqrestore(&npe_lock, flags);
1168 destroy_hdlc_queues(port);
1169 release_hdlc_queues(port);
1174 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1175 unsigned short parity)
1177 struct port *port = dev_to_port(dev);
1179 if (encoding != ENCODING_NRZ)
1183 case PARITY_CRC16_PR1_CCITT:
1187 case PARITY_CRC32_PR1_CCITT:
1188 port->hdlc_cfg = PKT_HDLC_CRC_32;
1196 static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1197 u32 *best, u32 *best_diff, u32 *reg)
1199 /* a is 10-bit, b is 10-bit, c is 12-bit */
1203 new_rate = timer_freq * (u64)(c + 1);
1204 do_div(new_rate, a * (c + 1) + b + 1);
1205 new_diff = abs((u32)new_rate - rate);
1207 if (new_diff < *best_diff) {
1209 *best_diff = new_diff;
1210 *reg = (a << 22) | (b << 12) | c;
1215 static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1217 u32 a, b, diff = 0xFFFFFFFF;
1219 a = timer_freq / rate;
1221 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1222 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1225 if (a == 0) { /* > 66.666 MHz */
1226 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1230 if (rate * a == timer_freq) { /* don't divide by 0 later */
1231 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1235 for (b = 0; b < 0x400; b++) {
1236 u64 c = (b + 1) * (u64)rate;
1238 do_div(c, timer_freq - rate * a);
1240 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1241 if (b == 0 && /* also try a bit higher rate */
1242 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1245 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1249 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1251 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1257 static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
1259 const size_t size = sizeof(sync_serial_settings);
1260 sync_serial_settings new_line;
1261 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1262 struct port *port = dev_to_port(dev);
1263 unsigned long flags;
1266 switch (ifs->type) {
1268 ifs->type = IF_IFACE_V35;
1269 if (ifs->size < size) {
1270 ifs->size = size; /* data size wanted */
1273 memset(&new_line, 0, sizeof(new_line));
1274 new_line.clock_type = port->clock_type;
1275 new_line.clock_rate = port->clock_rate;
1276 new_line.loopback = port->loopback;
1277 if (copy_to_user(line, &new_line, size))
1281 case IF_IFACE_SYNC_SERIAL:
1283 if (!capable(CAP_NET_ADMIN))
1285 if (copy_from_user(&new_line, line, size))
1288 clk = new_line.clock_type;
1289 if (port->plat->set_clock)
1290 clk = port->plat->set_clock(port->id, clk);
1292 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1293 return -EINVAL; /* No such clock setting */
1295 if (new_line.loopback != 0 && new_line.loopback != 1)
1298 port->clock_type = clk; /* Update settings */
1299 if (clk == CLOCK_INT) {
1300 find_best_clock(port->plat->timer_freq,
1301 new_line.clock_rate,
1302 &port->clock_rate, &port->clock_reg);
1304 port->clock_rate = 0;
1305 port->clock_reg = CLK42X_SPEED_2048KHZ;
1307 port->loopback = new_line.loopback;
1309 spin_lock_irqsave(&npe_lock, flags);
1311 if (dev->flags & IFF_UP)
1314 if (port->loopback || port->carrier)
1315 netif_carrier_on(port->netdev);
1317 netif_carrier_off(port->netdev);
1318 spin_unlock_irqrestore(&npe_lock, flags);
1323 return hdlc_ioctl(dev, ifs);
1327 /*****************************************************************************
1329 ****************************************************************************/
1331 static const struct net_device_ops hss_hdlc_ops = {
1332 .ndo_open = hss_hdlc_open,
1333 .ndo_stop = hss_hdlc_close,
1334 .ndo_start_xmit = hdlc_start_xmit,
1335 .ndo_siocwandev = hss_hdlc_ioctl,
1338 static int hss_init_one(struct platform_device *pdev)
1341 struct net_device *dev;
1345 port = kzalloc(sizeof(*port), GFP_KERNEL);
1349 port->npe = npe_request(0);
1355 dev = alloc_hdlcdev(port);
1356 port->netdev = alloc_hdlcdev(port);
1357 if (!port->netdev) {
1362 SET_NETDEV_DEV(dev, &pdev->dev);
1363 hdlc = dev_to_hdlc(dev);
1364 hdlc->attach = hss_hdlc_attach;
1365 hdlc->xmit = hss_hdlc_xmit;
1366 dev->netdev_ops = &hss_hdlc_ops;
1367 dev->tx_queue_len = 100;
1368 port->clock_type = CLOCK_EXT;
1369 port->clock_rate = 0;
1370 port->clock_reg = CLK42X_SPEED_2048KHZ;
1371 port->id = pdev->id;
1372 port->dev = &pdev->dev;
1373 port->plat = pdev->dev.platform_data;
1374 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1376 err = register_hdlc_device(dev);
1378 goto err_free_netdev;
1380 platform_set_drvdata(pdev, port);
1382 netdev_info(dev, "initialized\n");
1388 npe_release(port->npe);
1394 static int hss_remove_one(struct platform_device *pdev)
1396 struct port *port = platform_get_drvdata(pdev);
1398 unregister_hdlc_device(port->netdev);
1399 free_netdev(port->netdev);
1400 npe_release(port->npe);
1405 static struct platform_driver ixp4xx_hss_driver = {
1406 .driver.name = DRV_NAME,
1407 .probe = hss_init_one,
1408 .remove = hss_remove_one,
1411 static int __init hss_init_module(void)
1413 if ((ixp4xx_read_feature_bits() &
1414 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1415 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1418 return platform_driver_register(&ixp4xx_hss_driver);
1421 static void __exit hss_cleanup_module(void)
1423 platform_driver_unregister(&ixp4xx_hss_driver);
1426 MODULE_AUTHOR("Krzysztof Halasa");
1427 MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1428 MODULE_LICENSE("GPL v2");
1429 MODULE_ALIAS("platform:ixp4xx_hss");
1430 module_init(hss_init_module);
1431 module_exit(hss_cleanup_module);