2 * Linux driver for VMware's vmxnet3 ethernet NIC.
4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
23 * Maintained by: pv-drivers@vmware.com
27 #include <linux/module.h>
28 #include <net/ip6_checksum.h>
30 #include "vmxnet3_int.h"
32 char vmxnet3_driver_name[] = "vmxnet3";
33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
37 * Last entry must be all 0s
39 static const struct pci_device_id vmxnet3_pciid_table[] = {
40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
46 static int enable_mq = 1;
49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
52 * Enable/Disable the given intr
55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
69 * Enable/Disable all intrs used by the device
72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
135 * Check the link state. This may start or stop the tx queue.
138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
144 spin_lock_irqsave(&adapter->cmd_lock, flags);
145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
153 netif_carrier_on(adapter->netdev);
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
161 netdev_info(adapter->netdev, "NIC Link is Down\n");
162 netif_carrier_off(adapter->netdev);
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
172 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
176 u32 events = le32_to_cpu(adapter->shared->ecr);
180 vmxnet3_ack_events(adapter, events);
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
184 vmxnet3_check_link(adapter, true);
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
188 spin_lock_irqsave(&adapter->cmd_lock, flags);
189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
206 schedule_work(&adapter->work);
210 #ifdef __BIG_ENDIAN_BITFIELD
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
244 *dst = cpu_to_le32(*src);
249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
263 /* Used to read bitfield values from double words. */
264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
275 #endif /* __BIG_ENDIAN_BITFIELD */
277 #ifdef __BIG_ENDIAN_BITFIELD
279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
308 #endif /* __BIG_ENDIAN_BITFIELD */
312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
339 skb = tq->buf_info[eop_idx].skb;
341 tq->buf_info[eop_idx].skb = NULL;
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
358 dev_kfree_skb_any(skb);
364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
368 union Vmxnet3_GenericDesc *gdesc;
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 /* Prevent any &gdesc->tcd field from being (speculatively)
373 * read before (&gdesc->tcd)->gen is read.
377 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
378 &gdesc->tcd), tq, adapter->pdev,
381 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
386 spin_lock(&tq->tx_lock);
387 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
388 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
389 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
390 netif_carrier_ok(adapter->netdev))) {
391 vmxnet3_tq_wake(tq, adapter);
393 spin_unlock(&tq->tx_lock);
400 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
401 struct vmxnet3_adapter *adapter)
405 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
406 struct vmxnet3_tx_buf_info *tbi;
408 tbi = tq->buf_info + tq->tx_ring.next2comp;
410 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
412 dev_kfree_skb_any(tbi->skb);
415 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
418 /* sanity check, verify all buffers are indeed unmapped and freed */
419 for (i = 0; i < tq->tx_ring.size; i++) {
420 BUG_ON(tq->buf_info[i].skb != NULL ||
421 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
424 tq->tx_ring.gen = VMXNET3_INIT_GEN;
425 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
427 tq->comp_ring.gen = VMXNET3_INIT_GEN;
428 tq->comp_ring.next2proc = 0;
433 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
434 struct vmxnet3_adapter *adapter)
436 if (tq->tx_ring.base) {
437 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
438 sizeof(struct Vmxnet3_TxDesc),
439 tq->tx_ring.base, tq->tx_ring.basePA);
440 tq->tx_ring.base = NULL;
442 if (tq->data_ring.base) {
443 dma_free_coherent(&adapter->pdev->dev,
444 tq->data_ring.size * tq->txdata_desc_size,
445 tq->data_ring.base, tq->data_ring.basePA);
446 tq->data_ring.base = NULL;
448 if (tq->comp_ring.base) {
449 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
450 sizeof(struct Vmxnet3_TxCompDesc),
451 tq->comp_ring.base, tq->comp_ring.basePA);
452 tq->comp_ring.base = NULL;
459 /* Destroy all tx queues */
461 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
465 for (i = 0; i < adapter->num_tx_queues; i++)
466 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
471 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
472 struct vmxnet3_adapter *adapter)
476 /* reset the tx ring contents to 0 and reset the tx ring states */
477 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
478 sizeof(struct Vmxnet3_TxDesc));
479 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
480 tq->tx_ring.gen = VMXNET3_INIT_GEN;
482 memset(tq->data_ring.base, 0,
483 tq->data_ring.size * tq->txdata_desc_size);
485 /* reset the tx comp ring contents to 0 and reset comp ring states */
486 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
487 sizeof(struct Vmxnet3_TxCompDesc));
488 tq->comp_ring.next2proc = 0;
489 tq->comp_ring.gen = VMXNET3_INIT_GEN;
491 /* reset the bookkeeping data */
492 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
493 for (i = 0; i < tq->tx_ring.size; i++)
494 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
496 /* stats are not reset */
501 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
502 struct vmxnet3_adapter *adapter)
504 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
505 tq->comp_ring.base || tq->buf_info);
507 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
508 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
509 &tq->tx_ring.basePA, GFP_KERNEL);
510 if (!tq->tx_ring.base) {
511 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
515 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
516 tq->data_ring.size * tq->txdata_desc_size,
517 &tq->data_ring.basePA, GFP_KERNEL);
518 if (!tq->data_ring.base) {
519 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
523 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
524 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
525 &tq->comp_ring.basePA, GFP_KERNEL);
526 if (!tq->comp_ring.base) {
527 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
531 tq->buf_info = kcalloc_node(tq->tx_ring.size, sizeof(tq->buf_info[0]),
533 dev_to_node(&adapter->pdev->dev));
540 vmxnet3_tq_destroy(tq, adapter);
545 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
549 for (i = 0; i < adapter->num_tx_queues; i++)
550 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
554 * starting from ring->next2fill, allocate rx buffers for the given ring
555 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
556 * are allocated or allocation fails
560 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
561 int num_to_alloc, struct vmxnet3_adapter *adapter)
563 int num_allocated = 0;
564 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
565 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
568 while (num_allocated <= num_to_alloc) {
569 struct vmxnet3_rx_buf_info *rbi;
570 union Vmxnet3_GenericDesc *gd;
572 rbi = rbi_base + ring->next2fill;
573 gd = ring->base + ring->next2fill;
575 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
576 if (rbi->skb == NULL) {
577 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
580 if (unlikely(rbi->skb == NULL)) {
581 rq->stats.rx_buf_alloc_failure++;
585 rbi->dma_addr = dma_map_single(
587 rbi->skb->data, rbi->len,
589 if (dma_mapping_error(&adapter->pdev->dev,
591 dev_kfree_skb_any(rbi->skb);
592 rq->stats.rx_buf_alloc_failure++;
596 /* rx buffer skipped by the device */
598 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
600 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
601 rbi->len != PAGE_SIZE);
603 if (rbi->page == NULL) {
604 rbi->page = alloc_page(GFP_ATOMIC);
605 if (unlikely(rbi->page == NULL)) {
606 rq->stats.rx_buf_alloc_failure++;
609 rbi->dma_addr = dma_map_page(
611 rbi->page, 0, PAGE_SIZE,
613 if (dma_mapping_error(&adapter->pdev->dev,
616 rq->stats.rx_buf_alloc_failure++;
620 /* rx buffers skipped by the device */
622 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
625 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
626 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
629 /* Fill the last buffer but dont mark it ready, or else the
630 * device will think that the queue is full */
631 if (num_allocated == num_to_alloc)
634 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
636 vmxnet3_cmd_ring_adv_next2fill(ring);
639 netdev_dbg(adapter->netdev,
640 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
641 num_allocated, ring->next2fill, ring->next2comp);
643 /* so that the device can distinguish a full ring and an empty ring */
644 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
646 return num_allocated;
651 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
652 struct vmxnet3_rx_buf_info *rbi)
654 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
656 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
658 __skb_frag_set_page(frag, rbi->page);
659 skb_frag_off_set(frag, 0);
660 skb_frag_size_set(frag, rcd->len);
661 skb->data_len += rcd->len;
662 skb->truesize += PAGE_SIZE;
663 skb_shinfo(skb)->nr_frags++;
668 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
669 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
670 struct vmxnet3_adapter *adapter)
673 unsigned long buf_offset;
675 union Vmxnet3_GenericDesc *gdesc;
676 struct vmxnet3_tx_buf_info *tbi = NULL;
678 BUG_ON(ctx->copy_size > skb_headlen(skb));
680 /* use the previous gen bit for the SOP desc */
681 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
683 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
684 gdesc = ctx->sop_txd; /* both loops below can be skipped */
686 /* no need to map the buffer if headers are copied */
687 if (ctx->copy_size) {
688 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
689 tq->tx_ring.next2fill *
690 tq->txdata_desc_size);
691 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
692 ctx->sop_txd->dword[3] = 0;
694 tbi = tq->buf_info + tq->tx_ring.next2fill;
695 tbi->map_type = VMXNET3_MAP_NONE;
697 netdev_dbg(adapter->netdev,
698 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
699 tq->tx_ring.next2fill,
700 le64_to_cpu(ctx->sop_txd->txd.addr),
701 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
702 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
704 /* use the right gen for non-SOP desc */
705 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
708 /* linear part can use multiple tx desc if it's big */
709 len = skb_headlen(skb) - ctx->copy_size;
710 buf_offset = ctx->copy_size;
714 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
718 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
719 /* spec says that for TxDesc.len, 0 == 2^14 */
722 tbi = tq->buf_info + tq->tx_ring.next2fill;
723 tbi->map_type = VMXNET3_MAP_SINGLE;
724 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
725 skb->data + buf_offset, buf_size,
727 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
732 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
733 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
735 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
736 gdesc->dword[2] = cpu_to_le32(dw2);
739 netdev_dbg(adapter->netdev,
740 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
741 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
742 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
743 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
744 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
747 buf_offset += buf_size;
750 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
751 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
755 len = skb_frag_size(frag);
757 tbi = tq->buf_info + tq->tx_ring.next2fill;
758 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
762 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
763 /* spec says that for TxDesc.len, 0 == 2^14 */
765 tbi->map_type = VMXNET3_MAP_PAGE;
766 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
767 buf_offset, buf_size,
769 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
774 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
775 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
777 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
778 gdesc->dword[2] = cpu_to_le32(dw2);
781 netdev_dbg(adapter->netdev,
782 "txd[%u]: 0x%llx %u %u\n",
783 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
784 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
785 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
786 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
789 buf_offset += buf_size;
793 ctx->eop_txd = gdesc;
795 /* set the last buf_info for the pkt */
797 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
803 /* Init all tx queues */
805 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
809 for (i = 0; i < adapter->num_tx_queues; i++)
810 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
815 * parse relevant protocol headers:
816 * For a tso pkt, relevant headers are L2/3/4 including options
817 * For a pkt requesting csum offloading, they are L2/3 and may include L4
818 * if it's a TCP/UDP pkt
821 * -1: error happens during parsing
822 * 0: protocol headers parsed, but too big to be copied
823 * 1: protocol headers parsed and copied
826 * 1. related *ctx fields are updated.
827 * 2. ctx->copy_size is # of bytes copied
828 * 3. the portion to be copied is guaranteed to be in the linear part
832 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
833 struct vmxnet3_tx_ctx *ctx,
834 struct vmxnet3_adapter *adapter)
838 if (ctx->mss) { /* TSO */
839 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
840 ctx->l4_offset = skb_inner_transport_offset(skb);
841 ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
842 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
844 ctx->l4_offset = skb_transport_offset(skb);
845 ctx->l4_hdr_size = tcp_hdrlen(skb);
846 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
849 if (skb->ip_summed == CHECKSUM_PARTIAL) {
850 /* For encap packets, skb_checksum_start_offset refers
851 * to inner L4 offset. Thus, below works for encap as
852 * well as non-encap case
854 ctx->l4_offset = skb_checksum_start_offset(skb);
856 if (VMXNET3_VERSION_GE_4(adapter) &&
857 skb->encapsulation) {
858 struct iphdr *iph = inner_ip_hdr(skb);
860 if (iph->version == 4) {
861 protocol = iph->protocol;
863 const struct ipv6hdr *ipv6h;
865 ipv6h = inner_ipv6_hdr(skb);
866 protocol = ipv6h->nexthdr;
870 const struct iphdr *iph = ip_hdr(skb);
872 protocol = iph->protocol;
873 } else if (ctx->ipv6) {
874 const struct ipv6hdr *ipv6h;
876 ipv6h = ipv6_hdr(skb);
877 protocol = ipv6h->nexthdr;
883 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
887 ctx->l4_hdr_size = sizeof(struct udphdr);
890 ctx->l4_hdr_size = 0;
894 ctx->copy_size = min(ctx->l4_offset +
895 ctx->l4_hdr_size, skb->len);
898 ctx->l4_hdr_size = 0;
899 /* copy as much as allowed */
900 ctx->copy_size = min_t(unsigned int,
901 tq->txdata_desc_size,
905 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
906 ctx->copy_size = skb->len;
908 /* make sure headers are accessible directly */
909 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
913 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
914 tq->stats.oversized_hdr++;
925 * copy relevant protocol headers to the transmit ring:
926 * For a tso pkt, relevant headers are L2/3/4 including options
927 * For a pkt requesting csum offloading, they are L2/3 and may include L4
928 * if it's a TCP/UDP pkt
931 * Note that this requires that vmxnet3_parse_hdr be called first to set the
932 * appropriate bits in ctx first
935 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
936 struct vmxnet3_tx_ctx *ctx,
937 struct vmxnet3_adapter *adapter)
939 struct Vmxnet3_TxDataDesc *tdd;
941 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
942 tq->tx_ring.next2fill *
943 tq->txdata_desc_size);
945 memcpy(tdd->data, skb->data, ctx->copy_size);
946 netdev_dbg(adapter->netdev,
947 "copy %u bytes to dataRing[%u]\n",
948 ctx->copy_size, tq->tx_ring.next2fill);
953 vmxnet3_prepare_inner_tso(struct sk_buff *skb,
954 struct vmxnet3_tx_ctx *ctx)
956 struct tcphdr *tcph = inner_tcp_hdr(skb);
957 struct iphdr *iph = inner_ip_hdr(skb);
959 if (iph->version == 4) {
961 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
964 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
966 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
972 vmxnet3_prepare_tso(struct sk_buff *skb,
973 struct vmxnet3_tx_ctx *ctx)
975 struct tcphdr *tcph = tcp_hdr(skb);
978 struct iphdr *iph = ip_hdr(skb);
981 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
983 } else if (ctx->ipv6) {
984 tcp_v6_gso_csum_prep(skb);
988 static int txd_estimate(const struct sk_buff *skb)
990 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
993 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
994 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
996 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1002 * Transmits a pkt thru a given tq
1004 * NETDEV_TX_OK: descriptors are setup successfully
1005 * NETDEV_TX_OK: error occurred, the pkt is dropped
1006 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
1009 * 1. tx ring may be changed
1010 * 2. tq stats may be updated accordingly
1011 * 3. shared->txNumDeferred may be updated
1015 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1016 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1021 int tx_num_deferred;
1022 unsigned long flags;
1023 struct vmxnet3_tx_ctx ctx;
1024 union Vmxnet3_GenericDesc *gdesc;
1025 #ifdef __BIG_ENDIAN_BITFIELD
1026 /* Use temporary descriptor to avoid touching bits multiple times */
1027 union Vmxnet3_GenericDesc tempTxDesc;
1030 count = txd_estimate(skb);
1032 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1033 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1035 ctx.mss = skb_shinfo(skb)->gso_size;
1037 if (skb_header_cloned(skb)) {
1038 if (unlikely(pskb_expand_head(skb, 0, 0,
1039 GFP_ATOMIC) != 0)) {
1040 tq->stats.drop_tso++;
1043 tq->stats.copy_skb_header++;
1045 if (skb->encapsulation) {
1046 vmxnet3_prepare_inner_tso(skb, &ctx);
1048 vmxnet3_prepare_tso(skb, &ctx);
1051 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1053 /* non-tso pkts must not use more than
1054 * VMXNET3_MAX_TXD_PER_PKT entries
1056 if (skb_linearize(skb) != 0) {
1057 tq->stats.drop_too_many_frags++;
1060 tq->stats.linearized++;
1062 /* recalculate the # of descriptors to use */
1063 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1067 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1069 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1070 /* hdrs parsed, check against other limits */
1072 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1073 VMXNET3_MAX_TX_BUF_SIZE)) {
1074 tq->stats.drop_oversized_hdr++;
1078 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1079 if (unlikely(ctx.l4_offset +
1081 VMXNET3_MAX_CSUM_OFFSET)) {
1082 tq->stats.drop_oversized_hdr++;
1088 tq->stats.drop_hdr_inspect_err++;
1092 spin_lock_irqsave(&tq->tx_lock, flags);
1094 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1095 tq->stats.tx_ring_full++;
1096 netdev_dbg(adapter->netdev,
1097 "tx queue stopped on %s, next2comp %u"
1098 " next2fill %u\n", adapter->netdev->name,
1099 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1101 vmxnet3_tq_stop(tq, adapter);
1102 spin_unlock_irqrestore(&tq->tx_lock, flags);
1103 return NETDEV_TX_BUSY;
1107 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1109 /* fill tx descs related to addr & len */
1110 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1111 goto unlock_drop_pkt;
1113 /* setup the EOP desc */
1114 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1116 /* setup the SOP desc */
1117 #ifdef __BIG_ENDIAN_BITFIELD
1118 gdesc = &tempTxDesc;
1119 gdesc->dword[2] = ctx.sop_txd->dword[2];
1120 gdesc->dword[3] = ctx.sop_txd->dword[3];
1122 gdesc = ctx.sop_txd;
1124 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1126 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1127 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1128 gdesc->txd.om = VMXNET3_OM_ENCAP;
1129 gdesc->txd.msscof = ctx.mss;
1131 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1134 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1135 gdesc->txd.om = VMXNET3_OM_TSO;
1136 gdesc->txd.msscof = ctx.mss;
1138 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1140 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1141 if (VMXNET3_VERSION_GE_4(adapter) &&
1142 skb->encapsulation) {
1143 gdesc->txd.hlen = ctx.l4_offset +
1145 gdesc->txd.om = VMXNET3_OM_ENCAP;
1146 gdesc->txd.msscof = 0; /* Reserved */
1148 gdesc->txd.hlen = ctx.l4_offset;
1149 gdesc->txd.om = VMXNET3_OM_CSUM;
1150 gdesc->txd.msscof = ctx.l4_offset +
1155 gdesc->txd.msscof = 0;
1159 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1160 tx_num_deferred += num_pkts;
1162 if (skb_vlan_tag_present(skb)) {
1164 gdesc->txd.tci = skb_vlan_tag_get(skb);
1167 /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1168 * all other writes to &gdesc->txd.
1172 /* finally flips the GEN bit of the SOP desc. */
1173 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1175 #ifdef __BIG_ENDIAN_BITFIELD
1176 /* Finished updating in bitfields of Tx Desc, so write them in original
1179 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1180 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1181 gdesc = ctx.sop_txd;
1183 netdev_dbg(adapter->netdev,
1184 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1186 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1187 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1189 spin_unlock_irqrestore(&tq->tx_lock, flags);
1191 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1192 tq->shared->txNumDeferred = 0;
1193 VMXNET3_WRITE_BAR0_REG(adapter,
1194 VMXNET3_REG_TXPROD + tq->qid * 8,
1195 tq->tx_ring.next2fill);
1198 return NETDEV_TX_OK;
1201 spin_unlock_irqrestore(&tq->tx_lock, flags);
1203 tq->stats.drop_total++;
1204 dev_kfree_skb_any(skb);
1205 return NETDEV_TX_OK;
1210 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1212 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1214 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1215 return vmxnet3_tq_xmit(skb,
1216 &adapter->tx_queue[skb->queue_mapping],
1222 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1223 struct sk_buff *skb,
1224 union Vmxnet3_GenericDesc *gdesc)
1226 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1227 if (gdesc->rcd.v4 &&
1228 (le32_to_cpu(gdesc->dword[3]) &
1229 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1230 skb->ip_summed = CHECKSUM_UNNECESSARY;
1231 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1232 !(le32_to_cpu(gdesc->dword[0]) &
1233 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1234 WARN_ON_ONCE(gdesc->rcd.frg &&
1235 !(le32_to_cpu(gdesc->dword[0]) &
1236 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1237 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1238 (1 << VMXNET3_RCD_TUC_SHIFT))) {
1239 skb->ip_summed = CHECKSUM_UNNECESSARY;
1240 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1241 !(le32_to_cpu(gdesc->dword[0]) &
1242 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1243 WARN_ON_ONCE(gdesc->rcd.frg &&
1244 !(le32_to_cpu(gdesc->dword[0]) &
1245 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1247 if (gdesc->rcd.csum) {
1248 skb->csum = htons(gdesc->rcd.csum);
1249 skb->ip_summed = CHECKSUM_PARTIAL;
1251 skb_checksum_none_assert(skb);
1255 skb_checksum_none_assert(skb);
1261 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1262 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1264 rq->stats.drop_err++;
1266 rq->stats.drop_fcs++;
1268 rq->stats.drop_total++;
1271 * We do not unmap and chain the rx buffer to the skb.
1272 * We basically pretend this buffer is not used and will be recycled
1273 * by vmxnet3_rq_alloc_rx_buf()
1277 * ctx->skb may be NULL if this is the first and the only one
1281 dev_kfree_skb_irq(ctx->skb);
1288 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1289 union Vmxnet3_GenericDesc *gdesc)
1295 struct vlan_ethhdr *veth;
1297 struct ipv6hdr *ipv6;
1300 BUG_ON(gdesc->rcd.tcp == 0);
1302 maplen = skb_headlen(skb);
1303 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1306 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1307 skb->protocol == cpu_to_be16(ETH_P_8021AD))
1308 hlen = sizeof(struct vlan_ethhdr);
1310 hlen = sizeof(struct ethhdr);
1312 hdr.eth = eth_hdr(skb);
1313 if (gdesc->rcd.v4) {
1314 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1315 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1317 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1318 hlen = hdr.ipv4->ihl << 2;
1319 hdr.ptr += hdr.ipv4->ihl << 2;
1320 } else if (gdesc->rcd.v6) {
1321 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1322 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1324 /* Use an estimated value, since we also need to handle
1327 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1328 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1329 hlen = sizeof(struct ipv6hdr);
1330 hdr.ptr += sizeof(struct ipv6hdr);
1332 /* Non-IP pkt, dont estimate header length */
1336 if (hlen + sizeof(struct tcphdr) > maplen)
1339 return (hlen + (hdr.tcp->doff << 2));
1343 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1344 struct vmxnet3_adapter *adapter, int quota)
1346 static const u32 rxprod_reg[2] = {
1347 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1350 bool skip_page_frags = false;
1351 struct Vmxnet3_RxCompDesc *rcd;
1352 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1353 u16 segCnt = 0, mss = 0;
1354 #ifdef __BIG_ENDIAN_BITFIELD
1355 struct Vmxnet3_RxDesc rxCmdDesc;
1356 struct Vmxnet3_RxCompDesc rxComp;
1358 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1360 while (rcd->gen == rq->comp_ring.gen) {
1361 struct vmxnet3_rx_buf_info *rbi;
1362 struct sk_buff *skb, *new_skb = NULL;
1363 struct page *new_page = NULL;
1364 dma_addr_t new_dma_addr;
1366 struct Vmxnet3_RxDesc *rxd;
1368 struct vmxnet3_cmd_ring *ring = NULL;
1369 if (num_pkts >= quota) {
1370 /* we may stop even before we see the EOP desc of
1376 /* Prevent any rcd field from being (speculatively) read before
1381 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1382 rcd->rqID != rq->dataRingQid);
1384 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1385 ring = rq->rx_ring + ring_idx;
1386 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1388 rbi = rq->buf_info[ring_idx] + idx;
1390 BUG_ON(rxd->addr != rbi->dma_addr ||
1391 rxd->len != rbi->len);
1393 if (unlikely(rcd->eop && rcd->err)) {
1394 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1398 if (rcd->sop) { /* first buf of the pkt */
1399 bool rxDataRingUsed;
1402 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1403 (rcd->rqID != rq->qid &&
1404 rcd->rqID != rq->dataRingQid));
1406 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1407 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1409 if (unlikely(rcd->len == 0)) {
1410 /* Pretend the rx buffer is skipped. */
1411 BUG_ON(!(rcd->sop && rcd->eop));
1412 netdev_dbg(adapter->netdev,
1413 "rxRing[%u][%u] 0 length\n",
1418 skip_page_frags = false;
1419 ctx->skb = rbi->skb;
1422 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1423 len = rxDataRingUsed ? rcd->len : rbi->len;
1424 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1426 if (new_skb == NULL) {
1427 /* Skb allocation failed, do not handover this
1428 * skb to stack. Reuse it. Drop the existing pkt
1430 rq->stats.rx_buf_alloc_failure++;
1432 rq->stats.drop_total++;
1433 skip_page_frags = true;
1437 if (rxDataRingUsed) {
1440 BUG_ON(rcd->len > rq->data_ring.desc_size);
1443 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1444 memcpy(new_skb->data,
1445 &rq->data_ring.base[sz], rcd->len);
1447 ctx->skb = rbi->skb;
1450 dma_map_single(&adapter->pdev->dev,
1451 new_skb->data, rbi->len,
1452 PCI_DMA_FROMDEVICE);
1453 if (dma_mapping_error(&adapter->pdev->dev,
1455 dev_kfree_skb(new_skb);
1456 /* Skb allocation failed, do not
1457 * handover this skb to stack. Reuse
1458 * it. Drop the existing pkt.
1460 rq->stats.rx_buf_alloc_failure++;
1462 rq->stats.drop_total++;
1463 skip_page_frags = true;
1467 dma_unmap_single(&adapter->pdev->dev,
1470 PCI_DMA_FROMDEVICE);
1472 /* Immediate refill */
1474 rbi->dma_addr = new_dma_addr;
1475 rxd->addr = cpu_to_le64(rbi->dma_addr);
1476 rxd->len = rbi->len;
1480 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1481 (adapter->netdev->features & NETIF_F_RXHASH))
1482 skb_set_hash(ctx->skb,
1483 le32_to_cpu(rcd->rssHash),
1486 skb_put(ctx->skb, rcd->len);
1488 if (VMXNET3_VERSION_GE_2(adapter) &&
1489 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1490 struct Vmxnet3_RxCompDescExt *rcdlro;
1491 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1493 segCnt = rcdlro->segCnt;
1494 WARN_ON_ONCE(segCnt == 0);
1496 if (unlikely(segCnt <= 1))
1502 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1504 /* non SOP buffer must be type 1 in most cases */
1505 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1506 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1508 /* If an sop buffer was dropped, skip all
1509 * following non-sop fragments. They will be reused.
1511 if (skip_page_frags)
1515 new_page = alloc_page(GFP_ATOMIC);
1516 /* Replacement page frag could not be allocated.
1517 * Reuse this page. Drop the pkt and free the
1518 * skb which contained this page as a frag. Skip
1519 * processing all the following non-sop frags.
1521 if (unlikely(!new_page)) {
1522 rq->stats.rx_buf_alloc_failure++;
1523 dev_kfree_skb(ctx->skb);
1525 skip_page_frags = true;
1528 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1531 PCI_DMA_FROMDEVICE);
1532 if (dma_mapping_error(&adapter->pdev->dev,
1535 rq->stats.rx_buf_alloc_failure++;
1536 dev_kfree_skb(ctx->skb);
1538 skip_page_frags = true;
1542 dma_unmap_page(&adapter->pdev->dev,
1543 rbi->dma_addr, rbi->len,
1544 PCI_DMA_FROMDEVICE);
1546 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1548 /* Immediate refill */
1549 rbi->page = new_page;
1550 rbi->dma_addr = new_dma_addr;
1551 rxd->addr = cpu_to_le64(rbi->dma_addr);
1552 rxd->len = rbi->len;
1559 u32 mtu = adapter->netdev->mtu;
1560 skb->len += skb->data_len;
1562 vmxnet3_rx_csum(adapter, skb,
1563 (union Vmxnet3_GenericDesc *)rcd);
1564 skb->protocol = eth_type_trans(skb, adapter->netdev);
1566 !(adapter->netdev->features & NETIF_F_LRO))
1569 if (segCnt != 0 && mss != 0) {
1570 skb_shinfo(skb)->gso_type = rcd->v4 ?
1571 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1572 skb_shinfo(skb)->gso_size = mss;
1573 skb_shinfo(skb)->gso_segs = segCnt;
1574 } else if (segCnt != 0 || skb->len > mtu) {
1577 hlen = vmxnet3_get_hdr_len(adapter, skb,
1578 (union Vmxnet3_GenericDesc *)rcd);
1582 skb_shinfo(skb)->gso_type =
1583 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1585 skb_shinfo(skb)->gso_segs = segCnt;
1586 skb_shinfo(skb)->gso_size =
1587 DIV_ROUND_UP(skb->len -
1590 skb_shinfo(skb)->gso_size = mtu - hlen;
1594 if (unlikely(rcd->ts))
1595 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1597 if (adapter->netdev->features & NETIF_F_LRO)
1598 netif_receive_skb(skb);
1600 napi_gro_receive(&rq->napi, skb);
1607 /* device may have skipped some rx descs */
1608 ring->next2comp = idx;
1609 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1610 ring = rq->rx_ring + ring_idx;
1612 /* Ensure that the writes to rxd->gen bits will be observed
1613 * after all other writes to rxd objects.
1617 while (num_to_alloc) {
1618 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1622 /* Recv desc is ready to be used by the device */
1623 rxd->gen = ring->gen;
1624 vmxnet3_cmd_ring_adv_next2fill(ring);
1628 /* if needed, update the register */
1629 if (unlikely(rq->shared->updateRxProd)) {
1630 VMXNET3_WRITE_BAR0_REG(adapter,
1631 rxprod_reg[ring_idx] + rq->qid * 8,
1635 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1636 vmxnet3_getRxComp(rcd,
1637 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1645 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1646 struct vmxnet3_adapter *adapter)
1649 struct Vmxnet3_RxDesc *rxd;
1651 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1652 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1653 #ifdef __BIG_ENDIAN_BITFIELD
1654 struct Vmxnet3_RxDesc rxDesc;
1656 vmxnet3_getRxDesc(rxd,
1657 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1659 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1660 rq->buf_info[ring_idx][i].skb) {
1661 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1662 rxd->len, PCI_DMA_FROMDEVICE);
1663 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1664 rq->buf_info[ring_idx][i].skb = NULL;
1665 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1666 rq->buf_info[ring_idx][i].page) {
1667 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1668 rxd->len, PCI_DMA_FROMDEVICE);
1669 put_page(rq->buf_info[ring_idx][i].page);
1670 rq->buf_info[ring_idx][i].page = NULL;
1674 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1675 rq->rx_ring[ring_idx].next2fill =
1676 rq->rx_ring[ring_idx].next2comp = 0;
1679 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1680 rq->comp_ring.next2proc = 0;
1685 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1689 for (i = 0; i < adapter->num_rx_queues; i++)
1690 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1694 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1695 struct vmxnet3_adapter *adapter)
1700 /* all rx buffers must have already been freed */
1701 for (i = 0; i < 2; i++) {
1702 if (rq->buf_info[i]) {
1703 for (j = 0; j < rq->rx_ring[i].size; j++)
1704 BUG_ON(rq->buf_info[i][j].page != NULL);
1709 for (i = 0; i < 2; i++) {
1710 if (rq->rx_ring[i].base) {
1711 dma_free_coherent(&adapter->pdev->dev,
1713 * sizeof(struct Vmxnet3_RxDesc),
1714 rq->rx_ring[i].base,
1715 rq->rx_ring[i].basePA);
1716 rq->rx_ring[i].base = NULL;
1720 if (rq->data_ring.base) {
1721 dma_free_coherent(&adapter->pdev->dev,
1722 rq->rx_ring[0].size * rq->data_ring.desc_size,
1723 rq->data_ring.base, rq->data_ring.basePA);
1724 rq->data_ring.base = NULL;
1727 if (rq->comp_ring.base) {
1728 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1729 * sizeof(struct Vmxnet3_RxCompDesc),
1730 rq->comp_ring.base, rq->comp_ring.basePA);
1731 rq->comp_ring.base = NULL;
1734 kfree(rq->buf_info[0]);
1735 rq->buf_info[0] = NULL;
1736 rq->buf_info[1] = NULL;
1740 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1744 for (i = 0; i < adapter->num_rx_queues; i++) {
1745 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1747 if (rq->data_ring.base) {
1748 dma_free_coherent(&adapter->pdev->dev,
1749 (rq->rx_ring[0].size *
1750 rq->data_ring.desc_size),
1752 rq->data_ring.basePA);
1753 rq->data_ring.base = NULL;
1754 rq->data_ring.desc_size = 0;
1760 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1761 struct vmxnet3_adapter *adapter)
1765 /* initialize buf_info */
1766 for (i = 0; i < rq->rx_ring[0].size; i++) {
1768 /* 1st buf for a pkt is skbuff */
1769 if (i % adapter->rx_buf_per_pkt == 0) {
1770 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1771 rq->buf_info[0][i].len = adapter->skb_buf_size;
1772 } else { /* subsequent bufs for a pkt is frag */
1773 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1774 rq->buf_info[0][i].len = PAGE_SIZE;
1777 for (i = 0; i < rq->rx_ring[1].size; i++) {
1778 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1779 rq->buf_info[1][i].len = PAGE_SIZE;
1782 /* reset internal state and allocate buffers for both rings */
1783 for (i = 0; i < 2; i++) {
1784 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1786 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1787 sizeof(struct Vmxnet3_RxDesc));
1788 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1790 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1792 /* at least has 1 rx buffer for the 1st ring */
1795 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1797 /* reset the comp ring */
1798 rq->comp_ring.next2proc = 0;
1799 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1800 sizeof(struct Vmxnet3_RxCompDesc));
1801 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1804 rq->rx_ctx.skb = NULL;
1806 /* stats are not reset */
1812 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1816 for (i = 0; i < adapter->num_rx_queues; i++) {
1817 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1818 if (unlikely(err)) {
1819 dev_err(&adapter->netdev->dev, "%s: failed to "
1820 "initialize rx queue%i\n",
1821 adapter->netdev->name, i);
1831 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1835 struct vmxnet3_rx_buf_info *bi;
1837 for (i = 0; i < 2; i++) {
1839 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1840 rq->rx_ring[i].base = dma_alloc_coherent(
1841 &adapter->pdev->dev, sz,
1842 &rq->rx_ring[i].basePA,
1844 if (!rq->rx_ring[i].base) {
1845 netdev_err(adapter->netdev,
1846 "failed to allocate rx ring %d\n", i);
1851 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1852 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1853 rq->data_ring.base =
1854 dma_alloc_coherent(&adapter->pdev->dev, sz,
1855 &rq->data_ring.basePA,
1857 if (!rq->data_ring.base) {
1858 netdev_err(adapter->netdev,
1859 "rx data ring will be disabled\n");
1860 adapter->rxdataring_enabled = false;
1863 rq->data_ring.base = NULL;
1864 rq->data_ring.desc_size = 0;
1867 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1868 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1869 &rq->comp_ring.basePA,
1871 if (!rq->comp_ring.base) {
1872 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1876 bi = kcalloc_node(rq->rx_ring[0].size + rq->rx_ring[1].size,
1877 sizeof(rq->buf_info[0][0]), GFP_KERNEL,
1878 dev_to_node(&adapter->pdev->dev));
1882 rq->buf_info[0] = bi;
1883 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1888 vmxnet3_rq_destroy(rq, adapter);
1894 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1898 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1900 for (i = 0; i < adapter->num_rx_queues; i++) {
1901 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1902 if (unlikely(err)) {
1903 dev_err(&adapter->netdev->dev,
1904 "%s: failed to create rx queue%i\n",
1905 adapter->netdev->name, i);
1910 if (!adapter->rxdataring_enabled)
1911 vmxnet3_rq_destroy_all_rxdataring(adapter);
1915 vmxnet3_rq_destroy_all(adapter);
1920 /* Multiple queue aware polling function for tx and rx */
1923 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1925 int rcd_done = 0, i;
1926 if (unlikely(adapter->shared->ecr))
1927 vmxnet3_process_events(adapter);
1928 for (i = 0; i < adapter->num_tx_queues; i++)
1929 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1931 for (i = 0; i < adapter->num_rx_queues; i++)
1932 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1939 vmxnet3_poll(struct napi_struct *napi, int budget)
1941 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1942 struct vmxnet3_rx_queue, napi);
1945 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1947 if (rxd_done < budget) {
1948 napi_complete_done(napi, rxd_done);
1949 vmxnet3_enable_all_intrs(rx_queue->adapter);
1955 * NAPI polling function for MSI-X mode with multiple Rx queues
1956 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1960 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1962 struct vmxnet3_rx_queue *rq = container_of(napi,
1963 struct vmxnet3_rx_queue, napi);
1964 struct vmxnet3_adapter *adapter = rq->adapter;
1967 /* When sharing interrupt with corresponding tx queue, process
1968 * tx completions in that queue as well
1970 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1971 struct vmxnet3_tx_queue *tq =
1972 &adapter->tx_queue[rq - adapter->rx_queue];
1973 vmxnet3_tq_tx_complete(tq, adapter);
1976 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
1978 if (rxd_done < budget) {
1979 napi_complete_done(napi, rxd_done);
1980 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
1986 #ifdef CONFIG_PCI_MSI
1989 * Handle completion interrupts on tx queues
1990 * Returns whether or not the intr is handled
1994 vmxnet3_msix_tx(int irq, void *data)
1996 struct vmxnet3_tx_queue *tq = data;
1997 struct vmxnet3_adapter *adapter = tq->adapter;
1999 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2000 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2002 /* Handle the case where only one irq is allocate for all tx queues */
2003 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2005 for (i = 0; i < adapter->num_tx_queues; i++) {
2006 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2007 vmxnet3_tq_tx_complete(txq, adapter);
2010 vmxnet3_tq_tx_complete(tq, adapter);
2012 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2019 * Handle completion interrupts on rx queues. Returns whether or not the
2024 vmxnet3_msix_rx(int irq, void *data)
2026 struct vmxnet3_rx_queue *rq = data;
2027 struct vmxnet3_adapter *adapter = rq->adapter;
2029 /* disable intr if needed */
2030 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2031 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2032 napi_schedule(&rq->napi);
2038 *----------------------------------------------------------------------------
2040 * vmxnet3_msix_event --
2042 * vmxnet3 msix event intr handler
2045 * whether or not the intr is handled
2047 *----------------------------------------------------------------------------
2051 vmxnet3_msix_event(int irq, void *data)
2053 struct net_device *dev = data;
2054 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2056 /* disable intr if needed */
2057 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2058 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2060 if (adapter->shared->ecr)
2061 vmxnet3_process_events(adapter);
2063 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2068 #endif /* CONFIG_PCI_MSI */
2071 /* Interrupt handler for vmxnet3 */
2073 vmxnet3_intr(int irq, void *dev_id)
2075 struct net_device *dev = dev_id;
2076 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2078 if (adapter->intr.type == VMXNET3_IT_INTX) {
2079 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2080 if (unlikely(icr == 0))
2086 /* disable intr if needed */
2087 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2088 vmxnet3_disable_all_intrs(adapter);
2090 napi_schedule(&adapter->rx_queue[0].napi);
2095 #ifdef CONFIG_NET_POLL_CONTROLLER
2097 /* netpoll callback. */
2099 vmxnet3_netpoll(struct net_device *netdev)
2101 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2103 switch (adapter->intr.type) {
2104 #ifdef CONFIG_PCI_MSI
2105 case VMXNET3_IT_MSIX: {
2107 for (i = 0; i < adapter->num_rx_queues; i++)
2108 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2112 case VMXNET3_IT_MSI:
2114 vmxnet3_intr(0, adapter->netdev);
2119 #endif /* CONFIG_NET_POLL_CONTROLLER */
2122 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2124 struct vmxnet3_intr *intr = &adapter->intr;
2128 #ifdef CONFIG_PCI_MSI
2129 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2130 for (i = 0; i < adapter->num_tx_queues; i++) {
2131 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2132 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2133 adapter->netdev->name, vector);
2135 intr->msix_entries[vector].vector,
2137 adapter->tx_queue[i].name,
2138 &adapter->tx_queue[i]);
2140 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2141 adapter->netdev->name, vector);
2144 dev_err(&adapter->netdev->dev,
2145 "Failed to request irq for MSIX, %s, "
2147 adapter->tx_queue[i].name, err);
2151 /* Handle the case where only 1 MSIx was allocated for
2153 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2154 for (; i < adapter->num_tx_queues; i++)
2155 adapter->tx_queue[i].comp_ring.intr_idx
2160 adapter->tx_queue[i].comp_ring.intr_idx
2164 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2167 for (i = 0; i < adapter->num_rx_queues; i++) {
2168 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2169 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2170 adapter->netdev->name, vector);
2172 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2173 adapter->netdev->name, vector);
2174 err = request_irq(intr->msix_entries[vector].vector,
2176 adapter->rx_queue[i].name,
2177 &(adapter->rx_queue[i]));
2179 netdev_err(adapter->netdev,
2180 "Failed to request irq for MSIX, "
2182 adapter->rx_queue[i].name, err);
2186 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2189 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2190 adapter->netdev->name, vector);
2191 err = request_irq(intr->msix_entries[vector].vector,
2192 vmxnet3_msix_event, 0,
2193 intr->event_msi_vector_name, adapter->netdev);
2194 intr->event_intr_idx = vector;
2196 } else if (intr->type == VMXNET3_IT_MSI) {
2197 adapter->num_rx_queues = 1;
2198 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2199 adapter->netdev->name, adapter->netdev);
2202 adapter->num_rx_queues = 1;
2203 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2204 IRQF_SHARED, adapter->netdev->name,
2206 #ifdef CONFIG_PCI_MSI
2209 intr->num_intrs = vector + 1;
2211 netdev_err(adapter->netdev,
2212 "Failed to request irq (intr type:%d), error %d\n",
2215 /* Number of rx queues will not change after this */
2216 for (i = 0; i < adapter->num_rx_queues; i++) {
2217 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2219 rq->qid2 = i + adapter->num_rx_queues;
2220 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2223 /* init our intr settings */
2224 for (i = 0; i < intr->num_intrs; i++)
2225 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2226 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2227 adapter->intr.event_intr_idx = 0;
2228 for (i = 0; i < adapter->num_tx_queues; i++)
2229 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2230 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2233 netdev_info(adapter->netdev,
2234 "intr type %u, mode %u, %u vectors allocated\n",
2235 intr->type, intr->mask_mode, intr->num_intrs);
2243 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2245 struct vmxnet3_intr *intr = &adapter->intr;
2246 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2248 switch (intr->type) {
2249 #ifdef CONFIG_PCI_MSI
2250 case VMXNET3_IT_MSIX:
2254 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2255 for (i = 0; i < adapter->num_tx_queues; i++) {
2256 free_irq(intr->msix_entries[vector++].vector,
2257 &(adapter->tx_queue[i]));
2258 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2263 for (i = 0; i < adapter->num_rx_queues; i++) {
2264 free_irq(intr->msix_entries[vector++].vector,
2265 &(adapter->rx_queue[i]));
2268 free_irq(intr->msix_entries[vector].vector,
2270 BUG_ON(vector >= intr->num_intrs);
2274 case VMXNET3_IT_MSI:
2275 free_irq(adapter->pdev->irq, adapter->netdev);
2277 case VMXNET3_IT_INTX:
2278 free_irq(adapter->pdev->irq, adapter->netdev);
2287 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2289 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2292 /* allow untagged pkts */
2293 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2295 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2296 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2301 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2303 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2305 if (!(netdev->flags & IFF_PROMISC)) {
2306 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2307 unsigned long flags;
2309 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2310 spin_lock_irqsave(&adapter->cmd_lock, flags);
2311 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2312 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2313 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2316 set_bit(vid, adapter->active_vlans);
2323 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2325 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2327 if (!(netdev->flags & IFF_PROMISC)) {
2328 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2329 unsigned long flags;
2331 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2332 spin_lock_irqsave(&adapter->cmd_lock, flags);
2333 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2334 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2335 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2338 clear_bit(vid, adapter->active_vlans);
2345 vmxnet3_copy_mc(struct net_device *netdev)
2348 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2350 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2352 /* We may be called with BH disabled */
2353 buf = kmalloc(sz, GFP_ATOMIC);
2355 struct netdev_hw_addr *ha;
2358 netdev_for_each_mc_addr(ha, netdev)
2359 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2368 vmxnet3_set_mc(struct net_device *netdev)
2370 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2371 unsigned long flags;
2372 struct Vmxnet3_RxFilterConf *rxConf =
2373 &adapter->shared->devRead.rxFilterConf;
2374 u8 *new_table = NULL;
2375 dma_addr_t new_table_pa = 0;
2376 bool new_table_pa_valid = false;
2377 u32 new_mode = VMXNET3_RXM_UCAST;
2379 if (netdev->flags & IFF_PROMISC) {
2380 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2381 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2383 new_mode |= VMXNET3_RXM_PROMISC;
2385 vmxnet3_restore_vlan(adapter);
2388 if (netdev->flags & IFF_BROADCAST)
2389 new_mode |= VMXNET3_RXM_BCAST;
2391 if (netdev->flags & IFF_ALLMULTI)
2392 new_mode |= VMXNET3_RXM_ALL_MULTI;
2394 if (!netdev_mc_empty(netdev)) {
2395 new_table = vmxnet3_copy_mc(netdev);
2397 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2399 rxConf->mfTableLen = cpu_to_le16(sz);
2400 new_table_pa = dma_map_single(
2401 &adapter->pdev->dev,
2405 if (!dma_mapping_error(&adapter->pdev->dev,
2407 new_mode |= VMXNET3_RXM_MCAST;
2408 new_table_pa_valid = true;
2409 rxConf->mfTablePA = cpu_to_le64(
2413 if (!new_table_pa_valid) {
2415 "failed to copy mcast list, setting ALL_MULTI\n");
2416 new_mode |= VMXNET3_RXM_ALL_MULTI;
2420 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2421 rxConf->mfTableLen = 0;
2422 rxConf->mfTablePA = 0;
2425 spin_lock_irqsave(&adapter->cmd_lock, flags);
2426 if (new_mode != rxConf->rxMode) {
2427 rxConf->rxMode = cpu_to_le32(new_mode);
2428 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2429 VMXNET3_CMD_UPDATE_RX_MODE);
2430 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2431 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2434 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2435 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2436 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2438 if (new_table_pa_valid)
2439 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2440 rxConf->mfTableLen, PCI_DMA_TODEVICE);
2445 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2449 for (i = 0; i < adapter->num_rx_queues; i++)
2450 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2455 * Set up driver_shared based on settings in adapter.
2459 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2461 struct Vmxnet3_DriverShared *shared = adapter->shared;
2462 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2463 struct Vmxnet3_TxQueueConf *tqc;
2464 struct Vmxnet3_RxQueueConf *rqc;
2467 memset(shared, 0, sizeof(*shared));
2469 /* driver settings */
2470 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2471 devRead->misc.driverInfo.version = cpu_to_le32(
2472 VMXNET3_DRIVER_VERSION_NUM);
2473 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2474 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2475 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2476 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2477 *((u32 *)&devRead->misc.driverInfo.gos));
2478 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2479 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2481 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2482 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2484 /* set up feature flags */
2485 if (adapter->netdev->features & NETIF_F_RXCSUM)
2486 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2488 if (adapter->netdev->features & NETIF_F_LRO) {
2489 devRead->misc.uptFeatures |= UPT1_F_LRO;
2490 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2492 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2493 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2495 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2496 NETIF_F_GSO_UDP_TUNNEL_CSUM))
2497 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2499 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2500 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2501 devRead->misc.queueDescLen = cpu_to_le32(
2502 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2503 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2505 /* tx queue settings */
2506 devRead->misc.numTxQueues = adapter->num_tx_queues;
2507 for (i = 0; i < adapter->num_tx_queues; i++) {
2508 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2509 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2510 tqc = &adapter->tqd_start[i].conf;
2511 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2512 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2513 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2514 tqc->ddPA = cpu_to_le64(~0ULL);
2515 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2516 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2517 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2518 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2519 tqc->ddLen = cpu_to_le32(0);
2520 tqc->intrIdx = tq->comp_ring.intr_idx;
2523 /* rx queue settings */
2524 devRead->misc.numRxQueues = adapter->num_rx_queues;
2525 for (i = 0; i < adapter->num_rx_queues; i++) {
2526 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2527 rqc = &adapter->rqd_start[i].conf;
2528 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2529 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2530 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2531 rqc->ddPA = cpu_to_le64(~0ULL);
2532 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2533 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2534 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2535 rqc->ddLen = cpu_to_le32(0);
2536 rqc->intrIdx = rq->comp_ring.intr_idx;
2537 if (VMXNET3_VERSION_GE_3(adapter)) {
2538 rqc->rxDataRingBasePA =
2539 cpu_to_le64(rq->data_ring.basePA);
2540 rqc->rxDataRingDescSize =
2541 cpu_to_le16(rq->data_ring.desc_size);
2546 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2549 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2551 devRead->misc.uptFeatures |= UPT1_F_RSS;
2552 devRead->misc.numRxQueues = adapter->num_rx_queues;
2553 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2554 UPT1_RSS_HASH_TYPE_IPV4 |
2555 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2556 UPT1_RSS_HASH_TYPE_IPV6;
2557 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2558 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2559 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2560 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2562 for (i = 0; i < rssConf->indTableSize; i++)
2563 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2564 i, adapter->num_rx_queues);
2566 devRead->rssConfDesc.confVer = 1;
2567 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2568 devRead->rssConfDesc.confPA =
2569 cpu_to_le64(adapter->rss_conf_pa);
2572 #endif /* VMXNET3_RSS */
2575 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2577 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2578 for (i = 0; i < adapter->intr.num_intrs; i++)
2579 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2581 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2582 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2584 /* rx filter settings */
2585 devRead->rxFilterConf.rxMode = 0;
2586 vmxnet3_restore_vlan(adapter);
2587 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2589 /* the rest are already zeroed */
2593 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2595 struct Vmxnet3_DriverShared *shared = adapter->shared;
2596 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2597 unsigned long flags;
2599 if (!VMXNET3_VERSION_GE_3(adapter))
2602 spin_lock_irqsave(&adapter->cmd_lock, flags);
2603 cmdInfo->varConf.confVer = 1;
2604 cmdInfo->varConf.confLen =
2605 cpu_to_le32(sizeof(*adapter->coal_conf));
2606 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2608 if (adapter->default_coal_mode) {
2609 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2610 VMXNET3_CMD_GET_COALESCE);
2612 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2613 VMXNET3_CMD_SET_COALESCE);
2616 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2620 vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2622 struct Vmxnet3_DriverShared *shared = adapter->shared;
2623 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2624 unsigned long flags;
2626 if (!VMXNET3_VERSION_GE_4(adapter))
2629 spin_lock_irqsave(&adapter->cmd_lock, flags);
2631 if (adapter->default_rss_fields) {
2632 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2633 VMXNET3_CMD_GET_RSS_FIELDS);
2634 adapter->rss_fields =
2635 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2637 cmdInfo->setRssFields = adapter->rss_fields;
2638 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2639 VMXNET3_CMD_SET_RSS_FIELDS);
2640 /* Not all requested RSS may get applied, so get and
2641 * cache what was actually applied.
2643 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2644 VMXNET3_CMD_GET_RSS_FIELDS);
2645 adapter->rss_fields =
2646 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2649 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2653 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2657 unsigned long flags;
2659 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2660 " ring sizes %u %u %u\n", adapter->netdev->name,
2661 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2662 adapter->tx_queue[0].tx_ring.size,
2663 adapter->rx_queue[0].rx_ring[0].size,
2664 adapter->rx_queue[0].rx_ring[1].size);
2666 vmxnet3_tq_init_all(adapter);
2667 err = vmxnet3_rq_init_all(adapter);
2669 netdev_err(adapter->netdev,
2670 "Failed to init rx queue error %d\n", err);
2674 err = vmxnet3_request_irqs(adapter);
2676 netdev_err(adapter->netdev,
2677 "Failed to setup irq for error %d\n", err);
2681 vmxnet3_setup_driver_shared(adapter);
2683 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2684 adapter->shared_pa));
2685 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2686 adapter->shared_pa));
2687 spin_lock_irqsave(&adapter->cmd_lock, flags);
2688 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2689 VMXNET3_CMD_ACTIVATE_DEV);
2690 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2691 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2694 netdev_err(adapter->netdev,
2695 "Failed to activate dev: error %u\n", ret);
2700 vmxnet3_init_coalesce(adapter);
2701 vmxnet3_init_rssfields(adapter);
2703 for (i = 0; i < adapter->num_rx_queues; i++) {
2704 VMXNET3_WRITE_BAR0_REG(adapter,
2705 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2706 adapter->rx_queue[i].rx_ring[0].next2fill);
2707 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2708 (i * VMXNET3_REG_ALIGN)),
2709 adapter->rx_queue[i].rx_ring[1].next2fill);
2712 /* Apply the rx filter settins last. */
2713 vmxnet3_set_mc(adapter->netdev);
2716 * Check link state when first activating device. It will start the
2717 * tx queue if the link is up.
2719 vmxnet3_check_link(adapter, true);
2720 for (i = 0; i < adapter->num_rx_queues; i++)
2721 napi_enable(&adapter->rx_queue[i].napi);
2722 vmxnet3_enable_all_intrs(adapter);
2723 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2727 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2728 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2729 vmxnet3_free_irqs(adapter);
2732 /* free up buffers we allocated */
2733 vmxnet3_rq_cleanup_all(adapter);
2739 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2741 unsigned long flags;
2742 spin_lock_irqsave(&adapter->cmd_lock, flags);
2743 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2744 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2749 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2752 unsigned long flags;
2753 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2757 spin_lock_irqsave(&adapter->cmd_lock, flags);
2758 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2759 VMXNET3_CMD_QUIESCE_DEV);
2760 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2761 vmxnet3_disable_all_intrs(adapter);
2763 for (i = 0; i < adapter->num_rx_queues; i++)
2764 napi_disable(&adapter->rx_queue[i].napi);
2765 netif_tx_disable(adapter->netdev);
2766 adapter->link_speed = 0;
2767 netif_carrier_off(adapter->netdev);
2769 vmxnet3_tq_cleanup_all(adapter);
2770 vmxnet3_rq_cleanup_all(adapter);
2771 vmxnet3_free_irqs(adapter);
2777 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2782 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2784 tmp = (mac[5] << 8) | mac[4];
2785 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2790 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2792 struct sockaddr *addr = p;
2793 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2795 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2796 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2802 /* ==================== initialization and cleanup routines ============ */
2805 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
2808 unsigned long mmio_start, mmio_len;
2809 struct pci_dev *pdev = adapter->pdev;
2811 err = pci_enable_device(pdev);
2813 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2817 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2818 vmxnet3_driver_name);
2821 "Failed to request region for adapter: error %d\n", err);
2822 goto err_enable_device;
2825 pci_set_master(pdev);
2827 mmio_start = pci_resource_start(pdev, 0);
2828 mmio_len = pci_resource_len(pdev, 0);
2829 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2830 if (!adapter->hw_addr0) {
2831 dev_err(&pdev->dev, "Failed to map bar0\n");
2836 mmio_start = pci_resource_start(pdev, 1);
2837 mmio_len = pci_resource_len(pdev, 1);
2838 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2839 if (!adapter->hw_addr1) {
2840 dev_err(&pdev->dev, "Failed to map bar1\n");
2847 iounmap(adapter->hw_addr0);
2849 pci_release_selected_regions(pdev, (1 << 2) - 1);
2851 pci_disable_device(pdev);
2857 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2859 BUG_ON(!adapter->pdev);
2861 iounmap(adapter->hw_addr0);
2862 iounmap(adapter->hw_addr1);
2863 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2864 pci_disable_device(adapter->pdev);
2869 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2871 size_t sz, i, ring0_size, ring1_size, comp_size;
2872 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2873 VMXNET3_MAX_ETH_HDR_SIZE) {
2874 adapter->skb_buf_size = adapter->netdev->mtu +
2875 VMXNET3_MAX_ETH_HDR_SIZE;
2876 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2877 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2879 adapter->rx_buf_per_pkt = 1;
2881 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2882 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2883 VMXNET3_MAX_ETH_HDR_SIZE;
2884 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2888 * for simplicity, force the ring0 size to be a multiple of
2889 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2891 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2892 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2893 ring0_size = (ring0_size + sz - 1) / sz * sz;
2894 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2896 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2897 ring1_size = (ring1_size + sz - 1) / sz * sz;
2898 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2900 comp_size = ring0_size + ring1_size;
2902 for (i = 0; i < adapter->num_rx_queues; i++) {
2903 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2905 rq->rx_ring[0].size = ring0_size;
2906 rq->rx_ring[1].size = ring1_size;
2907 rq->comp_ring.size = comp_size;
2913 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2914 u32 rx_ring_size, u32 rx_ring2_size,
2915 u16 txdata_desc_size, u16 rxdata_desc_size)
2919 for (i = 0; i < adapter->num_tx_queues; i++) {
2920 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2921 tq->tx_ring.size = tx_ring_size;
2922 tq->data_ring.size = tx_ring_size;
2923 tq->comp_ring.size = tx_ring_size;
2924 tq->txdata_desc_size = txdata_desc_size;
2925 tq->shared = &adapter->tqd_start[i].ctrl;
2927 tq->adapter = adapter;
2929 err = vmxnet3_tq_create(tq, adapter);
2931 * Too late to change num_tx_queues. We cannot do away with
2932 * lesser number of queues than what we asked for
2938 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2939 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2940 vmxnet3_adjust_rx_ring_size(adapter);
2942 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
2943 for (i = 0; i < adapter->num_rx_queues; i++) {
2944 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2945 /* qid and qid2 for rx queues will be assigned later when num
2946 * of rx queues is finalized after allocating intrs */
2947 rq->shared = &adapter->rqd_start[i].ctrl;
2948 rq->adapter = adapter;
2949 rq->data_ring.desc_size = rxdata_desc_size;
2950 err = vmxnet3_rq_create(rq, adapter);
2953 netdev_err(adapter->netdev,
2954 "Could not allocate any rx queues. "
2958 netdev_info(adapter->netdev,
2959 "Number of rx queues changed "
2961 adapter->num_rx_queues = i;
2968 if (!adapter->rxdataring_enabled)
2969 vmxnet3_rq_destroy_all_rxdataring(adapter);
2973 vmxnet3_tq_destroy_all(adapter);
2978 vmxnet3_open(struct net_device *netdev)
2980 struct vmxnet3_adapter *adapter;
2983 adapter = netdev_priv(netdev);
2985 for (i = 0; i < adapter->num_tx_queues; i++)
2986 spin_lock_init(&adapter->tx_queue[i].tx_lock);
2988 if (VMXNET3_VERSION_GE_3(adapter)) {
2989 unsigned long flags;
2990 u16 txdata_desc_size;
2992 spin_lock_irqsave(&adapter->cmd_lock, flags);
2993 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2994 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
2995 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
2997 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2999 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3000 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3001 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3002 adapter->txdata_desc_size =
3003 sizeof(struct Vmxnet3_TxDataDesc);
3005 adapter->txdata_desc_size = txdata_desc_size;
3008 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3011 err = vmxnet3_create_queues(adapter,
3012 adapter->tx_ring_size,
3013 adapter->rx_ring_size,
3014 adapter->rx_ring2_size,
3015 adapter->txdata_desc_size,
3016 adapter->rxdata_desc_size);
3020 err = vmxnet3_activate_dev(adapter);
3027 vmxnet3_rq_destroy_all(adapter);
3028 vmxnet3_tq_destroy_all(adapter);
3035 vmxnet3_close(struct net_device *netdev)
3037 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3040 * Reset_work may be in the middle of resetting the device, wait for its
3043 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3044 usleep_range(1000, 2000);
3046 vmxnet3_quiesce_dev(adapter);
3048 vmxnet3_rq_destroy_all(adapter);
3049 vmxnet3_tq_destroy_all(adapter);
3051 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3059 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3064 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3065 * vmxnet3_close() will deadlock.
3067 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3069 /* we need to enable NAPI, otherwise dev_close will deadlock */
3070 for (i = 0; i < adapter->num_rx_queues; i++)
3071 napi_enable(&adapter->rx_queue[i].napi);
3073 * Need to clear the quiesce bit to ensure that vmxnet3_close
3074 * can quiesce the device properly
3076 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3077 dev_close(adapter->netdev);
3082 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3084 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3087 netdev->mtu = new_mtu;
3090 * Reset_work may be in the middle of resetting the device, wait for its
3093 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3094 usleep_range(1000, 2000);
3096 if (netif_running(netdev)) {
3097 vmxnet3_quiesce_dev(adapter);
3098 vmxnet3_reset_dev(adapter);
3100 /* we need to re-create the rx queue based on the new mtu */
3101 vmxnet3_rq_destroy_all(adapter);
3102 vmxnet3_adjust_rx_ring_size(adapter);
3103 err = vmxnet3_rq_create_all(adapter);
3106 "failed to re-create rx queues, "
3107 " error %d. Closing it.\n", err);
3111 err = vmxnet3_activate_dev(adapter);
3114 "failed to re-activate, error %d. "
3115 "Closing it\n", err);
3121 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3123 vmxnet3_force_close(adapter);
3130 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3132 struct net_device *netdev = adapter->netdev;
3134 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3135 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3136 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3139 if (VMXNET3_VERSION_GE_4(adapter)) {
3140 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3141 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3143 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3144 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3145 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3146 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3147 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3151 netdev->hw_features |= NETIF_F_HIGHDMA;
3152 netdev->vlan_features = netdev->hw_features &
3153 ~(NETIF_F_HW_VLAN_CTAG_TX |
3154 NETIF_F_HW_VLAN_CTAG_RX);
3155 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3160 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3164 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3167 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3168 mac[4] = tmp & 0xff;
3169 mac[5] = (tmp >> 8) & 0xff;
3172 #ifdef CONFIG_PCI_MSI
3175 * Enable MSIx vectors.
3177 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3179 * number of vectors which were enabled otherwise (this number is greater
3180 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3184 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3186 int ret = pci_enable_msix_range(adapter->pdev,
3187 adapter->intr.msix_entries, nvec, nvec);
3189 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3190 dev_err(&adapter->netdev->dev,
3191 "Failed to enable %d MSI-X, trying %d\n",
3192 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3194 ret = pci_enable_msix_range(adapter->pdev,
3195 adapter->intr.msix_entries,
3196 VMXNET3_LINUX_MIN_MSIX_VECT,
3197 VMXNET3_LINUX_MIN_MSIX_VECT);
3201 dev_err(&adapter->netdev->dev,
3202 "Failed to enable MSI-X, error: %d\n", ret);
3209 #endif /* CONFIG_PCI_MSI */
3212 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3215 unsigned long flags;
3218 spin_lock_irqsave(&adapter->cmd_lock, flags);
3219 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3220 VMXNET3_CMD_GET_CONF_INTR);
3221 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3222 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3223 adapter->intr.type = cfg & 0x3;
3224 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3226 if (adapter->intr.type == VMXNET3_IT_AUTO) {
3227 adapter->intr.type = VMXNET3_IT_MSIX;
3230 #ifdef CONFIG_PCI_MSI
3231 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3234 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3235 1 : adapter->num_tx_queues;
3236 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3237 0 : adapter->num_rx_queues;
3238 nvec += 1; /* for link event */
3239 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3240 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3242 for (i = 0; i < nvec; i++)
3243 adapter->intr.msix_entries[i].entry = i;
3245 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3249 /* If we cannot allocate one MSIx vector per queue
3250 * then limit the number of rx queues to 1
3252 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
3253 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3254 || adapter->num_rx_queues != 1) {
3255 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3256 netdev_err(adapter->netdev,
3257 "Number of rx queues : 1\n");
3258 adapter->num_rx_queues = 1;
3262 adapter->intr.num_intrs = nvec;
3266 /* If we cannot allocate MSIx vectors use only one rx queue */
3267 dev_info(&adapter->pdev->dev,
3268 "Failed to enable MSI-X, error %d. "
3269 "Limiting #rx queues to 1, try MSI.\n", nvec);
3271 adapter->intr.type = VMXNET3_IT_MSI;
3274 if (adapter->intr.type == VMXNET3_IT_MSI) {
3275 if (!pci_enable_msi(adapter->pdev)) {
3276 adapter->num_rx_queues = 1;
3277 adapter->intr.num_intrs = 1;
3281 #endif /* CONFIG_PCI_MSI */
3283 adapter->num_rx_queues = 1;
3284 dev_info(&adapter->netdev->dev,
3285 "Using INTx interrupt, #Rx queues: 1.\n");
3286 adapter->intr.type = VMXNET3_IT_INTX;
3288 /* INT-X related setting */
3289 adapter->intr.num_intrs = 1;
3294 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3296 if (adapter->intr.type == VMXNET3_IT_MSIX)
3297 pci_disable_msix(adapter->pdev);
3298 else if (adapter->intr.type == VMXNET3_IT_MSI)
3299 pci_disable_msi(adapter->pdev);
3301 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3306 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3308 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3309 adapter->tx_timeout_count++;
3311 netdev_err(adapter->netdev, "tx hang\n");
3312 schedule_work(&adapter->work);
3317 vmxnet3_reset_work(struct work_struct *data)
3319 struct vmxnet3_adapter *adapter;
3321 adapter = container_of(data, struct vmxnet3_adapter, work);
3323 /* if another thread is resetting the device, no need to proceed */
3324 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3327 /* if the device is closed, we must leave it alone */
3329 if (netif_running(adapter->netdev)) {
3330 netdev_notice(adapter->netdev, "resetting\n");
3331 vmxnet3_quiesce_dev(adapter);
3332 vmxnet3_reset_dev(adapter);
3333 vmxnet3_activate_dev(adapter);
3335 netdev_info(adapter->netdev, "already closed\n");
3339 netif_wake_queue(adapter->netdev);
3340 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3345 vmxnet3_probe_device(struct pci_dev *pdev,
3346 const struct pci_device_id *id)
3348 static const struct net_device_ops vmxnet3_netdev_ops = {
3349 .ndo_open = vmxnet3_open,
3350 .ndo_stop = vmxnet3_close,
3351 .ndo_start_xmit = vmxnet3_xmit_frame,
3352 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3353 .ndo_change_mtu = vmxnet3_change_mtu,
3354 .ndo_fix_features = vmxnet3_fix_features,
3355 .ndo_set_features = vmxnet3_set_features,
3356 .ndo_features_check = vmxnet3_features_check,
3357 .ndo_get_stats64 = vmxnet3_get_stats64,
3358 .ndo_tx_timeout = vmxnet3_tx_timeout,
3359 .ndo_set_rx_mode = vmxnet3_set_mc,
3360 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3361 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3362 #ifdef CONFIG_NET_POLL_CONTROLLER
3363 .ndo_poll_controller = vmxnet3_netpoll,
3369 struct net_device *netdev;
3370 struct vmxnet3_adapter *adapter;
3376 if (!pci_msi_enabled())
3381 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3382 (int)num_online_cpus());
3386 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3389 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3390 (int)num_online_cpus());
3394 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3395 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3396 max(num_tx_queues, num_rx_queues));
3397 dev_info(&pdev->dev,
3398 "# of Tx queues : %d, # of Rx queues : %d\n",
3399 num_tx_queues, num_rx_queues);
3404 pci_set_drvdata(pdev, netdev);
3405 adapter = netdev_priv(netdev);
3406 adapter->netdev = netdev;
3407 adapter->pdev = pdev;
3409 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3410 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3411 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3413 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
3414 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
3416 "pci_set_consistent_dma_mask failed\n");
3422 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
3424 "pci_set_dma_mask failed\n");
3431 spin_lock_init(&adapter->cmd_lock);
3432 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3433 sizeof(struct vmxnet3_adapter),
3435 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3436 dev_err(&pdev->dev, "Failed to map dma\n");
3440 adapter->shared = dma_alloc_coherent(
3441 &adapter->pdev->dev,
3442 sizeof(struct Vmxnet3_DriverShared),
3443 &adapter->shared_pa, GFP_KERNEL);
3444 if (!adapter->shared) {
3445 dev_err(&pdev->dev, "Failed to allocate memory\n");
3447 goto err_alloc_shared;
3450 adapter->num_rx_queues = num_rx_queues;
3451 adapter->num_tx_queues = num_tx_queues;
3452 adapter->rx_buf_per_pkt = 1;
3454 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3455 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3456 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3457 &adapter->queue_desc_pa,
3460 if (!adapter->tqd_start) {
3461 dev_err(&pdev->dev, "Failed to allocate memory\n");
3463 goto err_alloc_queue_desc;
3465 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3466 adapter->num_tx_queues);
3468 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3469 sizeof(struct Vmxnet3_PMConf),
3470 &adapter->pm_conf_pa,
3472 if (adapter->pm_conf == NULL) {
3479 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3480 sizeof(struct UPT1_RSSConf),
3481 &adapter->rss_conf_pa,
3483 if (adapter->rss_conf == NULL) {
3487 #endif /* VMXNET3_RSS */
3489 err = vmxnet3_alloc_pci_resources(adapter);
3493 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3494 if (ver & (1 << VMXNET3_REV_4)) {
3495 VMXNET3_WRITE_BAR1_REG(adapter,
3497 1 << VMXNET3_REV_4);
3498 adapter->version = VMXNET3_REV_4 + 1;
3499 } else if (ver & (1 << VMXNET3_REV_3)) {
3500 VMXNET3_WRITE_BAR1_REG(adapter,
3502 1 << VMXNET3_REV_3);
3503 adapter->version = VMXNET3_REV_3 + 1;
3504 } else if (ver & (1 << VMXNET3_REV_2)) {
3505 VMXNET3_WRITE_BAR1_REG(adapter,
3507 1 << VMXNET3_REV_2);
3508 adapter->version = VMXNET3_REV_2 + 1;
3509 } else if (ver & (1 << VMXNET3_REV_1)) {
3510 VMXNET3_WRITE_BAR1_REG(adapter,
3512 1 << VMXNET3_REV_1);
3513 adapter->version = VMXNET3_REV_1 + 1;
3516 "Incompatible h/w version (0x%x) for adapter\n", ver);
3520 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3522 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3524 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3527 "Incompatible upt version (0x%x) for adapter\n", ver);
3532 if (VMXNET3_VERSION_GE_3(adapter)) {
3533 adapter->coal_conf =
3534 dma_alloc_coherent(&adapter->pdev->dev,
3535 sizeof(struct Vmxnet3_CoalesceScheme)
3537 &adapter->coal_conf_pa,
3539 if (!adapter->coal_conf) {
3543 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3544 adapter->default_coal_mode = true;
3547 if (VMXNET3_VERSION_GE_4(adapter)) {
3548 adapter->default_rss_fields = true;
3549 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
3552 SET_NETDEV_DEV(netdev, &pdev->dev);
3553 vmxnet3_declare_features(adapter, dma64);
3555 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3556 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3558 if (adapter->num_tx_queues == adapter->num_rx_queues)
3559 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3561 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3563 vmxnet3_alloc_intr_resources(adapter);
3566 if (adapter->num_rx_queues > 1 &&
3567 adapter->intr.type == VMXNET3_IT_MSIX) {
3568 adapter->rss = true;
3569 netdev->hw_features |= NETIF_F_RXHASH;
3570 netdev->features |= NETIF_F_RXHASH;
3571 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3573 adapter->rss = false;
3577 vmxnet3_read_mac_addr(adapter, mac);
3578 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3580 netdev->netdev_ops = &vmxnet3_netdev_ops;
3581 vmxnet3_set_ethtool_ops(netdev);
3582 netdev->watchdog_timeo = 5 * HZ;
3584 /* MTU range: 60 - 9000 */
3585 netdev->min_mtu = VMXNET3_MIN_MTU;
3586 netdev->max_mtu = VMXNET3_MAX_MTU;
3588 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3589 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3591 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3593 for (i = 0; i < adapter->num_rx_queues; i++) {
3594 netif_napi_add(adapter->netdev,
3595 &adapter->rx_queue[i].napi,
3596 vmxnet3_poll_rx_only, 64);
3599 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3603 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3604 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3606 netif_carrier_off(netdev);
3607 err = register_netdev(netdev);
3610 dev_err(&pdev->dev, "Failed to register adapter\n");
3614 vmxnet3_check_link(adapter, false);
3618 if (VMXNET3_VERSION_GE_3(adapter)) {
3619 dma_free_coherent(&adapter->pdev->dev,
3620 sizeof(struct Vmxnet3_CoalesceScheme),
3621 adapter->coal_conf, adapter->coal_conf_pa);
3623 vmxnet3_free_intr_resources(adapter);
3625 vmxnet3_free_pci_resources(adapter);
3628 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3629 adapter->rss_conf, adapter->rss_conf_pa);
3632 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3633 adapter->pm_conf, adapter->pm_conf_pa);
3635 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3636 adapter->queue_desc_pa);
3637 err_alloc_queue_desc:
3638 dma_free_coherent(&adapter->pdev->dev,
3639 sizeof(struct Vmxnet3_DriverShared),
3640 adapter->shared, adapter->shared_pa);
3642 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3643 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3645 free_netdev(netdev);
3651 vmxnet3_remove_device(struct pci_dev *pdev)
3653 struct net_device *netdev = pci_get_drvdata(pdev);
3654 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3660 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3661 (int)num_online_cpus());
3665 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3667 cancel_work_sync(&adapter->work);
3669 unregister_netdev(netdev);
3671 vmxnet3_free_intr_resources(adapter);
3672 vmxnet3_free_pci_resources(adapter);
3673 if (VMXNET3_VERSION_GE_3(adapter)) {
3674 dma_free_coherent(&adapter->pdev->dev,
3675 sizeof(struct Vmxnet3_CoalesceScheme),
3676 adapter->coal_conf, adapter->coal_conf_pa);
3679 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3680 adapter->rss_conf, adapter->rss_conf_pa);
3682 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3683 adapter->pm_conf, adapter->pm_conf_pa);
3685 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3686 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3687 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3688 adapter->queue_desc_pa);
3689 dma_free_coherent(&adapter->pdev->dev,
3690 sizeof(struct Vmxnet3_DriverShared),
3691 adapter->shared, adapter->shared_pa);
3692 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3693 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3694 free_netdev(netdev);
3697 static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3699 struct net_device *netdev = pci_get_drvdata(pdev);
3700 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3701 unsigned long flags;
3703 /* Reset_work may be in the middle of resetting the device, wait for its
3706 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3707 usleep_range(1000, 2000);
3709 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3711 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3714 spin_lock_irqsave(&adapter->cmd_lock, flags);
3715 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3716 VMXNET3_CMD_QUIESCE_DEV);
3717 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3718 vmxnet3_disable_all_intrs(adapter);
3720 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3727 vmxnet3_suspend(struct device *device)
3729 struct pci_dev *pdev = to_pci_dev(device);
3730 struct net_device *netdev = pci_get_drvdata(pdev);
3731 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3732 struct Vmxnet3_PMConf *pmConf;
3733 struct ethhdr *ehdr;
3734 struct arphdr *ahdr;
3736 struct in_device *in_dev;
3737 struct in_ifaddr *ifa;
3738 unsigned long flags;
3741 if (!netif_running(netdev))
3744 for (i = 0; i < adapter->num_rx_queues; i++)
3745 napi_disable(&adapter->rx_queue[i].napi);
3747 vmxnet3_disable_all_intrs(adapter);
3748 vmxnet3_free_irqs(adapter);
3749 vmxnet3_free_intr_resources(adapter);
3751 netif_device_detach(netdev);
3752 netif_tx_stop_all_queues(netdev);
3754 /* Create wake-up filters. */
3755 pmConf = adapter->pm_conf;
3756 memset(pmConf, 0, sizeof(*pmConf));
3758 if (adapter->wol & WAKE_UCAST) {
3759 pmConf->filters[i].patternSize = ETH_ALEN;
3760 pmConf->filters[i].maskSize = 1;
3761 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3762 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3764 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3768 if (adapter->wol & WAKE_ARP) {
3771 in_dev = __in_dev_get_rcu(netdev);
3777 ifa = rcu_dereference(in_dev->ifa_list);
3783 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3784 sizeof(struct arphdr) + /* ARP header */
3785 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3786 2 * sizeof(u32); /*2 IPv4 addresses */
3787 pmConf->filters[i].maskSize =
3788 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3790 /* ETH_P_ARP in Ethernet header. */
3791 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3792 ehdr->h_proto = htons(ETH_P_ARP);
3794 /* ARPOP_REQUEST in ARP header. */
3795 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3796 ahdr->ar_op = htons(ARPOP_REQUEST);
3797 arpreq = (u8 *)(ahdr + 1);
3799 /* The Unicast IPv4 address in 'tip' field. */
3800 arpreq += 2 * ETH_ALEN + sizeof(u32);
3801 *(__be32 *)arpreq = ifa->ifa_address;
3805 /* The mask for the relevant bits. */
3806 pmConf->filters[i].mask[0] = 0x00;
3807 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3808 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3809 pmConf->filters[i].mask[3] = 0x00;
3810 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3811 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3813 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3818 if (adapter->wol & WAKE_MAGIC)
3819 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3821 pmConf->numFilters = i;
3823 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3824 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3826 adapter->shared->devRead.pmConfDesc.confPA =
3827 cpu_to_le64(adapter->pm_conf_pa);
3829 spin_lock_irqsave(&adapter->cmd_lock, flags);
3830 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3831 VMXNET3_CMD_UPDATE_PMCFG);
3832 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3834 pci_save_state(pdev);
3835 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3837 pci_disable_device(pdev);
3838 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3845 vmxnet3_resume(struct device *device)
3848 unsigned long flags;
3849 struct pci_dev *pdev = to_pci_dev(device);
3850 struct net_device *netdev = pci_get_drvdata(pdev);
3851 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3853 if (!netif_running(netdev))
3856 pci_set_power_state(pdev, PCI_D0);
3857 pci_restore_state(pdev);
3858 err = pci_enable_device_mem(pdev);
3862 pci_enable_wake(pdev, PCI_D0, 0);
3864 vmxnet3_alloc_intr_resources(adapter);
3866 /* During hibernate and suspend, device has to be reinitialized as the
3867 * device state need not be preserved.
3870 /* Need not check adapter state as other reset tasks cannot run during
3873 spin_lock_irqsave(&adapter->cmd_lock, flags);
3874 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3875 VMXNET3_CMD_QUIESCE_DEV);
3876 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3877 vmxnet3_tq_cleanup_all(adapter);
3878 vmxnet3_rq_cleanup_all(adapter);
3880 vmxnet3_reset_dev(adapter);
3881 err = vmxnet3_activate_dev(adapter);
3884 "failed to re-activate on resume, error: %d", err);
3885 vmxnet3_force_close(adapter);
3888 netif_device_attach(netdev);
3893 static const struct dev_pm_ops vmxnet3_pm_ops = {
3894 .suspend = vmxnet3_suspend,
3895 .resume = vmxnet3_resume,
3896 .freeze = vmxnet3_suspend,
3897 .restore = vmxnet3_resume,
3901 static struct pci_driver vmxnet3_driver = {
3902 .name = vmxnet3_driver_name,
3903 .id_table = vmxnet3_pciid_table,
3904 .probe = vmxnet3_probe_device,
3905 .remove = vmxnet3_remove_device,
3906 .shutdown = vmxnet3_shutdown_device,
3908 .driver.pm = &vmxnet3_pm_ops,
3914 vmxnet3_init_module(void)
3916 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
3917 VMXNET3_DRIVER_VERSION_REPORT);
3918 return pci_register_driver(&vmxnet3_driver);
3921 module_init(vmxnet3_init_module);
3925 vmxnet3_exit_module(void)
3927 pci_unregister_driver(&vmxnet3_driver);
3930 module_exit(vmxnet3_exit_module);
3932 MODULE_AUTHOR("VMware, Inc.");
3933 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3934 MODULE_LICENSE("GPL v2");
3935 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);