2 * Linux driver for VMware's vmxnet3 ethernet NIC.
4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
23 * Maintained by: pv-drivers@vmware.com
27 #include <linux/module.h>
28 #include <net/ip6_checksum.h>
30 #include "vmxnet3_int.h"
32 char vmxnet3_driver_name[] = "vmxnet3";
33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
37 * Last entry must be all 0s
39 static const struct pci_device_id vmxnet3_pciid_table[] = {
40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
46 static int enable_mq = 1;
49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
52 * Enable/Disable the given intr
55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
69 * Enable/Disable all intrs used by the device
72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
135 * Check the link state. This may start or stop the tx queue.
138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
144 spin_lock_irqsave(&adapter->cmd_lock, flags);
145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
153 netif_carrier_on(adapter->netdev);
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
161 netdev_info(adapter->netdev, "NIC Link is Down\n");
162 netif_carrier_off(adapter->netdev);
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
172 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
176 u32 events = le32_to_cpu(adapter->shared->ecr);
180 vmxnet3_ack_events(adapter, events);
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
184 vmxnet3_check_link(adapter, true);
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
188 spin_lock_irqsave(&adapter->cmd_lock, flags);
189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
206 schedule_work(&adapter->work);
210 #ifdef __BIG_ENDIAN_BITFIELD
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
244 *dst = cpu_to_le32(*src);
249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
263 /* Used to read bitfield values from double words. */
264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
275 #endif /* __BIG_ENDIAN_BITFIELD */
277 #ifdef __BIG_ENDIAN_BITFIELD
279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
308 #endif /* __BIG_ENDIAN_BITFIELD */
312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
339 skb = tq->buf_info[eop_idx].skb;
341 tq->buf_info[eop_idx].skb = NULL;
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
358 dev_kfree_skb_any(skb);
364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
368 union Vmxnet3_GenericDesc *gdesc;
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 /* Prevent any &gdesc->tcd field from being (speculatively)
373 * read before (&gdesc->tcd)->gen is read.
377 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
378 &gdesc->tcd), tq, adapter->pdev,
381 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
386 spin_lock(&tq->tx_lock);
387 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
388 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
389 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
390 netif_carrier_ok(adapter->netdev))) {
391 vmxnet3_tq_wake(tq, adapter);
393 spin_unlock(&tq->tx_lock);
400 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
401 struct vmxnet3_adapter *adapter)
405 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
406 struct vmxnet3_tx_buf_info *tbi;
408 tbi = tq->buf_info + tq->tx_ring.next2comp;
410 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
412 dev_kfree_skb_any(tbi->skb);
415 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
418 /* sanity check, verify all buffers are indeed unmapped and freed */
419 for (i = 0; i < tq->tx_ring.size; i++) {
420 BUG_ON(tq->buf_info[i].skb != NULL ||
421 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
424 tq->tx_ring.gen = VMXNET3_INIT_GEN;
425 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
427 tq->comp_ring.gen = VMXNET3_INIT_GEN;
428 tq->comp_ring.next2proc = 0;
433 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
434 struct vmxnet3_adapter *adapter)
436 if (tq->tx_ring.base) {
437 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
438 sizeof(struct Vmxnet3_TxDesc),
439 tq->tx_ring.base, tq->tx_ring.basePA);
440 tq->tx_ring.base = NULL;
442 if (tq->data_ring.base) {
443 dma_free_coherent(&adapter->pdev->dev,
444 tq->data_ring.size * tq->txdata_desc_size,
445 tq->data_ring.base, tq->data_ring.basePA);
446 tq->data_ring.base = NULL;
448 if (tq->comp_ring.base) {
449 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
450 sizeof(struct Vmxnet3_TxCompDesc),
451 tq->comp_ring.base, tq->comp_ring.basePA);
452 tq->comp_ring.base = NULL;
455 dma_free_coherent(&adapter->pdev->dev,
456 tq->tx_ring.size * sizeof(tq->buf_info[0]),
457 tq->buf_info, tq->buf_info_pa);
463 /* Destroy all tx queues */
465 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
469 for (i = 0; i < adapter->num_tx_queues; i++)
470 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
475 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
476 struct vmxnet3_adapter *adapter)
480 /* reset the tx ring contents to 0 and reset the tx ring states */
481 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
482 sizeof(struct Vmxnet3_TxDesc));
483 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
484 tq->tx_ring.gen = VMXNET3_INIT_GEN;
486 memset(tq->data_ring.base, 0,
487 tq->data_ring.size * tq->txdata_desc_size);
489 /* reset the tx comp ring contents to 0 and reset comp ring states */
490 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
491 sizeof(struct Vmxnet3_TxCompDesc));
492 tq->comp_ring.next2proc = 0;
493 tq->comp_ring.gen = VMXNET3_INIT_GEN;
495 /* reset the bookkeeping data */
496 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
497 for (i = 0; i < tq->tx_ring.size; i++)
498 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
500 /* stats are not reset */
505 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
506 struct vmxnet3_adapter *adapter)
510 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
511 tq->comp_ring.base || tq->buf_info);
513 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
514 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
515 &tq->tx_ring.basePA, GFP_KERNEL);
516 if (!tq->tx_ring.base) {
517 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
521 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
522 tq->data_ring.size * tq->txdata_desc_size,
523 &tq->data_ring.basePA, GFP_KERNEL);
524 if (!tq->data_ring.base) {
525 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
529 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
530 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
531 &tq->comp_ring.basePA, GFP_KERNEL);
532 if (!tq->comp_ring.base) {
533 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
537 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
538 tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz,
539 &tq->buf_info_pa, GFP_KERNEL);
546 vmxnet3_tq_destroy(tq, adapter);
551 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
555 for (i = 0; i < adapter->num_tx_queues; i++)
556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
560 * starting from ring->next2fill, allocate rx buffers for the given ring
561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
562 * are allocated or allocation fails
566 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
567 int num_to_alloc, struct vmxnet3_adapter *adapter)
569 int num_allocated = 0;
570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
574 while (num_allocated <= num_to_alloc) {
575 struct vmxnet3_rx_buf_info *rbi;
576 union Vmxnet3_GenericDesc *gd;
578 rbi = rbi_base + ring->next2fill;
579 gd = ring->base + ring->next2fill;
581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
582 if (rbi->skb == NULL) {
583 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
586 if (unlikely(rbi->skb == NULL)) {
587 rq->stats.rx_buf_alloc_failure++;
591 rbi->dma_addr = dma_map_single(
593 rbi->skb->data, rbi->len,
595 if (dma_mapping_error(&adapter->pdev->dev,
597 dev_kfree_skb_any(rbi->skb);
598 rq->stats.rx_buf_alloc_failure++;
602 /* rx buffer skipped by the device */
604 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
606 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
607 rbi->len != PAGE_SIZE);
609 if (rbi->page == NULL) {
610 rbi->page = alloc_page(GFP_ATOMIC);
611 if (unlikely(rbi->page == NULL)) {
612 rq->stats.rx_buf_alloc_failure++;
615 rbi->dma_addr = dma_map_page(
617 rbi->page, 0, PAGE_SIZE,
619 if (dma_mapping_error(&adapter->pdev->dev,
622 rq->stats.rx_buf_alloc_failure++;
626 /* rx buffers skipped by the device */
628 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
631 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
632 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
635 /* Fill the last buffer but dont mark it ready, or else the
636 * device will think that the queue is full */
637 if (num_allocated == num_to_alloc)
640 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
642 vmxnet3_cmd_ring_adv_next2fill(ring);
645 netdev_dbg(adapter->netdev,
646 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
647 num_allocated, ring->next2fill, ring->next2comp);
649 /* so that the device can distinguish a full ring and an empty ring */
650 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
652 return num_allocated;
657 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
658 struct vmxnet3_rx_buf_info *rbi)
660 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
662 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
664 __skb_frag_set_page(frag, rbi->page);
665 skb_frag_off_set(frag, 0);
666 skb_frag_size_set(frag, rcd->len);
667 skb->data_len += rcd->len;
668 skb->truesize += PAGE_SIZE;
669 skb_shinfo(skb)->nr_frags++;
674 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
675 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
676 struct vmxnet3_adapter *adapter)
679 unsigned long buf_offset;
681 union Vmxnet3_GenericDesc *gdesc;
682 struct vmxnet3_tx_buf_info *tbi = NULL;
684 BUG_ON(ctx->copy_size > skb_headlen(skb));
686 /* use the previous gen bit for the SOP desc */
687 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
689 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
690 gdesc = ctx->sop_txd; /* both loops below can be skipped */
692 /* no need to map the buffer if headers are copied */
693 if (ctx->copy_size) {
694 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
695 tq->tx_ring.next2fill *
696 tq->txdata_desc_size);
697 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
698 ctx->sop_txd->dword[3] = 0;
700 tbi = tq->buf_info + tq->tx_ring.next2fill;
701 tbi->map_type = VMXNET3_MAP_NONE;
703 netdev_dbg(adapter->netdev,
704 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
705 tq->tx_ring.next2fill,
706 le64_to_cpu(ctx->sop_txd->txd.addr),
707 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
708 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
710 /* use the right gen for non-SOP desc */
711 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
714 /* linear part can use multiple tx desc if it's big */
715 len = skb_headlen(skb) - ctx->copy_size;
716 buf_offset = ctx->copy_size;
720 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
724 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
725 /* spec says that for TxDesc.len, 0 == 2^14 */
728 tbi = tq->buf_info + tq->tx_ring.next2fill;
729 tbi->map_type = VMXNET3_MAP_SINGLE;
730 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
731 skb->data + buf_offset, buf_size,
733 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
738 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
739 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
741 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
742 gdesc->dword[2] = cpu_to_le32(dw2);
745 netdev_dbg(adapter->netdev,
746 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
747 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
748 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
749 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
750 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
753 buf_offset += buf_size;
756 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
757 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
761 len = skb_frag_size(frag);
763 tbi = tq->buf_info + tq->tx_ring.next2fill;
764 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
768 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
769 /* spec says that for TxDesc.len, 0 == 2^14 */
771 tbi->map_type = VMXNET3_MAP_PAGE;
772 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
773 buf_offset, buf_size,
775 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
780 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
781 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
783 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
784 gdesc->dword[2] = cpu_to_le32(dw2);
787 netdev_dbg(adapter->netdev,
788 "txd[%u]: 0x%llx %u %u\n",
789 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
790 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
791 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
792 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
795 buf_offset += buf_size;
799 ctx->eop_txd = gdesc;
801 /* set the last buf_info for the pkt */
803 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
809 /* Init all tx queues */
811 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
815 for (i = 0; i < adapter->num_tx_queues; i++)
816 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
821 * parse relevant protocol headers:
822 * For a tso pkt, relevant headers are L2/3/4 including options
823 * For a pkt requesting csum offloading, they are L2/3 and may include L4
824 * if it's a TCP/UDP pkt
827 * -1: error happens during parsing
828 * 0: protocol headers parsed, but too big to be copied
829 * 1: protocol headers parsed and copied
832 * 1. related *ctx fields are updated.
833 * 2. ctx->copy_size is # of bytes copied
834 * 3. the portion to be copied is guaranteed to be in the linear part
838 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
839 struct vmxnet3_tx_ctx *ctx,
840 struct vmxnet3_adapter *adapter)
844 if (ctx->mss) { /* TSO */
845 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
846 ctx->l4_offset = skb_inner_transport_offset(skb);
847 ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
848 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
850 ctx->l4_offset = skb_transport_offset(skb);
851 ctx->l4_hdr_size = tcp_hdrlen(skb);
852 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
855 if (skb->ip_summed == CHECKSUM_PARTIAL) {
856 /* For encap packets, skb_checksum_start_offset refers
857 * to inner L4 offset. Thus, below works for encap as
858 * well as non-encap case
860 ctx->l4_offset = skb_checksum_start_offset(skb);
862 if (VMXNET3_VERSION_GE_4(adapter) &&
863 skb->encapsulation) {
864 struct iphdr *iph = inner_ip_hdr(skb);
866 if (iph->version == 4) {
867 protocol = iph->protocol;
869 const struct ipv6hdr *ipv6h;
871 ipv6h = inner_ipv6_hdr(skb);
872 protocol = ipv6h->nexthdr;
876 const struct iphdr *iph = ip_hdr(skb);
878 protocol = iph->protocol;
879 } else if (ctx->ipv6) {
880 const struct ipv6hdr *ipv6h;
882 ipv6h = ipv6_hdr(skb);
883 protocol = ipv6h->nexthdr;
889 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
893 ctx->l4_hdr_size = sizeof(struct udphdr);
896 ctx->l4_hdr_size = 0;
900 ctx->copy_size = min(ctx->l4_offset +
901 ctx->l4_hdr_size, skb->len);
904 ctx->l4_hdr_size = 0;
905 /* copy as much as allowed */
906 ctx->copy_size = min_t(unsigned int,
907 tq->txdata_desc_size,
911 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
912 ctx->copy_size = skb->len;
914 /* make sure headers are accessible directly */
915 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
919 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
920 tq->stats.oversized_hdr++;
931 * copy relevant protocol headers to the transmit ring:
932 * For a tso pkt, relevant headers are L2/3/4 including options
933 * For a pkt requesting csum offloading, they are L2/3 and may include L4
934 * if it's a TCP/UDP pkt
937 * Note that this requires that vmxnet3_parse_hdr be called first to set the
938 * appropriate bits in ctx first
941 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
942 struct vmxnet3_tx_ctx *ctx,
943 struct vmxnet3_adapter *adapter)
945 struct Vmxnet3_TxDataDesc *tdd;
947 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
948 tq->tx_ring.next2fill *
949 tq->txdata_desc_size);
951 memcpy(tdd->data, skb->data, ctx->copy_size);
952 netdev_dbg(adapter->netdev,
953 "copy %u bytes to dataRing[%u]\n",
954 ctx->copy_size, tq->tx_ring.next2fill);
959 vmxnet3_prepare_inner_tso(struct sk_buff *skb,
960 struct vmxnet3_tx_ctx *ctx)
962 struct tcphdr *tcph = inner_tcp_hdr(skb);
963 struct iphdr *iph = inner_ip_hdr(skb);
965 if (iph->version == 4) {
967 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
970 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
972 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
978 vmxnet3_prepare_tso(struct sk_buff *skb,
979 struct vmxnet3_tx_ctx *ctx)
981 struct tcphdr *tcph = tcp_hdr(skb);
984 struct iphdr *iph = ip_hdr(skb);
987 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
989 } else if (ctx->ipv6) {
990 tcp_v6_gso_csum_prep(skb);
994 static int txd_estimate(const struct sk_buff *skb)
996 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
999 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1000 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1002 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1008 * Transmits a pkt thru a given tq
1010 * NETDEV_TX_OK: descriptors are setup successfully
1011 * NETDEV_TX_OK: error occurred, the pkt is dropped
1012 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
1015 * 1. tx ring may be changed
1016 * 2. tq stats may be updated accordingly
1017 * 3. shared->txNumDeferred may be updated
1021 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1022 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1027 int tx_num_deferred;
1028 unsigned long flags;
1029 struct vmxnet3_tx_ctx ctx;
1030 union Vmxnet3_GenericDesc *gdesc;
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032 /* Use temporary descriptor to avoid touching bits multiple times */
1033 union Vmxnet3_GenericDesc tempTxDesc;
1035 struct udphdr *udph;
1037 count = txd_estimate(skb);
1039 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1040 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1042 ctx.mss = skb_shinfo(skb)->gso_size;
1044 if (skb_header_cloned(skb)) {
1045 if (unlikely(pskb_expand_head(skb, 0, 0,
1046 GFP_ATOMIC) != 0)) {
1047 tq->stats.drop_tso++;
1050 tq->stats.copy_skb_header++;
1052 if (skb->encapsulation) {
1053 vmxnet3_prepare_inner_tso(skb, &ctx);
1055 vmxnet3_prepare_tso(skb, &ctx);
1058 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1060 /* non-tso pkts must not use more than
1061 * VMXNET3_MAX_TXD_PER_PKT entries
1063 if (skb_linearize(skb) != 0) {
1064 tq->stats.drop_too_many_frags++;
1067 tq->stats.linearized++;
1069 /* recalculate the # of descriptors to use */
1070 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1074 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1076 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1077 /* hdrs parsed, check against other limits */
1079 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1080 VMXNET3_MAX_TX_BUF_SIZE)) {
1081 tq->stats.drop_oversized_hdr++;
1085 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1086 if (unlikely(ctx.l4_offset +
1088 VMXNET3_MAX_CSUM_OFFSET)) {
1089 tq->stats.drop_oversized_hdr++;
1095 tq->stats.drop_hdr_inspect_err++;
1099 spin_lock_irqsave(&tq->tx_lock, flags);
1101 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1102 tq->stats.tx_ring_full++;
1103 netdev_dbg(adapter->netdev,
1104 "tx queue stopped on %s, next2comp %u"
1105 " next2fill %u\n", adapter->netdev->name,
1106 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1108 vmxnet3_tq_stop(tq, adapter);
1109 spin_unlock_irqrestore(&tq->tx_lock, flags);
1110 return NETDEV_TX_BUSY;
1114 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1116 /* fill tx descs related to addr & len */
1117 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1118 goto unlock_drop_pkt;
1120 /* setup the EOP desc */
1121 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1123 /* setup the SOP desc */
1124 #ifdef __BIG_ENDIAN_BITFIELD
1125 gdesc = &tempTxDesc;
1126 gdesc->dword[2] = ctx.sop_txd->dword[2];
1127 gdesc->dword[3] = ctx.sop_txd->dword[3];
1129 gdesc = ctx.sop_txd;
1131 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1133 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1134 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1135 gdesc->txd.om = VMXNET3_OM_ENCAP;
1136 gdesc->txd.msscof = ctx.mss;
1138 udph = udp_hdr(skb);
1142 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1143 gdesc->txd.om = VMXNET3_OM_TSO;
1144 gdesc->txd.msscof = ctx.mss;
1146 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1148 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1149 if (VMXNET3_VERSION_GE_4(adapter) &&
1150 skb->encapsulation) {
1151 gdesc->txd.hlen = ctx.l4_offset +
1153 gdesc->txd.om = VMXNET3_OM_ENCAP;
1154 gdesc->txd.msscof = 0; /* Reserved */
1156 gdesc->txd.hlen = ctx.l4_offset;
1157 gdesc->txd.om = VMXNET3_OM_CSUM;
1158 gdesc->txd.msscof = ctx.l4_offset +
1163 gdesc->txd.msscof = 0;
1167 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1168 tx_num_deferred += num_pkts;
1170 if (skb_vlan_tag_present(skb)) {
1172 gdesc->txd.tci = skb_vlan_tag_get(skb);
1175 /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1176 * all other writes to &gdesc->txd.
1180 /* finally flips the GEN bit of the SOP desc. */
1181 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1183 #ifdef __BIG_ENDIAN_BITFIELD
1184 /* Finished updating in bitfields of Tx Desc, so write them in original
1187 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1188 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1189 gdesc = ctx.sop_txd;
1191 netdev_dbg(adapter->netdev,
1192 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1194 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1195 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1197 spin_unlock_irqrestore(&tq->tx_lock, flags);
1199 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1200 tq->shared->txNumDeferred = 0;
1201 VMXNET3_WRITE_BAR0_REG(adapter,
1202 VMXNET3_REG_TXPROD + tq->qid * 8,
1203 tq->tx_ring.next2fill);
1206 return NETDEV_TX_OK;
1209 spin_unlock_irqrestore(&tq->tx_lock, flags);
1211 tq->stats.drop_total++;
1212 dev_kfree_skb_any(skb);
1213 return NETDEV_TX_OK;
1218 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1220 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1222 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1223 return vmxnet3_tq_xmit(skb,
1224 &adapter->tx_queue[skb->queue_mapping],
1230 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1231 struct sk_buff *skb,
1232 union Vmxnet3_GenericDesc *gdesc)
1234 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1235 if (gdesc->rcd.v4 &&
1236 (le32_to_cpu(gdesc->dword[3]) &
1237 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1238 skb->ip_summed = CHECKSUM_UNNECESSARY;
1239 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1240 !(le32_to_cpu(gdesc->dword[0]) &
1241 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1242 WARN_ON_ONCE(gdesc->rcd.frg &&
1243 !(le32_to_cpu(gdesc->dword[0]) &
1244 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1245 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1246 (1 << VMXNET3_RCD_TUC_SHIFT))) {
1247 skb->ip_summed = CHECKSUM_UNNECESSARY;
1248 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1249 !(le32_to_cpu(gdesc->dword[0]) &
1250 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1251 WARN_ON_ONCE(gdesc->rcd.frg &&
1252 !(le32_to_cpu(gdesc->dword[0]) &
1253 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1255 if (gdesc->rcd.csum) {
1256 skb->csum = htons(gdesc->rcd.csum);
1257 skb->ip_summed = CHECKSUM_PARTIAL;
1259 skb_checksum_none_assert(skb);
1263 skb_checksum_none_assert(skb);
1269 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1270 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1272 rq->stats.drop_err++;
1274 rq->stats.drop_fcs++;
1276 rq->stats.drop_total++;
1279 * We do not unmap and chain the rx buffer to the skb.
1280 * We basically pretend this buffer is not used and will be recycled
1281 * by vmxnet3_rq_alloc_rx_buf()
1285 * ctx->skb may be NULL if this is the first and the only one
1289 dev_kfree_skb_irq(ctx->skb);
1296 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1297 union Vmxnet3_GenericDesc *gdesc)
1303 struct vlan_ethhdr *veth;
1305 struct ipv6hdr *ipv6;
1308 BUG_ON(gdesc->rcd.tcp == 0);
1310 maplen = skb_headlen(skb);
1311 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1314 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1315 skb->protocol == cpu_to_be16(ETH_P_8021AD))
1316 hlen = sizeof(struct vlan_ethhdr);
1318 hlen = sizeof(struct ethhdr);
1320 hdr.eth = eth_hdr(skb);
1321 if (gdesc->rcd.v4) {
1322 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1323 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1325 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1326 hlen = hdr.ipv4->ihl << 2;
1327 hdr.ptr += hdr.ipv4->ihl << 2;
1328 } else if (gdesc->rcd.v6) {
1329 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1330 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1332 /* Use an estimated value, since we also need to handle
1335 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1336 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1337 hlen = sizeof(struct ipv6hdr);
1338 hdr.ptr += sizeof(struct ipv6hdr);
1340 /* Non-IP pkt, dont estimate header length */
1344 if (hlen + sizeof(struct tcphdr) > maplen)
1347 return (hlen + (hdr.tcp->doff << 2));
1351 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1352 struct vmxnet3_adapter *adapter, int quota)
1354 static const u32 rxprod_reg[2] = {
1355 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1358 bool skip_page_frags = false;
1359 struct Vmxnet3_RxCompDesc *rcd;
1360 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1361 u16 segCnt = 0, mss = 0;
1362 #ifdef __BIG_ENDIAN_BITFIELD
1363 struct Vmxnet3_RxDesc rxCmdDesc;
1364 struct Vmxnet3_RxCompDesc rxComp;
1366 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1368 while (rcd->gen == rq->comp_ring.gen) {
1369 struct vmxnet3_rx_buf_info *rbi;
1370 struct sk_buff *skb, *new_skb = NULL;
1371 struct page *new_page = NULL;
1372 dma_addr_t new_dma_addr;
1374 struct Vmxnet3_RxDesc *rxd;
1376 struct vmxnet3_cmd_ring *ring = NULL;
1377 if (num_pkts >= quota) {
1378 /* we may stop even before we see the EOP desc of
1384 /* Prevent any rcd field from being (speculatively) read before
1389 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1390 rcd->rqID != rq->dataRingQid);
1392 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1393 ring = rq->rx_ring + ring_idx;
1394 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1396 rbi = rq->buf_info[ring_idx] + idx;
1398 BUG_ON(rxd->addr != rbi->dma_addr ||
1399 rxd->len != rbi->len);
1401 if (unlikely(rcd->eop && rcd->err)) {
1402 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1406 if (rcd->sop) { /* first buf of the pkt */
1407 bool rxDataRingUsed;
1410 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1411 (rcd->rqID != rq->qid &&
1412 rcd->rqID != rq->dataRingQid));
1414 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1415 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1417 if (unlikely(rcd->len == 0)) {
1418 /* Pretend the rx buffer is skipped. */
1419 BUG_ON(!(rcd->sop && rcd->eop));
1420 netdev_dbg(adapter->netdev,
1421 "rxRing[%u][%u] 0 length\n",
1426 skip_page_frags = false;
1427 ctx->skb = rbi->skb;
1430 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1431 len = rxDataRingUsed ? rcd->len : rbi->len;
1432 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1434 if (new_skb == NULL) {
1435 /* Skb allocation failed, do not handover this
1436 * skb to stack. Reuse it. Drop the existing pkt
1438 rq->stats.rx_buf_alloc_failure++;
1440 rq->stats.drop_total++;
1441 skip_page_frags = true;
1445 if (rxDataRingUsed) {
1448 BUG_ON(rcd->len > rq->data_ring.desc_size);
1451 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1452 memcpy(new_skb->data,
1453 &rq->data_ring.base[sz], rcd->len);
1455 ctx->skb = rbi->skb;
1458 dma_map_single(&adapter->pdev->dev,
1459 new_skb->data, rbi->len,
1460 PCI_DMA_FROMDEVICE);
1461 if (dma_mapping_error(&adapter->pdev->dev,
1463 dev_kfree_skb(new_skb);
1464 /* Skb allocation failed, do not
1465 * handover this skb to stack. Reuse
1466 * it. Drop the existing pkt.
1468 rq->stats.rx_buf_alloc_failure++;
1470 rq->stats.drop_total++;
1471 skip_page_frags = true;
1475 dma_unmap_single(&adapter->pdev->dev,
1478 PCI_DMA_FROMDEVICE);
1480 /* Immediate refill */
1482 rbi->dma_addr = new_dma_addr;
1483 rxd->addr = cpu_to_le64(rbi->dma_addr);
1484 rxd->len = rbi->len;
1488 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1489 (adapter->netdev->features & NETIF_F_RXHASH))
1490 skb_set_hash(ctx->skb,
1491 le32_to_cpu(rcd->rssHash),
1494 skb_put(ctx->skb, rcd->len);
1496 if (VMXNET3_VERSION_GE_2(adapter) &&
1497 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1498 struct Vmxnet3_RxCompDescExt *rcdlro;
1499 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1501 segCnt = rcdlro->segCnt;
1502 WARN_ON_ONCE(segCnt == 0);
1504 if (unlikely(segCnt <= 1))
1510 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1512 /* non SOP buffer must be type 1 in most cases */
1513 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1514 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1516 /* If an sop buffer was dropped, skip all
1517 * following non-sop fragments. They will be reused.
1519 if (skip_page_frags)
1523 new_page = alloc_page(GFP_ATOMIC);
1524 /* Replacement page frag could not be allocated.
1525 * Reuse this page. Drop the pkt and free the
1526 * skb which contained this page as a frag. Skip
1527 * processing all the following non-sop frags.
1529 if (unlikely(!new_page)) {
1530 rq->stats.rx_buf_alloc_failure++;
1531 dev_kfree_skb(ctx->skb);
1533 skip_page_frags = true;
1536 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1539 PCI_DMA_FROMDEVICE);
1540 if (dma_mapping_error(&adapter->pdev->dev,
1543 rq->stats.rx_buf_alloc_failure++;
1544 dev_kfree_skb(ctx->skb);
1546 skip_page_frags = true;
1550 dma_unmap_page(&adapter->pdev->dev,
1551 rbi->dma_addr, rbi->len,
1552 PCI_DMA_FROMDEVICE);
1554 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1556 /* Immediate refill */
1557 rbi->page = new_page;
1558 rbi->dma_addr = new_dma_addr;
1559 rxd->addr = cpu_to_le64(rbi->dma_addr);
1560 rxd->len = rbi->len;
1567 u32 mtu = adapter->netdev->mtu;
1568 skb->len += skb->data_len;
1570 vmxnet3_rx_csum(adapter, skb,
1571 (union Vmxnet3_GenericDesc *)rcd);
1572 skb->protocol = eth_type_trans(skb, adapter->netdev);
1574 !(adapter->netdev->features & NETIF_F_LRO))
1577 if (segCnt != 0 && mss != 0) {
1578 skb_shinfo(skb)->gso_type = rcd->v4 ?
1579 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1580 skb_shinfo(skb)->gso_size = mss;
1581 skb_shinfo(skb)->gso_segs = segCnt;
1582 } else if (segCnt != 0 || skb->len > mtu) {
1585 hlen = vmxnet3_get_hdr_len(adapter, skb,
1586 (union Vmxnet3_GenericDesc *)rcd);
1590 skb_shinfo(skb)->gso_type =
1591 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1593 skb_shinfo(skb)->gso_segs = segCnt;
1594 skb_shinfo(skb)->gso_size =
1595 DIV_ROUND_UP(skb->len -
1598 skb_shinfo(skb)->gso_size = mtu - hlen;
1602 if (unlikely(rcd->ts))
1603 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1605 if (adapter->netdev->features & NETIF_F_LRO)
1606 netif_receive_skb(skb);
1608 napi_gro_receive(&rq->napi, skb);
1615 /* device may have skipped some rx descs */
1616 ring->next2comp = idx;
1617 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1618 ring = rq->rx_ring + ring_idx;
1620 /* Ensure that the writes to rxd->gen bits will be observed
1621 * after all other writes to rxd objects.
1625 while (num_to_alloc) {
1626 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1630 /* Recv desc is ready to be used by the device */
1631 rxd->gen = ring->gen;
1632 vmxnet3_cmd_ring_adv_next2fill(ring);
1636 /* if needed, update the register */
1637 if (unlikely(rq->shared->updateRxProd)) {
1638 VMXNET3_WRITE_BAR0_REG(adapter,
1639 rxprod_reg[ring_idx] + rq->qid * 8,
1643 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1644 vmxnet3_getRxComp(rcd,
1645 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1653 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1654 struct vmxnet3_adapter *adapter)
1657 struct Vmxnet3_RxDesc *rxd;
1659 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1660 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1661 #ifdef __BIG_ENDIAN_BITFIELD
1662 struct Vmxnet3_RxDesc rxDesc;
1664 vmxnet3_getRxDesc(rxd,
1665 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1667 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1668 rq->buf_info[ring_idx][i].skb) {
1669 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1670 rxd->len, PCI_DMA_FROMDEVICE);
1671 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1672 rq->buf_info[ring_idx][i].skb = NULL;
1673 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1674 rq->buf_info[ring_idx][i].page) {
1675 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1676 rxd->len, PCI_DMA_FROMDEVICE);
1677 put_page(rq->buf_info[ring_idx][i].page);
1678 rq->buf_info[ring_idx][i].page = NULL;
1682 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1683 rq->rx_ring[ring_idx].next2fill =
1684 rq->rx_ring[ring_idx].next2comp = 0;
1687 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1688 rq->comp_ring.next2proc = 0;
1693 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1697 for (i = 0; i < adapter->num_rx_queues; i++)
1698 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1702 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1703 struct vmxnet3_adapter *adapter)
1708 /* all rx buffers must have already been freed */
1709 for (i = 0; i < 2; i++) {
1710 if (rq->buf_info[i]) {
1711 for (j = 0; j < rq->rx_ring[i].size; j++)
1712 BUG_ON(rq->buf_info[i][j].page != NULL);
1717 for (i = 0; i < 2; i++) {
1718 if (rq->rx_ring[i].base) {
1719 dma_free_coherent(&adapter->pdev->dev,
1721 * sizeof(struct Vmxnet3_RxDesc),
1722 rq->rx_ring[i].base,
1723 rq->rx_ring[i].basePA);
1724 rq->rx_ring[i].base = NULL;
1728 if (rq->data_ring.base) {
1729 dma_free_coherent(&adapter->pdev->dev,
1730 rq->rx_ring[0].size * rq->data_ring.desc_size,
1731 rq->data_ring.base, rq->data_ring.basePA);
1732 rq->data_ring.base = NULL;
1735 if (rq->comp_ring.base) {
1736 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1737 * sizeof(struct Vmxnet3_RxCompDesc),
1738 rq->comp_ring.base, rq->comp_ring.basePA);
1739 rq->comp_ring.base = NULL;
1742 if (rq->buf_info[0]) {
1743 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1744 (rq->rx_ring[0].size + rq->rx_ring[1].size);
1745 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1747 rq->buf_info[0] = rq->buf_info[1] = NULL;
1752 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1756 for (i = 0; i < adapter->num_rx_queues; i++) {
1757 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1759 if (rq->data_ring.base) {
1760 dma_free_coherent(&adapter->pdev->dev,
1761 (rq->rx_ring[0].size *
1762 rq->data_ring.desc_size),
1764 rq->data_ring.basePA);
1765 rq->data_ring.base = NULL;
1766 rq->data_ring.desc_size = 0;
1772 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1773 struct vmxnet3_adapter *adapter)
1777 /* initialize buf_info */
1778 for (i = 0; i < rq->rx_ring[0].size; i++) {
1780 /* 1st buf for a pkt is skbuff */
1781 if (i % adapter->rx_buf_per_pkt == 0) {
1782 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1783 rq->buf_info[0][i].len = adapter->skb_buf_size;
1784 } else { /* subsequent bufs for a pkt is frag */
1785 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1786 rq->buf_info[0][i].len = PAGE_SIZE;
1789 for (i = 0; i < rq->rx_ring[1].size; i++) {
1790 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1791 rq->buf_info[1][i].len = PAGE_SIZE;
1794 /* reset internal state and allocate buffers for both rings */
1795 for (i = 0; i < 2; i++) {
1796 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1798 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1799 sizeof(struct Vmxnet3_RxDesc));
1800 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1802 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1804 /* at least has 1 rx buffer for the 1st ring */
1807 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1809 /* reset the comp ring */
1810 rq->comp_ring.next2proc = 0;
1811 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1812 sizeof(struct Vmxnet3_RxCompDesc));
1813 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1816 rq->rx_ctx.skb = NULL;
1818 /* stats are not reset */
1824 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1828 for (i = 0; i < adapter->num_rx_queues; i++) {
1829 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1830 if (unlikely(err)) {
1831 dev_err(&adapter->netdev->dev, "%s: failed to "
1832 "initialize rx queue%i\n",
1833 adapter->netdev->name, i);
1843 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1847 struct vmxnet3_rx_buf_info *bi;
1849 for (i = 0; i < 2; i++) {
1851 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1852 rq->rx_ring[i].base = dma_alloc_coherent(
1853 &adapter->pdev->dev, sz,
1854 &rq->rx_ring[i].basePA,
1856 if (!rq->rx_ring[i].base) {
1857 netdev_err(adapter->netdev,
1858 "failed to allocate rx ring %d\n", i);
1863 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1864 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1865 rq->data_ring.base =
1866 dma_alloc_coherent(&adapter->pdev->dev, sz,
1867 &rq->data_ring.basePA,
1869 if (!rq->data_ring.base) {
1870 netdev_err(adapter->netdev,
1871 "rx data ring will be disabled\n");
1872 adapter->rxdataring_enabled = false;
1875 rq->data_ring.base = NULL;
1876 rq->data_ring.desc_size = 0;
1879 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1880 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1881 &rq->comp_ring.basePA,
1883 if (!rq->comp_ring.base) {
1884 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1888 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1889 rq->rx_ring[1].size);
1890 bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1895 rq->buf_info[0] = bi;
1896 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1901 vmxnet3_rq_destroy(rq, adapter);
1907 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1911 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1913 for (i = 0; i < adapter->num_rx_queues; i++) {
1914 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1915 if (unlikely(err)) {
1916 dev_err(&adapter->netdev->dev,
1917 "%s: failed to create rx queue%i\n",
1918 adapter->netdev->name, i);
1923 if (!adapter->rxdataring_enabled)
1924 vmxnet3_rq_destroy_all_rxdataring(adapter);
1928 vmxnet3_rq_destroy_all(adapter);
1933 /* Multiple queue aware polling function for tx and rx */
1936 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1938 int rcd_done = 0, i;
1939 if (unlikely(adapter->shared->ecr))
1940 vmxnet3_process_events(adapter);
1941 for (i = 0; i < adapter->num_tx_queues; i++)
1942 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1944 for (i = 0; i < adapter->num_rx_queues; i++)
1945 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1952 vmxnet3_poll(struct napi_struct *napi, int budget)
1954 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1955 struct vmxnet3_rx_queue, napi);
1958 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1960 if (rxd_done < budget) {
1961 napi_complete_done(napi, rxd_done);
1962 vmxnet3_enable_all_intrs(rx_queue->adapter);
1968 * NAPI polling function for MSI-X mode with multiple Rx queues
1969 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1973 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1975 struct vmxnet3_rx_queue *rq = container_of(napi,
1976 struct vmxnet3_rx_queue, napi);
1977 struct vmxnet3_adapter *adapter = rq->adapter;
1980 /* When sharing interrupt with corresponding tx queue, process
1981 * tx completions in that queue as well
1983 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1984 struct vmxnet3_tx_queue *tq =
1985 &adapter->tx_queue[rq - adapter->rx_queue];
1986 vmxnet3_tq_tx_complete(tq, adapter);
1989 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
1991 if (rxd_done < budget) {
1992 napi_complete_done(napi, rxd_done);
1993 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
1999 #ifdef CONFIG_PCI_MSI
2002 * Handle completion interrupts on tx queues
2003 * Returns whether or not the intr is handled
2007 vmxnet3_msix_tx(int irq, void *data)
2009 struct vmxnet3_tx_queue *tq = data;
2010 struct vmxnet3_adapter *adapter = tq->adapter;
2012 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2013 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2015 /* Handle the case where only one irq is allocate for all tx queues */
2016 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2018 for (i = 0; i < adapter->num_tx_queues; i++) {
2019 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2020 vmxnet3_tq_tx_complete(txq, adapter);
2023 vmxnet3_tq_tx_complete(tq, adapter);
2025 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2032 * Handle completion interrupts on rx queues. Returns whether or not the
2037 vmxnet3_msix_rx(int irq, void *data)
2039 struct vmxnet3_rx_queue *rq = data;
2040 struct vmxnet3_adapter *adapter = rq->adapter;
2042 /* disable intr if needed */
2043 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2044 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2045 napi_schedule(&rq->napi);
2051 *----------------------------------------------------------------------------
2053 * vmxnet3_msix_event --
2055 * vmxnet3 msix event intr handler
2058 * whether or not the intr is handled
2060 *----------------------------------------------------------------------------
2064 vmxnet3_msix_event(int irq, void *data)
2066 struct net_device *dev = data;
2067 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2069 /* disable intr if needed */
2070 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2071 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2073 if (adapter->shared->ecr)
2074 vmxnet3_process_events(adapter);
2076 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2081 #endif /* CONFIG_PCI_MSI */
2084 /* Interrupt handler for vmxnet3 */
2086 vmxnet3_intr(int irq, void *dev_id)
2088 struct net_device *dev = dev_id;
2089 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2091 if (adapter->intr.type == VMXNET3_IT_INTX) {
2092 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2093 if (unlikely(icr == 0))
2099 /* disable intr if needed */
2100 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2101 vmxnet3_disable_all_intrs(adapter);
2103 napi_schedule(&adapter->rx_queue[0].napi);
2108 #ifdef CONFIG_NET_POLL_CONTROLLER
2110 /* netpoll callback. */
2112 vmxnet3_netpoll(struct net_device *netdev)
2114 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2116 switch (adapter->intr.type) {
2117 #ifdef CONFIG_PCI_MSI
2118 case VMXNET3_IT_MSIX: {
2120 for (i = 0; i < adapter->num_rx_queues; i++)
2121 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2125 case VMXNET3_IT_MSI:
2127 vmxnet3_intr(0, adapter->netdev);
2132 #endif /* CONFIG_NET_POLL_CONTROLLER */
2135 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2137 struct vmxnet3_intr *intr = &adapter->intr;
2141 #ifdef CONFIG_PCI_MSI
2142 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2143 for (i = 0; i < adapter->num_tx_queues; i++) {
2144 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2145 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2146 adapter->netdev->name, vector);
2148 intr->msix_entries[vector].vector,
2150 adapter->tx_queue[i].name,
2151 &adapter->tx_queue[i]);
2153 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2154 adapter->netdev->name, vector);
2157 dev_err(&adapter->netdev->dev,
2158 "Failed to request irq for MSIX, %s, "
2160 adapter->tx_queue[i].name, err);
2164 /* Handle the case where only 1 MSIx was allocated for
2166 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2167 for (; i < adapter->num_tx_queues; i++)
2168 adapter->tx_queue[i].comp_ring.intr_idx
2173 adapter->tx_queue[i].comp_ring.intr_idx
2177 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2180 for (i = 0; i < adapter->num_rx_queues; i++) {
2181 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2182 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2183 adapter->netdev->name, vector);
2185 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2186 adapter->netdev->name, vector);
2187 err = request_irq(intr->msix_entries[vector].vector,
2189 adapter->rx_queue[i].name,
2190 &(adapter->rx_queue[i]));
2192 netdev_err(adapter->netdev,
2193 "Failed to request irq for MSIX, "
2195 adapter->rx_queue[i].name, err);
2199 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2202 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2203 adapter->netdev->name, vector);
2204 err = request_irq(intr->msix_entries[vector].vector,
2205 vmxnet3_msix_event, 0,
2206 intr->event_msi_vector_name, adapter->netdev);
2207 intr->event_intr_idx = vector;
2209 } else if (intr->type == VMXNET3_IT_MSI) {
2210 adapter->num_rx_queues = 1;
2211 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2212 adapter->netdev->name, adapter->netdev);
2215 adapter->num_rx_queues = 1;
2216 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2217 IRQF_SHARED, adapter->netdev->name,
2219 #ifdef CONFIG_PCI_MSI
2222 intr->num_intrs = vector + 1;
2224 netdev_err(adapter->netdev,
2225 "Failed to request irq (intr type:%d), error %d\n",
2228 /* Number of rx queues will not change after this */
2229 for (i = 0; i < adapter->num_rx_queues; i++) {
2230 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2232 rq->qid2 = i + adapter->num_rx_queues;
2233 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2236 /* init our intr settings */
2237 for (i = 0; i < intr->num_intrs; i++)
2238 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2239 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2240 adapter->intr.event_intr_idx = 0;
2241 for (i = 0; i < adapter->num_tx_queues; i++)
2242 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2243 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2246 netdev_info(adapter->netdev,
2247 "intr type %u, mode %u, %u vectors allocated\n",
2248 intr->type, intr->mask_mode, intr->num_intrs);
2256 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2258 struct vmxnet3_intr *intr = &adapter->intr;
2259 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2261 switch (intr->type) {
2262 #ifdef CONFIG_PCI_MSI
2263 case VMXNET3_IT_MSIX:
2267 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2268 for (i = 0; i < adapter->num_tx_queues; i++) {
2269 free_irq(intr->msix_entries[vector++].vector,
2270 &(adapter->tx_queue[i]));
2271 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2276 for (i = 0; i < adapter->num_rx_queues; i++) {
2277 free_irq(intr->msix_entries[vector++].vector,
2278 &(adapter->rx_queue[i]));
2281 free_irq(intr->msix_entries[vector].vector,
2283 BUG_ON(vector >= intr->num_intrs);
2287 case VMXNET3_IT_MSI:
2288 free_irq(adapter->pdev->irq, adapter->netdev);
2290 case VMXNET3_IT_INTX:
2291 free_irq(adapter->pdev->irq, adapter->netdev);
2300 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2302 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2305 /* allow untagged pkts */
2306 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2308 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2309 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2314 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2316 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2318 if (!(netdev->flags & IFF_PROMISC)) {
2319 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2320 unsigned long flags;
2322 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2323 spin_lock_irqsave(&adapter->cmd_lock, flags);
2324 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2325 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2326 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2329 set_bit(vid, adapter->active_vlans);
2336 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2338 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2340 if (!(netdev->flags & IFF_PROMISC)) {
2341 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2342 unsigned long flags;
2344 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2345 spin_lock_irqsave(&adapter->cmd_lock, flags);
2346 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2347 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2348 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2351 clear_bit(vid, adapter->active_vlans);
2358 vmxnet3_copy_mc(struct net_device *netdev)
2361 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2363 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2365 /* We may be called with BH disabled */
2366 buf = kmalloc(sz, GFP_ATOMIC);
2368 struct netdev_hw_addr *ha;
2371 netdev_for_each_mc_addr(ha, netdev)
2372 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2381 vmxnet3_set_mc(struct net_device *netdev)
2383 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2384 unsigned long flags;
2385 struct Vmxnet3_RxFilterConf *rxConf =
2386 &adapter->shared->devRead.rxFilterConf;
2387 u8 *new_table = NULL;
2388 dma_addr_t new_table_pa = 0;
2389 bool new_table_pa_valid = false;
2390 u32 new_mode = VMXNET3_RXM_UCAST;
2392 if (netdev->flags & IFF_PROMISC) {
2393 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2394 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2396 new_mode |= VMXNET3_RXM_PROMISC;
2398 vmxnet3_restore_vlan(adapter);
2401 if (netdev->flags & IFF_BROADCAST)
2402 new_mode |= VMXNET3_RXM_BCAST;
2404 if (netdev->flags & IFF_ALLMULTI)
2405 new_mode |= VMXNET3_RXM_ALL_MULTI;
2407 if (!netdev_mc_empty(netdev)) {
2408 new_table = vmxnet3_copy_mc(netdev);
2410 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2412 rxConf->mfTableLen = cpu_to_le16(sz);
2413 new_table_pa = dma_map_single(
2414 &adapter->pdev->dev,
2418 if (!dma_mapping_error(&adapter->pdev->dev,
2420 new_mode |= VMXNET3_RXM_MCAST;
2421 new_table_pa_valid = true;
2422 rxConf->mfTablePA = cpu_to_le64(
2426 if (!new_table_pa_valid) {
2428 "failed to copy mcast list, setting ALL_MULTI\n");
2429 new_mode |= VMXNET3_RXM_ALL_MULTI;
2433 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2434 rxConf->mfTableLen = 0;
2435 rxConf->mfTablePA = 0;
2438 spin_lock_irqsave(&adapter->cmd_lock, flags);
2439 if (new_mode != rxConf->rxMode) {
2440 rxConf->rxMode = cpu_to_le32(new_mode);
2441 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2442 VMXNET3_CMD_UPDATE_RX_MODE);
2443 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2444 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2447 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2448 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2449 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2451 if (new_table_pa_valid)
2452 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2453 rxConf->mfTableLen, PCI_DMA_TODEVICE);
2458 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2462 for (i = 0; i < adapter->num_rx_queues; i++)
2463 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2468 * Set up driver_shared based on settings in adapter.
2472 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2474 struct Vmxnet3_DriverShared *shared = adapter->shared;
2475 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2476 struct Vmxnet3_TxQueueConf *tqc;
2477 struct Vmxnet3_RxQueueConf *rqc;
2480 memset(shared, 0, sizeof(*shared));
2482 /* driver settings */
2483 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2484 devRead->misc.driverInfo.version = cpu_to_le32(
2485 VMXNET3_DRIVER_VERSION_NUM);
2486 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2487 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2488 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2489 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2490 *((u32 *)&devRead->misc.driverInfo.gos));
2491 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2492 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2494 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2495 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2497 /* set up feature flags */
2498 if (adapter->netdev->features & NETIF_F_RXCSUM)
2499 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2501 if (adapter->netdev->features & NETIF_F_LRO) {
2502 devRead->misc.uptFeatures |= UPT1_F_LRO;
2503 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2505 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2506 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2508 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2509 NETIF_F_GSO_UDP_TUNNEL_CSUM))
2510 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2512 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2513 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2514 devRead->misc.queueDescLen = cpu_to_le32(
2515 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2516 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2518 /* tx queue settings */
2519 devRead->misc.numTxQueues = adapter->num_tx_queues;
2520 for (i = 0; i < adapter->num_tx_queues; i++) {
2521 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2522 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2523 tqc = &adapter->tqd_start[i].conf;
2524 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2525 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2526 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2527 tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
2528 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2529 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2530 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2531 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2532 tqc->ddLen = cpu_to_le32(
2533 sizeof(struct vmxnet3_tx_buf_info) *
2535 tqc->intrIdx = tq->comp_ring.intr_idx;
2538 /* rx queue settings */
2539 devRead->misc.numRxQueues = adapter->num_rx_queues;
2540 for (i = 0; i < adapter->num_rx_queues; i++) {
2541 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2542 rqc = &adapter->rqd_start[i].conf;
2543 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2544 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2545 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2546 rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
2547 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2548 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2549 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2550 rqc->ddLen = cpu_to_le32(
2551 sizeof(struct vmxnet3_rx_buf_info) *
2552 (rqc->rxRingSize[0] +
2553 rqc->rxRingSize[1]));
2554 rqc->intrIdx = rq->comp_ring.intr_idx;
2555 if (VMXNET3_VERSION_GE_3(adapter)) {
2556 rqc->rxDataRingBasePA =
2557 cpu_to_le64(rq->data_ring.basePA);
2558 rqc->rxDataRingDescSize =
2559 cpu_to_le16(rq->data_ring.desc_size);
2564 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2567 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2569 devRead->misc.uptFeatures |= UPT1_F_RSS;
2570 devRead->misc.numRxQueues = adapter->num_rx_queues;
2571 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2572 UPT1_RSS_HASH_TYPE_IPV4 |
2573 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2574 UPT1_RSS_HASH_TYPE_IPV6;
2575 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2576 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2577 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2578 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2580 for (i = 0; i < rssConf->indTableSize; i++)
2581 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2582 i, adapter->num_rx_queues);
2584 devRead->rssConfDesc.confVer = 1;
2585 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2586 devRead->rssConfDesc.confPA =
2587 cpu_to_le64(adapter->rss_conf_pa);
2590 #endif /* VMXNET3_RSS */
2593 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2595 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2596 for (i = 0; i < adapter->intr.num_intrs; i++)
2597 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2599 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2600 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2602 /* rx filter settings */
2603 devRead->rxFilterConf.rxMode = 0;
2604 vmxnet3_restore_vlan(adapter);
2605 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2607 /* the rest are already zeroed */
2611 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2613 struct Vmxnet3_DriverShared *shared = adapter->shared;
2614 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2615 unsigned long flags;
2617 if (!VMXNET3_VERSION_GE_3(adapter))
2620 spin_lock_irqsave(&adapter->cmd_lock, flags);
2621 cmdInfo->varConf.confVer = 1;
2622 cmdInfo->varConf.confLen =
2623 cpu_to_le32(sizeof(*adapter->coal_conf));
2624 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2626 if (adapter->default_coal_mode) {
2627 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2628 VMXNET3_CMD_GET_COALESCE);
2630 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2631 VMXNET3_CMD_SET_COALESCE);
2634 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2638 vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2640 struct Vmxnet3_DriverShared *shared = adapter->shared;
2641 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2642 unsigned long flags;
2644 if (!VMXNET3_VERSION_GE_4(adapter))
2647 spin_lock_irqsave(&adapter->cmd_lock, flags);
2649 if (adapter->default_rss_fields) {
2650 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2651 VMXNET3_CMD_GET_RSS_FIELDS);
2652 adapter->rss_fields =
2653 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2655 cmdInfo->setRssFields = adapter->rss_fields;
2656 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2657 VMXNET3_CMD_SET_RSS_FIELDS);
2658 /* Not all requested RSS may get applied, so get and
2659 * cache what was actually applied.
2661 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2662 VMXNET3_CMD_GET_RSS_FIELDS);
2663 adapter->rss_fields =
2664 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2667 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2671 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2675 unsigned long flags;
2677 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2678 " ring sizes %u %u %u\n", adapter->netdev->name,
2679 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2680 adapter->tx_queue[0].tx_ring.size,
2681 adapter->rx_queue[0].rx_ring[0].size,
2682 adapter->rx_queue[0].rx_ring[1].size);
2684 vmxnet3_tq_init_all(adapter);
2685 err = vmxnet3_rq_init_all(adapter);
2687 netdev_err(adapter->netdev,
2688 "Failed to init rx queue error %d\n", err);
2692 err = vmxnet3_request_irqs(adapter);
2694 netdev_err(adapter->netdev,
2695 "Failed to setup irq for error %d\n", err);
2699 vmxnet3_setup_driver_shared(adapter);
2701 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2702 adapter->shared_pa));
2703 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2704 adapter->shared_pa));
2705 spin_lock_irqsave(&adapter->cmd_lock, flags);
2706 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2707 VMXNET3_CMD_ACTIVATE_DEV);
2708 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2709 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2712 netdev_err(adapter->netdev,
2713 "Failed to activate dev: error %u\n", ret);
2718 vmxnet3_init_coalesce(adapter);
2719 vmxnet3_init_rssfields(adapter);
2721 for (i = 0; i < adapter->num_rx_queues; i++) {
2722 VMXNET3_WRITE_BAR0_REG(adapter,
2723 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2724 adapter->rx_queue[i].rx_ring[0].next2fill);
2725 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2726 (i * VMXNET3_REG_ALIGN)),
2727 adapter->rx_queue[i].rx_ring[1].next2fill);
2730 /* Apply the rx filter settins last. */
2731 vmxnet3_set_mc(adapter->netdev);
2734 * Check link state when first activating device. It will start the
2735 * tx queue if the link is up.
2737 vmxnet3_check_link(adapter, true);
2738 for (i = 0; i < adapter->num_rx_queues; i++)
2739 napi_enable(&adapter->rx_queue[i].napi);
2740 vmxnet3_enable_all_intrs(adapter);
2741 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2745 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2746 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2747 vmxnet3_free_irqs(adapter);
2750 /* free up buffers we allocated */
2751 vmxnet3_rq_cleanup_all(adapter);
2757 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2759 unsigned long flags;
2760 spin_lock_irqsave(&adapter->cmd_lock, flags);
2761 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2762 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2767 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2770 unsigned long flags;
2771 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2775 spin_lock_irqsave(&adapter->cmd_lock, flags);
2776 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2777 VMXNET3_CMD_QUIESCE_DEV);
2778 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2779 vmxnet3_disable_all_intrs(adapter);
2781 for (i = 0; i < adapter->num_rx_queues; i++)
2782 napi_disable(&adapter->rx_queue[i].napi);
2783 netif_tx_disable(adapter->netdev);
2784 adapter->link_speed = 0;
2785 netif_carrier_off(adapter->netdev);
2787 vmxnet3_tq_cleanup_all(adapter);
2788 vmxnet3_rq_cleanup_all(adapter);
2789 vmxnet3_free_irqs(adapter);
2795 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2800 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2802 tmp = (mac[5] << 8) | mac[4];
2803 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2808 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2810 struct sockaddr *addr = p;
2811 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2813 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2814 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2820 /* ==================== initialization and cleanup routines ============ */
2823 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
2826 unsigned long mmio_start, mmio_len;
2827 struct pci_dev *pdev = adapter->pdev;
2829 err = pci_enable_device(pdev);
2831 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2835 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2836 vmxnet3_driver_name);
2839 "Failed to request region for adapter: error %d\n", err);
2840 goto err_enable_device;
2843 pci_set_master(pdev);
2845 mmio_start = pci_resource_start(pdev, 0);
2846 mmio_len = pci_resource_len(pdev, 0);
2847 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2848 if (!adapter->hw_addr0) {
2849 dev_err(&pdev->dev, "Failed to map bar0\n");
2854 mmio_start = pci_resource_start(pdev, 1);
2855 mmio_len = pci_resource_len(pdev, 1);
2856 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2857 if (!adapter->hw_addr1) {
2858 dev_err(&pdev->dev, "Failed to map bar1\n");
2865 iounmap(adapter->hw_addr0);
2867 pci_release_selected_regions(pdev, (1 << 2) - 1);
2869 pci_disable_device(pdev);
2875 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2877 BUG_ON(!adapter->pdev);
2879 iounmap(adapter->hw_addr0);
2880 iounmap(adapter->hw_addr1);
2881 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2882 pci_disable_device(adapter->pdev);
2887 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2889 size_t sz, i, ring0_size, ring1_size, comp_size;
2890 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2891 VMXNET3_MAX_ETH_HDR_SIZE) {
2892 adapter->skb_buf_size = adapter->netdev->mtu +
2893 VMXNET3_MAX_ETH_HDR_SIZE;
2894 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2895 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2897 adapter->rx_buf_per_pkt = 1;
2899 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2900 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2901 VMXNET3_MAX_ETH_HDR_SIZE;
2902 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2906 * for simplicity, force the ring0 size to be a multiple of
2907 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2909 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2910 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2911 ring0_size = (ring0_size + sz - 1) / sz * sz;
2912 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2914 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2915 ring1_size = (ring1_size + sz - 1) / sz * sz;
2916 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2918 comp_size = ring0_size + ring1_size;
2920 for (i = 0; i < adapter->num_rx_queues; i++) {
2921 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2923 rq->rx_ring[0].size = ring0_size;
2924 rq->rx_ring[1].size = ring1_size;
2925 rq->comp_ring.size = comp_size;
2931 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2932 u32 rx_ring_size, u32 rx_ring2_size,
2933 u16 txdata_desc_size, u16 rxdata_desc_size)
2937 for (i = 0; i < adapter->num_tx_queues; i++) {
2938 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2939 tq->tx_ring.size = tx_ring_size;
2940 tq->data_ring.size = tx_ring_size;
2941 tq->comp_ring.size = tx_ring_size;
2942 tq->txdata_desc_size = txdata_desc_size;
2943 tq->shared = &adapter->tqd_start[i].ctrl;
2945 tq->adapter = adapter;
2947 err = vmxnet3_tq_create(tq, adapter);
2949 * Too late to change num_tx_queues. We cannot do away with
2950 * lesser number of queues than what we asked for
2956 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2957 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2958 vmxnet3_adjust_rx_ring_size(adapter);
2960 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
2961 for (i = 0; i < adapter->num_rx_queues; i++) {
2962 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2963 /* qid and qid2 for rx queues will be assigned later when num
2964 * of rx queues is finalized after allocating intrs */
2965 rq->shared = &adapter->rqd_start[i].ctrl;
2966 rq->adapter = adapter;
2967 rq->data_ring.desc_size = rxdata_desc_size;
2968 err = vmxnet3_rq_create(rq, adapter);
2971 netdev_err(adapter->netdev,
2972 "Could not allocate any rx queues. "
2976 netdev_info(adapter->netdev,
2977 "Number of rx queues changed "
2979 adapter->num_rx_queues = i;
2986 if (!adapter->rxdataring_enabled)
2987 vmxnet3_rq_destroy_all_rxdataring(adapter);
2991 vmxnet3_tq_destroy_all(adapter);
2996 vmxnet3_open(struct net_device *netdev)
2998 struct vmxnet3_adapter *adapter;
3001 adapter = netdev_priv(netdev);
3003 for (i = 0; i < adapter->num_tx_queues; i++)
3004 spin_lock_init(&adapter->tx_queue[i].tx_lock);
3006 if (VMXNET3_VERSION_GE_3(adapter)) {
3007 unsigned long flags;
3008 u16 txdata_desc_size;
3010 spin_lock_irqsave(&adapter->cmd_lock, flags);
3011 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3012 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
3013 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
3015 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3017 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3018 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3019 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3020 adapter->txdata_desc_size =
3021 sizeof(struct Vmxnet3_TxDataDesc);
3023 adapter->txdata_desc_size = txdata_desc_size;
3026 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3029 err = vmxnet3_create_queues(adapter,
3030 adapter->tx_ring_size,
3031 adapter->rx_ring_size,
3032 adapter->rx_ring2_size,
3033 adapter->txdata_desc_size,
3034 adapter->rxdata_desc_size);
3038 err = vmxnet3_activate_dev(adapter);
3045 vmxnet3_rq_destroy_all(adapter);
3046 vmxnet3_tq_destroy_all(adapter);
3053 vmxnet3_close(struct net_device *netdev)
3055 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3058 * Reset_work may be in the middle of resetting the device, wait for its
3061 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3062 usleep_range(1000, 2000);
3064 vmxnet3_quiesce_dev(adapter);
3066 vmxnet3_rq_destroy_all(adapter);
3067 vmxnet3_tq_destroy_all(adapter);
3069 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3077 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3082 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3083 * vmxnet3_close() will deadlock.
3085 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3087 /* we need to enable NAPI, otherwise dev_close will deadlock */
3088 for (i = 0; i < adapter->num_rx_queues; i++)
3089 napi_enable(&adapter->rx_queue[i].napi);
3091 * Need to clear the quiesce bit to ensure that vmxnet3_close
3092 * can quiesce the device properly
3094 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3095 dev_close(adapter->netdev);
3100 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3102 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3105 netdev->mtu = new_mtu;
3108 * Reset_work may be in the middle of resetting the device, wait for its
3111 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3112 usleep_range(1000, 2000);
3114 if (netif_running(netdev)) {
3115 vmxnet3_quiesce_dev(adapter);
3116 vmxnet3_reset_dev(adapter);
3118 /* we need to re-create the rx queue based on the new mtu */
3119 vmxnet3_rq_destroy_all(adapter);
3120 vmxnet3_adjust_rx_ring_size(adapter);
3121 err = vmxnet3_rq_create_all(adapter);
3124 "failed to re-create rx queues, "
3125 " error %d. Closing it.\n", err);
3129 err = vmxnet3_activate_dev(adapter);
3132 "failed to re-activate, error %d. "
3133 "Closing it\n", err);
3139 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3141 vmxnet3_force_close(adapter);
3148 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3150 struct net_device *netdev = adapter->netdev;
3152 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3153 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3154 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3157 if (VMXNET3_VERSION_GE_4(adapter)) {
3158 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3159 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3161 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3162 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3163 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3164 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3165 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3169 netdev->hw_features |= NETIF_F_HIGHDMA;
3170 netdev->vlan_features = netdev->hw_features &
3171 ~(NETIF_F_HW_VLAN_CTAG_TX |
3172 NETIF_F_HW_VLAN_CTAG_RX);
3173 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3178 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3182 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3185 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3186 mac[4] = tmp & 0xff;
3187 mac[5] = (tmp >> 8) & 0xff;
3190 #ifdef CONFIG_PCI_MSI
3193 * Enable MSIx vectors.
3195 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3197 * number of vectors which were enabled otherwise (this number is greater
3198 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3202 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3204 int ret = pci_enable_msix_range(adapter->pdev,
3205 adapter->intr.msix_entries, nvec, nvec);
3207 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3208 dev_err(&adapter->netdev->dev,
3209 "Failed to enable %d MSI-X, trying %d\n",
3210 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3212 ret = pci_enable_msix_range(adapter->pdev,
3213 adapter->intr.msix_entries,
3214 VMXNET3_LINUX_MIN_MSIX_VECT,
3215 VMXNET3_LINUX_MIN_MSIX_VECT);
3219 dev_err(&adapter->netdev->dev,
3220 "Failed to enable MSI-X, error: %d\n", ret);
3227 #endif /* CONFIG_PCI_MSI */
3230 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3233 unsigned long flags;
3236 spin_lock_irqsave(&adapter->cmd_lock, flags);
3237 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3238 VMXNET3_CMD_GET_CONF_INTR);
3239 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3240 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3241 adapter->intr.type = cfg & 0x3;
3242 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3244 if (adapter->intr.type == VMXNET3_IT_AUTO) {
3245 adapter->intr.type = VMXNET3_IT_MSIX;
3248 #ifdef CONFIG_PCI_MSI
3249 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3252 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3253 1 : adapter->num_tx_queues;
3254 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3255 0 : adapter->num_rx_queues;
3256 nvec += 1; /* for link event */
3257 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3258 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3260 for (i = 0; i < nvec; i++)
3261 adapter->intr.msix_entries[i].entry = i;
3263 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3267 /* If we cannot allocate one MSIx vector per queue
3268 * then limit the number of rx queues to 1
3270 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
3271 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3272 || adapter->num_rx_queues != 1) {
3273 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3274 netdev_err(adapter->netdev,
3275 "Number of rx queues : 1\n");
3276 adapter->num_rx_queues = 1;
3280 adapter->intr.num_intrs = nvec;
3284 /* If we cannot allocate MSIx vectors use only one rx queue */
3285 dev_info(&adapter->pdev->dev,
3286 "Failed to enable MSI-X, error %d. "
3287 "Limiting #rx queues to 1, try MSI.\n", nvec);
3289 adapter->intr.type = VMXNET3_IT_MSI;
3292 if (adapter->intr.type == VMXNET3_IT_MSI) {
3293 if (!pci_enable_msi(adapter->pdev)) {
3294 adapter->num_rx_queues = 1;
3295 adapter->intr.num_intrs = 1;
3299 #endif /* CONFIG_PCI_MSI */
3301 adapter->num_rx_queues = 1;
3302 dev_info(&adapter->netdev->dev,
3303 "Using INTx interrupt, #Rx queues: 1.\n");
3304 adapter->intr.type = VMXNET3_IT_INTX;
3306 /* INT-X related setting */
3307 adapter->intr.num_intrs = 1;
3312 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3314 if (adapter->intr.type == VMXNET3_IT_MSIX)
3315 pci_disable_msix(adapter->pdev);
3316 else if (adapter->intr.type == VMXNET3_IT_MSI)
3317 pci_disable_msi(adapter->pdev);
3319 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3324 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3326 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3327 adapter->tx_timeout_count++;
3329 netdev_err(adapter->netdev, "tx hang\n");
3330 schedule_work(&adapter->work);
3335 vmxnet3_reset_work(struct work_struct *data)
3337 struct vmxnet3_adapter *adapter;
3339 adapter = container_of(data, struct vmxnet3_adapter, work);
3341 /* if another thread is resetting the device, no need to proceed */
3342 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3345 /* if the device is closed, we must leave it alone */
3347 if (netif_running(adapter->netdev)) {
3348 netdev_notice(adapter->netdev, "resetting\n");
3349 vmxnet3_quiesce_dev(adapter);
3350 vmxnet3_reset_dev(adapter);
3351 vmxnet3_activate_dev(adapter);
3353 netdev_info(adapter->netdev, "already closed\n");
3357 netif_wake_queue(adapter->netdev);
3358 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3363 vmxnet3_probe_device(struct pci_dev *pdev,
3364 const struct pci_device_id *id)
3366 static const struct net_device_ops vmxnet3_netdev_ops = {
3367 .ndo_open = vmxnet3_open,
3368 .ndo_stop = vmxnet3_close,
3369 .ndo_start_xmit = vmxnet3_xmit_frame,
3370 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3371 .ndo_change_mtu = vmxnet3_change_mtu,
3372 .ndo_fix_features = vmxnet3_fix_features,
3373 .ndo_set_features = vmxnet3_set_features,
3374 .ndo_get_stats64 = vmxnet3_get_stats64,
3375 .ndo_tx_timeout = vmxnet3_tx_timeout,
3376 .ndo_set_rx_mode = vmxnet3_set_mc,
3377 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3378 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3379 #ifdef CONFIG_NET_POLL_CONTROLLER
3380 .ndo_poll_controller = vmxnet3_netpoll,
3386 struct net_device *netdev;
3387 struct vmxnet3_adapter *adapter;
3393 if (!pci_msi_enabled())
3398 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3399 (int)num_online_cpus());
3403 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3406 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3407 (int)num_online_cpus());
3411 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3412 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3413 max(num_tx_queues, num_rx_queues));
3414 dev_info(&pdev->dev,
3415 "# of Tx queues : %d, # of Rx queues : %d\n",
3416 num_tx_queues, num_rx_queues);
3421 pci_set_drvdata(pdev, netdev);
3422 adapter = netdev_priv(netdev);
3423 adapter->netdev = netdev;
3424 adapter->pdev = pdev;
3426 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3427 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3428 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3430 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
3431 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
3433 "pci_set_consistent_dma_mask failed\n");
3439 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
3441 "pci_set_dma_mask failed\n");
3448 spin_lock_init(&adapter->cmd_lock);
3449 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3450 sizeof(struct vmxnet3_adapter),
3452 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3453 dev_err(&pdev->dev, "Failed to map dma\n");
3457 adapter->shared = dma_alloc_coherent(
3458 &adapter->pdev->dev,
3459 sizeof(struct Vmxnet3_DriverShared),
3460 &adapter->shared_pa, GFP_KERNEL);
3461 if (!adapter->shared) {
3462 dev_err(&pdev->dev, "Failed to allocate memory\n");
3464 goto err_alloc_shared;
3467 adapter->num_rx_queues = num_rx_queues;
3468 adapter->num_tx_queues = num_tx_queues;
3469 adapter->rx_buf_per_pkt = 1;
3471 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3472 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3473 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3474 &adapter->queue_desc_pa,
3477 if (!adapter->tqd_start) {
3478 dev_err(&pdev->dev, "Failed to allocate memory\n");
3480 goto err_alloc_queue_desc;
3482 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3483 adapter->num_tx_queues);
3485 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3486 sizeof(struct Vmxnet3_PMConf),
3487 &adapter->pm_conf_pa,
3489 if (adapter->pm_conf == NULL) {
3496 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3497 sizeof(struct UPT1_RSSConf),
3498 &adapter->rss_conf_pa,
3500 if (adapter->rss_conf == NULL) {
3504 #endif /* VMXNET3_RSS */
3506 err = vmxnet3_alloc_pci_resources(adapter);
3510 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3511 if (ver & (1 << VMXNET3_REV_4)) {
3512 VMXNET3_WRITE_BAR1_REG(adapter,
3514 1 << VMXNET3_REV_4);
3515 adapter->version = VMXNET3_REV_4 + 1;
3516 } else if (ver & (1 << VMXNET3_REV_3)) {
3517 VMXNET3_WRITE_BAR1_REG(adapter,
3519 1 << VMXNET3_REV_3);
3520 adapter->version = VMXNET3_REV_3 + 1;
3521 } else if (ver & (1 << VMXNET3_REV_2)) {
3522 VMXNET3_WRITE_BAR1_REG(adapter,
3524 1 << VMXNET3_REV_2);
3525 adapter->version = VMXNET3_REV_2 + 1;
3526 } else if (ver & (1 << VMXNET3_REV_1)) {
3527 VMXNET3_WRITE_BAR1_REG(adapter,
3529 1 << VMXNET3_REV_1);
3530 adapter->version = VMXNET3_REV_1 + 1;
3533 "Incompatible h/w version (0x%x) for adapter\n", ver);
3537 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3539 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3541 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3544 "Incompatible upt version (0x%x) for adapter\n", ver);
3549 if (VMXNET3_VERSION_GE_3(adapter)) {
3550 adapter->coal_conf =
3551 dma_alloc_coherent(&adapter->pdev->dev,
3552 sizeof(struct Vmxnet3_CoalesceScheme)
3554 &adapter->coal_conf_pa,
3556 if (!adapter->coal_conf) {
3560 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3561 adapter->default_coal_mode = true;
3564 if (VMXNET3_VERSION_GE_4(adapter)) {
3565 adapter->default_rss_fields = true;
3566 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
3569 SET_NETDEV_DEV(netdev, &pdev->dev);
3570 vmxnet3_declare_features(adapter, dma64);
3572 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3573 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3575 if (adapter->num_tx_queues == adapter->num_rx_queues)
3576 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3578 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3580 vmxnet3_alloc_intr_resources(adapter);
3583 if (adapter->num_rx_queues > 1 &&
3584 adapter->intr.type == VMXNET3_IT_MSIX) {
3585 adapter->rss = true;
3586 netdev->hw_features |= NETIF_F_RXHASH;
3587 netdev->features |= NETIF_F_RXHASH;
3588 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3590 adapter->rss = false;
3594 vmxnet3_read_mac_addr(adapter, mac);
3595 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3597 netdev->netdev_ops = &vmxnet3_netdev_ops;
3598 vmxnet3_set_ethtool_ops(netdev);
3599 netdev->watchdog_timeo = 5 * HZ;
3601 /* MTU range: 60 - 9000 */
3602 netdev->min_mtu = VMXNET3_MIN_MTU;
3603 netdev->max_mtu = VMXNET3_MAX_MTU;
3605 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3606 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3608 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3610 for (i = 0; i < adapter->num_rx_queues; i++) {
3611 netif_napi_add(adapter->netdev,
3612 &adapter->rx_queue[i].napi,
3613 vmxnet3_poll_rx_only, 64);
3616 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3620 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3621 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3623 netif_carrier_off(netdev);
3624 err = register_netdev(netdev);
3627 dev_err(&pdev->dev, "Failed to register adapter\n");
3631 vmxnet3_check_link(adapter, false);
3635 if (VMXNET3_VERSION_GE_3(adapter)) {
3636 dma_free_coherent(&adapter->pdev->dev,
3637 sizeof(struct Vmxnet3_CoalesceScheme),
3638 adapter->coal_conf, adapter->coal_conf_pa);
3640 vmxnet3_free_intr_resources(adapter);
3642 vmxnet3_free_pci_resources(adapter);
3645 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3646 adapter->rss_conf, adapter->rss_conf_pa);
3649 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3650 adapter->pm_conf, adapter->pm_conf_pa);
3652 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3653 adapter->queue_desc_pa);
3654 err_alloc_queue_desc:
3655 dma_free_coherent(&adapter->pdev->dev,
3656 sizeof(struct Vmxnet3_DriverShared),
3657 adapter->shared, adapter->shared_pa);
3659 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3660 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3662 free_netdev(netdev);
3668 vmxnet3_remove_device(struct pci_dev *pdev)
3670 struct net_device *netdev = pci_get_drvdata(pdev);
3671 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3677 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3678 (int)num_online_cpus());
3682 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3684 cancel_work_sync(&adapter->work);
3686 unregister_netdev(netdev);
3688 vmxnet3_free_intr_resources(adapter);
3689 vmxnet3_free_pci_resources(adapter);
3690 if (VMXNET3_VERSION_GE_3(adapter)) {
3691 dma_free_coherent(&adapter->pdev->dev,
3692 sizeof(struct Vmxnet3_CoalesceScheme),
3693 adapter->coal_conf, adapter->coal_conf_pa);
3696 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3697 adapter->rss_conf, adapter->rss_conf_pa);
3699 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3700 adapter->pm_conf, adapter->pm_conf_pa);
3702 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3703 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3704 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3705 adapter->queue_desc_pa);
3706 dma_free_coherent(&adapter->pdev->dev,
3707 sizeof(struct Vmxnet3_DriverShared),
3708 adapter->shared, adapter->shared_pa);
3709 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3710 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3711 free_netdev(netdev);
3714 static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3716 struct net_device *netdev = pci_get_drvdata(pdev);
3717 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3718 unsigned long flags;
3720 /* Reset_work may be in the middle of resetting the device, wait for its
3723 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3724 usleep_range(1000, 2000);
3726 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3728 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3731 spin_lock_irqsave(&adapter->cmd_lock, flags);
3732 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3733 VMXNET3_CMD_QUIESCE_DEV);
3734 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3735 vmxnet3_disable_all_intrs(adapter);
3737 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3744 vmxnet3_suspend(struct device *device)
3746 struct pci_dev *pdev = to_pci_dev(device);
3747 struct net_device *netdev = pci_get_drvdata(pdev);
3748 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3749 struct Vmxnet3_PMConf *pmConf;
3750 struct ethhdr *ehdr;
3751 struct arphdr *ahdr;
3753 struct in_device *in_dev;
3754 struct in_ifaddr *ifa;
3755 unsigned long flags;
3758 if (!netif_running(netdev))
3761 for (i = 0; i < adapter->num_rx_queues; i++)
3762 napi_disable(&adapter->rx_queue[i].napi);
3764 vmxnet3_disable_all_intrs(adapter);
3765 vmxnet3_free_irqs(adapter);
3766 vmxnet3_free_intr_resources(adapter);
3768 netif_device_detach(netdev);
3769 netif_tx_stop_all_queues(netdev);
3771 /* Create wake-up filters. */
3772 pmConf = adapter->pm_conf;
3773 memset(pmConf, 0, sizeof(*pmConf));
3775 if (adapter->wol & WAKE_UCAST) {
3776 pmConf->filters[i].patternSize = ETH_ALEN;
3777 pmConf->filters[i].maskSize = 1;
3778 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3779 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3781 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3785 if (adapter->wol & WAKE_ARP) {
3788 in_dev = __in_dev_get_rcu(netdev);
3794 ifa = rcu_dereference(in_dev->ifa_list);
3800 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3801 sizeof(struct arphdr) + /* ARP header */
3802 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3803 2 * sizeof(u32); /*2 IPv4 addresses */
3804 pmConf->filters[i].maskSize =
3805 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3807 /* ETH_P_ARP in Ethernet header. */
3808 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3809 ehdr->h_proto = htons(ETH_P_ARP);
3811 /* ARPOP_REQUEST in ARP header. */
3812 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3813 ahdr->ar_op = htons(ARPOP_REQUEST);
3814 arpreq = (u8 *)(ahdr + 1);
3816 /* The Unicast IPv4 address in 'tip' field. */
3817 arpreq += 2 * ETH_ALEN + sizeof(u32);
3818 *(__be32 *)arpreq = ifa->ifa_address;
3822 /* The mask for the relevant bits. */
3823 pmConf->filters[i].mask[0] = 0x00;
3824 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3825 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3826 pmConf->filters[i].mask[3] = 0x00;
3827 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3828 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3830 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3835 if (adapter->wol & WAKE_MAGIC)
3836 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3838 pmConf->numFilters = i;
3840 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3841 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3843 adapter->shared->devRead.pmConfDesc.confPA =
3844 cpu_to_le64(adapter->pm_conf_pa);
3846 spin_lock_irqsave(&adapter->cmd_lock, flags);
3847 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3848 VMXNET3_CMD_UPDATE_PMCFG);
3849 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3851 pci_save_state(pdev);
3852 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3854 pci_disable_device(pdev);
3855 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3862 vmxnet3_resume(struct device *device)
3865 unsigned long flags;
3866 struct pci_dev *pdev = to_pci_dev(device);
3867 struct net_device *netdev = pci_get_drvdata(pdev);
3868 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3870 if (!netif_running(netdev))
3873 pci_set_power_state(pdev, PCI_D0);
3874 pci_restore_state(pdev);
3875 err = pci_enable_device_mem(pdev);
3879 pci_enable_wake(pdev, PCI_D0, 0);
3881 vmxnet3_alloc_intr_resources(adapter);
3883 /* During hibernate and suspend, device has to be reinitialized as the
3884 * device state need not be preserved.
3887 /* Need not check adapter state as other reset tasks cannot run during
3890 spin_lock_irqsave(&adapter->cmd_lock, flags);
3891 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3892 VMXNET3_CMD_QUIESCE_DEV);
3893 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3894 vmxnet3_tq_cleanup_all(adapter);
3895 vmxnet3_rq_cleanup_all(adapter);
3897 vmxnet3_reset_dev(adapter);
3898 err = vmxnet3_activate_dev(adapter);
3901 "failed to re-activate on resume, error: %d", err);
3902 vmxnet3_force_close(adapter);
3905 netif_device_attach(netdev);
3910 static const struct dev_pm_ops vmxnet3_pm_ops = {
3911 .suspend = vmxnet3_suspend,
3912 .resume = vmxnet3_resume,
3913 .freeze = vmxnet3_suspend,
3914 .restore = vmxnet3_resume,
3918 static struct pci_driver vmxnet3_driver = {
3919 .name = vmxnet3_driver_name,
3920 .id_table = vmxnet3_pciid_table,
3921 .probe = vmxnet3_probe_device,
3922 .remove = vmxnet3_remove_device,
3923 .shutdown = vmxnet3_shutdown_device,
3925 .driver.pm = &vmxnet3_pm_ops,
3931 vmxnet3_init_module(void)
3933 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
3934 VMXNET3_DRIVER_VERSION_REPORT);
3935 return pci_register_driver(&vmxnet3_driver);
3938 module_init(vmxnet3_init_module);
3942 vmxnet3_exit_module(void)
3944 pci_unregister_driver(&vmxnet3_driver);
3947 module_exit(vmxnet3_exit_module);
3949 MODULE_AUTHOR("VMware, Inc.");
3950 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3951 MODULE_LICENSE("GPL v2");
3952 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);