2 * Linux driver for VMware's vmxnet3 ethernet NIC.
4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
23 * Maintained by: pv-drivers@vmware.com
27 #include <linux/module.h>
28 #include <net/ip6_checksum.h>
30 #include "vmxnet3_int.h"
32 char vmxnet3_driver_name[] = "vmxnet3";
33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
37 * Last entry must be all 0s
39 static const struct pci_device_id vmxnet3_pciid_table[] = {
40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
46 static int enable_mq = 1;
49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
52 * Enable/Disable the given intr
55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
69 * Enable/Disable all intrs used by the device
72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
135 * Check the link state. This may start or stop the tx queue.
138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
144 spin_lock_irqsave(&adapter->cmd_lock, flags);
145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
153 netif_carrier_on(adapter->netdev);
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
161 netdev_info(adapter->netdev, "NIC Link is Down\n");
162 netif_carrier_off(adapter->netdev);
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
172 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
176 u32 events = le32_to_cpu(adapter->shared->ecr);
180 vmxnet3_ack_events(adapter, events);
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
184 vmxnet3_check_link(adapter, true);
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
188 spin_lock_irqsave(&adapter->cmd_lock, flags);
189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
206 schedule_work(&adapter->work);
210 #ifdef __BIG_ENDIAN_BITFIELD
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
244 *dst = cpu_to_le32(*src);
249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
263 /* Used to read bitfield values from double words. */
264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
275 #endif /* __BIG_ENDIAN_BITFIELD */
277 #ifdef __BIG_ENDIAN_BITFIELD
279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
308 #endif /* __BIG_ENDIAN_BITFIELD */
312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
339 skb = tq->buf_info[eop_idx].skb;
341 tq->buf_info[eop_idx].skb = NULL;
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
358 dev_kfree_skb_any(skb);
364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
368 union Vmxnet3_GenericDesc *gdesc;
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 /* Prevent any &gdesc->tcd field from being (speculatively)
373 * read before (&gdesc->tcd)->gen is read.
377 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
378 &gdesc->tcd), tq, adapter->pdev,
381 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
386 spin_lock(&tq->tx_lock);
387 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
388 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
389 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
390 netif_carrier_ok(adapter->netdev))) {
391 vmxnet3_tq_wake(tq, adapter);
393 spin_unlock(&tq->tx_lock);
400 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
401 struct vmxnet3_adapter *adapter)
405 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
406 struct vmxnet3_tx_buf_info *tbi;
408 tbi = tq->buf_info + tq->tx_ring.next2comp;
410 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
412 dev_kfree_skb_any(tbi->skb);
415 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
418 /* sanity check, verify all buffers are indeed unmapped and freed */
419 for (i = 0; i < tq->tx_ring.size; i++) {
420 BUG_ON(tq->buf_info[i].skb != NULL ||
421 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
424 tq->tx_ring.gen = VMXNET3_INIT_GEN;
425 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
427 tq->comp_ring.gen = VMXNET3_INIT_GEN;
428 tq->comp_ring.next2proc = 0;
433 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
434 struct vmxnet3_adapter *adapter)
436 if (tq->tx_ring.base) {
437 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
438 sizeof(struct Vmxnet3_TxDesc),
439 tq->tx_ring.base, tq->tx_ring.basePA);
440 tq->tx_ring.base = NULL;
442 if (tq->data_ring.base) {
443 dma_free_coherent(&adapter->pdev->dev,
444 tq->data_ring.size * tq->txdata_desc_size,
445 tq->data_ring.base, tq->data_ring.basePA);
446 tq->data_ring.base = NULL;
448 if (tq->comp_ring.base) {
449 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
450 sizeof(struct Vmxnet3_TxCompDesc),
451 tq->comp_ring.base, tq->comp_ring.basePA);
452 tq->comp_ring.base = NULL;
455 dma_free_coherent(&adapter->pdev->dev,
456 tq->tx_ring.size * sizeof(tq->buf_info[0]),
457 tq->buf_info, tq->buf_info_pa);
463 /* Destroy all tx queues */
465 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
469 for (i = 0; i < adapter->num_tx_queues; i++)
470 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
475 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
476 struct vmxnet3_adapter *adapter)
480 /* reset the tx ring contents to 0 and reset the tx ring states */
481 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
482 sizeof(struct Vmxnet3_TxDesc));
483 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
484 tq->tx_ring.gen = VMXNET3_INIT_GEN;
486 memset(tq->data_ring.base, 0,
487 tq->data_ring.size * tq->txdata_desc_size);
489 /* reset the tx comp ring contents to 0 and reset comp ring states */
490 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
491 sizeof(struct Vmxnet3_TxCompDesc));
492 tq->comp_ring.next2proc = 0;
493 tq->comp_ring.gen = VMXNET3_INIT_GEN;
495 /* reset the bookkeeping data */
496 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
497 for (i = 0; i < tq->tx_ring.size; i++)
498 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
500 /* stats are not reset */
505 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
506 struct vmxnet3_adapter *adapter)
510 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
511 tq->comp_ring.base || tq->buf_info);
513 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
514 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
515 &tq->tx_ring.basePA, GFP_KERNEL);
516 if (!tq->tx_ring.base) {
517 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
521 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
522 tq->data_ring.size * tq->txdata_desc_size,
523 &tq->data_ring.basePA, GFP_KERNEL);
524 if (!tq->data_ring.base) {
525 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
529 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
530 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
531 &tq->comp_ring.basePA, GFP_KERNEL);
532 if (!tq->comp_ring.base) {
533 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
537 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
538 tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz,
539 &tq->buf_info_pa, GFP_KERNEL);
546 vmxnet3_tq_destroy(tq, adapter);
551 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
555 for (i = 0; i < adapter->num_tx_queues; i++)
556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
560 * starting from ring->next2fill, allocate rx buffers for the given ring
561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
562 * are allocated or allocation fails
566 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
567 int num_to_alloc, struct vmxnet3_adapter *adapter)
569 int num_allocated = 0;
570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
574 while (num_allocated <= num_to_alloc) {
575 struct vmxnet3_rx_buf_info *rbi;
576 union Vmxnet3_GenericDesc *gd;
578 rbi = rbi_base + ring->next2fill;
579 gd = ring->base + ring->next2fill;
581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
582 if (rbi->skb == NULL) {
583 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
586 if (unlikely(rbi->skb == NULL)) {
587 rq->stats.rx_buf_alloc_failure++;
591 rbi->dma_addr = dma_map_single(
593 rbi->skb->data, rbi->len,
595 if (dma_mapping_error(&adapter->pdev->dev,
597 dev_kfree_skb_any(rbi->skb);
598 rq->stats.rx_buf_alloc_failure++;
602 /* rx buffer skipped by the device */
604 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
606 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
607 rbi->len != PAGE_SIZE);
609 if (rbi->page == NULL) {
610 rbi->page = alloc_page(GFP_ATOMIC);
611 if (unlikely(rbi->page == NULL)) {
612 rq->stats.rx_buf_alloc_failure++;
615 rbi->dma_addr = dma_map_page(
617 rbi->page, 0, PAGE_SIZE,
619 if (dma_mapping_error(&adapter->pdev->dev,
622 rq->stats.rx_buf_alloc_failure++;
626 /* rx buffers skipped by the device */
628 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
631 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
632 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
635 /* Fill the last buffer but dont mark it ready, or else the
636 * device will think that the queue is full */
637 if (num_allocated == num_to_alloc)
640 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
642 vmxnet3_cmd_ring_adv_next2fill(ring);
645 netdev_dbg(adapter->netdev,
646 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
647 num_allocated, ring->next2fill, ring->next2comp);
649 /* so that the device can distinguish a full ring and an empty ring */
650 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
652 return num_allocated;
657 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
658 struct vmxnet3_rx_buf_info *rbi)
660 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
662 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
664 __skb_frag_set_page(frag, rbi->page);
665 skb_frag_off_set(frag, 0);
666 skb_frag_size_set(frag, rcd->len);
667 skb->data_len += rcd->len;
668 skb->truesize += PAGE_SIZE;
669 skb_shinfo(skb)->nr_frags++;
674 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
675 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
676 struct vmxnet3_adapter *adapter)
679 unsigned long buf_offset;
681 union Vmxnet3_GenericDesc *gdesc;
682 struct vmxnet3_tx_buf_info *tbi = NULL;
684 BUG_ON(ctx->copy_size > skb_headlen(skb));
686 /* use the previous gen bit for the SOP desc */
687 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
689 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
690 gdesc = ctx->sop_txd; /* both loops below can be skipped */
692 /* no need to map the buffer if headers are copied */
693 if (ctx->copy_size) {
694 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
695 tq->tx_ring.next2fill *
696 tq->txdata_desc_size);
697 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
698 ctx->sop_txd->dword[3] = 0;
700 tbi = tq->buf_info + tq->tx_ring.next2fill;
701 tbi->map_type = VMXNET3_MAP_NONE;
703 netdev_dbg(adapter->netdev,
704 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
705 tq->tx_ring.next2fill,
706 le64_to_cpu(ctx->sop_txd->txd.addr),
707 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
708 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
710 /* use the right gen for non-SOP desc */
711 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
714 /* linear part can use multiple tx desc if it's big */
715 len = skb_headlen(skb) - ctx->copy_size;
716 buf_offset = ctx->copy_size;
720 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
724 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
725 /* spec says that for TxDesc.len, 0 == 2^14 */
728 tbi = tq->buf_info + tq->tx_ring.next2fill;
729 tbi->map_type = VMXNET3_MAP_SINGLE;
730 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
731 skb->data + buf_offset, buf_size,
733 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
738 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
739 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
741 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
742 gdesc->dword[2] = cpu_to_le32(dw2);
745 netdev_dbg(adapter->netdev,
746 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
747 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
748 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
749 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
750 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
753 buf_offset += buf_size;
756 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
757 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
761 len = skb_frag_size(frag);
763 tbi = tq->buf_info + tq->tx_ring.next2fill;
764 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
768 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
769 /* spec says that for TxDesc.len, 0 == 2^14 */
771 tbi->map_type = VMXNET3_MAP_PAGE;
772 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
773 buf_offset, buf_size,
775 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
780 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
781 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
783 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
784 gdesc->dword[2] = cpu_to_le32(dw2);
787 netdev_dbg(adapter->netdev,
788 "txd[%u]: 0x%llx %u %u\n",
789 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
790 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
791 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
792 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
795 buf_offset += buf_size;
799 ctx->eop_txd = gdesc;
801 /* set the last buf_info for the pkt */
803 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
809 /* Init all tx queues */
811 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
815 for (i = 0; i < adapter->num_tx_queues; i++)
816 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
821 * parse relevant protocol headers:
822 * For a tso pkt, relevant headers are L2/3/4 including options
823 * For a pkt requesting csum offloading, they are L2/3 and may include L4
824 * if it's a TCP/UDP pkt
827 * -1: error happens during parsing
828 * 0: protocol headers parsed, but too big to be copied
829 * 1: protocol headers parsed and copied
832 * 1. related *ctx fields are updated.
833 * 2. ctx->copy_size is # of bytes copied
834 * 3. the portion to be copied is guaranteed to be in the linear part
838 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
839 struct vmxnet3_tx_ctx *ctx,
840 struct vmxnet3_adapter *adapter)
844 if (ctx->mss) { /* TSO */
845 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
846 ctx->l4_offset = skb_inner_transport_offset(skb);
847 ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
848 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
850 ctx->l4_offset = skb_transport_offset(skb);
851 ctx->l4_hdr_size = tcp_hdrlen(skb);
852 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
855 if (skb->ip_summed == CHECKSUM_PARTIAL) {
856 /* For encap packets, skb_checksum_start_offset refers
857 * to inner L4 offset. Thus, below works for encap as
858 * well as non-encap case
860 ctx->l4_offset = skb_checksum_start_offset(skb);
862 if (VMXNET3_VERSION_GE_4(adapter) &&
863 skb->encapsulation) {
864 struct iphdr *iph = inner_ip_hdr(skb);
866 if (iph->version == 4) {
867 protocol = iph->protocol;
869 const struct ipv6hdr *ipv6h;
871 ipv6h = inner_ipv6_hdr(skb);
872 protocol = ipv6h->nexthdr;
876 const struct iphdr *iph = ip_hdr(skb);
878 protocol = iph->protocol;
879 } else if (ctx->ipv6) {
880 const struct ipv6hdr *ipv6h;
882 ipv6h = ipv6_hdr(skb);
883 protocol = ipv6h->nexthdr;
889 ctx->l4_hdr_size = tcp_hdrlen(skb);
892 ctx->l4_hdr_size = sizeof(struct udphdr);
895 ctx->l4_hdr_size = 0;
899 ctx->copy_size = min(ctx->l4_offset +
900 ctx->l4_hdr_size, skb->len);
903 ctx->l4_hdr_size = 0;
904 /* copy as much as allowed */
905 ctx->copy_size = min_t(unsigned int,
906 tq->txdata_desc_size,
910 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
911 ctx->copy_size = skb->len;
913 /* make sure headers are accessible directly */
914 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
918 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
919 tq->stats.oversized_hdr++;
930 * copy relevant protocol headers to the transmit ring:
931 * For a tso pkt, relevant headers are L2/3/4 including options
932 * For a pkt requesting csum offloading, they are L2/3 and may include L4
933 * if it's a TCP/UDP pkt
936 * Note that this requires that vmxnet3_parse_hdr be called first to set the
937 * appropriate bits in ctx first
940 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
941 struct vmxnet3_tx_ctx *ctx,
942 struct vmxnet3_adapter *adapter)
944 struct Vmxnet3_TxDataDesc *tdd;
946 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
947 tq->tx_ring.next2fill *
948 tq->txdata_desc_size);
950 memcpy(tdd->data, skb->data, ctx->copy_size);
951 netdev_dbg(adapter->netdev,
952 "copy %u bytes to dataRing[%u]\n",
953 ctx->copy_size, tq->tx_ring.next2fill);
958 vmxnet3_prepare_inner_tso(struct sk_buff *skb,
959 struct vmxnet3_tx_ctx *ctx)
961 struct tcphdr *tcph = inner_tcp_hdr(skb);
962 struct iphdr *iph = inner_ip_hdr(skb);
964 if (iph->version == 4) {
966 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
969 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
971 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
977 vmxnet3_prepare_tso(struct sk_buff *skb,
978 struct vmxnet3_tx_ctx *ctx)
980 struct tcphdr *tcph = tcp_hdr(skb);
983 struct iphdr *iph = ip_hdr(skb);
986 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
988 } else if (ctx->ipv6) {
989 tcp_v6_gso_csum_prep(skb);
993 static int txd_estimate(const struct sk_buff *skb)
995 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
998 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
999 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1001 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1007 * Transmits a pkt thru a given tq
1009 * NETDEV_TX_OK: descriptors are setup successfully
1010 * NETDEV_TX_OK: error occurred, the pkt is dropped
1011 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
1014 * 1. tx ring may be changed
1015 * 2. tq stats may be updated accordingly
1016 * 3. shared->txNumDeferred may be updated
1020 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1021 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1026 int tx_num_deferred;
1027 unsigned long flags;
1028 struct vmxnet3_tx_ctx ctx;
1029 union Vmxnet3_GenericDesc *gdesc;
1030 #ifdef __BIG_ENDIAN_BITFIELD
1031 /* Use temporary descriptor to avoid touching bits multiple times */
1032 union Vmxnet3_GenericDesc tempTxDesc;
1034 struct udphdr *udph;
1036 count = txd_estimate(skb);
1038 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1039 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1041 ctx.mss = skb_shinfo(skb)->gso_size;
1043 if (skb_header_cloned(skb)) {
1044 if (unlikely(pskb_expand_head(skb, 0, 0,
1045 GFP_ATOMIC) != 0)) {
1046 tq->stats.drop_tso++;
1049 tq->stats.copy_skb_header++;
1051 if (skb->encapsulation) {
1052 vmxnet3_prepare_inner_tso(skb, &ctx);
1054 vmxnet3_prepare_tso(skb, &ctx);
1057 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1059 /* non-tso pkts must not use more than
1060 * VMXNET3_MAX_TXD_PER_PKT entries
1062 if (skb_linearize(skb) != 0) {
1063 tq->stats.drop_too_many_frags++;
1066 tq->stats.linearized++;
1068 /* recalculate the # of descriptors to use */
1069 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1073 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1075 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1076 /* hdrs parsed, check against other limits */
1078 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1079 VMXNET3_MAX_TX_BUF_SIZE)) {
1080 tq->stats.drop_oversized_hdr++;
1084 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1085 if (unlikely(ctx.l4_offset +
1087 VMXNET3_MAX_CSUM_OFFSET)) {
1088 tq->stats.drop_oversized_hdr++;
1094 tq->stats.drop_hdr_inspect_err++;
1098 spin_lock_irqsave(&tq->tx_lock, flags);
1100 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1101 tq->stats.tx_ring_full++;
1102 netdev_dbg(adapter->netdev,
1103 "tx queue stopped on %s, next2comp %u"
1104 " next2fill %u\n", adapter->netdev->name,
1105 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1107 vmxnet3_tq_stop(tq, adapter);
1108 spin_unlock_irqrestore(&tq->tx_lock, flags);
1109 return NETDEV_TX_BUSY;
1113 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1115 /* fill tx descs related to addr & len */
1116 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1117 goto unlock_drop_pkt;
1119 /* setup the EOP desc */
1120 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1122 /* setup the SOP desc */
1123 #ifdef __BIG_ENDIAN_BITFIELD
1124 gdesc = &tempTxDesc;
1125 gdesc->dword[2] = ctx.sop_txd->dword[2];
1126 gdesc->dword[3] = ctx.sop_txd->dword[3];
1128 gdesc = ctx.sop_txd;
1130 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1132 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1133 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1134 gdesc->txd.om = VMXNET3_OM_ENCAP;
1135 gdesc->txd.msscof = ctx.mss;
1137 udph = udp_hdr(skb);
1141 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1142 gdesc->txd.om = VMXNET3_OM_TSO;
1143 gdesc->txd.msscof = ctx.mss;
1145 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1147 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1148 if (VMXNET3_VERSION_GE_4(adapter) &&
1149 skb->encapsulation) {
1150 gdesc->txd.hlen = ctx.l4_offset +
1152 gdesc->txd.om = VMXNET3_OM_ENCAP;
1153 gdesc->txd.msscof = 0; /* Reserved */
1155 gdesc->txd.hlen = ctx.l4_offset;
1156 gdesc->txd.om = VMXNET3_OM_CSUM;
1157 gdesc->txd.msscof = ctx.l4_offset +
1162 gdesc->txd.msscof = 0;
1166 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1167 tx_num_deferred += num_pkts;
1169 if (skb_vlan_tag_present(skb)) {
1171 gdesc->txd.tci = skb_vlan_tag_get(skb);
1174 /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1175 * all other writes to &gdesc->txd.
1179 /* finally flips the GEN bit of the SOP desc. */
1180 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1182 #ifdef __BIG_ENDIAN_BITFIELD
1183 /* Finished updating in bitfields of Tx Desc, so write them in original
1186 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1187 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1188 gdesc = ctx.sop_txd;
1190 netdev_dbg(adapter->netdev,
1191 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1193 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1194 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1196 spin_unlock_irqrestore(&tq->tx_lock, flags);
1198 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1199 tq->shared->txNumDeferred = 0;
1200 VMXNET3_WRITE_BAR0_REG(adapter,
1201 VMXNET3_REG_TXPROD + tq->qid * 8,
1202 tq->tx_ring.next2fill);
1205 return NETDEV_TX_OK;
1208 spin_unlock_irqrestore(&tq->tx_lock, flags);
1210 tq->stats.drop_total++;
1211 dev_kfree_skb_any(skb);
1212 return NETDEV_TX_OK;
1217 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1219 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1221 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1222 return vmxnet3_tq_xmit(skb,
1223 &adapter->tx_queue[skb->queue_mapping],
1229 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1230 struct sk_buff *skb,
1231 union Vmxnet3_GenericDesc *gdesc)
1233 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1234 if (gdesc->rcd.v4 &&
1235 (le32_to_cpu(gdesc->dword[3]) &
1236 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1237 skb->ip_summed = CHECKSUM_UNNECESSARY;
1238 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1239 !(le32_to_cpu(gdesc->dword[0]) &
1240 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1241 WARN_ON_ONCE(gdesc->rcd.frg &&
1242 !(le32_to_cpu(gdesc->dword[0]) &
1243 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1244 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1245 (1 << VMXNET3_RCD_TUC_SHIFT))) {
1246 skb->ip_summed = CHECKSUM_UNNECESSARY;
1247 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1248 !(le32_to_cpu(gdesc->dword[0]) &
1249 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1250 WARN_ON_ONCE(gdesc->rcd.frg &&
1251 !(le32_to_cpu(gdesc->dword[0]) &
1252 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1254 if (gdesc->rcd.csum) {
1255 skb->csum = htons(gdesc->rcd.csum);
1256 skb->ip_summed = CHECKSUM_PARTIAL;
1258 skb_checksum_none_assert(skb);
1262 skb_checksum_none_assert(skb);
1268 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1269 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1271 rq->stats.drop_err++;
1273 rq->stats.drop_fcs++;
1275 rq->stats.drop_total++;
1278 * We do not unmap and chain the rx buffer to the skb.
1279 * We basically pretend this buffer is not used and will be recycled
1280 * by vmxnet3_rq_alloc_rx_buf()
1284 * ctx->skb may be NULL if this is the first and the only one
1288 dev_kfree_skb_irq(ctx->skb);
1295 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1296 union Vmxnet3_GenericDesc *gdesc)
1302 struct vlan_ethhdr *veth;
1304 struct ipv6hdr *ipv6;
1307 BUG_ON(gdesc->rcd.tcp == 0);
1309 maplen = skb_headlen(skb);
1310 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1313 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1314 skb->protocol == cpu_to_be16(ETH_P_8021AD))
1315 hlen = sizeof(struct vlan_ethhdr);
1317 hlen = sizeof(struct ethhdr);
1319 hdr.eth = eth_hdr(skb);
1320 if (gdesc->rcd.v4) {
1321 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1322 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1324 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1325 hlen = hdr.ipv4->ihl << 2;
1326 hdr.ptr += hdr.ipv4->ihl << 2;
1327 } else if (gdesc->rcd.v6) {
1328 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1329 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1331 /* Use an estimated value, since we also need to handle
1334 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1335 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1336 hlen = sizeof(struct ipv6hdr);
1337 hdr.ptr += sizeof(struct ipv6hdr);
1339 /* Non-IP pkt, dont estimate header length */
1343 if (hlen + sizeof(struct tcphdr) > maplen)
1346 return (hlen + (hdr.tcp->doff << 2));
1350 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1351 struct vmxnet3_adapter *adapter, int quota)
1353 static const u32 rxprod_reg[2] = {
1354 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1357 bool skip_page_frags = false;
1358 struct Vmxnet3_RxCompDesc *rcd;
1359 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1360 u16 segCnt = 0, mss = 0;
1361 #ifdef __BIG_ENDIAN_BITFIELD
1362 struct Vmxnet3_RxDesc rxCmdDesc;
1363 struct Vmxnet3_RxCompDesc rxComp;
1365 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1367 while (rcd->gen == rq->comp_ring.gen) {
1368 struct vmxnet3_rx_buf_info *rbi;
1369 struct sk_buff *skb, *new_skb = NULL;
1370 struct page *new_page = NULL;
1371 dma_addr_t new_dma_addr;
1373 struct Vmxnet3_RxDesc *rxd;
1375 struct vmxnet3_cmd_ring *ring = NULL;
1376 if (num_pkts >= quota) {
1377 /* we may stop even before we see the EOP desc of
1383 /* Prevent any rcd field from being (speculatively) read before
1388 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1389 rcd->rqID != rq->dataRingQid);
1391 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1392 ring = rq->rx_ring + ring_idx;
1393 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1395 rbi = rq->buf_info[ring_idx] + idx;
1397 BUG_ON(rxd->addr != rbi->dma_addr ||
1398 rxd->len != rbi->len);
1400 if (unlikely(rcd->eop && rcd->err)) {
1401 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1405 if (rcd->sop) { /* first buf of the pkt */
1406 bool rxDataRingUsed;
1409 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1410 (rcd->rqID != rq->qid &&
1411 rcd->rqID != rq->dataRingQid));
1413 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1414 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1416 if (unlikely(rcd->len == 0)) {
1417 /* Pretend the rx buffer is skipped. */
1418 BUG_ON(!(rcd->sop && rcd->eop));
1419 netdev_dbg(adapter->netdev,
1420 "rxRing[%u][%u] 0 length\n",
1425 skip_page_frags = false;
1426 ctx->skb = rbi->skb;
1429 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1430 len = rxDataRingUsed ? rcd->len : rbi->len;
1431 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1433 if (new_skb == NULL) {
1434 /* Skb allocation failed, do not handover this
1435 * skb to stack. Reuse it. Drop the existing pkt
1437 rq->stats.rx_buf_alloc_failure++;
1439 rq->stats.drop_total++;
1440 skip_page_frags = true;
1444 if (rxDataRingUsed) {
1447 BUG_ON(rcd->len > rq->data_ring.desc_size);
1450 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1451 memcpy(new_skb->data,
1452 &rq->data_ring.base[sz], rcd->len);
1454 ctx->skb = rbi->skb;
1457 dma_map_single(&adapter->pdev->dev,
1458 new_skb->data, rbi->len,
1459 PCI_DMA_FROMDEVICE);
1460 if (dma_mapping_error(&adapter->pdev->dev,
1462 dev_kfree_skb(new_skb);
1463 /* Skb allocation failed, do not
1464 * handover this skb to stack. Reuse
1465 * it. Drop the existing pkt.
1467 rq->stats.rx_buf_alloc_failure++;
1469 rq->stats.drop_total++;
1470 skip_page_frags = true;
1474 dma_unmap_single(&adapter->pdev->dev,
1477 PCI_DMA_FROMDEVICE);
1479 /* Immediate refill */
1481 rbi->dma_addr = new_dma_addr;
1482 rxd->addr = cpu_to_le64(rbi->dma_addr);
1483 rxd->len = rbi->len;
1487 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1488 (adapter->netdev->features & NETIF_F_RXHASH))
1489 skb_set_hash(ctx->skb,
1490 le32_to_cpu(rcd->rssHash),
1493 skb_put(ctx->skb, rcd->len);
1495 if (VMXNET3_VERSION_GE_2(adapter) &&
1496 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1497 struct Vmxnet3_RxCompDescExt *rcdlro;
1498 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1500 segCnt = rcdlro->segCnt;
1501 WARN_ON_ONCE(segCnt == 0);
1503 if (unlikely(segCnt <= 1))
1509 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1511 /* non SOP buffer must be type 1 in most cases */
1512 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1513 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1515 /* If an sop buffer was dropped, skip all
1516 * following non-sop fragments. They will be reused.
1518 if (skip_page_frags)
1522 new_page = alloc_page(GFP_ATOMIC);
1523 /* Replacement page frag could not be allocated.
1524 * Reuse this page. Drop the pkt and free the
1525 * skb which contained this page as a frag. Skip
1526 * processing all the following non-sop frags.
1528 if (unlikely(!new_page)) {
1529 rq->stats.rx_buf_alloc_failure++;
1530 dev_kfree_skb(ctx->skb);
1532 skip_page_frags = true;
1535 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1538 PCI_DMA_FROMDEVICE);
1539 if (dma_mapping_error(&adapter->pdev->dev,
1542 rq->stats.rx_buf_alloc_failure++;
1543 dev_kfree_skb(ctx->skb);
1545 skip_page_frags = true;
1549 dma_unmap_page(&adapter->pdev->dev,
1550 rbi->dma_addr, rbi->len,
1551 PCI_DMA_FROMDEVICE);
1553 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1555 /* Immediate refill */
1556 rbi->page = new_page;
1557 rbi->dma_addr = new_dma_addr;
1558 rxd->addr = cpu_to_le64(rbi->dma_addr);
1559 rxd->len = rbi->len;
1566 u32 mtu = adapter->netdev->mtu;
1567 skb->len += skb->data_len;
1569 vmxnet3_rx_csum(adapter, skb,
1570 (union Vmxnet3_GenericDesc *)rcd);
1571 skb->protocol = eth_type_trans(skb, adapter->netdev);
1573 !(adapter->netdev->features & NETIF_F_LRO))
1576 if (segCnt != 0 && mss != 0) {
1577 skb_shinfo(skb)->gso_type = rcd->v4 ?
1578 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1579 skb_shinfo(skb)->gso_size = mss;
1580 skb_shinfo(skb)->gso_segs = segCnt;
1581 } else if (segCnt != 0 || skb->len > mtu) {
1584 hlen = vmxnet3_get_hdr_len(adapter, skb,
1585 (union Vmxnet3_GenericDesc *)rcd);
1589 skb_shinfo(skb)->gso_type =
1590 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1592 skb_shinfo(skb)->gso_segs = segCnt;
1593 skb_shinfo(skb)->gso_size =
1594 DIV_ROUND_UP(skb->len -
1597 skb_shinfo(skb)->gso_size = mtu - hlen;
1601 if (unlikely(rcd->ts))
1602 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1604 if (adapter->netdev->features & NETIF_F_LRO)
1605 netif_receive_skb(skb);
1607 napi_gro_receive(&rq->napi, skb);
1614 /* device may have skipped some rx descs */
1615 ring->next2comp = idx;
1616 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1617 ring = rq->rx_ring + ring_idx;
1619 /* Ensure that the writes to rxd->gen bits will be observed
1620 * after all other writes to rxd objects.
1624 while (num_to_alloc) {
1625 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1629 /* Recv desc is ready to be used by the device */
1630 rxd->gen = ring->gen;
1631 vmxnet3_cmd_ring_adv_next2fill(ring);
1635 /* if needed, update the register */
1636 if (unlikely(rq->shared->updateRxProd)) {
1637 VMXNET3_WRITE_BAR0_REG(adapter,
1638 rxprod_reg[ring_idx] + rq->qid * 8,
1642 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1643 vmxnet3_getRxComp(rcd,
1644 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1652 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1653 struct vmxnet3_adapter *adapter)
1656 struct Vmxnet3_RxDesc *rxd;
1658 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1659 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661 struct Vmxnet3_RxDesc rxDesc;
1663 vmxnet3_getRxDesc(rxd,
1664 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1666 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1667 rq->buf_info[ring_idx][i].skb) {
1668 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1669 rxd->len, PCI_DMA_FROMDEVICE);
1670 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1671 rq->buf_info[ring_idx][i].skb = NULL;
1672 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1673 rq->buf_info[ring_idx][i].page) {
1674 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1675 rxd->len, PCI_DMA_FROMDEVICE);
1676 put_page(rq->buf_info[ring_idx][i].page);
1677 rq->buf_info[ring_idx][i].page = NULL;
1681 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1682 rq->rx_ring[ring_idx].next2fill =
1683 rq->rx_ring[ring_idx].next2comp = 0;
1686 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1687 rq->comp_ring.next2proc = 0;
1692 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1696 for (i = 0; i < adapter->num_rx_queues; i++)
1697 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1701 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1702 struct vmxnet3_adapter *adapter)
1707 /* all rx buffers must have already been freed */
1708 for (i = 0; i < 2; i++) {
1709 if (rq->buf_info[i]) {
1710 for (j = 0; j < rq->rx_ring[i].size; j++)
1711 BUG_ON(rq->buf_info[i][j].page != NULL);
1716 for (i = 0; i < 2; i++) {
1717 if (rq->rx_ring[i].base) {
1718 dma_free_coherent(&adapter->pdev->dev,
1720 * sizeof(struct Vmxnet3_RxDesc),
1721 rq->rx_ring[i].base,
1722 rq->rx_ring[i].basePA);
1723 rq->rx_ring[i].base = NULL;
1727 if (rq->data_ring.base) {
1728 dma_free_coherent(&adapter->pdev->dev,
1729 rq->rx_ring[0].size * rq->data_ring.desc_size,
1730 rq->data_ring.base, rq->data_ring.basePA);
1731 rq->data_ring.base = NULL;
1734 if (rq->comp_ring.base) {
1735 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1736 * sizeof(struct Vmxnet3_RxCompDesc),
1737 rq->comp_ring.base, rq->comp_ring.basePA);
1738 rq->comp_ring.base = NULL;
1741 if (rq->buf_info[0]) {
1742 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1743 (rq->rx_ring[0].size + rq->rx_ring[1].size);
1744 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1746 rq->buf_info[0] = rq->buf_info[1] = NULL;
1751 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1755 for (i = 0; i < adapter->num_rx_queues; i++) {
1756 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1758 if (rq->data_ring.base) {
1759 dma_free_coherent(&adapter->pdev->dev,
1760 (rq->rx_ring[0].size *
1761 rq->data_ring.desc_size),
1763 rq->data_ring.basePA);
1764 rq->data_ring.base = NULL;
1765 rq->data_ring.desc_size = 0;
1771 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1772 struct vmxnet3_adapter *adapter)
1776 /* initialize buf_info */
1777 for (i = 0; i < rq->rx_ring[0].size; i++) {
1779 /* 1st buf for a pkt is skbuff */
1780 if (i % adapter->rx_buf_per_pkt == 0) {
1781 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1782 rq->buf_info[0][i].len = adapter->skb_buf_size;
1783 } else { /* subsequent bufs for a pkt is frag */
1784 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1785 rq->buf_info[0][i].len = PAGE_SIZE;
1788 for (i = 0; i < rq->rx_ring[1].size; i++) {
1789 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1790 rq->buf_info[1][i].len = PAGE_SIZE;
1793 /* reset internal state and allocate buffers for both rings */
1794 for (i = 0; i < 2; i++) {
1795 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1797 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1798 sizeof(struct Vmxnet3_RxDesc));
1799 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1801 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1803 /* at least has 1 rx buffer for the 1st ring */
1806 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1808 /* reset the comp ring */
1809 rq->comp_ring.next2proc = 0;
1810 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1811 sizeof(struct Vmxnet3_RxCompDesc));
1812 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1815 rq->rx_ctx.skb = NULL;
1817 /* stats are not reset */
1823 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1827 for (i = 0; i < adapter->num_rx_queues; i++) {
1828 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1829 if (unlikely(err)) {
1830 dev_err(&adapter->netdev->dev, "%s: failed to "
1831 "initialize rx queue%i\n",
1832 adapter->netdev->name, i);
1842 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1846 struct vmxnet3_rx_buf_info *bi;
1848 for (i = 0; i < 2; i++) {
1850 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1851 rq->rx_ring[i].base = dma_alloc_coherent(
1852 &adapter->pdev->dev, sz,
1853 &rq->rx_ring[i].basePA,
1855 if (!rq->rx_ring[i].base) {
1856 netdev_err(adapter->netdev,
1857 "failed to allocate rx ring %d\n", i);
1862 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1863 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1864 rq->data_ring.base =
1865 dma_alloc_coherent(&adapter->pdev->dev, sz,
1866 &rq->data_ring.basePA,
1868 if (!rq->data_ring.base) {
1869 netdev_err(adapter->netdev,
1870 "rx data ring will be disabled\n");
1871 adapter->rxdataring_enabled = false;
1874 rq->data_ring.base = NULL;
1875 rq->data_ring.desc_size = 0;
1878 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1879 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1880 &rq->comp_ring.basePA,
1882 if (!rq->comp_ring.base) {
1883 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1887 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1888 rq->rx_ring[1].size);
1889 bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1894 rq->buf_info[0] = bi;
1895 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1900 vmxnet3_rq_destroy(rq, adapter);
1906 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1910 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1912 for (i = 0; i < adapter->num_rx_queues; i++) {
1913 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1914 if (unlikely(err)) {
1915 dev_err(&adapter->netdev->dev,
1916 "%s: failed to create rx queue%i\n",
1917 adapter->netdev->name, i);
1922 if (!adapter->rxdataring_enabled)
1923 vmxnet3_rq_destroy_all_rxdataring(adapter);
1927 vmxnet3_rq_destroy_all(adapter);
1932 /* Multiple queue aware polling function for tx and rx */
1935 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1937 int rcd_done = 0, i;
1938 if (unlikely(adapter->shared->ecr))
1939 vmxnet3_process_events(adapter);
1940 for (i = 0; i < adapter->num_tx_queues; i++)
1941 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1943 for (i = 0; i < adapter->num_rx_queues; i++)
1944 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1951 vmxnet3_poll(struct napi_struct *napi, int budget)
1953 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1954 struct vmxnet3_rx_queue, napi);
1957 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1959 if (rxd_done < budget) {
1960 napi_complete_done(napi, rxd_done);
1961 vmxnet3_enable_all_intrs(rx_queue->adapter);
1967 * NAPI polling function for MSI-X mode with multiple Rx queues
1968 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1972 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1974 struct vmxnet3_rx_queue *rq = container_of(napi,
1975 struct vmxnet3_rx_queue, napi);
1976 struct vmxnet3_adapter *adapter = rq->adapter;
1979 /* When sharing interrupt with corresponding tx queue, process
1980 * tx completions in that queue as well
1982 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1983 struct vmxnet3_tx_queue *tq =
1984 &adapter->tx_queue[rq - adapter->rx_queue];
1985 vmxnet3_tq_tx_complete(tq, adapter);
1988 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
1990 if (rxd_done < budget) {
1991 napi_complete_done(napi, rxd_done);
1992 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
1998 #ifdef CONFIG_PCI_MSI
2001 * Handle completion interrupts on tx queues
2002 * Returns whether or not the intr is handled
2006 vmxnet3_msix_tx(int irq, void *data)
2008 struct vmxnet3_tx_queue *tq = data;
2009 struct vmxnet3_adapter *adapter = tq->adapter;
2011 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2012 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2014 /* Handle the case where only one irq is allocate for all tx queues */
2015 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2017 for (i = 0; i < adapter->num_tx_queues; i++) {
2018 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2019 vmxnet3_tq_tx_complete(txq, adapter);
2022 vmxnet3_tq_tx_complete(tq, adapter);
2024 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2031 * Handle completion interrupts on rx queues. Returns whether or not the
2036 vmxnet3_msix_rx(int irq, void *data)
2038 struct vmxnet3_rx_queue *rq = data;
2039 struct vmxnet3_adapter *adapter = rq->adapter;
2041 /* disable intr if needed */
2042 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2043 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2044 napi_schedule(&rq->napi);
2050 *----------------------------------------------------------------------------
2052 * vmxnet3_msix_event --
2054 * vmxnet3 msix event intr handler
2057 * whether or not the intr is handled
2059 *----------------------------------------------------------------------------
2063 vmxnet3_msix_event(int irq, void *data)
2065 struct net_device *dev = data;
2066 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2068 /* disable intr if needed */
2069 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2070 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2072 if (adapter->shared->ecr)
2073 vmxnet3_process_events(adapter);
2075 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2080 #endif /* CONFIG_PCI_MSI */
2083 /* Interrupt handler for vmxnet3 */
2085 vmxnet3_intr(int irq, void *dev_id)
2087 struct net_device *dev = dev_id;
2088 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2090 if (adapter->intr.type == VMXNET3_IT_INTX) {
2091 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2092 if (unlikely(icr == 0))
2098 /* disable intr if needed */
2099 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2100 vmxnet3_disable_all_intrs(adapter);
2102 napi_schedule(&adapter->rx_queue[0].napi);
2107 #ifdef CONFIG_NET_POLL_CONTROLLER
2109 /* netpoll callback. */
2111 vmxnet3_netpoll(struct net_device *netdev)
2113 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2115 switch (adapter->intr.type) {
2116 #ifdef CONFIG_PCI_MSI
2117 case VMXNET3_IT_MSIX: {
2119 for (i = 0; i < adapter->num_rx_queues; i++)
2120 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2124 case VMXNET3_IT_MSI:
2126 vmxnet3_intr(0, adapter->netdev);
2131 #endif /* CONFIG_NET_POLL_CONTROLLER */
2134 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2136 struct vmxnet3_intr *intr = &adapter->intr;
2140 #ifdef CONFIG_PCI_MSI
2141 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2142 for (i = 0; i < adapter->num_tx_queues; i++) {
2143 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2144 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2145 adapter->netdev->name, vector);
2147 intr->msix_entries[vector].vector,
2149 adapter->tx_queue[i].name,
2150 &adapter->tx_queue[i]);
2152 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2153 adapter->netdev->name, vector);
2156 dev_err(&adapter->netdev->dev,
2157 "Failed to request irq for MSIX, %s, "
2159 adapter->tx_queue[i].name, err);
2163 /* Handle the case where only 1 MSIx was allocated for
2165 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2166 for (; i < adapter->num_tx_queues; i++)
2167 adapter->tx_queue[i].comp_ring.intr_idx
2172 adapter->tx_queue[i].comp_ring.intr_idx
2176 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2179 for (i = 0; i < adapter->num_rx_queues; i++) {
2180 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2181 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2182 adapter->netdev->name, vector);
2184 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2185 adapter->netdev->name, vector);
2186 err = request_irq(intr->msix_entries[vector].vector,
2188 adapter->rx_queue[i].name,
2189 &(adapter->rx_queue[i]));
2191 netdev_err(adapter->netdev,
2192 "Failed to request irq for MSIX, "
2194 adapter->rx_queue[i].name, err);
2198 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2201 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2202 adapter->netdev->name, vector);
2203 err = request_irq(intr->msix_entries[vector].vector,
2204 vmxnet3_msix_event, 0,
2205 intr->event_msi_vector_name, adapter->netdev);
2206 intr->event_intr_idx = vector;
2208 } else if (intr->type == VMXNET3_IT_MSI) {
2209 adapter->num_rx_queues = 1;
2210 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2211 adapter->netdev->name, adapter->netdev);
2214 adapter->num_rx_queues = 1;
2215 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2216 IRQF_SHARED, adapter->netdev->name,
2218 #ifdef CONFIG_PCI_MSI
2221 intr->num_intrs = vector + 1;
2223 netdev_err(adapter->netdev,
2224 "Failed to request irq (intr type:%d), error %d\n",
2227 /* Number of rx queues will not change after this */
2228 for (i = 0; i < adapter->num_rx_queues; i++) {
2229 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2231 rq->qid2 = i + adapter->num_rx_queues;
2232 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2235 /* init our intr settings */
2236 for (i = 0; i < intr->num_intrs; i++)
2237 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2238 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2239 adapter->intr.event_intr_idx = 0;
2240 for (i = 0; i < adapter->num_tx_queues; i++)
2241 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2242 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2245 netdev_info(adapter->netdev,
2246 "intr type %u, mode %u, %u vectors allocated\n",
2247 intr->type, intr->mask_mode, intr->num_intrs);
2255 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2257 struct vmxnet3_intr *intr = &adapter->intr;
2258 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2260 switch (intr->type) {
2261 #ifdef CONFIG_PCI_MSI
2262 case VMXNET3_IT_MSIX:
2266 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2267 for (i = 0; i < adapter->num_tx_queues; i++) {
2268 free_irq(intr->msix_entries[vector++].vector,
2269 &(adapter->tx_queue[i]));
2270 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2275 for (i = 0; i < adapter->num_rx_queues; i++) {
2276 free_irq(intr->msix_entries[vector++].vector,
2277 &(adapter->rx_queue[i]));
2280 free_irq(intr->msix_entries[vector].vector,
2282 BUG_ON(vector >= intr->num_intrs);
2286 case VMXNET3_IT_MSI:
2287 free_irq(adapter->pdev->irq, adapter->netdev);
2289 case VMXNET3_IT_INTX:
2290 free_irq(adapter->pdev->irq, adapter->netdev);
2299 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2301 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2304 /* allow untagged pkts */
2305 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2307 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2308 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2313 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2315 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2317 if (!(netdev->flags & IFF_PROMISC)) {
2318 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2319 unsigned long flags;
2321 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2322 spin_lock_irqsave(&adapter->cmd_lock, flags);
2323 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2324 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2325 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2328 set_bit(vid, adapter->active_vlans);
2335 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2337 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2339 if (!(netdev->flags & IFF_PROMISC)) {
2340 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2341 unsigned long flags;
2343 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2344 spin_lock_irqsave(&adapter->cmd_lock, flags);
2345 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2346 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2347 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2350 clear_bit(vid, adapter->active_vlans);
2357 vmxnet3_copy_mc(struct net_device *netdev)
2360 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2362 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2364 /* We may be called with BH disabled */
2365 buf = kmalloc(sz, GFP_ATOMIC);
2367 struct netdev_hw_addr *ha;
2370 netdev_for_each_mc_addr(ha, netdev)
2371 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2380 vmxnet3_set_mc(struct net_device *netdev)
2382 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2383 unsigned long flags;
2384 struct Vmxnet3_RxFilterConf *rxConf =
2385 &adapter->shared->devRead.rxFilterConf;
2386 u8 *new_table = NULL;
2387 dma_addr_t new_table_pa = 0;
2388 bool new_table_pa_valid = false;
2389 u32 new_mode = VMXNET3_RXM_UCAST;
2391 if (netdev->flags & IFF_PROMISC) {
2392 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2393 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2395 new_mode |= VMXNET3_RXM_PROMISC;
2397 vmxnet3_restore_vlan(adapter);
2400 if (netdev->flags & IFF_BROADCAST)
2401 new_mode |= VMXNET3_RXM_BCAST;
2403 if (netdev->flags & IFF_ALLMULTI)
2404 new_mode |= VMXNET3_RXM_ALL_MULTI;
2406 if (!netdev_mc_empty(netdev)) {
2407 new_table = vmxnet3_copy_mc(netdev);
2409 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2411 rxConf->mfTableLen = cpu_to_le16(sz);
2412 new_table_pa = dma_map_single(
2413 &adapter->pdev->dev,
2417 if (!dma_mapping_error(&adapter->pdev->dev,
2419 new_mode |= VMXNET3_RXM_MCAST;
2420 new_table_pa_valid = true;
2421 rxConf->mfTablePA = cpu_to_le64(
2425 if (!new_table_pa_valid) {
2427 "failed to copy mcast list, setting ALL_MULTI\n");
2428 new_mode |= VMXNET3_RXM_ALL_MULTI;
2432 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2433 rxConf->mfTableLen = 0;
2434 rxConf->mfTablePA = 0;
2437 spin_lock_irqsave(&adapter->cmd_lock, flags);
2438 if (new_mode != rxConf->rxMode) {
2439 rxConf->rxMode = cpu_to_le32(new_mode);
2440 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2441 VMXNET3_CMD_UPDATE_RX_MODE);
2442 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2443 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2446 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2447 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2448 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2450 if (new_table_pa_valid)
2451 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2452 rxConf->mfTableLen, PCI_DMA_TODEVICE);
2457 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2461 for (i = 0; i < adapter->num_rx_queues; i++)
2462 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2467 * Set up driver_shared based on settings in adapter.
2471 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2473 struct Vmxnet3_DriverShared *shared = adapter->shared;
2474 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2475 struct Vmxnet3_TxQueueConf *tqc;
2476 struct Vmxnet3_RxQueueConf *rqc;
2479 memset(shared, 0, sizeof(*shared));
2481 /* driver settings */
2482 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2483 devRead->misc.driverInfo.version = cpu_to_le32(
2484 VMXNET3_DRIVER_VERSION_NUM);
2485 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2486 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2487 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2488 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2489 *((u32 *)&devRead->misc.driverInfo.gos));
2490 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2491 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2493 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2494 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2496 /* set up feature flags */
2497 if (adapter->netdev->features & NETIF_F_RXCSUM)
2498 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2500 if (adapter->netdev->features & NETIF_F_LRO) {
2501 devRead->misc.uptFeatures |= UPT1_F_LRO;
2502 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2504 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2505 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2507 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2508 NETIF_F_GSO_UDP_TUNNEL_CSUM))
2509 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2511 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2512 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2513 devRead->misc.queueDescLen = cpu_to_le32(
2514 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2515 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2517 /* tx queue settings */
2518 devRead->misc.numTxQueues = adapter->num_tx_queues;
2519 for (i = 0; i < adapter->num_tx_queues; i++) {
2520 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2521 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2522 tqc = &adapter->tqd_start[i].conf;
2523 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2524 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2525 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2526 tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
2527 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2528 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2529 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2530 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2531 tqc->ddLen = cpu_to_le32(
2532 sizeof(struct vmxnet3_tx_buf_info) *
2534 tqc->intrIdx = tq->comp_ring.intr_idx;
2537 /* rx queue settings */
2538 devRead->misc.numRxQueues = adapter->num_rx_queues;
2539 for (i = 0; i < adapter->num_rx_queues; i++) {
2540 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2541 rqc = &adapter->rqd_start[i].conf;
2542 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2543 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2544 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2545 rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
2546 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2547 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2548 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2549 rqc->ddLen = cpu_to_le32(
2550 sizeof(struct vmxnet3_rx_buf_info) *
2551 (rqc->rxRingSize[0] +
2552 rqc->rxRingSize[1]));
2553 rqc->intrIdx = rq->comp_ring.intr_idx;
2554 if (VMXNET3_VERSION_GE_3(adapter)) {
2555 rqc->rxDataRingBasePA =
2556 cpu_to_le64(rq->data_ring.basePA);
2557 rqc->rxDataRingDescSize =
2558 cpu_to_le16(rq->data_ring.desc_size);
2563 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2566 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2568 devRead->misc.uptFeatures |= UPT1_F_RSS;
2569 devRead->misc.numRxQueues = adapter->num_rx_queues;
2570 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2571 UPT1_RSS_HASH_TYPE_IPV4 |
2572 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2573 UPT1_RSS_HASH_TYPE_IPV6;
2574 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2575 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2576 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2577 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2579 for (i = 0; i < rssConf->indTableSize; i++)
2580 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2581 i, adapter->num_rx_queues);
2583 devRead->rssConfDesc.confVer = 1;
2584 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2585 devRead->rssConfDesc.confPA =
2586 cpu_to_le64(adapter->rss_conf_pa);
2589 #endif /* VMXNET3_RSS */
2592 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2594 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2595 for (i = 0; i < adapter->intr.num_intrs; i++)
2596 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2598 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2599 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2601 /* rx filter settings */
2602 devRead->rxFilterConf.rxMode = 0;
2603 vmxnet3_restore_vlan(adapter);
2604 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2606 /* the rest are already zeroed */
2610 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2612 struct Vmxnet3_DriverShared *shared = adapter->shared;
2613 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2614 unsigned long flags;
2616 if (!VMXNET3_VERSION_GE_3(adapter))
2619 spin_lock_irqsave(&adapter->cmd_lock, flags);
2620 cmdInfo->varConf.confVer = 1;
2621 cmdInfo->varConf.confLen =
2622 cpu_to_le32(sizeof(*adapter->coal_conf));
2623 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2625 if (adapter->default_coal_mode) {
2626 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2627 VMXNET3_CMD_GET_COALESCE);
2629 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2630 VMXNET3_CMD_SET_COALESCE);
2633 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2637 vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2639 struct Vmxnet3_DriverShared *shared = adapter->shared;
2640 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2641 unsigned long flags;
2643 if (!VMXNET3_VERSION_GE_4(adapter))
2646 spin_lock_irqsave(&adapter->cmd_lock, flags);
2648 if (adapter->default_rss_fields) {
2649 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2650 VMXNET3_CMD_GET_RSS_FIELDS);
2651 adapter->rss_fields =
2652 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2654 cmdInfo->setRssFields = adapter->rss_fields;
2655 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2656 VMXNET3_CMD_SET_RSS_FIELDS);
2657 /* Not all requested RSS may get applied, so get and
2658 * cache what was actually applied.
2660 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2661 VMXNET3_CMD_GET_RSS_FIELDS);
2662 adapter->rss_fields =
2663 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2666 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2670 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2674 unsigned long flags;
2676 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2677 " ring sizes %u %u %u\n", adapter->netdev->name,
2678 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2679 adapter->tx_queue[0].tx_ring.size,
2680 adapter->rx_queue[0].rx_ring[0].size,
2681 adapter->rx_queue[0].rx_ring[1].size);
2683 vmxnet3_tq_init_all(adapter);
2684 err = vmxnet3_rq_init_all(adapter);
2686 netdev_err(adapter->netdev,
2687 "Failed to init rx queue error %d\n", err);
2691 err = vmxnet3_request_irqs(adapter);
2693 netdev_err(adapter->netdev,
2694 "Failed to setup irq for error %d\n", err);
2698 vmxnet3_setup_driver_shared(adapter);
2700 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2701 adapter->shared_pa));
2702 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2703 adapter->shared_pa));
2704 spin_lock_irqsave(&adapter->cmd_lock, flags);
2705 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2706 VMXNET3_CMD_ACTIVATE_DEV);
2707 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2708 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2711 netdev_err(adapter->netdev,
2712 "Failed to activate dev: error %u\n", ret);
2717 vmxnet3_init_coalesce(adapter);
2718 vmxnet3_init_rssfields(adapter);
2720 for (i = 0; i < adapter->num_rx_queues; i++) {
2721 VMXNET3_WRITE_BAR0_REG(adapter,
2722 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2723 adapter->rx_queue[i].rx_ring[0].next2fill);
2724 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2725 (i * VMXNET3_REG_ALIGN)),
2726 adapter->rx_queue[i].rx_ring[1].next2fill);
2729 /* Apply the rx filter settins last. */
2730 vmxnet3_set_mc(adapter->netdev);
2733 * Check link state when first activating device. It will start the
2734 * tx queue if the link is up.
2736 vmxnet3_check_link(adapter, true);
2737 for (i = 0; i < adapter->num_rx_queues; i++)
2738 napi_enable(&adapter->rx_queue[i].napi);
2739 vmxnet3_enable_all_intrs(adapter);
2740 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2744 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2745 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2746 vmxnet3_free_irqs(adapter);
2749 /* free up buffers we allocated */
2750 vmxnet3_rq_cleanup_all(adapter);
2756 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2758 unsigned long flags;
2759 spin_lock_irqsave(&adapter->cmd_lock, flags);
2760 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2761 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2766 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2769 unsigned long flags;
2770 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2774 spin_lock_irqsave(&adapter->cmd_lock, flags);
2775 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2776 VMXNET3_CMD_QUIESCE_DEV);
2777 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2778 vmxnet3_disable_all_intrs(adapter);
2780 for (i = 0; i < adapter->num_rx_queues; i++)
2781 napi_disable(&adapter->rx_queue[i].napi);
2782 netif_tx_disable(adapter->netdev);
2783 adapter->link_speed = 0;
2784 netif_carrier_off(adapter->netdev);
2786 vmxnet3_tq_cleanup_all(adapter);
2787 vmxnet3_rq_cleanup_all(adapter);
2788 vmxnet3_free_irqs(adapter);
2794 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2799 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2801 tmp = (mac[5] << 8) | mac[4];
2802 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2807 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2809 struct sockaddr *addr = p;
2810 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2812 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2813 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2819 /* ==================== initialization and cleanup routines ============ */
2822 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
2825 unsigned long mmio_start, mmio_len;
2826 struct pci_dev *pdev = adapter->pdev;
2828 err = pci_enable_device(pdev);
2830 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2834 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2835 vmxnet3_driver_name);
2838 "Failed to request region for adapter: error %d\n", err);
2839 goto err_enable_device;
2842 pci_set_master(pdev);
2844 mmio_start = pci_resource_start(pdev, 0);
2845 mmio_len = pci_resource_len(pdev, 0);
2846 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2847 if (!adapter->hw_addr0) {
2848 dev_err(&pdev->dev, "Failed to map bar0\n");
2853 mmio_start = pci_resource_start(pdev, 1);
2854 mmio_len = pci_resource_len(pdev, 1);
2855 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2856 if (!adapter->hw_addr1) {
2857 dev_err(&pdev->dev, "Failed to map bar1\n");
2864 iounmap(adapter->hw_addr0);
2866 pci_release_selected_regions(pdev, (1 << 2) - 1);
2868 pci_disable_device(pdev);
2874 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2876 BUG_ON(!adapter->pdev);
2878 iounmap(adapter->hw_addr0);
2879 iounmap(adapter->hw_addr1);
2880 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2881 pci_disable_device(adapter->pdev);
2886 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2888 size_t sz, i, ring0_size, ring1_size, comp_size;
2889 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2890 VMXNET3_MAX_ETH_HDR_SIZE) {
2891 adapter->skb_buf_size = adapter->netdev->mtu +
2892 VMXNET3_MAX_ETH_HDR_SIZE;
2893 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2894 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2896 adapter->rx_buf_per_pkt = 1;
2898 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2899 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2900 VMXNET3_MAX_ETH_HDR_SIZE;
2901 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2905 * for simplicity, force the ring0 size to be a multiple of
2906 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2908 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2909 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2910 ring0_size = (ring0_size + sz - 1) / sz * sz;
2911 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2913 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2914 ring1_size = (ring1_size + sz - 1) / sz * sz;
2915 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2917 comp_size = ring0_size + ring1_size;
2919 for (i = 0; i < adapter->num_rx_queues; i++) {
2920 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2922 rq->rx_ring[0].size = ring0_size;
2923 rq->rx_ring[1].size = ring1_size;
2924 rq->comp_ring.size = comp_size;
2930 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2931 u32 rx_ring_size, u32 rx_ring2_size,
2932 u16 txdata_desc_size, u16 rxdata_desc_size)
2936 for (i = 0; i < adapter->num_tx_queues; i++) {
2937 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2938 tq->tx_ring.size = tx_ring_size;
2939 tq->data_ring.size = tx_ring_size;
2940 tq->comp_ring.size = tx_ring_size;
2941 tq->txdata_desc_size = txdata_desc_size;
2942 tq->shared = &adapter->tqd_start[i].ctrl;
2944 tq->adapter = adapter;
2946 err = vmxnet3_tq_create(tq, adapter);
2948 * Too late to change num_tx_queues. We cannot do away with
2949 * lesser number of queues than what we asked for
2955 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2956 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2957 vmxnet3_adjust_rx_ring_size(adapter);
2959 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
2960 for (i = 0; i < adapter->num_rx_queues; i++) {
2961 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2962 /* qid and qid2 for rx queues will be assigned later when num
2963 * of rx queues is finalized after allocating intrs */
2964 rq->shared = &adapter->rqd_start[i].ctrl;
2965 rq->adapter = adapter;
2966 rq->data_ring.desc_size = rxdata_desc_size;
2967 err = vmxnet3_rq_create(rq, adapter);
2970 netdev_err(adapter->netdev,
2971 "Could not allocate any rx queues. "
2975 netdev_info(adapter->netdev,
2976 "Number of rx queues changed "
2978 adapter->num_rx_queues = i;
2985 if (!adapter->rxdataring_enabled)
2986 vmxnet3_rq_destroy_all_rxdataring(adapter);
2990 vmxnet3_tq_destroy_all(adapter);
2995 vmxnet3_open(struct net_device *netdev)
2997 struct vmxnet3_adapter *adapter;
3000 adapter = netdev_priv(netdev);
3002 for (i = 0; i < adapter->num_tx_queues; i++)
3003 spin_lock_init(&adapter->tx_queue[i].tx_lock);
3005 if (VMXNET3_VERSION_GE_3(adapter)) {
3006 unsigned long flags;
3007 u16 txdata_desc_size;
3009 spin_lock_irqsave(&adapter->cmd_lock, flags);
3010 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3011 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
3012 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
3014 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3016 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3017 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3018 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3019 adapter->txdata_desc_size =
3020 sizeof(struct Vmxnet3_TxDataDesc);
3022 adapter->txdata_desc_size = txdata_desc_size;
3025 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3028 err = vmxnet3_create_queues(adapter,
3029 adapter->tx_ring_size,
3030 adapter->rx_ring_size,
3031 adapter->rx_ring2_size,
3032 adapter->txdata_desc_size,
3033 adapter->rxdata_desc_size);
3037 err = vmxnet3_activate_dev(adapter);
3044 vmxnet3_rq_destroy_all(adapter);
3045 vmxnet3_tq_destroy_all(adapter);
3052 vmxnet3_close(struct net_device *netdev)
3054 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3057 * Reset_work may be in the middle of resetting the device, wait for its
3060 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3061 usleep_range(1000, 2000);
3063 vmxnet3_quiesce_dev(adapter);
3065 vmxnet3_rq_destroy_all(adapter);
3066 vmxnet3_tq_destroy_all(adapter);
3068 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3076 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3081 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3082 * vmxnet3_close() will deadlock.
3084 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3086 /* we need to enable NAPI, otherwise dev_close will deadlock */
3087 for (i = 0; i < adapter->num_rx_queues; i++)
3088 napi_enable(&adapter->rx_queue[i].napi);
3090 * Need to clear the quiesce bit to ensure that vmxnet3_close
3091 * can quiesce the device properly
3093 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3094 dev_close(adapter->netdev);
3099 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3101 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3104 netdev->mtu = new_mtu;
3107 * Reset_work may be in the middle of resetting the device, wait for its
3110 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3111 usleep_range(1000, 2000);
3113 if (netif_running(netdev)) {
3114 vmxnet3_quiesce_dev(adapter);
3115 vmxnet3_reset_dev(adapter);
3117 /* we need to re-create the rx queue based on the new mtu */
3118 vmxnet3_rq_destroy_all(adapter);
3119 vmxnet3_adjust_rx_ring_size(adapter);
3120 err = vmxnet3_rq_create_all(adapter);
3123 "failed to re-create rx queues, "
3124 " error %d. Closing it.\n", err);
3128 err = vmxnet3_activate_dev(adapter);
3131 "failed to re-activate, error %d. "
3132 "Closing it\n", err);
3138 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3140 vmxnet3_force_close(adapter);
3147 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3149 struct net_device *netdev = adapter->netdev;
3151 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3152 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3153 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3156 if (VMXNET3_VERSION_GE_4(adapter)) {
3157 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3158 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3160 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3161 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3162 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3163 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3164 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3168 netdev->hw_features |= NETIF_F_HIGHDMA;
3169 netdev->vlan_features = netdev->hw_features &
3170 ~(NETIF_F_HW_VLAN_CTAG_TX |
3171 NETIF_F_HW_VLAN_CTAG_RX);
3172 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3177 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3181 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3184 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3185 mac[4] = tmp & 0xff;
3186 mac[5] = (tmp >> 8) & 0xff;
3189 #ifdef CONFIG_PCI_MSI
3192 * Enable MSIx vectors.
3194 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3196 * number of vectors which were enabled otherwise (this number is greater
3197 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3201 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3203 int ret = pci_enable_msix_range(adapter->pdev,
3204 adapter->intr.msix_entries, nvec, nvec);
3206 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3207 dev_err(&adapter->netdev->dev,
3208 "Failed to enable %d MSI-X, trying %d\n",
3209 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3211 ret = pci_enable_msix_range(adapter->pdev,
3212 adapter->intr.msix_entries,
3213 VMXNET3_LINUX_MIN_MSIX_VECT,
3214 VMXNET3_LINUX_MIN_MSIX_VECT);
3218 dev_err(&adapter->netdev->dev,
3219 "Failed to enable MSI-X, error: %d\n", ret);
3226 #endif /* CONFIG_PCI_MSI */
3229 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3232 unsigned long flags;
3235 spin_lock_irqsave(&adapter->cmd_lock, flags);
3236 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3237 VMXNET3_CMD_GET_CONF_INTR);
3238 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3239 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3240 adapter->intr.type = cfg & 0x3;
3241 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3243 if (adapter->intr.type == VMXNET3_IT_AUTO) {
3244 adapter->intr.type = VMXNET3_IT_MSIX;
3247 #ifdef CONFIG_PCI_MSI
3248 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3251 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3252 1 : adapter->num_tx_queues;
3253 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3254 0 : adapter->num_rx_queues;
3255 nvec += 1; /* for link event */
3256 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3257 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3259 for (i = 0; i < nvec; i++)
3260 adapter->intr.msix_entries[i].entry = i;
3262 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3266 /* If we cannot allocate one MSIx vector per queue
3267 * then limit the number of rx queues to 1
3269 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
3270 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3271 || adapter->num_rx_queues != 1) {
3272 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3273 netdev_err(adapter->netdev,
3274 "Number of rx queues : 1\n");
3275 adapter->num_rx_queues = 1;
3279 adapter->intr.num_intrs = nvec;
3283 /* If we cannot allocate MSIx vectors use only one rx queue */
3284 dev_info(&adapter->pdev->dev,
3285 "Failed to enable MSI-X, error %d. "
3286 "Limiting #rx queues to 1, try MSI.\n", nvec);
3288 adapter->intr.type = VMXNET3_IT_MSI;
3291 if (adapter->intr.type == VMXNET3_IT_MSI) {
3292 if (!pci_enable_msi(adapter->pdev)) {
3293 adapter->num_rx_queues = 1;
3294 adapter->intr.num_intrs = 1;
3298 #endif /* CONFIG_PCI_MSI */
3300 adapter->num_rx_queues = 1;
3301 dev_info(&adapter->netdev->dev,
3302 "Using INTx interrupt, #Rx queues: 1.\n");
3303 adapter->intr.type = VMXNET3_IT_INTX;
3305 /* INT-X related setting */
3306 adapter->intr.num_intrs = 1;
3311 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3313 if (adapter->intr.type == VMXNET3_IT_MSIX)
3314 pci_disable_msix(adapter->pdev);
3315 else if (adapter->intr.type == VMXNET3_IT_MSI)
3316 pci_disable_msi(adapter->pdev);
3318 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3323 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3325 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3326 adapter->tx_timeout_count++;
3328 netdev_err(adapter->netdev, "tx hang\n");
3329 schedule_work(&adapter->work);
3334 vmxnet3_reset_work(struct work_struct *data)
3336 struct vmxnet3_adapter *adapter;
3338 adapter = container_of(data, struct vmxnet3_adapter, work);
3340 /* if another thread is resetting the device, no need to proceed */
3341 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3344 /* if the device is closed, we must leave it alone */
3346 if (netif_running(adapter->netdev)) {
3347 netdev_notice(adapter->netdev, "resetting\n");
3348 vmxnet3_quiesce_dev(adapter);
3349 vmxnet3_reset_dev(adapter);
3350 vmxnet3_activate_dev(adapter);
3352 netdev_info(adapter->netdev, "already closed\n");
3356 netif_wake_queue(adapter->netdev);
3357 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3362 vmxnet3_probe_device(struct pci_dev *pdev,
3363 const struct pci_device_id *id)
3365 static const struct net_device_ops vmxnet3_netdev_ops = {
3366 .ndo_open = vmxnet3_open,
3367 .ndo_stop = vmxnet3_close,
3368 .ndo_start_xmit = vmxnet3_xmit_frame,
3369 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3370 .ndo_change_mtu = vmxnet3_change_mtu,
3371 .ndo_fix_features = vmxnet3_fix_features,
3372 .ndo_set_features = vmxnet3_set_features,
3373 .ndo_get_stats64 = vmxnet3_get_stats64,
3374 .ndo_tx_timeout = vmxnet3_tx_timeout,
3375 .ndo_set_rx_mode = vmxnet3_set_mc,
3376 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3377 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3378 #ifdef CONFIG_NET_POLL_CONTROLLER
3379 .ndo_poll_controller = vmxnet3_netpoll,
3385 struct net_device *netdev;
3386 struct vmxnet3_adapter *adapter;
3392 if (!pci_msi_enabled())
3397 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3398 (int)num_online_cpus());
3402 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3405 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3406 (int)num_online_cpus());
3410 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3411 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3412 max(num_tx_queues, num_rx_queues));
3413 dev_info(&pdev->dev,
3414 "# of Tx queues : %d, # of Rx queues : %d\n",
3415 num_tx_queues, num_rx_queues);
3420 pci_set_drvdata(pdev, netdev);
3421 adapter = netdev_priv(netdev);
3422 adapter->netdev = netdev;
3423 adapter->pdev = pdev;
3425 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3426 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3427 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3429 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
3430 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
3432 "pci_set_consistent_dma_mask failed\n");
3438 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
3440 "pci_set_dma_mask failed\n");
3447 spin_lock_init(&adapter->cmd_lock);
3448 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3449 sizeof(struct vmxnet3_adapter),
3451 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3452 dev_err(&pdev->dev, "Failed to map dma\n");
3456 adapter->shared = dma_alloc_coherent(
3457 &adapter->pdev->dev,
3458 sizeof(struct Vmxnet3_DriverShared),
3459 &adapter->shared_pa, GFP_KERNEL);
3460 if (!adapter->shared) {
3461 dev_err(&pdev->dev, "Failed to allocate memory\n");
3463 goto err_alloc_shared;
3466 adapter->num_rx_queues = num_rx_queues;
3467 adapter->num_tx_queues = num_tx_queues;
3468 adapter->rx_buf_per_pkt = 1;
3470 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3471 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3472 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3473 &adapter->queue_desc_pa,
3476 if (!adapter->tqd_start) {
3477 dev_err(&pdev->dev, "Failed to allocate memory\n");
3479 goto err_alloc_queue_desc;
3481 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3482 adapter->num_tx_queues);
3484 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3485 sizeof(struct Vmxnet3_PMConf),
3486 &adapter->pm_conf_pa,
3488 if (adapter->pm_conf == NULL) {
3495 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3496 sizeof(struct UPT1_RSSConf),
3497 &adapter->rss_conf_pa,
3499 if (adapter->rss_conf == NULL) {
3503 #endif /* VMXNET3_RSS */
3505 err = vmxnet3_alloc_pci_resources(adapter);
3509 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3510 if (ver & (1 << VMXNET3_REV_4)) {
3511 VMXNET3_WRITE_BAR1_REG(adapter,
3513 1 << VMXNET3_REV_4);
3514 adapter->version = VMXNET3_REV_4 + 1;
3515 } else if (ver & (1 << VMXNET3_REV_3)) {
3516 VMXNET3_WRITE_BAR1_REG(adapter,
3518 1 << VMXNET3_REV_3);
3519 adapter->version = VMXNET3_REV_3 + 1;
3520 } else if (ver & (1 << VMXNET3_REV_2)) {
3521 VMXNET3_WRITE_BAR1_REG(adapter,
3523 1 << VMXNET3_REV_2);
3524 adapter->version = VMXNET3_REV_2 + 1;
3525 } else if (ver & (1 << VMXNET3_REV_1)) {
3526 VMXNET3_WRITE_BAR1_REG(adapter,
3528 1 << VMXNET3_REV_1);
3529 adapter->version = VMXNET3_REV_1 + 1;
3532 "Incompatible h/w version (0x%x) for adapter\n", ver);
3536 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3538 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3540 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3543 "Incompatible upt version (0x%x) for adapter\n", ver);
3548 if (VMXNET3_VERSION_GE_3(adapter)) {
3549 adapter->coal_conf =
3550 dma_alloc_coherent(&adapter->pdev->dev,
3551 sizeof(struct Vmxnet3_CoalesceScheme)
3553 &adapter->coal_conf_pa,
3555 if (!adapter->coal_conf) {
3559 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3560 adapter->default_coal_mode = true;
3563 if (VMXNET3_VERSION_GE_4(adapter)) {
3564 adapter->default_rss_fields = true;
3565 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
3568 SET_NETDEV_DEV(netdev, &pdev->dev);
3569 vmxnet3_declare_features(adapter, dma64);
3571 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3572 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3574 if (adapter->num_tx_queues == adapter->num_rx_queues)
3575 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3577 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3579 vmxnet3_alloc_intr_resources(adapter);
3582 if (adapter->num_rx_queues > 1 &&
3583 adapter->intr.type == VMXNET3_IT_MSIX) {
3584 adapter->rss = true;
3585 netdev->hw_features |= NETIF_F_RXHASH;
3586 netdev->features |= NETIF_F_RXHASH;
3587 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3589 adapter->rss = false;
3593 vmxnet3_read_mac_addr(adapter, mac);
3594 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3596 netdev->netdev_ops = &vmxnet3_netdev_ops;
3597 vmxnet3_set_ethtool_ops(netdev);
3598 netdev->watchdog_timeo = 5 * HZ;
3600 /* MTU range: 60 - 9000 */
3601 netdev->min_mtu = VMXNET3_MIN_MTU;
3602 netdev->max_mtu = VMXNET3_MAX_MTU;
3604 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3605 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3607 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3609 for (i = 0; i < adapter->num_rx_queues; i++) {
3610 netif_napi_add(adapter->netdev,
3611 &adapter->rx_queue[i].napi,
3612 vmxnet3_poll_rx_only, 64);
3615 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3619 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3620 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3622 netif_carrier_off(netdev);
3623 err = register_netdev(netdev);
3626 dev_err(&pdev->dev, "Failed to register adapter\n");
3630 vmxnet3_check_link(adapter, false);
3634 if (VMXNET3_VERSION_GE_3(adapter)) {
3635 dma_free_coherent(&adapter->pdev->dev,
3636 sizeof(struct Vmxnet3_CoalesceScheme),
3637 adapter->coal_conf, adapter->coal_conf_pa);
3639 vmxnet3_free_intr_resources(adapter);
3641 vmxnet3_free_pci_resources(adapter);
3644 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3645 adapter->rss_conf, adapter->rss_conf_pa);
3648 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3649 adapter->pm_conf, adapter->pm_conf_pa);
3651 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3652 adapter->queue_desc_pa);
3653 err_alloc_queue_desc:
3654 dma_free_coherent(&adapter->pdev->dev,
3655 sizeof(struct Vmxnet3_DriverShared),
3656 adapter->shared, adapter->shared_pa);
3658 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3659 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3661 free_netdev(netdev);
3667 vmxnet3_remove_device(struct pci_dev *pdev)
3669 struct net_device *netdev = pci_get_drvdata(pdev);
3670 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3676 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3677 (int)num_online_cpus());
3681 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3683 cancel_work_sync(&adapter->work);
3685 unregister_netdev(netdev);
3687 vmxnet3_free_intr_resources(adapter);
3688 vmxnet3_free_pci_resources(adapter);
3689 if (VMXNET3_VERSION_GE_3(adapter)) {
3690 dma_free_coherent(&adapter->pdev->dev,
3691 sizeof(struct Vmxnet3_CoalesceScheme),
3692 adapter->coal_conf, adapter->coal_conf_pa);
3695 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3696 adapter->rss_conf, adapter->rss_conf_pa);
3698 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3699 adapter->pm_conf, adapter->pm_conf_pa);
3701 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3702 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3703 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3704 adapter->queue_desc_pa);
3705 dma_free_coherent(&adapter->pdev->dev,
3706 sizeof(struct Vmxnet3_DriverShared),
3707 adapter->shared, adapter->shared_pa);
3708 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3709 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3710 free_netdev(netdev);
3713 static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3715 struct net_device *netdev = pci_get_drvdata(pdev);
3716 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3717 unsigned long flags;
3719 /* Reset_work may be in the middle of resetting the device, wait for its
3722 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3723 usleep_range(1000, 2000);
3725 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3727 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3730 spin_lock_irqsave(&adapter->cmd_lock, flags);
3731 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3732 VMXNET3_CMD_QUIESCE_DEV);
3733 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3734 vmxnet3_disable_all_intrs(adapter);
3736 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3743 vmxnet3_suspend(struct device *device)
3745 struct pci_dev *pdev = to_pci_dev(device);
3746 struct net_device *netdev = pci_get_drvdata(pdev);
3747 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3748 struct Vmxnet3_PMConf *pmConf;
3749 struct ethhdr *ehdr;
3750 struct arphdr *ahdr;
3752 struct in_device *in_dev;
3753 struct in_ifaddr *ifa;
3754 unsigned long flags;
3757 if (!netif_running(netdev))
3760 for (i = 0; i < adapter->num_rx_queues; i++)
3761 napi_disable(&adapter->rx_queue[i].napi);
3763 vmxnet3_disable_all_intrs(adapter);
3764 vmxnet3_free_irqs(adapter);
3765 vmxnet3_free_intr_resources(adapter);
3767 netif_device_detach(netdev);
3768 netif_tx_stop_all_queues(netdev);
3770 /* Create wake-up filters. */
3771 pmConf = adapter->pm_conf;
3772 memset(pmConf, 0, sizeof(*pmConf));
3774 if (adapter->wol & WAKE_UCAST) {
3775 pmConf->filters[i].patternSize = ETH_ALEN;
3776 pmConf->filters[i].maskSize = 1;
3777 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3778 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3780 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3784 if (adapter->wol & WAKE_ARP) {
3787 in_dev = __in_dev_get_rcu(netdev);
3793 ifa = rcu_dereference(in_dev->ifa_list);
3799 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3800 sizeof(struct arphdr) + /* ARP header */
3801 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3802 2 * sizeof(u32); /*2 IPv4 addresses */
3803 pmConf->filters[i].maskSize =
3804 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3806 /* ETH_P_ARP in Ethernet header. */
3807 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3808 ehdr->h_proto = htons(ETH_P_ARP);
3810 /* ARPOP_REQUEST in ARP header. */
3811 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3812 ahdr->ar_op = htons(ARPOP_REQUEST);
3813 arpreq = (u8 *)(ahdr + 1);
3815 /* The Unicast IPv4 address in 'tip' field. */
3816 arpreq += 2 * ETH_ALEN + sizeof(u32);
3817 *(__be32 *)arpreq = ifa->ifa_address;
3821 /* The mask for the relevant bits. */
3822 pmConf->filters[i].mask[0] = 0x00;
3823 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3824 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3825 pmConf->filters[i].mask[3] = 0x00;
3826 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3827 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3829 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3834 if (adapter->wol & WAKE_MAGIC)
3835 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3837 pmConf->numFilters = i;
3839 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3840 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3842 adapter->shared->devRead.pmConfDesc.confPA =
3843 cpu_to_le64(adapter->pm_conf_pa);
3845 spin_lock_irqsave(&adapter->cmd_lock, flags);
3846 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3847 VMXNET3_CMD_UPDATE_PMCFG);
3848 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3850 pci_save_state(pdev);
3851 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3853 pci_disable_device(pdev);
3854 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3861 vmxnet3_resume(struct device *device)
3864 unsigned long flags;
3865 struct pci_dev *pdev = to_pci_dev(device);
3866 struct net_device *netdev = pci_get_drvdata(pdev);
3867 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3869 if (!netif_running(netdev))
3872 pci_set_power_state(pdev, PCI_D0);
3873 pci_restore_state(pdev);
3874 err = pci_enable_device_mem(pdev);
3878 pci_enable_wake(pdev, PCI_D0, 0);
3880 vmxnet3_alloc_intr_resources(adapter);
3882 /* During hibernate and suspend, device has to be reinitialized as the
3883 * device state need not be preserved.
3886 /* Need not check adapter state as other reset tasks cannot run during
3889 spin_lock_irqsave(&adapter->cmd_lock, flags);
3890 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3891 VMXNET3_CMD_QUIESCE_DEV);
3892 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3893 vmxnet3_tq_cleanup_all(adapter);
3894 vmxnet3_rq_cleanup_all(adapter);
3896 vmxnet3_reset_dev(adapter);
3897 err = vmxnet3_activate_dev(adapter);
3900 "failed to re-activate on resume, error: %d", err);
3901 vmxnet3_force_close(adapter);
3904 netif_device_attach(netdev);
3909 static const struct dev_pm_ops vmxnet3_pm_ops = {
3910 .suspend = vmxnet3_suspend,
3911 .resume = vmxnet3_resume,
3912 .freeze = vmxnet3_suspend,
3913 .restore = vmxnet3_resume,
3917 static struct pci_driver vmxnet3_driver = {
3918 .name = vmxnet3_driver_name,
3919 .id_table = vmxnet3_pciid_table,
3920 .probe = vmxnet3_probe_device,
3921 .remove = vmxnet3_remove_device,
3922 .shutdown = vmxnet3_shutdown_device,
3924 .driver.pm = &vmxnet3_pm_ops,
3930 vmxnet3_init_module(void)
3932 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
3933 VMXNET3_DRIVER_VERSION_REPORT);
3934 return pci_register_driver(&vmxnet3_driver);
3937 module_init(vmxnet3_init_module);
3941 vmxnet3_exit_module(void)
3943 pci_unregister_driver(&vmxnet3_driver);
3946 module_exit(vmxnet3_exit_module);
3948 MODULE_AUTHOR("VMware, Inc.");
3949 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3950 MODULE_LICENSE("GPL v2");
3951 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);