r8152: replace several functions about phy patch request
[linux-2.6-microblaze.git] / drivers / net / usb / r8152.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "11"
33
34 /* Information for net */
35 #define NET_VERSION             "11"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PLA_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_UPHY_TIMER          0xd388
61 #define PLA_SUSPEND_FLAG        0xd38a
62 #define PLA_INDICATE_FALG       0xd38c
63 #define PLA_MACDBG_PRE          0xd38c  /* RTL_VER_04 only */
64 #define PLA_MACDBG_POST         0xd38e  /* RTL_VER_04 only */
65 #define PLA_EXTRA_STATUS        0xd398
66 #define PLA_EFUSE_DATA          0xdd00
67 #define PLA_EFUSE_CMD           0xdd02
68 #define PLA_LEDSEL              0xdd90
69 #define PLA_LED_FEATURE         0xdd92
70 #define PLA_PHYAR               0xde00
71 #define PLA_BOOT_CTRL           0xe004
72 #define PLA_LWAKE_CTRL_REG      0xe007
73 #define PLA_GPHY_INTR_IMR       0xe022
74 #define PLA_EEE_CR              0xe040
75 #define PLA_EEEP_CR             0xe080
76 #define PLA_MAC_PWR_CTRL        0xe0c0
77 #define PLA_MAC_PWR_CTRL2       0xe0ca
78 #define PLA_MAC_PWR_CTRL3       0xe0cc
79 #define PLA_MAC_PWR_CTRL4       0xe0ce
80 #define PLA_WDT6_CTRL           0xe428
81 #define PLA_TCR0                0xe610
82 #define PLA_TCR1                0xe612
83 #define PLA_MTPS                0xe615
84 #define PLA_TXFIFO_CTRL         0xe618
85 #define PLA_RSTTALLY            0xe800
86 #define PLA_CR                  0xe813
87 #define PLA_CRWECR              0xe81c
88 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
89 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
90 #define PLA_CONFIG5             0xe822
91 #define PLA_PHY_PWR             0xe84c
92 #define PLA_OOB_CTRL            0xe84f
93 #define PLA_CPCR                0xe854
94 #define PLA_MISC_0              0xe858
95 #define PLA_MISC_1              0xe85a
96 #define PLA_OCP_GPHY_BASE       0xe86c
97 #define PLA_TALLYCNT            0xe890
98 #define PLA_SFF_STS_7           0xe8de
99 #define PLA_PHYSTATUS           0xe908
100 #define PLA_CONFIG6             0xe90a /* CONFIG6 */
101 #define PLA_BP_BA               0xfc26
102 #define PLA_BP_0                0xfc28
103 #define PLA_BP_1                0xfc2a
104 #define PLA_BP_2                0xfc2c
105 #define PLA_BP_3                0xfc2e
106 #define PLA_BP_4                0xfc30
107 #define PLA_BP_5                0xfc32
108 #define PLA_BP_6                0xfc34
109 #define PLA_BP_7                0xfc36
110 #define PLA_BP_EN               0xfc38
111
112 #define USB_USB2PHY             0xb41e
113 #define USB_SSPHYLINK1          0xb426
114 #define USB_SSPHYLINK2          0xb428
115 #define USB_U2P3_CTRL           0xb460
116 #define USB_CSR_DUMMY1          0xb464
117 #define USB_CSR_DUMMY2          0xb466
118 #define USB_DEV_STAT            0xb808
119 #define USB_CONNECT_TIMER       0xcbf8
120 #define USB_MSC_TIMER           0xcbfc
121 #define USB_BURST_SIZE          0xcfc0
122 #define USB_FW_FIX_EN0          0xcfca
123 #define USB_FW_FIX_EN1          0xcfcc
124 #define USB_LPM_CONFIG          0xcfd8
125 #define USB_CSTMR               0xcfef  /* RTL8153A */
126 #define USB_FW_CTRL             0xd334  /* RTL8153B */
127 #define USB_FC_TIMER            0xd340
128 #define USB_USB_CTRL            0xd406
129 #define USB_PHY_CTRL            0xd408
130 #define USB_TX_AGG              0xd40a
131 #define USB_RX_BUF_TH           0xd40c
132 #define USB_USB_TIMER           0xd428
133 #define USB_RX_EARLY_TIMEOUT    0xd42c
134 #define USB_RX_EARLY_SIZE       0xd42e
135 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
136 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
137 #define USB_TX_DMA              0xd434
138 #define USB_UPT_RXDMA_OWN       0xd437
139 #define USB_TOLERANCE           0xd490
140 #define USB_LPM_CTRL            0xd41a
141 #define USB_BMU_RESET           0xd4b0
142 #define USB_U1U2_TIMER          0xd4da
143 #define USB_FW_TASK             0xd4e8  /* RTL8153B */
144 #define USB_UPS_CTRL            0xd800
145 #define USB_POWER_CUT           0xd80a
146 #define USB_MISC_0              0xd81a
147 #define USB_MISC_1              0xd81f
148 #define USB_AFE_CTRL2           0xd824
149 #define USB_UPS_CFG             0xd842
150 #define USB_UPS_FLAGS           0xd848
151 #define USB_WDT1_CTRL           0xe404
152 #define USB_WDT11_CTRL          0xe43c
153 #define USB_BP_BA               PLA_BP_BA
154 #define USB_BP_0                PLA_BP_0
155 #define USB_BP_1                PLA_BP_1
156 #define USB_BP_2                PLA_BP_2
157 #define USB_BP_3                PLA_BP_3
158 #define USB_BP_4                PLA_BP_4
159 #define USB_BP_5                PLA_BP_5
160 #define USB_BP_6                PLA_BP_6
161 #define USB_BP_7                PLA_BP_7
162 #define USB_BP_EN               PLA_BP_EN       /* RTL8153A */
163 #define USB_BP_8                0xfc38          /* RTL8153B */
164 #define USB_BP_9                0xfc3a
165 #define USB_BP_10               0xfc3c
166 #define USB_BP_11               0xfc3e
167 #define USB_BP_12               0xfc40
168 #define USB_BP_13               0xfc42
169 #define USB_BP_14               0xfc44
170 #define USB_BP_15               0xfc46
171 #define USB_BP2_EN              0xfc48
172
173 /* OCP Registers */
174 #define OCP_ALDPS_CONFIG        0x2010
175 #define OCP_EEE_CONFIG1         0x2080
176 #define OCP_EEE_CONFIG2         0x2092
177 #define OCP_EEE_CONFIG3         0x2094
178 #define OCP_BASE_MII            0xa400
179 #define OCP_EEE_AR              0xa41a
180 #define OCP_EEE_DATA            0xa41c
181 #define OCP_PHY_STATUS          0xa420
182 #define OCP_NCTL_CFG            0xa42c
183 #define OCP_POWER_CFG           0xa430
184 #define OCP_EEE_CFG             0xa432
185 #define OCP_SRAM_ADDR           0xa436
186 #define OCP_SRAM_DATA           0xa438
187 #define OCP_DOWN_SPEED          0xa442
188 #define OCP_EEE_ABLE            0xa5c4
189 #define OCP_EEE_ADV             0xa5d0
190 #define OCP_EEE_LPABLE          0xa5d2
191 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
192 #define OCP_PHY_PATCH_STAT      0xb800
193 #define OCP_PHY_PATCH_CMD       0xb820
194 #define OCP_PHY_LOCK            0xb82e
195 #define OCP_ADC_IOFFSET         0xbcfc
196 #define OCP_ADC_CFG             0xbc06
197 #define OCP_SYSCLK_CFG          0xc416
198
199 /* SRAM Register */
200 #define SRAM_GREEN_CFG          0x8011
201 #define SRAM_LPF_CFG            0x8012
202 #define SRAM_10M_AMP1           0x8080
203 #define SRAM_10M_AMP2           0x8082
204 #define SRAM_IMPEDANCE          0x8084
205 #define SRAM_PHY_LOCK           0xb82e
206
207 /* PLA_RCR */
208 #define RCR_AAP                 0x00000001
209 #define RCR_APM                 0x00000002
210 #define RCR_AM                  0x00000004
211 #define RCR_AB                  0x00000008
212 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
213
214 /* PLA_RXFIFO_CTRL0 */
215 #define RXFIFO_THR1_NORMAL      0x00080002
216 #define RXFIFO_THR1_OOB         0x01800003
217
218 /* PLA_RXFIFO_CTRL1 */
219 #define RXFIFO_THR2_FULL        0x00000060
220 #define RXFIFO_THR2_HIGH        0x00000038
221 #define RXFIFO_THR2_OOB         0x0000004a
222 #define RXFIFO_THR2_NORMAL      0x00a0
223
224 /* PLA_RXFIFO_CTRL2 */
225 #define RXFIFO_THR3_FULL        0x00000078
226 #define RXFIFO_THR3_HIGH        0x00000048
227 #define RXFIFO_THR3_OOB         0x0000005a
228 #define RXFIFO_THR3_NORMAL      0x0110
229
230 /* PLA_TXFIFO_CTRL */
231 #define TXFIFO_THR_NORMAL       0x00400008
232 #define TXFIFO_THR_NORMAL2      0x01000008
233
234 /* PLA_DMY_REG0 */
235 #define ECM_ALDPS               0x0002
236
237 /* PLA_FMC */
238 #define FMC_FCR_MCU_EN          0x0001
239
240 /* PLA_EEEP_CR */
241 #define EEEP_CR_EEEP_TX         0x0002
242
243 /* PLA_WDT6_CTRL */
244 #define WDT6_SET_MODE           0x0010
245
246 /* PLA_TCR0 */
247 #define TCR0_TX_EMPTY           0x0800
248 #define TCR0_AUTO_FIFO          0x0080
249
250 /* PLA_TCR1 */
251 #define VERSION_MASK            0x7cf0
252
253 /* PLA_MTPS */
254 #define MTPS_JUMBO              (12 * 1024 / 64)
255 #define MTPS_DEFAULT            (6 * 1024 / 64)
256
257 /* PLA_RSTTALLY */
258 #define TALLY_RESET             0x0001
259
260 /* PLA_CR */
261 #define CR_RST                  0x10
262 #define CR_RE                   0x08
263 #define CR_TE                   0x04
264
265 /* PLA_CRWECR */
266 #define CRWECR_NORAML           0x00
267 #define CRWECR_CONFIG           0xc0
268
269 /* PLA_OOB_CTRL */
270 #define NOW_IS_OOB              0x80
271 #define TXFIFO_EMPTY            0x20
272 #define RXFIFO_EMPTY            0x10
273 #define LINK_LIST_READY         0x02
274 #define DIS_MCU_CLROOB          0x01
275 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
276
277 /* PLA_MISC_1 */
278 #define RXDY_GATED_EN           0x0008
279
280 /* PLA_SFF_STS_7 */
281 #define RE_INIT_LL              0x8000
282 #define MCU_BORW_EN             0x4000
283
284 /* PLA_CPCR */
285 #define CPCR_RX_VLAN            0x0040
286
287 /* PLA_CFG_WOL */
288 #define MAGIC_EN                0x0001
289
290 /* PLA_TEREDO_CFG */
291 #define TEREDO_SEL              0x8000
292 #define TEREDO_WAKE_MASK        0x7f00
293 #define TEREDO_RS_EVENT_MASK    0x00fe
294 #define OOB_TEREDO_EN           0x0001
295
296 /* PLA_BDC_CR */
297 #define ALDPS_PROXY_MODE        0x0001
298
299 /* PLA_EFUSE_CMD */
300 #define EFUSE_READ_CMD          BIT(15)
301 #define EFUSE_DATA_BIT16        BIT(7)
302
303 /* PLA_CONFIG34 */
304 #define LINK_ON_WAKE_EN         0x0010
305 #define LINK_OFF_WAKE_EN        0x0008
306
307 /* PLA_CONFIG6 */
308 #define LANWAKE_CLR_EN          BIT(0)
309
310 /* PLA_CONFIG5 */
311 #define BWF_EN                  0x0040
312 #define MWF_EN                  0x0020
313 #define UWF_EN                  0x0010
314 #define LAN_WAKE_EN             0x0002
315
316 /* PLA_LED_FEATURE */
317 #define LED_MODE_MASK           0x0700
318
319 /* PLA_PHY_PWR */
320 #define TX_10M_IDLE_EN          0x0080
321 #define PFM_PWM_SWITCH          0x0040
322 #define TEST_IO_OFF             BIT(4)
323
324 /* PLA_MAC_PWR_CTRL */
325 #define D3_CLK_GATED_EN         0x00004000
326 #define MCU_CLK_RATIO           0x07010f07
327 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
328 #define ALDPS_SPDWN_RATIO       0x0f87
329
330 /* PLA_MAC_PWR_CTRL2 */
331 #define EEE_SPDWN_RATIO         0x8007
332 #define MAC_CLK_SPDWN_EN        BIT(15)
333
334 /* PLA_MAC_PWR_CTRL3 */
335 #define PLA_MCU_SPDWN_EN        BIT(14)
336 #define PKT_AVAIL_SPDWN_EN      0x0100
337 #define SUSPEND_SPDWN_EN        0x0004
338 #define U1U2_SPDWN_EN           0x0002
339 #define L1_SPDWN_EN             0x0001
340
341 /* PLA_MAC_PWR_CTRL4 */
342 #define PWRSAVE_SPDWN_EN        0x1000
343 #define RXDV_SPDWN_EN           0x0800
344 #define TX10MIDLE_EN            0x0100
345 #define TP100_SPDWN_EN          0x0020
346 #define TP500_SPDWN_EN          0x0010
347 #define TP1000_SPDWN_EN         0x0008
348 #define EEE_SPDWN_EN            0x0001
349
350 /* PLA_GPHY_INTR_IMR */
351 #define GPHY_STS_MSK            0x0001
352 #define SPEED_DOWN_MSK          0x0002
353 #define SPDWN_RXDV_MSK          0x0004
354 #define SPDWN_LINKCHG_MSK       0x0008
355
356 /* PLA_PHYAR */
357 #define PHYAR_FLAG              0x80000000
358
359 /* PLA_EEE_CR */
360 #define EEE_RX_EN               0x0001
361 #define EEE_TX_EN               0x0002
362
363 /* PLA_BOOT_CTRL */
364 #define AUTOLOAD_DONE           0x0002
365
366 /* PLA_LWAKE_CTRL_REG */
367 #define LANWAKE_PIN             BIT(7)
368
369 /* PLA_SUSPEND_FLAG */
370 #define LINK_CHG_EVENT          BIT(0)
371
372 /* PLA_INDICATE_FALG */
373 #define UPCOMING_RUNTIME_D3     BIT(0)
374
375 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
376 #define DEBUG_OE                BIT(0)
377 #define DEBUG_LTSSM             0x0082
378
379 /* PLA_EXTRA_STATUS */
380 #define CUR_LINK_OK             BIT(15)
381 #define U3P3_CHECK_EN           BIT(7)  /* RTL_VER_05 only */
382 #define LINK_CHANGE_FLAG        BIT(8)
383 #define POLL_LINK_CHG           BIT(0)
384
385 /* USB_USB2PHY */
386 #define USB2PHY_SUSPEND         0x0001
387 #define USB2PHY_L1              0x0002
388
389 /* USB_SSPHYLINK1 */
390 #define DELAY_PHY_PWR_CHG       BIT(1)
391
392 /* USB_SSPHYLINK2 */
393 #define pwd_dn_scale_mask       0x3ffe
394 #define pwd_dn_scale(x)         ((x) << 1)
395
396 /* USB_CSR_DUMMY1 */
397 #define DYNAMIC_BURST           0x0001
398
399 /* USB_CSR_DUMMY2 */
400 #define EP4_FULL_FC             0x0001
401
402 /* USB_DEV_STAT */
403 #define STAT_SPEED_MASK         0x0006
404 #define STAT_SPEED_HIGH         0x0000
405 #define STAT_SPEED_FULL         0x0002
406
407 /* USB_FW_FIX_EN0 */
408 #define FW_FIX_SUSPEND          BIT(14)
409
410 /* USB_FW_FIX_EN1 */
411 #define FW_IP_RESET_EN          BIT(9)
412
413 /* USB_LPM_CONFIG */
414 #define LPM_U1U2_EN             BIT(0)
415
416 /* USB_TX_AGG */
417 #define TX_AGG_MAX_THRESHOLD    0x03
418
419 /* USB_RX_BUF_TH */
420 #define RX_THR_SUPPER           0x0c350180
421 #define RX_THR_HIGH             0x7a120180
422 #define RX_THR_SLOW             0xffff0180
423 #define RX_THR_B                0x00010001
424
425 /* USB_TX_DMA */
426 #define TEST_MODE_DISABLE       0x00000001
427 #define TX_SIZE_ADJUST1         0x00000100
428
429 /* USB_BMU_RESET */
430 #define BMU_RESET_EP_IN         0x01
431 #define BMU_RESET_EP_OUT        0x02
432
433 /* USB_UPT_RXDMA_OWN */
434 #define OWN_UPDATE              BIT(0)
435 #define OWN_CLEAR               BIT(1)
436
437 /* USB_FW_TASK */
438 #define FC_PATCH_TASK           BIT(1)
439
440 /* USB_UPS_CTRL */
441 #define POWER_CUT               0x0100
442
443 /* USB_PM_CTRL_STATUS */
444 #define RESUME_INDICATE         0x0001
445
446 /* USB_CSTMR */
447 #define FORCE_SUPER             BIT(0)
448
449 /* USB_FW_CTRL */
450 #define FLOW_CTRL_PATCH_OPT     BIT(1)
451
452 /* USB_FC_TIMER */
453 #define CTRL_TIMER_EN           BIT(15)
454
455 /* USB_USB_CTRL */
456 #define RX_AGG_DISABLE          0x0010
457 #define RX_ZERO_EN              0x0080
458
459 /* USB_U2P3_CTRL */
460 #define U2P3_ENABLE             0x0001
461
462 /* USB_POWER_CUT */
463 #define PWR_EN                  0x0001
464 #define PHASE2_EN               0x0008
465 #define UPS_EN                  BIT(4)
466 #define USP_PREWAKE             BIT(5)
467
468 /* USB_MISC_0 */
469 #define PCUT_STATUS             0x0001
470
471 /* USB_RX_EARLY_TIMEOUT */
472 #define COALESCE_SUPER           85000U
473 #define COALESCE_HIGH           250000U
474 #define COALESCE_SLOW           524280U
475
476 /* USB_WDT1_CTRL */
477 #define WTD1_EN                 BIT(0)
478
479 /* USB_WDT11_CTRL */
480 #define TIMER11_EN              0x0001
481
482 /* USB_LPM_CTRL */
483 /* bit 4 ~ 5: fifo empty boundary */
484 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
485 /* bit 2 ~ 3: LMP timer */
486 #define LPM_TIMER_MASK          0x0c
487 #define LPM_TIMER_500MS         0x04    /* 500 ms */
488 #define LPM_TIMER_500US         0x0c    /* 500 us */
489 #define ROK_EXIT_LPM            0x02
490
491 /* USB_AFE_CTRL2 */
492 #define SEN_VAL_MASK            0xf800
493 #define SEN_VAL_NORMAL          0xa000
494 #define SEL_RXIDLE              0x0100
495
496 /* USB_UPS_CFG */
497 #define SAW_CNT_1MS_MASK        0x0fff
498
499 /* USB_UPS_FLAGS */
500 #define UPS_FLAGS_R_TUNE                BIT(0)
501 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
502 #define UPS_FLAGS_250M_CKDIV            BIT(2)
503 #define UPS_FLAGS_EN_ALDPS              BIT(3)
504 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
505 #define ups_flags_speed(x)              ((x) << 16)
506 #define UPS_FLAGS_EN_EEE                BIT(20)
507 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
508 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
509 #define UPS_FLAGS_EEE_PLLOFF_100        BIT(23)
510 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
511 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
512 #define UPS_FLAGS_EN_GREEN              BIT(26)
513 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
514
515 enum spd_duplex {
516         NWAY_10M_HALF,
517         NWAY_10M_FULL,
518         NWAY_100M_HALF,
519         NWAY_100M_FULL,
520         NWAY_1000M_FULL,
521         FORCE_10M_HALF,
522         FORCE_10M_FULL,
523         FORCE_100M_HALF,
524         FORCE_100M_FULL,
525 };
526
527 /* OCP_ALDPS_CONFIG */
528 #define ENPWRSAVE               0x8000
529 #define ENPDNPS                 0x0200
530 #define LINKENA                 0x0100
531 #define DIS_SDSAVE              0x0010
532
533 /* OCP_PHY_STATUS */
534 #define PHY_STAT_MASK           0x0007
535 #define PHY_STAT_EXT_INIT       2
536 #define PHY_STAT_LAN_ON         3
537 #define PHY_STAT_PWRDN          5
538
539 /* OCP_NCTL_CFG */
540 #define PGA_RETURN_EN           BIT(1)
541
542 /* OCP_POWER_CFG */
543 #define EEE_CLKDIV_EN           0x8000
544 #define EN_ALDPS                0x0004
545 #define EN_10M_PLLOFF           0x0001
546
547 /* OCP_EEE_CONFIG1 */
548 #define RG_TXLPI_MSK_HFDUP      0x8000
549 #define RG_MATCLR_EN            0x4000
550 #define EEE_10_CAP              0x2000
551 #define EEE_NWAY_EN             0x1000
552 #define TX_QUIET_EN             0x0200
553 #define RX_QUIET_EN             0x0100
554 #define sd_rise_time_mask       0x0070
555 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
556 #define RG_RXLPI_MSK_HFDUP      0x0008
557 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
558
559 /* OCP_EEE_CONFIG2 */
560 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
561 #define RG_DACQUIET_EN          0x0400
562 #define RG_LDVQUIET_EN          0x0200
563 #define RG_CKRSEL               0x0020
564 #define RG_EEEPRG_EN            0x0010
565
566 /* OCP_EEE_CONFIG3 */
567 #define fast_snr_mask           0xff80
568 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
569 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
570 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
571
572 /* OCP_EEE_AR */
573 /* bit[15:14] function */
574 #define FUN_ADDR                0x0000
575 #define FUN_DATA                0x4000
576 /* bit[4:0] device addr */
577
578 /* OCP_EEE_CFG */
579 #define CTAP_SHORT_EN           0x0040
580 #define EEE10_EN                0x0010
581
582 /* OCP_DOWN_SPEED */
583 #define EN_EEE_CMODE            BIT(14)
584 #define EN_EEE_1000             BIT(13)
585 #define EN_EEE_100              BIT(12)
586 #define EN_10M_CLKDIV           BIT(11)
587 #define EN_10M_BGOFF            0x0080
588
589 /* OCP_PHY_STATE */
590 #define TXDIS_STATE             0x01
591 #define ABD_STATE               0x02
592
593 /* OCP_PHY_PATCH_STAT */
594 #define PATCH_READY             BIT(6)
595
596 /* OCP_PHY_PATCH_CMD */
597 #define PATCH_REQUEST           BIT(4)
598
599 /* OCP_PHY_LOCK */
600 #define PATCH_LOCK              BIT(0)
601
602 /* OCP_ADC_CFG */
603 #define CKADSEL_L               0x0100
604 #define ADC_EN                  0x0080
605 #define EN_EMI_L                0x0040
606
607 /* OCP_SYSCLK_CFG */
608 #define clk_div_expo(x)         (min(x, 5) << 8)
609
610 /* SRAM_GREEN_CFG */
611 #define GREEN_ETH_EN            BIT(15)
612 #define R_TUNE_EN               BIT(11)
613
614 /* SRAM_LPF_CFG */
615 #define LPF_AUTO_TUNE           0x8000
616
617 /* SRAM_10M_AMP1 */
618 #define GDAC_IB_UPALL           0x0008
619
620 /* SRAM_10M_AMP2 */
621 #define AMP_DN                  0x0200
622
623 /* SRAM_IMPEDANCE */
624 #define RX_DRIVING_MASK         0x6000
625
626 /* SRAM_PHY_LOCK */
627 #define PHY_PATCH_LOCK          0x0001
628
629 /* MAC PASSTHRU */
630 #define AD_MASK                 0xfee0
631 #define BND_MASK                0x0004
632 #define BD_MASK                 0x0001
633 #define EFUSE                   0xcfdb
634 #define PASS_THRU_MASK          0x1
635
636 #define BP4_SUPER_ONLY          0x1578  /* RTL_VER_04 only */
637
638 enum rtl_register_content {
639         _1000bps        = 0x10,
640         _100bps         = 0x08,
641         _10bps          = 0x04,
642         LINK_STATUS     = 0x02,
643         FULL_DUP        = 0x01,
644 };
645
646 #define RTL8152_MAX_TX          4
647 #define RTL8152_MAX_RX          10
648 #define INTBUFSIZE              2
649 #define TX_ALIGN                4
650 #define RX_ALIGN                8
651
652 #define RTL8152_RX_MAX_PENDING  4096
653 #define RTL8152_RXFG_HEADSZ     256
654
655 #define INTR_LINK               0x0004
656
657 #define RTL8153_MAX_PACKET      9216 /* 9K */
658 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
659                                  ETH_FCS_LEN)
660 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
661 #define RTL8153_RMS             RTL8153_MAX_PACKET
662 #define RTL8152_TX_TIMEOUT      (5 * HZ)
663 #define RTL8152_NAPI_WEIGHT     64
664 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
665                                  sizeof(struct rx_desc) + RX_ALIGN)
666
667 /* rtl8152 flags */
668 enum rtl8152_flags {
669         RTL8152_UNPLUG = 0,
670         RTL8152_SET_RX_MODE,
671         WORK_ENABLE,
672         RTL8152_LINK_CHG,
673         SELECTIVE_SUSPEND,
674         PHY_RESET,
675         SCHEDULE_TASKLET,
676         GREEN_ETHERNET,
677         DELL_TB_RX_AGG_BUG,
678         LENOVO_MACPASSTHRU,
679 };
680
681 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2       0x3082
682 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2              0xa387
683
684 struct tally_counter {
685         __le64  tx_packets;
686         __le64  rx_packets;
687         __le64  tx_errors;
688         __le32  rx_errors;
689         __le16  rx_missed;
690         __le16  align_errors;
691         __le32  tx_one_collision;
692         __le32  tx_multi_collision;
693         __le64  rx_unicast;
694         __le64  rx_broadcast;
695         __le32  rx_multicast;
696         __le16  tx_aborted;
697         __le16  tx_underrun;
698 };
699
700 struct rx_desc {
701         __le32 opts1;
702 #define RX_LEN_MASK                     0x7fff
703
704         __le32 opts2;
705 #define RD_UDP_CS                       BIT(23)
706 #define RD_TCP_CS                       BIT(22)
707 #define RD_IPV6_CS                      BIT(20)
708 #define RD_IPV4_CS                      BIT(19)
709
710         __le32 opts3;
711 #define IPF                             BIT(23) /* IP checksum fail */
712 #define UDPF                            BIT(22) /* UDP checksum fail */
713 #define TCPF                            BIT(21) /* TCP checksum fail */
714 #define RX_VLAN_TAG                     BIT(16)
715
716         __le32 opts4;
717         __le32 opts5;
718         __le32 opts6;
719 };
720
721 struct tx_desc {
722         __le32 opts1;
723 #define TX_FS                   BIT(31) /* First segment of a packet */
724 #define TX_LS                   BIT(30) /* Final segment of a packet */
725 #define GTSENDV4                BIT(28)
726 #define GTSENDV6                BIT(27)
727 #define GTTCPHO_SHIFT           18
728 #define GTTCPHO_MAX             0x7fU
729 #define TX_LEN_MAX              0x3ffffU
730
731         __le32 opts2;
732 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
733 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
734 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
735 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
736 #define MSS_SHIFT               17
737 #define MSS_MAX                 0x7ffU
738 #define TCPHO_SHIFT             17
739 #define TCPHO_MAX               0x7ffU
740 #define TX_VLAN_TAG             BIT(16)
741 };
742
743 struct r8152;
744
745 struct rx_agg {
746         struct list_head list, info_list;
747         struct urb *urb;
748         struct r8152 *context;
749         struct page *page;
750         void *buffer;
751 };
752
753 struct tx_agg {
754         struct list_head list;
755         struct urb *urb;
756         struct r8152 *context;
757         void *buffer;
758         void *head;
759         u32 skb_num;
760         u32 skb_len;
761 };
762
763 struct r8152 {
764         unsigned long flags;
765         struct usb_device *udev;
766         struct napi_struct napi;
767         struct usb_interface *intf;
768         struct net_device *netdev;
769         struct urb *intr_urb;
770         struct tx_agg tx_info[RTL8152_MAX_TX];
771         struct list_head rx_info, rx_used;
772         struct list_head rx_done, tx_free;
773         struct sk_buff_head tx_queue, rx_queue;
774         spinlock_t rx_lock, tx_lock;
775         struct delayed_work schedule, hw_phy_work;
776         struct mii_if_info mii;
777         struct mutex control;   /* use for hw setting */
778 #ifdef CONFIG_PM_SLEEP
779         struct notifier_block pm_notifier;
780 #endif
781         struct tasklet_struct tx_tl;
782
783         struct rtl_ops {
784                 void (*init)(struct r8152 *tp);
785                 int (*enable)(struct r8152 *tp);
786                 void (*disable)(struct r8152 *tp);
787                 void (*up)(struct r8152 *tp);
788                 void (*down)(struct r8152 *tp);
789                 void (*unload)(struct r8152 *tp);
790                 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
791                 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
792                 bool (*in_nway)(struct r8152 *tp);
793                 void (*hw_phy_cfg)(struct r8152 *tp);
794                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
795         } rtl_ops;
796
797         struct ups_info {
798                 u32 _10m_ckdiv:1;
799                 u32 _250m_ckdiv:1;
800                 u32 aldps:1;
801                 u32 lite_mode:2;
802                 u32 speed_duplex:4;
803                 u32 eee:1;
804                 u32 eee_lite:1;
805                 u32 eee_ckdiv:1;
806                 u32 eee_plloff_100:1;
807                 u32 eee_plloff_giga:1;
808                 u32 eee_cmod_lv:1;
809                 u32 green:1;
810                 u32 flow_control:1;
811                 u32 ctap_short_off:1;
812         } ups_info;
813
814 #define RTL_VER_SIZE            32
815
816         struct rtl_fw {
817                 const char *fw_name;
818                 const struct firmware *fw;
819
820                 char version[RTL_VER_SIZE];
821                 int (*pre_fw)(struct r8152 *tp);
822                 int (*post_fw)(struct r8152 *tp);
823
824                 bool retry;
825         } rtl_fw;
826
827         atomic_t rx_count;
828
829         bool eee_en;
830         int intr_interval;
831         u32 saved_wolopts;
832         u32 msg_enable;
833         u32 tx_qlen;
834         u32 coalesce;
835         u32 advertising;
836         u32 rx_buf_sz;
837         u32 rx_copybreak;
838         u32 rx_pending;
839
840         u16 ocp_base;
841         u16 speed;
842         u16 eee_adv;
843         u8 *intr_buff;
844         u8 version;
845         u8 duplex;
846         u8 autoneg;
847 };
848
849 /**
850  * struct fw_block - block type and total length
851  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
852  *      RTL_FW_USB and so on.
853  * @length: total length of the current block.
854  */
855 struct fw_block {
856         __le32 type;
857         __le32 length;
858 } __packed;
859
860 /**
861  * struct fw_header - header of the firmware file
862  * @checksum: checksum of sha256 which is calculated from the whole file
863  *      except the checksum field of the file. That is, calculate sha256
864  *      from the version field to the end of the file.
865  * @version: version of this firmware.
866  * @blocks: the first firmware block of the file
867  */
868 struct fw_header {
869         u8 checksum[32];
870         char version[RTL_VER_SIZE];
871         struct fw_block blocks[];
872 } __packed;
873
874 /**
875  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
876  *      The layout of the firmware block is:
877  *      <struct fw_mac> + <info> + <firmware data>.
878  * @blk_hdr: firmware descriptor (type, length)
879  * @fw_offset: offset of the firmware binary data. The start address of
880  *      the data would be the address of struct fw_mac + @fw_offset.
881  * @fw_reg: the register to load the firmware. Depends on chip.
882  * @bp_ba_addr: the register to write break point base address. Depends on
883  *      chip.
884  * @bp_ba_value: break point base address. Depends on chip.
885  * @bp_en_addr: the register to write break point enabled mask. Depends
886  *      on chip.
887  * @bp_en_value: break point enabled mask. Depends on the firmware.
888  * @bp_start: the start register of break points. Depends on chip.
889  * @bp_num: the break point number which needs to be set for this firmware.
890  *      Depends on the firmware.
891  * @bp: break points. Depends on firmware.
892  * @reserved: reserved space (unused)
893  * @fw_ver_reg: the register to store the fw version.
894  * @fw_ver_data: the firmware version of the current type.
895  * @info: additional information for debugging, and is followed by the
896  *      binary data of firmware.
897  */
898 struct fw_mac {
899         struct fw_block blk_hdr;
900         __le16 fw_offset;
901         __le16 fw_reg;
902         __le16 bp_ba_addr;
903         __le16 bp_ba_value;
904         __le16 bp_en_addr;
905         __le16 bp_en_value;
906         __le16 bp_start;
907         __le16 bp_num;
908         __le16 bp[16]; /* any value determined by firmware */
909         __le32 reserved;
910         __le16 fw_ver_reg;
911         u8 fw_ver_data;
912         char info[];
913 } __packed;
914
915 /**
916  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
917  *      This is used to set patch key when loading the firmware of PHY.
918  * @blk_hdr: firmware descriptor (type, length)
919  * @key_reg: the register to write the patch key.
920  * @key_data: patch key.
921  * @reserved: reserved space (unused)
922  */
923 struct fw_phy_patch_key {
924         struct fw_block blk_hdr;
925         __le16 key_reg;
926         __le16 key_data;
927         __le32 reserved;
928 } __packed;
929
930 /**
931  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
932  *      The layout of the firmware block is:
933  *      <struct fw_phy_nc> + <info> + <firmware data>.
934  * @blk_hdr: firmware descriptor (type, length)
935  * @fw_offset: offset of the firmware binary data. The start address of
936  *      the data would be the address of struct fw_phy_nc + @fw_offset.
937  * @fw_reg: the register to load the firmware. Depends on chip.
938  * @ba_reg: the register to write the base address. Depends on chip.
939  * @ba_data: base address. Depends on chip.
940  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
941  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
942  * @mode_reg: the regitster of switching the mode.
943  * @mode_pre: the mode needing to be set before loading the firmware.
944  * @mode_post: the mode to be set when finishing to load the firmware.
945  * @reserved: reserved space (unused)
946  * @bp_start: the start register of break points. Depends on chip.
947  * @bp_num: the break point number which needs to be set for this firmware.
948  *      Depends on the firmware.
949  * @bp: break points. Depends on firmware.
950  * @info: additional information for debugging, and is followed by the
951  *      binary data of firmware.
952  */
953 struct fw_phy_nc {
954         struct fw_block blk_hdr;
955         __le16 fw_offset;
956         __le16 fw_reg;
957         __le16 ba_reg;
958         __le16 ba_data;
959         __le16 patch_en_addr;
960         __le16 patch_en_value;
961         __le16 mode_reg;
962         __le16 mode_pre;
963         __le16 mode_post;
964         __le16 reserved;
965         __le16 bp_start;
966         __le16 bp_num;
967         __le16 bp[4];
968         char info[];
969 } __packed;
970
971 enum rtl_fw_type {
972         RTL_FW_END = 0,
973         RTL_FW_PLA,
974         RTL_FW_USB,
975         RTL_FW_PHY_START,
976         RTL_FW_PHY_STOP,
977         RTL_FW_PHY_NC,
978 };
979
980 enum rtl_version {
981         RTL_VER_UNKNOWN = 0,
982         RTL_VER_01,
983         RTL_VER_02,
984         RTL_VER_03,
985         RTL_VER_04,
986         RTL_VER_05,
987         RTL_VER_06,
988         RTL_VER_07,
989         RTL_VER_08,
990         RTL_VER_09,
991         RTL_VER_MAX
992 };
993
994 enum tx_csum_stat {
995         TX_CSUM_SUCCESS = 0,
996         TX_CSUM_TSO,
997         TX_CSUM_NONE
998 };
999
1000 #define RTL_ADVERTISED_10_HALF                  BIT(0)
1001 #define RTL_ADVERTISED_10_FULL                  BIT(1)
1002 #define RTL_ADVERTISED_100_HALF                 BIT(2)
1003 #define RTL_ADVERTISED_100_FULL                 BIT(3)
1004 #define RTL_ADVERTISED_1000_HALF                BIT(4)
1005 #define RTL_ADVERTISED_1000_FULL                BIT(5)
1006
1007 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1008  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1009  */
1010 static const int multicast_filter_limit = 32;
1011 static unsigned int agg_buf_sz = 16384;
1012
1013 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
1014                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
1015
1016 static
1017 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1018 {
1019         int ret;
1020         void *tmp;
1021
1022         tmp = kmalloc(size, GFP_KERNEL);
1023         if (!tmp)
1024                 return -ENOMEM;
1025
1026         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1027                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1028                               value, index, tmp, size, 500);
1029         if (ret < 0)
1030                 memset(data, 0xff, size);
1031         else
1032                 memcpy(data, tmp, size);
1033
1034         kfree(tmp);
1035
1036         return ret;
1037 }
1038
1039 static
1040 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1041 {
1042         int ret;
1043         void *tmp;
1044
1045         tmp = kmemdup(data, size, GFP_KERNEL);
1046         if (!tmp)
1047                 return -ENOMEM;
1048
1049         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1050                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1051                               value, index, tmp, size, 500);
1052
1053         kfree(tmp);
1054
1055         return ret;
1056 }
1057
1058 static void rtl_set_unplug(struct r8152 *tp)
1059 {
1060         if (tp->udev->state == USB_STATE_NOTATTACHED) {
1061                 set_bit(RTL8152_UNPLUG, &tp->flags);
1062                 smp_mb__after_atomic();
1063         }
1064 }
1065
1066 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1067                             void *data, u16 type)
1068 {
1069         u16 limit = 64;
1070         int ret = 0;
1071
1072         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1073                 return -ENODEV;
1074
1075         /* both size and indix must be 4 bytes align */
1076         if ((size & 3) || !size || (index & 3) || !data)
1077                 return -EPERM;
1078
1079         if ((u32)index + (u32)size > 0xffff)
1080                 return -EPERM;
1081
1082         while (size) {
1083                 if (size > limit) {
1084                         ret = get_registers(tp, index, type, limit, data);
1085                         if (ret < 0)
1086                                 break;
1087
1088                         index += limit;
1089                         data += limit;
1090                         size -= limit;
1091                 } else {
1092                         ret = get_registers(tp, index, type, size, data);
1093                         if (ret < 0)
1094                                 break;
1095
1096                         index += size;
1097                         data += size;
1098                         size = 0;
1099                         break;
1100                 }
1101         }
1102
1103         if (ret == -ENODEV)
1104                 rtl_set_unplug(tp);
1105
1106         return ret;
1107 }
1108
1109 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1110                              u16 size, void *data, u16 type)
1111 {
1112         int ret;
1113         u16 byteen_start, byteen_end, byen;
1114         u16 limit = 512;
1115
1116         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117                 return -ENODEV;
1118
1119         /* both size and indix must be 4 bytes align */
1120         if ((size & 3) || !size || (index & 3) || !data)
1121                 return -EPERM;
1122
1123         if ((u32)index + (u32)size > 0xffff)
1124                 return -EPERM;
1125
1126         byteen_start = byteen & BYTE_EN_START_MASK;
1127         byteen_end = byteen & BYTE_EN_END_MASK;
1128
1129         byen = byteen_start | (byteen_start << 4);
1130         ret = set_registers(tp, index, type | byen, 4, data);
1131         if (ret < 0)
1132                 goto error1;
1133
1134         index += 4;
1135         data += 4;
1136         size -= 4;
1137
1138         if (size) {
1139                 size -= 4;
1140
1141                 while (size) {
1142                         if (size > limit) {
1143                                 ret = set_registers(tp, index,
1144                                                     type | BYTE_EN_DWORD,
1145                                                     limit, data);
1146                                 if (ret < 0)
1147                                         goto error1;
1148
1149                                 index += limit;
1150                                 data += limit;
1151                                 size -= limit;
1152                         } else {
1153                                 ret = set_registers(tp, index,
1154                                                     type | BYTE_EN_DWORD,
1155                                                     size, data);
1156                                 if (ret < 0)
1157                                         goto error1;
1158
1159                                 index += size;
1160                                 data += size;
1161                                 size = 0;
1162                                 break;
1163                         }
1164                 }
1165
1166                 byen = byteen_end | (byteen_end >> 4);
1167                 ret = set_registers(tp, index, type | byen, 4, data);
1168                 if (ret < 0)
1169                         goto error1;
1170         }
1171
1172 error1:
1173         if (ret == -ENODEV)
1174                 rtl_set_unplug(tp);
1175
1176         return ret;
1177 }
1178
1179 static inline
1180 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1181 {
1182         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1183 }
1184
1185 static inline
1186 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1187 {
1188         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1189 }
1190
1191 static inline
1192 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1193 {
1194         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1195 }
1196
1197 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1198 {
1199         __le32 data;
1200
1201         generic_ocp_read(tp, index, sizeof(data), &data, type);
1202
1203         return __le32_to_cpu(data);
1204 }
1205
1206 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1207 {
1208         __le32 tmp = __cpu_to_le32(data);
1209
1210         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1211 }
1212
1213 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1214 {
1215         u32 data;
1216         __le32 tmp;
1217         u16 byen = BYTE_EN_WORD;
1218         u8 shift = index & 2;
1219
1220         index &= ~3;
1221         byen <<= shift;
1222
1223         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1224
1225         data = __le32_to_cpu(tmp);
1226         data >>= (shift * 8);
1227         data &= 0xffff;
1228
1229         return (u16)data;
1230 }
1231
1232 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1233 {
1234         u32 mask = 0xffff;
1235         __le32 tmp;
1236         u16 byen = BYTE_EN_WORD;
1237         u8 shift = index & 2;
1238
1239         data &= mask;
1240
1241         if (index & 2) {
1242                 byen <<= shift;
1243                 mask <<= (shift * 8);
1244                 data <<= (shift * 8);
1245                 index &= ~3;
1246         }
1247
1248         tmp = __cpu_to_le32(data);
1249
1250         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1251 }
1252
1253 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1254 {
1255         u32 data;
1256         __le32 tmp;
1257         u8 shift = index & 3;
1258
1259         index &= ~3;
1260
1261         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1262
1263         data = __le32_to_cpu(tmp);
1264         data >>= (shift * 8);
1265         data &= 0xff;
1266
1267         return (u8)data;
1268 }
1269
1270 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1271 {
1272         u32 mask = 0xff;
1273         __le32 tmp;
1274         u16 byen = BYTE_EN_BYTE;
1275         u8 shift = index & 3;
1276
1277         data &= mask;
1278
1279         if (index & 3) {
1280                 byen <<= shift;
1281                 mask <<= (shift * 8);
1282                 data <<= (shift * 8);
1283                 index &= ~3;
1284         }
1285
1286         tmp = __cpu_to_le32(data);
1287
1288         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1289 }
1290
1291 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1292 {
1293         u16 ocp_base, ocp_index;
1294
1295         ocp_base = addr & 0xf000;
1296         if (ocp_base != tp->ocp_base) {
1297                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1298                 tp->ocp_base = ocp_base;
1299         }
1300
1301         ocp_index = (addr & 0x0fff) | 0xb000;
1302         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1303 }
1304
1305 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1306 {
1307         u16 ocp_base, ocp_index;
1308
1309         ocp_base = addr & 0xf000;
1310         if (ocp_base != tp->ocp_base) {
1311                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1312                 tp->ocp_base = ocp_base;
1313         }
1314
1315         ocp_index = (addr & 0x0fff) | 0xb000;
1316         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1317 }
1318
1319 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1320 {
1321         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1322 }
1323
1324 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1325 {
1326         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1327 }
1328
1329 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1330 {
1331         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1332         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1333 }
1334
1335 static u16 sram_read(struct r8152 *tp, u16 addr)
1336 {
1337         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1338         return ocp_reg_read(tp, OCP_SRAM_DATA);
1339 }
1340
1341 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1342 {
1343         struct r8152 *tp = netdev_priv(netdev);
1344         int ret;
1345
1346         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1347                 return -ENODEV;
1348
1349         if (phy_id != R8152_PHY_ID)
1350                 return -EINVAL;
1351
1352         ret = r8152_mdio_read(tp, reg);
1353
1354         return ret;
1355 }
1356
1357 static
1358 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1359 {
1360         struct r8152 *tp = netdev_priv(netdev);
1361
1362         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1363                 return;
1364
1365         if (phy_id != R8152_PHY_ID)
1366                 return;
1367
1368         r8152_mdio_write(tp, reg, val);
1369 }
1370
1371 static int
1372 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1373
1374 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1375 {
1376         struct r8152 *tp = netdev_priv(netdev);
1377         struct sockaddr *addr = p;
1378         int ret = -EADDRNOTAVAIL;
1379
1380         if (!is_valid_ether_addr(addr->sa_data))
1381                 goto out1;
1382
1383         ret = usb_autopm_get_interface(tp->intf);
1384         if (ret < 0)
1385                 goto out1;
1386
1387         mutex_lock(&tp->control);
1388
1389         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1390
1391         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1392         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1393         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1394
1395         mutex_unlock(&tp->control);
1396
1397         usb_autopm_put_interface(tp->intf);
1398 out1:
1399         return ret;
1400 }
1401
1402 /* Devices containing proper chips can support a persistent
1403  * host system provided MAC address.
1404  * Examples of this are Dell TB15 and Dell WD15 docks
1405  */
1406 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1407 {
1408         acpi_status status;
1409         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1410         union acpi_object *obj;
1411         int ret = -EINVAL;
1412         u32 ocp_data;
1413         unsigned char buf[6];
1414         char *mac_obj_name;
1415         acpi_object_type mac_obj_type;
1416         int mac_strlen;
1417
1418         if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1419                 mac_obj_name = "\\MACA";
1420                 mac_obj_type = ACPI_TYPE_STRING;
1421                 mac_strlen = 0x16;
1422         } else {
1423                 /* test for -AD variant of RTL8153 */
1424                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1425                 if ((ocp_data & AD_MASK) == 0x1000) {
1426                         /* test for MAC address pass-through bit */
1427                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1428                         if ((ocp_data & PASS_THRU_MASK) != 1) {
1429                                 netif_dbg(tp, probe, tp->netdev,
1430                                                 "No efuse for RTL8153-AD MAC pass through\n");
1431                                 return -ENODEV;
1432                         }
1433                 } else {
1434                         /* test for RTL8153-BND and RTL8153-BD */
1435                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1436                         if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1437                                 netif_dbg(tp, probe, tp->netdev,
1438                                                 "Invalid variant for MAC pass through\n");
1439                                 return -ENODEV;
1440                         }
1441                 }
1442
1443                 mac_obj_name = "\\_SB.AMAC";
1444                 mac_obj_type = ACPI_TYPE_BUFFER;
1445                 mac_strlen = 0x17;
1446         }
1447
1448         /* returns _AUXMAC_#AABBCCDDEEFF# */
1449         status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1450         obj = (union acpi_object *)buffer.pointer;
1451         if (!ACPI_SUCCESS(status))
1452                 return -ENODEV;
1453         if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1454                 netif_warn(tp, probe, tp->netdev,
1455                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1456                            obj->type, obj->string.length);
1457                 goto amacout;
1458         }
1459
1460         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1461             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1462                 netif_warn(tp, probe, tp->netdev,
1463                            "Invalid header when reading pass-thru MAC addr\n");
1464                 goto amacout;
1465         }
1466         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1467         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1468                 netif_warn(tp, probe, tp->netdev,
1469                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1470                            ret, buf);
1471                 ret = -EINVAL;
1472                 goto amacout;
1473         }
1474         memcpy(sa->sa_data, buf, 6);
1475         netif_info(tp, probe, tp->netdev,
1476                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1477
1478 amacout:
1479         kfree(obj);
1480         return ret;
1481 }
1482
1483 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1484 {
1485         struct net_device *dev = tp->netdev;
1486         int ret;
1487
1488         sa->sa_family = dev->type;
1489
1490         ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1491         if (ret < 0) {
1492                 if (tp->version == RTL_VER_01) {
1493                         ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1494                 } else {
1495                         /* if device doesn't support MAC pass through this will
1496                          * be expected to be non-zero
1497                          */
1498                         ret = vendor_mac_passthru_addr_read(tp, sa);
1499                         if (ret < 0)
1500                                 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1501                                                    sa->sa_data);
1502                 }
1503         }
1504
1505         if (ret < 0) {
1506                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1507         } else if (!is_valid_ether_addr(sa->sa_data)) {
1508                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1509                           sa->sa_data);
1510                 eth_hw_addr_random(dev);
1511                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1512                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1513                            sa->sa_data);
1514                 return 0;
1515         }
1516
1517         return ret;
1518 }
1519
1520 static int set_ethernet_addr(struct r8152 *tp)
1521 {
1522         struct net_device *dev = tp->netdev;
1523         struct sockaddr sa;
1524         int ret;
1525
1526         ret = determine_ethernet_addr(tp, &sa);
1527         if (ret < 0)
1528                 return ret;
1529
1530         if (tp->version == RTL_VER_01)
1531                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1532         else
1533                 ret = rtl8152_set_mac_address(dev, &sa);
1534
1535         return ret;
1536 }
1537
1538 static void read_bulk_callback(struct urb *urb)
1539 {
1540         struct net_device *netdev;
1541         int status = urb->status;
1542         struct rx_agg *agg;
1543         struct r8152 *tp;
1544         unsigned long flags;
1545
1546         agg = urb->context;
1547         if (!agg)
1548                 return;
1549
1550         tp = agg->context;
1551         if (!tp)
1552                 return;
1553
1554         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1555                 return;
1556
1557         if (!test_bit(WORK_ENABLE, &tp->flags))
1558                 return;
1559
1560         netdev = tp->netdev;
1561
1562         /* When link down, the driver would cancel all bulks. */
1563         /* This avoid the re-submitting bulk */
1564         if (!netif_carrier_ok(netdev))
1565                 return;
1566
1567         usb_mark_last_busy(tp->udev);
1568
1569         switch (status) {
1570         case 0:
1571                 if (urb->actual_length < ETH_ZLEN)
1572                         break;
1573
1574                 spin_lock_irqsave(&tp->rx_lock, flags);
1575                 list_add_tail(&agg->list, &tp->rx_done);
1576                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1577                 napi_schedule(&tp->napi);
1578                 return;
1579         case -ESHUTDOWN:
1580                 rtl_set_unplug(tp);
1581                 netif_device_detach(tp->netdev);
1582                 return;
1583         case -ENOENT:
1584                 return; /* the urb is in unlink state */
1585         case -ETIME:
1586                 if (net_ratelimit())
1587                         netdev_warn(netdev, "maybe reset is needed?\n");
1588                 break;
1589         default:
1590                 if (net_ratelimit())
1591                         netdev_warn(netdev, "Rx status %d\n", status);
1592                 break;
1593         }
1594
1595         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1596 }
1597
1598 static void write_bulk_callback(struct urb *urb)
1599 {
1600         struct net_device_stats *stats;
1601         struct net_device *netdev;
1602         struct tx_agg *agg;
1603         struct r8152 *tp;
1604         unsigned long flags;
1605         int status = urb->status;
1606
1607         agg = urb->context;
1608         if (!agg)
1609                 return;
1610
1611         tp = agg->context;
1612         if (!tp)
1613                 return;
1614
1615         netdev = tp->netdev;
1616         stats = &netdev->stats;
1617         if (status) {
1618                 if (net_ratelimit())
1619                         netdev_warn(netdev, "Tx status %d\n", status);
1620                 stats->tx_errors += agg->skb_num;
1621         } else {
1622                 stats->tx_packets += agg->skb_num;
1623                 stats->tx_bytes += agg->skb_len;
1624         }
1625
1626         spin_lock_irqsave(&tp->tx_lock, flags);
1627         list_add_tail(&agg->list, &tp->tx_free);
1628         spin_unlock_irqrestore(&tp->tx_lock, flags);
1629
1630         usb_autopm_put_interface_async(tp->intf);
1631
1632         if (!netif_carrier_ok(netdev))
1633                 return;
1634
1635         if (!test_bit(WORK_ENABLE, &tp->flags))
1636                 return;
1637
1638         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1639                 return;
1640
1641         if (!skb_queue_empty(&tp->tx_queue))
1642                 tasklet_schedule(&tp->tx_tl);
1643 }
1644
1645 static void intr_callback(struct urb *urb)
1646 {
1647         struct r8152 *tp;
1648         __le16 *d;
1649         int status = urb->status;
1650         int res;
1651
1652         tp = urb->context;
1653         if (!tp)
1654                 return;
1655
1656         if (!test_bit(WORK_ENABLE, &tp->flags))
1657                 return;
1658
1659         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1660                 return;
1661
1662         switch (status) {
1663         case 0:                 /* success */
1664                 break;
1665         case -ECONNRESET:       /* unlink */
1666         case -ESHUTDOWN:
1667                 netif_device_detach(tp->netdev);
1668                 fallthrough;
1669         case -ENOENT:
1670         case -EPROTO:
1671                 netif_info(tp, intr, tp->netdev,
1672                            "Stop submitting intr, status %d\n", status);
1673                 return;
1674         case -EOVERFLOW:
1675                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1676                 goto resubmit;
1677         /* -EPIPE:  should clear the halt */
1678         default:
1679                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1680                 goto resubmit;
1681         }
1682
1683         d = urb->transfer_buffer;
1684         if (INTR_LINK & __le16_to_cpu(d[0])) {
1685                 if (!netif_carrier_ok(tp->netdev)) {
1686                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1687                         schedule_delayed_work(&tp->schedule, 0);
1688                 }
1689         } else {
1690                 if (netif_carrier_ok(tp->netdev)) {
1691                         netif_stop_queue(tp->netdev);
1692                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1693                         schedule_delayed_work(&tp->schedule, 0);
1694                 }
1695         }
1696
1697 resubmit:
1698         res = usb_submit_urb(urb, GFP_ATOMIC);
1699         if (res == -ENODEV) {
1700                 rtl_set_unplug(tp);
1701                 netif_device_detach(tp->netdev);
1702         } else if (res) {
1703                 netif_err(tp, intr, tp->netdev,
1704                           "can't resubmit intr, status %d\n", res);
1705         }
1706 }
1707
1708 static inline void *rx_agg_align(void *data)
1709 {
1710         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1711 }
1712
1713 static inline void *tx_agg_align(void *data)
1714 {
1715         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1716 }
1717
1718 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1719 {
1720         list_del(&agg->info_list);
1721
1722         usb_free_urb(agg->urb);
1723         put_page(agg->page);
1724         kfree(agg);
1725
1726         atomic_dec(&tp->rx_count);
1727 }
1728
1729 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1730 {
1731         struct net_device *netdev = tp->netdev;
1732         int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1733         unsigned int order = get_order(tp->rx_buf_sz);
1734         struct rx_agg *rx_agg;
1735         unsigned long flags;
1736
1737         rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1738         if (!rx_agg)
1739                 return NULL;
1740
1741         rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1742         if (!rx_agg->page)
1743                 goto free_rx;
1744
1745         rx_agg->buffer = page_address(rx_agg->page);
1746
1747         rx_agg->urb = usb_alloc_urb(0, mflags);
1748         if (!rx_agg->urb)
1749                 goto free_buf;
1750
1751         rx_agg->context = tp;
1752
1753         INIT_LIST_HEAD(&rx_agg->list);
1754         INIT_LIST_HEAD(&rx_agg->info_list);
1755         spin_lock_irqsave(&tp->rx_lock, flags);
1756         list_add_tail(&rx_agg->info_list, &tp->rx_info);
1757         spin_unlock_irqrestore(&tp->rx_lock, flags);
1758
1759         atomic_inc(&tp->rx_count);
1760
1761         return rx_agg;
1762
1763 free_buf:
1764         __free_pages(rx_agg->page, order);
1765 free_rx:
1766         kfree(rx_agg);
1767         return NULL;
1768 }
1769
1770 static void free_all_mem(struct r8152 *tp)
1771 {
1772         struct rx_agg *agg, *agg_next;
1773         unsigned long flags;
1774         int i;
1775
1776         spin_lock_irqsave(&tp->rx_lock, flags);
1777
1778         list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1779                 free_rx_agg(tp, agg);
1780
1781         spin_unlock_irqrestore(&tp->rx_lock, flags);
1782
1783         WARN_ON(atomic_read(&tp->rx_count));
1784
1785         for (i = 0; i < RTL8152_MAX_TX; i++) {
1786                 usb_free_urb(tp->tx_info[i].urb);
1787                 tp->tx_info[i].urb = NULL;
1788
1789                 kfree(tp->tx_info[i].buffer);
1790                 tp->tx_info[i].buffer = NULL;
1791                 tp->tx_info[i].head = NULL;
1792         }
1793
1794         usb_free_urb(tp->intr_urb);
1795         tp->intr_urb = NULL;
1796
1797         kfree(tp->intr_buff);
1798         tp->intr_buff = NULL;
1799 }
1800
1801 static int alloc_all_mem(struct r8152 *tp)
1802 {
1803         struct net_device *netdev = tp->netdev;
1804         struct usb_interface *intf = tp->intf;
1805         struct usb_host_interface *alt = intf->cur_altsetting;
1806         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1807         int node, i;
1808
1809         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1810
1811         spin_lock_init(&tp->rx_lock);
1812         spin_lock_init(&tp->tx_lock);
1813         INIT_LIST_HEAD(&tp->rx_info);
1814         INIT_LIST_HEAD(&tp->tx_free);
1815         INIT_LIST_HEAD(&tp->rx_done);
1816         skb_queue_head_init(&tp->tx_queue);
1817         skb_queue_head_init(&tp->rx_queue);
1818         atomic_set(&tp->rx_count, 0);
1819
1820         for (i = 0; i < RTL8152_MAX_RX; i++) {
1821                 if (!alloc_rx_agg(tp, GFP_KERNEL))
1822                         goto err1;
1823         }
1824
1825         for (i = 0; i < RTL8152_MAX_TX; i++) {
1826                 struct urb *urb;
1827                 u8 *buf;
1828
1829                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1830                 if (!buf)
1831                         goto err1;
1832
1833                 if (buf != tx_agg_align(buf)) {
1834                         kfree(buf);
1835                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1836                                            node);
1837                         if (!buf)
1838                                 goto err1;
1839                 }
1840
1841                 urb = usb_alloc_urb(0, GFP_KERNEL);
1842                 if (!urb) {
1843                         kfree(buf);
1844                         goto err1;
1845                 }
1846
1847                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1848                 tp->tx_info[i].context = tp;
1849                 tp->tx_info[i].urb = urb;
1850                 tp->tx_info[i].buffer = buf;
1851                 tp->tx_info[i].head = tx_agg_align(buf);
1852
1853                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1854         }
1855
1856         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1857         if (!tp->intr_urb)
1858                 goto err1;
1859
1860         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1861         if (!tp->intr_buff)
1862                 goto err1;
1863
1864         tp->intr_interval = (int)ep_intr->desc.bInterval;
1865         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1866                          tp->intr_buff, INTBUFSIZE, intr_callback,
1867                          tp, tp->intr_interval);
1868
1869         return 0;
1870
1871 err1:
1872         free_all_mem(tp);
1873         return -ENOMEM;
1874 }
1875
1876 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1877 {
1878         struct tx_agg *agg = NULL;
1879         unsigned long flags;
1880
1881         if (list_empty(&tp->tx_free))
1882                 return NULL;
1883
1884         spin_lock_irqsave(&tp->tx_lock, flags);
1885         if (!list_empty(&tp->tx_free)) {
1886                 struct list_head *cursor;
1887
1888                 cursor = tp->tx_free.next;
1889                 list_del_init(cursor);
1890                 agg = list_entry(cursor, struct tx_agg, list);
1891         }
1892         spin_unlock_irqrestore(&tp->tx_lock, flags);
1893
1894         return agg;
1895 }
1896
1897 /* r8152_csum_workaround()
1898  * The hw limits the value of the transport offset. When the offset is out of
1899  * range, calculate the checksum by sw.
1900  */
1901 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1902                                   struct sk_buff_head *list)
1903 {
1904         if (skb_shinfo(skb)->gso_size) {
1905                 netdev_features_t features = tp->netdev->features;
1906                 struct sk_buff *segs, *seg, *next;
1907                 struct sk_buff_head seg_list;
1908
1909                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1910                 segs = skb_gso_segment(skb, features);
1911                 if (IS_ERR(segs) || !segs)
1912                         goto drop;
1913
1914                 __skb_queue_head_init(&seg_list);
1915
1916                 skb_list_walk_safe(segs, seg, next) {
1917                         skb_mark_not_on_list(seg);
1918                         __skb_queue_tail(&seg_list, seg);
1919                 }
1920
1921                 skb_queue_splice(&seg_list, list);
1922                 dev_kfree_skb(skb);
1923         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1924                 if (skb_checksum_help(skb) < 0)
1925                         goto drop;
1926
1927                 __skb_queue_head(list, skb);
1928         } else {
1929                 struct net_device_stats *stats;
1930
1931 drop:
1932                 stats = &tp->netdev->stats;
1933                 stats->tx_dropped++;
1934                 dev_kfree_skb(skb);
1935         }
1936 }
1937
1938 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1939 {
1940         if (skb_vlan_tag_present(skb)) {
1941                 u32 opts2;
1942
1943                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1944                 desc->opts2 |= cpu_to_le32(opts2);
1945         }
1946 }
1947
1948 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1949 {
1950         u32 opts2 = le32_to_cpu(desc->opts2);
1951
1952         if (opts2 & RX_VLAN_TAG)
1953                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1954                                        swab16(opts2 & 0xffff));
1955 }
1956
1957 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1958                          struct sk_buff *skb, u32 len, u32 transport_offset)
1959 {
1960         u32 mss = skb_shinfo(skb)->gso_size;
1961         u32 opts1, opts2 = 0;
1962         int ret = TX_CSUM_SUCCESS;
1963
1964         WARN_ON_ONCE(len > TX_LEN_MAX);
1965
1966         opts1 = len | TX_FS | TX_LS;
1967
1968         if (mss) {
1969                 if (transport_offset > GTTCPHO_MAX) {
1970                         netif_warn(tp, tx_err, tp->netdev,
1971                                    "Invalid transport offset 0x%x for TSO\n",
1972                                    transport_offset);
1973                         ret = TX_CSUM_TSO;
1974                         goto unavailable;
1975                 }
1976
1977                 switch (vlan_get_protocol(skb)) {
1978                 case htons(ETH_P_IP):
1979                         opts1 |= GTSENDV4;
1980                         break;
1981
1982                 case htons(ETH_P_IPV6):
1983                         if (skb_cow_head(skb, 0)) {
1984                                 ret = TX_CSUM_TSO;
1985                                 goto unavailable;
1986                         }
1987                         tcp_v6_gso_csum_prep(skb);
1988                         opts1 |= GTSENDV6;
1989                         break;
1990
1991                 default:
1992                         WARN_ON_ONCE(1);
1993                         break;
1994                 }
1995
1996                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1997                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1998         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1999                 u8 ip_protocol;
2000
2001                 if (transport_offset > TCPHO_MAX) {
2002                         netif_warn(tp, tx_err, tp->netdev,
2003                                    "Invalid transport offset 0x%x\n",
2004                                    transport_offset);
2005                         ret = TX_CSUM_NONE;
2006                         goto unavailable;
2007                 }
2008
2009                 switch (vlan_get_protocol(skb)) {
2010                 case htons(ETH_P_IP):
2011                         opts2 |= IPV4_CS;
2012                         ip_protocol = ip_hdr(skb)->protocol;
2013                         break;
2014
2015                 case htons(ETH_P_IPV6):
2016                         opts2 |= IPV6_CS;
2017                         ip_protocol = ipv6_hdr(skb)->nexthdr;
2018                         break;
2019
2020                 default:
2021                         ip_protocol = IPPROTO_RAW;
2022                         break;
2023                 }
2024
2025                 if (ip_protocol == IPPROTO_TCP)
2026                         opts2 |= TCP_CS;
2027                 else if (ip_protocol == IPPROTO_UDP)
2028                         opts2 |= UDP_CS;
2029                 else
2030                         WARN_ON_ONCE(1);
2031
2032                 opts2 |= transport_offset << TCPHO_SHIFT;
2033         }
2034
2035         desc->opts2 = cpu_to_le32(opts2);
2036         desc->opts1 = cpu_to_le32(opts1);
2037
2038 unavailable:
2039         return ret;
2040 }
2041
2042 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2043 {
2044         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2045         int remain, ret;
2046         u8 *tx_data;
2047
2048         __skb_queue_head_init(&skb_head);
2049         spin_lock(&tx_queue->lock);
2050         skb_queue_splice_init(tx_queue, &skb_head);
2051         spin_unlock(&tx_queue->lock);
2052
2053         tx_data = agg->head;
2054         agg->skb_num = 0;
2055         agg->skb_len = 0;
2056         remain = agg_buf_sz;
2057
2058         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2059                 struct tx_desc *tx_desc;
2060                 struct sk_buff *skb;
2061                 unsigned int len;
2062                 u32 offset;
2063
2064                 skb = __skb_dequeue(&skb_head);
2065                 if (!skb)
2066                         break;
2067
2068                 len = skb->len + sizeof(*tx_desc);
2069
2070                 if (len > remain) {
2071                         __skb_queue_head(&skb_head, skb);
2072                         break;
2073                 }
2074
2075                 tx_data = tx_agg_align(tx_data);
2076                 tx_desc = (struct tx_desc *)tx_data;
2077
2078                 offset = (u32)skb_transport_offset(skb);
2079
2080                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2081                         r8152_csum_workaround(tp, skb, &skb_head);
2082                         continue;
2083                 }
2084
2085                 rtl_tx_vlan_tag(tx_desc, skb);
2086
2087                 tx_data += sizeof(*tx_desc);
2088
2089                 len = skb->len;
2090                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2091                         struct net_device_stats *stats = &tp->netdev->stats;
2092
2093                         stats->tx_dropped++;
2094                         dev_kfree_skb_any(skb);
2095                         tx_data -= sizeof(*tx_desc);
2096                         continue;
2097                 }
2098
2099                 tx_data += len;
2100                 agg->skb_len += len;
2101                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2102
2103                 dev_kfree_skb_any(skb);
2104
2105                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2106
2107                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2108                         break;
2109         }
2110
2111         if (!skb_queue_empty(&skb_head)) {
2112                 spin_lock(&tx_queue->lock);
2113                 skb_queue_splice(&skb_head, tx_queue);
2114                 spin_unlock(&tx_queue->lock);
2115         }
2116
2117         netif_tx_lock(tp->netdev);
2118
2119         if (netif_queue_stopped(tp->netdev) &&
2120             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2121                 netif_wake_queue(tp->netdev);
2122
2123         netif_tx_unlock(tp->netdev);
2124
2125         ret = usb_autopm_get_interface_async(tp->intf);
2126         if (ret < 0)
2127                 goto out_tx_fill;
2128
2129         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2130                           agg->head, (int)(tx_data - (u8 *)agg->head),
2131                           (usb_complete_t)write_bulk_callback, agg);
2132
2133         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2134         if (ret < 0)
2135                 usb_autopm_put_interface_async(tp->intf);
2136
2137 out_tx_fill:
2138         return ret;
2139 }
2140
2141 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2142 {
2143         u8 checksum = CHECKSUM_NONE;
2144         u32 opts2, opts3;
2145
2146         if (!(tp->netdev->features & NETIF_F_RXCSUM))
2147                 goto return_result;
2148
2149         opts2 = le32_to_cpu(rx_desc->opts2);
2150         opts3 = le32_to_cpu(rx_desc->opts3);
2151
2152         if (opts2 & RD_IPV4_CS) {
2153                 if (opts3 & IPF)
2154                         checksum = CHECKSUM_NONE;
2155                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2156                         checksum = CHECKSUM_UNNECESSARY;
2157                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2158                         checksum = CHECKSUM_UNNECESSARY;
2159         } else if (opts2 & RD_IPV6_CS) {
2160                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2161                         checksum = CHECKSUM_UNNECESSARY;
2162                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2163                         checksum = CHECKSUM_UNNECESSARY;
2164         }
2165
2166 return_result:
2167         return checksum;
2168 }
2169
2170 static inline bool rx_count_exceed(struct r8152 *tp)
2171 {
2172         return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2173 }
2174
2175 static inline int agg_offset(struct rx_agg *agg, void *addr)
2176 {
2177         return (int)(addr - agg->buffer);
2178 }
2179
2180 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2181 {
2182         struct rx_agg *agg, *agg_next, *agg_free = NULL;
2183         unsigned long flags;
2184
2185         spin_lock_irqsave(&tp->rx_lock, flags);
2186
2187         list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2188                 if (page_count(agg->page) == 1) {
2189                         if (!agg_free) {
2190                                 list_del_init(&agg->list);
2191                                 agg_free = agg;
2192                                 continue;
2193                         }
2194                         if (rx_count_exceed(tp)) {
2195                                 list_del_init(&agg->list);
2196                                 free_rx_agg(tp, agg);
2197                         }
2198                         break;
2199                 }
2200         }
2201
2202         spin_unlock_irqrestore(&tp->rx_lock, flags);
2203
2204         if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2205                 agg_free = alloc_rx_agg(tp, mflags);
2206
2207         return agg_free;
2208 }
2209
2210 static int rx_bottom(struct r8152 *tp, int budget)
2211 {
2212         unsigned long flags;
2213         struct list_head *cursor, *next, rx_queue;
2214         int ret = 0, work_done = 0;
2215         struct napi_struct *napi = &tp->napi;
2216
2217         if (!skb_queue_empty(&tp->rx_queue)) {
2218                 while (work_done < budget) {
2219                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2220                         struct net_device *netdev = tp->netdev;
2221                         struct net_device_stats *stats = &netdev->stats;
2222                         unsigned int pkt_len;
2223
2224                         if (!skb)
2225                                 break;
2226
2227                         pkt_len = skb->len;
2228                         napi_gro_receive(napi, skb);
2229                         work_done++;
2230                         stats->rx_packets++;
2231                         stats->rx_bytes += pkt_len;
2232                 }
2233         }
2234
2235         if (list_empty(&tp->rx_done))
2236                 goto out1;
2237
2238         INIT_LIST_HEAD(&rx_queue);
2239         spin_lock_irqsave(&tp->rx_lock, flags);
2240         list_splice_init(&tp->rx_done, &rx_queue);
2241         spin_unlock_irqrestore(&tp->rx_lock, flags);
2242
2243         list_for_each_safe(cursor, next, &rx_queue) {
2244                 struct rx_desc *rx_desc;
2245                 struct rx_agg *agg, *agg_free;
2246                 int len_used = 0;
2247                 struct urb *urb;
2248                 u8 *rx_data;
2249
2250                 list_del_init(cursor);
2251
2252                 agg = list_entry(cursor, struct rx_agg, list);
2253                 urb = agg->urb;
2254                 if (urb->actual_length < ETH_ZLEN)
2255                         goto submit;
2256
2257                 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2258
2259                 rx_desc = agg->buffer;
2260                 rx_data = agg->buffer;
2261                 len_used += sizeof(struct rx_desc);
2262
2263                 while (urb->actual_length > len_used) {
2264                         struct net_device *netdev = tp->netdev;
2265                         struct net_device_stats *stats = &netdev->stats;
2266                         unsigned int pkt_len, rx_frag_head_sz;
2267                         struct sk_buff *skb;
2268
2269                         /* limite the skb numbers for rx_queue */
2270                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2271                                 break;
2272
2273                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2274                         if (pkt_len < ETH_ZLEN)
2275                                 break;
2276
2277                         len_used += pkt_len;
2278                         if (urb->actual_length < len_used)
2279                                 break;
2280
2281                         pkt_len -= ETH_FCS_LEN;
2282                         rx_data += sizeof(struct rx_desc);
2283
2284                         if (!agg_free || tp->rx_copybreak > pkt_len)
2285                                 rx_frag_head_sz = pkt_len;
2286                         else
2287                                 rx_frag_head_sz = tp->rx_copybreak;
2288
2289                         skb = napi_alloc_skb(napi, rx_frag_head_sz);
2290                         if (!skb) {
2291                                 stats->rx_dropped++;
2292                                 goto find_next_rx;
2293                         }
2294
2295                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2296                         memcpy(skb->data, rx_data, rx_frag_head_sz);
2297                         skb_put(skb, rx_frag_head_sz);
2298                         pkt_len -= rx_frag_head_sz;
2299                         rx_data += rx_frag_head_sz;
2300                         if (pkt_len) {
2301                                 skb_add_rx_frag(skb, 0, agg->page,
2302                                                 agg_offset(agg, rx_data),
2303                                                 pkt_len,
2304                                                 SKB_DATA_ALIGN(pkt_len));
2305                                 get_page(agg->page);
2306                         }
2307
2308                         skb->protocol = eth_type_trans(skb, netdev);
2309                         rtl_rx_vlan_tag(rx_desc, skb);
2310                         if (work_done < budget) {
2311                                 work_done++;
2312                                 stats->rx_packets++;
2313                                 stats->rx_bytes += skb->len;
2314                                 napi_gro_receive(napi, skb);
2315                         } else {
2316                                 __skb_queue_tail(&tp->rx_queue, skb);
2317                         }
2318
2319 find_next_rx:
2320                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2321                         rx_desc = (struct rx_desc *)rx_data;
2322                         len_used = agg_offset(agg, rx_data);
2323                         len_used += sizeof(struct rx_desc);
2324                 }
2325
2326                 WARN_ON(!agg_free && page_count(agg->page) > 1);
2327
2328                 if (agg_free) {
2329                         spin_lock_irqsave(&tp->rx_lock, flags);
2330                         if (page_count(agg->page) == 1) {
2331                                 list_add(&agg_free->list, &tp->rx_used);
2332                         } else {
2333                                 list_add_tail(&agg->list, &tp->rx_used);
2334                                 agg = agg_free;
2335                                 urb = agg->urb;
2336                         }
2337                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2338                 }
2339
2340 submit:
2341                 if (!ret) {
2342                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2343                 } else {
2344                         urb->actual_length = 0;
2345                         list_add_tail(&agg->list, next);
2346                 }
2347         }
2348
2349         if (!list_empty(&rx_queue)) {
2350                 spin_lock_irqsave(&tp->rx_lock, flags);
2351                 list_splice_tail(&rx_queue, &tp->rx_done);
2352                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2353         }
2354
2355 out1:
2356         return work_done;
2357 }
2358
2359 static void tx_bottom(struct r8152 *tp)
2360 {
2361         int res;
2362
2363         do {
2364                 struct net_device *netdev = tp->netdev;
2365                 struct tx_agg *agg;
2366
2367                 if (skb_queue_empty(&tp->tx_queue))
2368                         break;
2369
2370                 agg = r8152_get_tx_agg(tp);
2371                 if (!agg)
2372                         break;
2373
2374                 res = r8152_tx_agg_fill(tp, agg);
2375                 if (!res)
2376                         continue;
2377
2378                 if (res == -ENODEV) {
2379                         rtl_set_unplug(tp);
2380                         netif_device_detach(netdev);
2381                 } else {
2382                         struct net_device_stats *stats = &netdev->stats;
2383                         unsigned long flags;
2384
2385                         netif_warn(tp, tx_err, netdev,
2386                                    "failed tx_urb %d\n", res);
2387                         stats->tx_dropped += agg->skb_num;
2388
2389                         spin_lock_irqsave(&tp->tx_lock, flags);
2390                         list_add_tail(&agg->list, &tp->tx_free);
2391                         spin_unlock_irqrestore(&tp->tx_lock, flags);
2392                 }
2393         } while (res == 0);
2394 }
2395
2396 static void bottom_half(struct tasklet_struct *t)
2397 {
2398         struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2399
2400         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2401                 return;
2402
2403         if (!test_bit(WORK_ENABLE, &tp->flags))
2404                 return;
2405
2406         /* When link down, the driver would cancel all bulks. */
2407         /* This avoid the re-submitting bulk */
2408         if (!netif_carrier_ok(tp->netdev))
2409                 return;
2410
2411         clear_bit(SCHEDULE_TASKLET, &tp->flags);
2412
2413         tx_bottom(tp);
2414 }
2415
2416 static int r8152_poll(struct napi_struct *napi, int budget)
2417 {
2418         struct r8152 *tp = container_of(napi, struct r8152, napi);
2419         int work_done;
2420
2421         work_done = rx_bottom(tp, budget);
2422
2423         if (work_done < budget) {
2424                 if (!napi_complete_done(napi, work_done))
2425                         goto out;
2426                 if (!list_empty(&tp->rx_done))
2427                         napi_schedule(napi);
2428         }
2429
2430 out:
2431         return work_done;
2432 }
2433
2434 static
2435 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2436 {
2437         int ret;
2438
2439         /* The rx would be stopped, so skip submitting */
2440         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2441             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2442                 return 0;
2443
2444         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2445                           agg->buffer, tp->rx_buf_sz,
2446                           (usb_complete_t)read_bulk_callback, agg);
2447
2448         ret = usb_submit_urb(agg->urb, mem_flags);
2449         if (ret == -ENODEV) {
2450                 rtl_set_unplug(tp);
2451                 netif_device_detach(tp->netdev);
2452         } else if (ret) {
2453                 struct urb *urb = agg->urb;
2454                 unsigned long flags;
2455
2456                 urb->actual_length = 0;
2457                 spin_lock_irqsave(&tp->rx_lock, flags);
2458                 list_add_tail(&agg->list, &tp->rx_done);
2459                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2460
2461                 netif_err(tp, rx_err, tp->netdev,
2462                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2463
2464                 napi_schedule(&tp->napi);
2465         }
2466
2467         return ret;
2468 }
2469
2470 static void rtl_drop_queued_tx(struct r8152 *tp)
2471 {
2472         struct net_device_stats *stats = &tp->netdev->stats;
2473         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2474         struct sk_buff *skb;
2475
2476         if (skb_queue_empty(tx_queue))
2477                 return;
2478
2479         __skb_queue_head_init(&skb_head);
2480         spin_lock_bh(&tx_queue->lock);
2481         skb_queue_splice_init(tx_queue, &skb_head);
2482         spin_unlock_bh(&tx_queue->lock);
2483
2484         while ((skb = __skb_dequeue(&skb_head))) {
2485                 dev_kfree_skb(skb);
2486                 stats->tx_dropped++;
2487         }
2488 }
2489
2490 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2491 {
2492         struct r8152 *tp = netdev_priv(netdev);
2493
2494         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2495
2496         usb_queue_reset_device(tp->intf);
2497 }
2498
2499 static void rtl8152_set_rx_mode(struct net_device *netdev)
2500 {
2501         struct r8152 *tp = netdev_priv(netdev);
2502
2503         if (netif_carrier_ok(netdev)) {
2504                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2505                 schedule_delayed_work(&tp->schedule, 0);
2506         }
2507 }
2508
2509 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2510 {
2511         struct r8152 *tp = netdev_priv(netdev);
2512         u32 mc_filter[2];       /* Multicast hash filter */
2513         __le32 tmp[2];
2514         u32 ocp_data;
2515
2516         netif_stop_queue(netdev);
2517         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2518         ocp_data &= ~RCR_ACPT_ALL;
2519         ocp_data |= RCR_AB | RCR_APM;
2520
2521         if (netdev->flags & IFF_PROMISC) {
2522                 /* Unconditionally log net taps. */
2523                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2524                 ocp_data |= RCR_AM | RCR_AAP;
2525                 mc_filter[1] = 0xffffffff;
2526                 mc_filter[0] = 0xffffffff;
2527         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2528                    (netdev->flags & IFF_ALLMULTI)) {
2529                 /* Too many to filter perfectly -- accept all multicasts. */
2530                 ocp_data |= RCR_AM;
2531                 mc_filter[1] = 0xffffffff;
2532                 mc_filter[0] = 0xffffffff;
2533         } else {
2534                 struct netdev_hw_addr *ha;
2535
2536                 mc_filter[1] = 0;
2537                 mc_filter[0] = 0;
2538                 netdev_for_each_mc_addr(ha, netdev) {
2539                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2540
2541                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2542                         ocp_data |= RCR_AM;
2543                 }
2544         }
2545
2546         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2547         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2548
2549         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2550         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2551         netif_wake_queue(netdev);
2552 }
2553
2554 static netdev_features_t
2555 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2556                        netdev_features_t features)
2557 {
2558         u32 mss = skb_shinfo(skb)->gso_size;
2559         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2560         int offset = skb_transport_offset(skb);
2561
2562         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2563                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2564         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2565                 features &= ~NETIF_F_GSO_MASK;
2566
2567         return features;
2568 }
2569
2570 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2571                                       struct net_device *netdev)
2572 {
2573         struct r8152 *tp = netdev_priv(netdev);
2574
2575         skb_tx_timestamp(skb);
2576
2577         skb_queue_tail(&tp->tx_queue, skb);
2578
2579         if (!list_empty(&tp->tx_free)) {
2580                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2581                         set_bit(SCHEDULE_TASKLET, &tp->flags);
2582                         schedule_delayed_work(&tp->schedule, 0);
2583                 } else {
2584                         usb_mark_last_busy(tp->udev);
2585                         tasklet_schedule(&tp->tx_tl);
2586                 }
2587         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2588                 netif_stop_queue(netdev);
2589         }
2590
2591         return NETDEV_TX_OK;
2592 }
2593
2594 static void r8152b_reset_packet_filter(struct r8152 *tp)
2595 {
2596         u32     ocp_data;
2597
2598         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2599         ocp_data &= ~FMC_FCR_MCU_EN;
2600         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2601         ocp_data |= FMC_FCR_MCU_EN;
2602         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2603 }
2604
2605 static void rtl8152_nic_reset(struct r8152 *tp)
2606 {
2607         int     i;
2608
2609         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2610
2611         for (i = 0; i < 1000; i++) {
2612                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2613                         break;
2614                 usleep_range(100, 400);
2615         }
2616 }
2617
2618 static void set_tx_qlen(struct r8152 *tp)
2619 {
2620         struct net_device *netdev = tp->netdev;
2621
2622         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2623                                     sizeof(struct tx_desc));
2624 }
2625
2626 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2627 {
2628         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2629 }
2630
2631 static void rtl_set_eee_plus(struct r8152 *tp)
2632 {
2633         u32 ocp_data;
2634         u8 speed;
2635
2636         speed = rtl8152_get_speed(tp);
2637         if (speed & _10bps) {
2638                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2639                 ocp_data |= EEEP_CR_EEEP_TX;
2640                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2641         } else {
2642                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2643                 ocp_data &= ~EEEP_CR_EEEP_TX;
2644                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2645         }
2646 }
2647
2648 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2649 {
2650         u32 ocp_data;
2651
2652         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2653         if (enable)
2654                 ocp_data |= RXDY_GATED_EN;
2655         else
2656                 ocp_data &= ~RXDY_GATED_EN;
2657         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2658 }
2659
2660 static int rtl_start_rx(struct r8152 *tp)
2661 {
2662         struct rx_agg *agg, *agg_next;
2663         struct list_head tmp_list;
2664         unsigned long flags;
2665         int ret = 0, i = 0;
2666
2667         INIT_LIST_HEAD(&tmp_list);
2668
2669         spin_lock_irqsave(&tp->rx_lock, flags);
2670
2671         INIT_LIST_HEAD(&tp->rx_done);
2672         INIT_LIST_HEAD(&tp->rx_used);
2673
2674         list_splice_init(&tp->rx_info, &tmp_list);
2675
2676         spin_unlock_irqrestore(&tp->rx_lock, flags);
2677
2678         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2679                 INIT_LIST_HEAD(&agg->list);
2680
2681                 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2682                 if (++i > RTL8152_MAX_RX) {
2683                         spin_lock_irqsave(&tp->rx_lock, flags);
2684                         list_add_tail(&agg->list, &tp->rx_used);
2685                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2686                 } else if (unlikely(ret < 0)) {
2687                         spin_lock_irqsave(&tp->rx_lock, flags);
2688                         list_add_tail(&agg->list, &tp->rx_done);
2689                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2690                 } else {
2691                         ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2692                 }
2693         }
2694
2695         spin_lock_irqsave(&tp->rx_lock, flags);
2696         WARN_ON(!list_empty(&tp->rx_info));
2697         list_splice(&tmp_list, &tp->rx_info);
2698         spin_unlock_irqrestore(&tp->rx_lock, flags);
2699
2700         return ret;
2701 }
2702
2703 static int rtl_stop_rx(struct r8152 *tp)
2704 {
2705         struct rx_agg *agg, *agg_next;
2706         struct list_head tmp_list;
2707         unsigned long flags;
2708
2709         INIT_LIST_HEAD(&tmp_list);
2710
2711         /* The usb_kill_urb() couldn't be used in atomic.
2712          * Therefore, move the list of rx_info to a tmp one.
2713          * Then, list_for_each_entry_safe could be used without
2714          * spin lock.
2715          */
2716
2717         spin_lock_irqsave(&tp->rx_lock, flags);
2718         list_splice_init(&tp->rx_info, &tmp_list);
2719         spin_unlock_irqrestore(&tp->rx_lock, flags);
2720
2721         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2722                 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2723                  * equal to 1, so the other ones could be freed safely.
2724                  */
2725                 if (page_count(agg->page) > 1)
2726                         free_rx_agg(tp, agg);
2727                 else
2728                         usb_kill_urb(agg->urb);
2729         }
2730
2731         /* Move back the list of temp to the rx_info */
2732         spin_lock_irqsave(&tp->rx_lock, flags);
2733         WARN_ON(!list_empty(&tp->rx_info));
2734         list_splice(&tmp_list, &tp->rx_info);
2735         spin_unlock_irqrestore(&tp->rx_lock, flags);
2736
2737         while (!skb_queue_empty(&tp->rx_queue))
2738                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2739
2740         return 0;
2741 }
2742
2743 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2744 {
2745         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2746                        OWN_UPDATE | OWN_CLEAR);
2747 }
2748
2749 static int rtl_enable(struct r8152 *tp)
2750 {
2751         u32 ocp_data;
2752
2753         r8152b_reset_packet_filter(tp);
2754
2755         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2756         ocp_data |= CR_RE | CR_TE;
2757         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2758
2759         switch (tp->version) {
2760         case RTL_VER_08:
2761         case RTL_VER_09:
2762                 r8153b_rx_agg_chg_indicate(tp);
2763                 break;
2764         default:
2765                 break;
2766         }
2767
2768         rxdy_gated_en(tp, false);
2769
2770         return 0;
2771 }
2772
2773 static int rtl8152_enable(struct r8152 *tp)
2774 {
2775         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2776                 return -ENODEV;
2777
2778         set_tx_qlen(tp);
2779         rtl_set_eee_plus(tp);
2780
2781         return rtl_enable(tp);
2782 }
2783
2784 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2785 {
2786         u32 ocp_data = tp->coalesce / 8;
2787
2788         switch (tp->version) {
2789         case RTL_VER_03:
2790         case RTL_VER_04:
2791         case RTL_VER_05:
2792         case RTL_VER_06:
2793                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2794                                ocp_data);
2795                 break;
2796
2797         case RTL_VER_08:
2798         case RTL_VER_09:
2799                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2800                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2801                  */
2802                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2803                                128 / 8);
2804                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2805                                ocp_data);
2806                 break;
2807
2808         default:
2809                 break;
2810         }
2811 }
2812
2813 static void r8153_set_rx_early_size(struct r8152 *tp)
2814 {
2815         u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2816
2817         switch (tp->version) {
2818         case RTL_VER_03:
2819         case RTL_VER_04:
2820         case RTL_VER_05:
2821         case RTL_VER_06:
2822                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2823                                ocp_data / 4);
2824                 break;
2825         case RTL_VER_08:
2826         case RTL_VER_09:
2827                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2828                                ocp_data / 8);
2829                 break;
2830         default:
2831                 WARN_ON_ONCE(1);
2832                 break;
2833         }
2834 }
2835
2836 static int rtl8153_enable(struct r8152 *tp)
2837 {
2838         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2839                 return -ENODEV;
2840
2841         set_tx_qlen(tp);
2842         rtl_set_eee_plus(tp);
2843         r8153_set_rx_early_timeout(tp);
2844         r8153_set_rx_early_size(tp);
2845
2846         if (tp->version == RTL_VER_09) {
2847                 u32 ocp_data;
2848
2849                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2850                 ocp_data &= ~FC_PATCH_TASK;
2851                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2852                 usleep_range(1000, 2000);
2853                 ocp_data |= FC_PATCH_TASK;
2854                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2855         }
2856
2857         return rtl_enable(tp);
2858 }
2859
2860 static void rtl_disable(struct r8152 *tp)
2861 {
2862         u32 ocp_data;
2863         int i;
2864
2865         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2866                 rtl_drop_queued_tx(tp);
2867                 return;
2868         }
2869
2870         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2871         ocp_data &= ~RCR_ACPT_ALL;
2872         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2873
2874         rtl_drop_queued_tx(tp);
2875
2876         for (i = 0; i < RTL8152_MAX_TX; i++)
2877                 usb_kill_urb(tp->tx_info[i].urb);
2878
2879         rxdy_gated_en(tp, true);
2880
2881         for (i = 0; i < 1000; i++) {
2882                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2883                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2884                         break;
2885                 usleep_range(1000, 2000);
2886         }
2887
2888         for (i = 0; i < 1000; i++) {
2889                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2890                         break;
2891                 usleep_range(1000, 2000);
2892         }
2893
2894         rtl_stop_rx(tp);
2895
2896         rtl8152_nic_reset(tp);
2897 }
2898
2899 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2900 {
2901         u32 ocp_data;
2902
2903         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2904         if (enable)
2905                 ocp_data |= POWER_CUT;
2906         else
2907                 ocp_data &= ~POWER_CUT;
2908         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2909
2910         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2911         ocp_data &= ~RESUME_INDICATE;
2912         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2913 }
2914
2915 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2916 {
2917         u32 ocp_data;
2918
2919         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2920         if (enable)
2921                 ocp_data |= CPCR_RX_VLAN;
2922         else
2923                 ocp_data &= ~CPCR_RX_VLAN;
2924         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2925 }
2926
2927 static int rtl8152_set_features(struct net_device *dev,
2928                                 netdev_features_t features)
2929 {
2930         netdev_features_t changed = features ^ dev->features;
2931         struct r8152 *tp = netdev_priv(dev);
2932         int ret;
2933
2934         ret = usb_autopm_get_interface(tp->intf);
2935         if (ret < 0)
2936                 goto out;
2937
2938         mutex_lock(&tp->control);
2939
2940         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2941                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2942                         rtl_rx_vlan_en(tp, true);
2943                 else
2944                         rtl_rx_vlan_en(tp, false);
2945         }
2946
2947         mutex_unlock(&tp->control);
2948
2949         usb_autopm_put_interface(tp->intf);
2950
2951 out:
2952         return ret;
2953 }
2954
2955 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2956
2957 static u32 __rtl_get_wol(struct r8152 *tp)
2958 {
2959         u32 ocp_data;
2960         u32 wolopts = 0;
2961
2962         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2963         if (ocp_data & LINK_ON_WAKE_EN)
2964                 wolopts |= WAKE_PHY;
2965
2966         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2967         if (ocp_data & UWF_EN)
2968                 wolopts |= WAKE_UCAST;
2969         if (ocp_data & BWF_EN)
2970                 wolopts |= WAKE_BCAST;
2971         if (ocp_data & MWF_EN)
2972                 wolopts |= WAKE_MCAST;
2973
2974         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2975         if (ocp_data & MAGIC_EN)
2976                 wolopts |= WAKE_MAGIC;
2977
2978         return wolopts;
2979 }
2980
2981 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2982 {
2983         u32 ocp_data;
2984
2985         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2986
2987         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2988         ocp_data &= ~LINK_ON_WAKE_EN;
2989         if (wolopts & WAKE_PHY)
2990                 ocp_data |= LINK_ON_WAKE_EN;
2991         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2992
2993         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2994         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2995         if (wolopts & WAKE_UCAST)
2996                 ocp_data |= UWF_EN;
2997         if (wolopts & WAKE_BCAST)
2998                 ocp_data |= BWF_EN;
2999         if (wolopts & WAKE_MCAST)
3000                 ocp_data |= MWF_EN;
3001         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3002
3003         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3004
3005         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3006         ocp_data &= ~MAGIC_EN;
3007         if (wolopts & WAKE_MAGIC)
3008                 ocp_data |= MAGIC_EN;
3009         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3010
3011         if (wolopts & WAKE_ANY)
3012                 device_set_wakeup_enable(&tp->udev->dev, true);
3013         else
3014                 device_set_wakeup_enable(&tp->udev->dev, false);
3015 }
3016
3017 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3018 {
3019         /* MAC clock speed down */
3020         if (enable) {
3021                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3022                                ALDPS_SPDWN_RATIO);
3023                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3024                                EEE_SPDWN_RATIO);
3025                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3026                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3027                                U1U2_SPDWN_EN | L1_SPDWN_EN);
3028                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3029                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3030                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3031                                TP1000_SPDWN_EN);
3032         } else {
3033                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3034                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3035                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3036                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3037         }
3038 }
3039
3040 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3041 {
3042         u8 u1u2[8];
3043
3044         if (enable)
3045                 memset(u1u2, 0xff, sizeof(u1u2));
3046         else
3047                 memset(u1u2, 0x00, sizeof(u1u2));
3048
3049         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3050 }
3051
3052 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3053 {
3054         u32 ocp_data;
3055
3056         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3057         if (enable)
3058                 ocp_data |= LPM_U1U2_EN;
3059         else
3060                 ocp_data &= ~LPM_U1U2_EN;
3061
3062         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3063 }
3064
3065 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3066 {
3067         u32 ocp_data;
3068
3069         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3070         if (enable)
3071                 ocp_data |= U2P3_ENABLE;
3072         else
3073                 ocp_data &= ~U2P3_ENABLE;
3074         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3075 }
3076
3077 static void r8153b_ups_flags(struct r8152 *tp)
3078 {
3079         u32 ups_flags = 0;
3080
3081         if (tp->ups_info.green)
3082                 ups_flags |= UPS_FLAGS_EN_GREEN;
3083
3084         if (tp->ups_info.aldps)
3085                 ups_flags |= UPS_FLAGS_EN_ALDPS;
3086
3087         if (tp->ups_info.eee)
3088                 ups_flags |= UPS_FLAGS_EN_EEE;
3089
3090         if (tp->ups_info.flow_control)
3091                 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3092
3093         if (tp->ups_info.eee_ckdiv)
3094                 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3095
3096         if (tp->ups_info.eee_cmod_lv)
3097                 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3098
3099         if (tp->ups_info._10m_ckdiv)
3100                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3101
3102         if (tp->ups_info.eee_plloff_100)
3103                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3104
3105         if (tp->ups_info.eee_plloff_giga)
3106                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3107
3108         if (tp->ups_info._250m_ckdiv)
3109                 ups_flags |= UPS_FLAGS_250M_CKDIV;
3110
3111         if (tp->ups_info.ctap_short_off)
3112                 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3113
3114         switch (tp->ups_info.speed_duplex) {
3115         case NWAY_10M_HALF:
3116                 ups_flags |= ups_flags_speed(1);
3117                 break;
3118         case NWAY_10M_FULL:
3119                 ups_flags |= ups_flags_speed(2);
3120                 break;
3121         case NWAY_100M_HALF:
3122                 ups_flags |= ups_flags_speed(3);
3123                 break;
3124         case NWAY_100M_FULL:
3125                 ups_flags |= ups_flags_speed(4);
3126                 break;
3127         case NWAY_1000M_FULL:
3128                 ups_flags |= ups_flags_speed(5);
3129                 break;
3130         case FORCE_10M_HALF:
3131                 ups_flags |= ups_flags_speed(6);
3132                 break;
3133         case FORCE_10M_FULL:
3134                 ups_flags |= ups_flags_speed(7);
3135                 break;
3136         case FORCE_100M_HALF:
3137                 ups_flags |= ups_flags_speed(8);
3138                 break;
3139         case FORCE_100M_FULL:
3140                 ups_flags |= ups_flags_speed(9);
3141                 break;
3142         default:
3143                 break;
3144         }
3145
3146         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3147 }
3148
3149 static void r8153b_green_en(struct r8152 *tp, bool enable)
3150 {
3151         u16 data;
3152
3153         if (enable) {
3154                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
3155                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3156                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3157         } else {
3158                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3159                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3160                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3161         }
3162
3163         data = sram_read(tp, SRAM_GREEN_CFG);
3164         data |= GREEN_ETH_EN;
3165         sram_write(tp, SRAM_GREEN_CFG, data);
3166
3167         tp->ups_info.green = enable;
3168 }
3169
3170 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3171 {
3172         u16 data;
3173         int i;
3174
3175         for (i = 0; i < 500; i++) {
3176                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3177                 data &= PHY_STAT_MASK;
3178                 if (desired) {
3179                         if (data == desired)
3180                                 break;
3181                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3182                            data == PHY_STAT_EXT_INIT) {
3183                         break;
3184                 }
3185
3186                 msleep(20);
3187                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3188                         break;
3189         }
3190
3191         return data;
3192 }
3193
3194 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3195 {
3196         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3197
3198         if (enable) {
3199                 r8153b_ups_flags(tp);
3200
3201                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3202                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3203
3204                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3205                 ocp_data |= BIT(0);
3206                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3207         } else {
3208                 u16 data;
3209
3210                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3211                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3212
3213                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3214                 ocp_data &= ~BIT(0);
3215                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3216
3217                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3218                 ocp_data &= ~PCUT_STATUS;
3219                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3220
3221                 data = r8153_phy_status(tp, 0);
3222
3223                 switch (data) {
3224                 case PHY_STAT_PWRDN:
3225                 case PHY_STAT_EXT_INIT:
3226                         r8153b_green_en(tp,
3227                                         test_bit(GREEN_ETHERNET, &tp->flags));
3228
3229                         data = r8152_mdio_read(tp, MII_BMCR);
3230                         data &= ~BMCR_PDOWN;
3231                         data |= BMCR_RESET;
3232                         r8152_mdio_write(tp, MII_BMCR, data);
3233
3234                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3235                         fallthrough;
3236
3237                 default:
3238                         if (data != PHY_STAT_LAN_ON)
3239                                 netif_warn(tp, link, tp->netdev,
3240                                            "PHY not ready");
3241                         break;
3242                 }
3243         }
3244 }
3245
3246 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3247 {
3248         u32 ocp_data;
3249
3250         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3251         if (enable)
3252                 ocp_data |= PWR_EN | PHASE2_EN;
3253         else
3254                 ocp_data &= ~(PWR_EN | PHASE2_EN);
3255         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3256
3257         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3258         ocp_data &= ~PCUT_STATUS;
3259         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3260 }
3261
3262 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3263 {
3264         u32 ocp_data;
3265
3266         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3267         if (enable)
3268                 ocp_data |= PWR_EN | PHASE2_EN;
3269         else
3270                 ocp_data &= ~PWR_EN;
3271         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3272
3273         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3274         ocp_data &= ~PCUT_STATUS;
3275         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3276 }
3277
3278 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3279 {
3280         u32 ocp_data;
3281
3282         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3283         if (enable)
3284                 ocp_data |= UPCOMING_RUNTIME_D3;
3285         else
3286                 ocp_data &= ~UPCOMING_RUNTIME_D3;
3287         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3288
3289         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3290         ocp_data &= ~LINK_CHG_EVENT;
3291         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3292
3293         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3294         ocp_data &= ~LINK_CHANGE_FLAG;
3295         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3296 }
3297
3298 static bool rtl_can_wakeup(struct r8152 *tp)
3299 {
3300         struct usb_device *udev = tp->udev;
3301
3302         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3303 }
3304
3305 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3306 {
3307         if (enable) {
3308                 u32 ocp_data;
3309
3310                 __rtl_set_wol(tp, WAKE_ANY);
3311
3312                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3313
3314                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3315                 ocp_data |= LINK_OFF_WAKE_EN;
3316                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3317
3318                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3319         } else {
3320                 u32 ocp_data;
3321
3322                 __rtl_set_wol(tp, tp->saved_wolopts);
3323
3324                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3325
3326                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3327                 ocp_data &= ~LINK_OFF_WAKE_EN;
3328                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3329
3330                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3331         }
3332 }
3333
3334 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3335 {
3336         if (enable) {
3337                 r8153_u1u2en(tp, false);
3338                 r8153_u2p3en(tp, false);
3339                 r8153_mac_clk_spd(tp, true);
3340                 rtl_runtime_suspend_enable(tp, true);
3341         } else {
3342                 rtl_runtime_suspend_enable(tp, false);
3343                 r8153_mac_clk_spd(tp, false);
3344
3345                 switch (tp->version) {
3346                 case RTL_VER_03:
3347                 case RTL_VER_04:
3348                         break;
3349                 case RTL_VER_05:
3350                 case RTL_VER_06:
3351                 default:
3352                         r8153_u2p3en(tp, true);
3353                         break;
3354                 }
3355
3356                 r8153_u1u2en(tp, true);
3357         }
3358 }
3359
3360 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3361 {
3362         if (enable) {
3363                 r8153_queue_wake(tp, true);
3364                 r8153b_u1u2en(tp, false);
3365                 r8153_u2p3en(tp, false);
3366                 rtl_runtime_suspend_enable(tp, true);
3367                 r8153b_ups_en(tp, true);
3368         } else {
3369                 r8153b_ups_en(tp, false);
3370                 r8153_queue_wake(tp, false);
3371                 rtl_runtime_suspend_enable(tp, false);
3372                 if (tp->udev->speed != USB_SPEED_HIGH)
3373                         r8153b_u1u2en(tp, true);
3374         }
3375 }
3376
3377 static void r8153_teredo_off(struct r8152 *tp)
3378 {
3379         u32 ocp_data;
3380
3381         switch (tp->version) {
3382         case RTL_VER_01:
3383         case RTL_VER_02:
3384         case RTL_VER_03:
3385         case RTL_VER_04:
3386         case RTL_VER_05:
3387         case RTL_VER_06:
3388         case RTL_VER_07:
3389                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3390                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3391                               OOB_TEREDO_EN);
3392                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3393                 break;
3394
3395         case RTL_VER_08:
3396         case RTL_VER_09:
3397                 /* The bit 0 ~ 7 are relative with teredo settings. They are
3398                  * W1C (write 1 to clear), so set all 1 to disable it.
3399                  */
3400                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3401                 break;
3402
3403         default:
3404                 break;
3405         }
3406
3407         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3408         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3409         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3410 }
3411
3412 static void rtl_reset_bmu(struct r8152 *tp)
3413 {
3414         u32 ocp_data;
3415
3416         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3417         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3418         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3419         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3420         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3421 }
3422
3423 /* Clear the bp to stop the firmware before loading a new one */
3424 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3425 {
3426         switch (tp->version) {
3427         case RTL_VER_01:
3428         case RTL_VER_02:
3429         case RTL_VER_07:
3430                 break;
3431         case RTL_VER_03:
3432         case RTL_VER_04:
3433         case RTL_VER_05:
3434         case RTL_VER_06:
3435                 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3436                 break;
3437         case RTL_VER_08:
3438         case RTL_VER_09:
3439         default:
3440                 if (type == MCU_TYPE_USB) {
3441                         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3442
3443                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3444                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3445                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3446                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3447                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3448                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3449                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3450                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3451                 } else {
3452                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3453                 }
3454                 break;
3455         }
3456
3457         ocp_write_word(tp, type, PLA_BP_0, 0);
3458         ocp_write_word(tp, type, PLA_BP_1, 0);
3459         ocp_write_word(tp, type, PLA_BP_2, 0);
3460         ocp_write_word(tp, type, PLA_BP_3, 0);
3461         ocp_write_word(tp, type, PLA_BP_4, 0);
3462         ocp_write_word(tp, type, PLA_BP_5, 0);
3463         ocp_write_word(tp, type, PLA_BP_6, 0);
3464         ocp_write_word(tp, type, PLA_BP_7, 0);
3465
3466         /* wait 3 ms to make sure the firmware is stopped */
3467         usleep_range(3000, 6000);
3468         ocp_write_word(tp, type, PLA_BP_BA, 0);
3469 }
3470
3471 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
3472 {
3473         u16 data, check;
3474         int i;
3475
3476         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3477         if (request) {
3478                 data |= PATCH_REQUEST;
3479                 check = 0;
3480         } else {
3481                 data &= ~PATCH_REQUEST;
3482                 check = PATCH_READY;
3483         }
3484         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3485
3486         for (i = 0; wait && i < 5000; i++) {
3487                 u32 ocp_data;
3488
3489                 usleep_range(1000, 2000);
3490                 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
3491                 if ((ocp_data & PATCH_READY) ^ check)
3492                         break;
3493         }
3494
3495         if (request && wait &&
3496             !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3497                 dev_err(&tp->intf->dev, "PHY patch request fail\n");
3498                 rtl_phy_patch_request(tp, false, false);
3499                 return -ETIME;
3500         } else {
3501                 return 0;
3502         }
3503 }
3504
3505 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
3506 {
3507         if (patch_key && key_addr) {
3508                 sram_write(tp, key_addr, patch_key);
3509                 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3510         } else if (key_addr) {
3511                 u16 data;
3512
3513                 sram_write(tp, 0x0000, 0x0000);
3514
3515                 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3516                 data &= ~PATCH_LOCK;
3517                 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3518
3519                 sram_write(tp, key_addr, 0x0000);
3520         } else {
3521                 WARN_ON_ONCE(1);
3522         }
3523 }
3524
3525 static int
3526 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
3527 {
3528         if (rtl_phy_patch_request(tp, true, wait))
3529                 return -ETIME;
3530
3531         rtl_patch_key_set(tp, key_addr, patch_key);
3532
3533         return 0;
3534 }
3535
3536 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
3537 {
3538         rtl_patch_key_set(tp, key_addr, 0);
3539
3540         rtl_phy_patch_request(tp, false, wait);
3541
3542         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3543
3544         return 0;
3545 }
3546
3547 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3548 {
3549         u32 length;
3550         u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3551         bool rc = false;
3552
3553         switch (tp->version) {
3554         case RTL_VER_04:
3555         case RTL_VER_05:
3556         case RTL_VER_06:
3557                 fw_reg = 0xa014;
3558                 ba_reg = 0xa012;
3559                 patch_en_addr = 0xa01a;
3560                 mode_reg = 0xb820;
3561                 bp_start = 0xa000;
3562                 break;
3563         default:
3564                 goto out;
3565         }
3566
3567         fw_offset = __le16_to_cpu(phy->fw_offset);
3568         if (fw_offset < sizeof(*phy)) {
3569                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3570                 goto out;
3571         }
3572
3573         length = __le32_to_cpu(phy->blk_hdr.length);
3574         if (length < fw_offset) {
3575                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3576                 goto out;
3577         }
3578
3579         length -= __le16_to_cpu(phy->fw_offset);
3580         if (!length || (length & 1)) {
3581                 dev_err(&tp->intf->dev, "invalid block length\n");
3582                 goto out;
3583         }
3584
3585         if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3586                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3587                 goto out;
3588         }
3589
3590         if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3591                 dev_err(&tp->intf->dev, "invalid base address register\n");
3592                 goto out;
3593         }
3594
3595         if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3596                 dev_err(&tp->intf->dev,
3597                         "invalid patch mode enabled register\n");
3598                 goto out;
3599         }
3600
3601         if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3602                 dev_err(&tp->intf->dev,
3603                         "invalid register to switch the mode\n");
3604                 goto out;
3605         }
3606
3607         if (__le16_to_cpu(phy->bp_start) != bp_start) {
3608                 dev_err(&tp->intf->dev,
3609                         "invalid start register of break point\n");
3610                 goto out;
3611         }
3612
3613         if (__le16_to_cpu(phy->bp_num) > 4) {
3614                 dev_err(&tp->intf->dev, "invalid break point number\n");
3615                 goto out;
3616         }
3617
3618         rc = true;
3619 out:
3620         return rc;
3621 }
3622
3623 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3624 {
3625         u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3626         bool rc = false;
3627         u32 length, type;
3628         int i, max_bp;
3629
3630         type = __le32_to_cpu(mac->blk_hdr.type);
3631         if (type == RTL_FW_PLA) {
3632                 switch (tp->version) {
3633                 case RTL_VER_01:
3634                 case RTL_VER_02:
3635                 case RTL_VER_07:
3636                         fw_reg = 0xf800;
3637                         bp_ba_addr = PLA_BP_BA;
3638                         bp_en_addr = 0;
3639                         bp_start = PLA_BP_0;
3640                         max_bp = 8;
3641                         break;
3642                 case RTL_VER_03:
3643                 case RTL_VER_04:
3644                 case RTL_VER_05:
3645                 case RTL_VER_06:
3646                 case RTL_VER_08:
3647                 case RTL_VER_09:
3648                         fw_reg = 0xf800;
3649                         bp_ba_addr = PLA_BP_BA;
3650                         bp_en_addr = PLA_BP_EN;
3651                         bp_start = PLA_BP_0;
3652                         max_bp = 8;
3653                         break;
3654                 default:
3655                         goto out;
3656                 }
3657         } else if (type == RTL_FW_USB) {
3658                 switch (tp->version) {
3659                 case RTL_VER_03:
3660                 case RTL_VER_04:
3661                 case RTL_VER_05:
3662                 case RTL_VER_06:
3663                         fw_reg = 0xf800;
3664                         bp_ba_addr = USB_BP_BA;
3665                         bp_en_addr = USB_BP_EN;
3666                         bp_start = USB_BP_0;
3667                         max_bp = 8;
3668                         break;
3669                 case RTL_VER_08:
3670                 case RTL_VER_09:
3671                         fw_reg = 0xe600;
3672                         bp_ba_addr = USB_BP_BA;
3673                         bp_en_addr = USB_BP2_EN;
3674                         bp_start = USB_BP_0;
3675                         max_bp = 16;
3676                         break;
3677                 case RTL_VER_01:
3678                 case RTL_VER_02:
3679                 case RTL_VER_07:
3680                 default:
3681                         goto out;
3682                 }
3683         } else {
3684                 goto out;
3685         }
3686
3687         fw_offset = __le16_to_cpu(mac->fw_offset);
3688         if (fw_offset < sizeof(*mac)) {
3689                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3690                 goto out;
3691         }
3692
3693         length = __le32_to_cpu(mac->blk_hdr.length);
3694         if (length < fw_offset) {
3695                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3696                 goto out;
3697         }
3698
3699         length -= fw_offset;
3700         if (length < 4 || (length & 3)) {
3701                 dev_err(&tp->intf->dev, "invalid block length\n");
3702                 goto out;
3703         }
3704
3705         if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3706                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3707                 goto out;
3708         }
3709
3710         if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3711                 dev_err(&tp->intf->dev, "invalid base address register\n");
3712                 goto out;
3713         }
3714
3715         if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3716                 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3717                 goto out;
3718         }
3719
3720         if (__le16_to_cpu(mac->bp_start) != bp_start) {
3721                 dev_err(&tp->intf->dev,
3722                         "invalid start register of break point\n");
3723                 goto out;
3724         }
3725
3726         if (__le16_to_cpu(mac->bp_num) > max_bp) {
3727                 dev_err(&tp->intf->dev, "invalid break point number\n");
3728                 goto out;
3729         }
3730
3731         for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3732                 if (mac->bp[i]) {
3733                         dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3734                         goto out;
3735                 }
3736         }
3737
3738         rc = true;
3739 out:
3740         return rc;
3741 }
3742
3743 /* Verify the checksum for the firmware file. It is calculated from the version
3744  * field to the end of the file. Compare the result with the checksum field to
3745  * make sure the file is correct.
3746  */
3747 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3748                                        struct fw_header *fw_hdr, size_t size)
3749 {
3750         unsigned char checksum[sizeof(fw_hdr->checksum)];
3751         struct crypto_shash *alg;
3752         struct shash_desc *sdesc;
3753         size_t len;
3754         long rc;
3755
3756         alg = crypto_alloc_shash("sha256", 0, 0);
3757         if (IS_ERR(alg)) {
3758                 rc = PTR_ERR(alg);
3759                 goto out;
3760         }
3761
3762         if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3763                 rc = -EFAULT;
3764                 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3765                         crypto_shash_digestsize(alg));
3766                 goto free_shash;
3767         }
3768
3769         len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3770         sdesc = kmalloc(len, GFP_KERNEL);
3771         if (!sdesc) {
3772                 rc = -ENOMEM;
3773                 goto free_shash;
3774         }
3775         sdesc->tfm = alg;
3776
3777         len = size - sizeof(fw_hdr->checksum);
3778         rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3779         kfree(sdesc);
3780         if (rc)
3781                 goto free_shash;
3782
3783         if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3784                 dev_err(&tp->intf->dev, "checksum fail\n");
3785                 rc = -EFAULT;
3786         }
3787
3788 free_shash:
3789         crypto_free_shash(alg);
3790 out:
3791         return rc;
3792 }
3793
3794 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3795 {
3796         const struct firmware *fw = rtl_fw->fw;
3797         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3798         struct fw_mac *pla = NULL, *usb = NULL;
3799         struct fw_phy_patch_key *start = NULL;
3800         struct fw_phy_nc *phy_nc = NULL;
3801         struct fw_block *stop = NULL;
3802         long ret = -EFAULT;
3803         int i;
3804
3805         if (fw->size < sizeof(*fw_hdr)) {
3806                 dev_err(&tp->intf->dev, "file too small\n");
3807                 goto fail;
3808         }
3809
3810         ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3811         if (ret)
3812                 goto fail;
3813
3814         ret = -EFAULT;
3815
3816         for (i = sizeof(*fw_hdr); i < fw->size;) {
3817                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3818                 u32 type;
3819
3820                 if ((i + sizeof(*block)) > fw->size)
3821                         goto fail;
3822
3823                 type = __le32_to_cpu(block->type);
3824                 switch (type) {
3825                 case RTL_FW_END:
3826                         if (__le32_to_cpu(block->length) != sizeof(*block))
3827                                 goto fail;
3828                         goto fw_end;
3829                 case RTL_FW_PLA:
3830                         if (pla) {
3831                                 dev_err(&tp->intf->dev,
3832                                         "multiple PLA firmware encountered");
3833                                 goto fail;
3834                         }
3835
3836                         pla = (struct fw_mac *)block;
3837                         if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3838                                 dev_err(&tp->intf->dev,
3839                                         "check PLA firmware failed\n");
3840                                 goto fail;
3841                         }
3842                         break;
3843                 case RTL_FW_USB:
3844                         if (usb) {
3845                                 dev_err(&tp->intf->dev,
3846                                         "multiple USB firmware encountered");
3847                                 goto fail;
3848                         }
3849
3850                         usb = (struct fw_mac *)block;
3851                         if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3852                                 dev_err(&tp->intf->dev,
3853                                         "check USB firmware failed\n");
3854                                 goto fail;
3855                         }
3856                         break;
3857                 case RTL_FW_PHY_START:
3858                         if (start || phy_nc || stop) {
3859                                 dev_err(&tp->intf->dev,
3860                                         "check PHY_START fail\n");
3861                                 goto fail;
3862                         }
3863
3864                         if (__le32_to_cpu(block->length) != sizeof(*start)) {
3865                                 dev_err(&tp->intf->dev,
3866                                         "Invalid length for PHY_START\n");
3867                                 goto fail;
3868                         }
3869
3870                         start = (struct fw_phy_patch_key *)block;
3871                         break;
3872                 case RTL_FW_PHY_STOP:
3873                         if (stop || !start) {
3874                                 dev_err(&tp->intf->dev,
3875                                         "Check PHY_STOP fail\n");
3876                                 goto fail;
3877                         }
3878
3879                         if (__le32_to_cpu(block->length) != sizeof(*block)) {
3880                                 dev_err(&tp->intf->dev,
3881                                         "Invalid length for PHY_STOP\n");
3882                                 goto fail;
3883                         }
3884
3885                         stop = block;
3886                         break;
3887                 case RTL_FW_PHY_NC:
3888                         if (!start || stop) {
3889                                 dev_err(&tp->intf->dev,
3890                                         "check PHY_NC fail\n");
3891                                 goto fail;
3892                         }
3893
3894                         if (phy_nc) {
3895                                 dev_err(&tp->intf->dev,
3896                                         "multiple PHY NC encountered\n");
3897                                 goto fail;
3898                         }
3899
3900                         phy_nc = (struct fw_phy_nc *)block;
3901                         if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3902                                 dev_err(&tp->intf->dev,
3903                                         "check PHY NC firmware failed\n");
3904                                 goto fail;
3905                         }
3906
3907                         break;
3908                 default:
3909                         dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3910                                  type);
3911                         break;
3912                 }
3913
3914                 /* next block */
3915                 i += ALIGN(__le32_to_cpu(block->length), 8);
3916         }
3917
3918 fw_end:
3919         if ((phy_nc || start) && !stop) {
3920                 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3921                 goto fail;
3922         }
3923
3924         return 0;
3925 fail:
3926         return ret;
3927 }
3928
3929 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3930 {
3931         u16 mode_reg, bp_index;
3932         u32 length, i, num;
3933         __le16 *data;
3934
3935         mode_reg = __le16_to_cpu(phy->mode_reg);
3936         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3937         sram_write(tp, __le16_to_cpu(phy->ba_reg),
3938                    __le16_to_cpu(phy->ba_data));
3939
3940         length = __le32_to_cpu(phy->blk_hdr.length);
3941         length -= __le16_to_cpu(phy->fw_offset);
3942         num = length / 2;
3943         data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3944
3945         ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3946         for (i = 0; i < num; i++)
3947                 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3948
3949         sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3950                    __le16_to_cpu(phy->patch_en_value));
3951
3952         bp_index = __le16_to_cpu(phy->bp_start);
3953         num = __le16_to_cpu(phy->bp_num);
3954         for (i = 0; i < num; i++) {
3955                 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3956                 bp_index += 2;
3957         }
3958
3959         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3960
3961         dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3962 }
3963
3964 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3965 {
3966         u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3967         u32 length;
3968         u8 *data;
3969         int i;
3970
3971         switch (__le32_to_cpu(mac->blk_hdr.type)) {
3972         case RTL_FW_PLA:
3973                 type = MCU_TYPE_PLA;
3974                 break;
3975         case RTL_FW_USB:
3976                 type = MCU_TYPE_USB;
3977                 break;
3978         default:
3979                 return;
3980         }
3981
3982         rtl_clear_bp(tp, type);
3983
3984         /* Enable backup/restore of MACDBG. This is required after clearing PLA
3985          * break points and before applying the PLA firmware.
3986          */
3987         if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3988             !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3989                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3990                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3991         }
3992
3993         length = __le32_to_cpu(mac->blk_hdr.length);
3994         length -= __le16_to_cpu(mac->fw_offset);
3995
3996         data = (u8 *)mac;
3997         data += __le16_to_cpu(mac->fw_offset);
3998
3999         generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
4000                           type);
4001
4002         ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
4003                        __le16_to_cpu(mac->bp_ba_value));
4004
4005         bp_index = __le16_to_cpu(mac->bp_start);
4006         bp_num = __le16_to_cpu(mac->bp_num);
4007         for (i = 0; i < bp_num; i++) {
4008                 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
4009                 bp_index += 2;
4010         }
4011
4012         bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
4013         if (bp_en_addr)
4014                 ocp_write_word(tp, type, bp_en_addr,
4015                                __le16_to_cpu(mac->bp_en_value));
4016
4017         fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4018         if (fw_ver_reg)
4019                 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4020                                mac->fw_ver_data);
4021
4022         dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4023 }
4024
4025 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
4026 {
4027         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4028         const struct firmware *fw;
4029         struct fw_header *fw_hdr;
4030         struct fw_phy_patch_key *key;
4031         u16 key_addr = 0;
4032         int i;
4033
4034         if (IS_ERR_OR_NULL(rtl_fw->fw))
4035                 return;
4036
4037         fw = rtl_fw->fw;
4038         fw_hdr = (struct fw_header *)fw->data;
4039
4040         if (rtl_fw->pre_fw)
4041                 rtl_fw->pre_fw(tp);
4042
4043         for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4044                 struct fw_block *block = (struct fw_block *)&fw->data[i];
4045
4046                 switch (__le32_to_cpu(block->type)) {
4047                 case RTL_FW_END:
4048                         goto post_fw;
4049                 case RTL_FW_PLA:
4050                 case RTL_FW_USB:
4051                         rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4052                         break;
4053                 case RTL_FW_PHY_START:
4054                         key = (struct fw_phy_patch_key *)block;
4055                         key_addr = __le16_to_cpu(key->key_reg);
4056                         rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
4057                         break;
4058                 case RTL_FW_PHY_STOP:
4059                         WARN_ON(!key_addr);
4060                         rtl_post_ram_code(tp, key_addr, !power_cut);
4061                         break;
4062                 case RTL_FW_PHY_NC:
4063                         rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4064                         break;
4065                 default:
4066                         break;
4067                 }
4068
4069                 i += ALIGN(__le32_to_cpu(block->length), 8);
4070         }
4071
4072 post_fw:
4073         if (rtl_fw->post_fw)
4074                 rtl_fw->post_fw(tp);
4075
4076         strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4077         dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4078 }
4079
4080 static void rtl8152_release_firmware(struct r8152 *tp)
4081 {
4082         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4083
4084         if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4085                 release_firmware(rtl_fw->fw);
4086                 rtl_fw->fw = NULL;
4087         }
4088 }
4089
4090 static int rtl8152_request_firmware(struct r8152 *tp)
4091 {
4092         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4093         long rc;
4094
4095         if (rtl_fw->fw || !rtl_fw->fw_name) {
4096                 dev_info(&tp->intf->dev, "skip request firmware\n");
4097                 rc = 0;
4098                 goto result;
4099         }
4100
4101         rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4102         if (rc < 0)
4103                 goto result;
4104
4105         rc = rtl8152_check_firmware(tp, rtl_fw);
4106         if (rc < 0)
4107                 release_firmware(rtl_fw->fw);
4108
4109 result:
4110         if (rc) {
4111                 rtl_fw->fw = ERR_PTR(rc);
4112
4113                 dev_warn(&tp->intf->dev,
4114                          "unable to load firmware patch %s (%ld)\n",
4115                          rtl_fw->fw_name, rc);
4116         }
4117
4118         return rc;
4119 }
4120
4121 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4122 {
4123         if (enable) {
4124                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4125                                                     LINKENA | DIS_SDSAVE);
4126         } else {
4127                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4128                                                     DIS_SDSAVE);
4129                 msleep(20);
4130         }
4131 }
4132
4133 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4134 {
4135         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4136         ocp_reg_write(tp, OCP_EEE_DATA, reg);
4137         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4138 }
4139
4140 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4141 {
4142         u16 data;
4143
4144         r8152_mmd_indirect(tp, dev, reg);
4145         data = ocp_reg_read(tp, OCP_EEE_DATA);
4146         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4147
4148         return data;
4149 }
4150
4151 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4152 {
4153         r8152_mmd_indirect(tp, dev, reg);
4154         ocp_reg_write(tp, OCP_EEE_DATA, data);
4155         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4156 }
4157
4158 static void r8152_eee_en(struct r8152 *tp, bool enable)
4159 {
4160         u16 config1, config2, config3;
4161         u32 ocp_data;
4162
4163         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4164         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4165         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4166         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4167
4168         if (enable) {
4169                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4170                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4171                 config1 |= sd_rise_time(1);
4172                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4173                 config3 |= fast_snr(42);
4174         } else {
4175                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4176                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4177                              RX_QUIET_EN);
4178                 config1 |= sd_rise_time(7);
4179                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4180                 config3 |= fast_snr(511);
4181         }
4182
4183         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4184         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4185         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4186         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4187 }
4188
4189 static void r8153_eee_en(struct r8152 *tp, bool enable)
4190 {
4191         u32 ocp_data;
4192         u16 config;
4193
4194         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4195         config = ocp_reg_read(tp, OCP_EEE_CFG);
4196
4197         if (enable) {
4198                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4199                 config |= EEE10_EN;
4200         } else {
4201                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4202                 config &= ~EEE10_EN;
4203         }
4204
4205         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4206         ocp_reg_write(tp, OCP_EEE_CFG, config);
4207
4208         tp->ups_info.eee = enable;
4209 }
4210
4211 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4212 {
4213         switch (tp->version) {
4214         case RTL_VER_01:
4215         case RTL_VER_02:
4216         case RTL_VER_07:
4217                 if (enable) {
4218                         r8152_eee_en(tp, true);
4219                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4220                                         tp->eee_adv);
4221                 } else {
4222                         r8152_eee_en(tp, false);
4223                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4224                 }
4225                 break;
4226         case RTL_VER_03:
4227         case RTL_VER_04:
4228         case RTL_VER_05:
4229         case RTL_VER_06:
4230         case RTL_VER_08:
4231         case RTL_VER_09:
4232                 if (enable) {
4233                         r8153_eee_en(tp, true);
4234                         ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4235                 } else {
4236                         r8153_eee_en(tp, false);
4237                         ocp_reg_write(tp, OCP_EEE_ADV, 0);
4238                 }
4239                 break;
4240         default:
4241                 break;
4242         }
4243 }
4244
4245 static void r8152b_enable_fc(struct r8152 *tp)
4246 {
4247         u16 anar;
4248
4249         anar = r8152_mdio_read(tp, MII_ADVERTISE);
4250         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4251         r8152_mdio_write(tp, MII_ADVERTISE, anar);
4252
4253         tp->ups_info.flow_control = true;
4254 }
4255
4256 static void rtl8152_disable(struct r8152 *tp)
4257 {
4258         r8152_aldps_en(tp, false);
4259         rtl_disable(tp);
4260         r8152_aldps_en(tp, true);
4261 }
4262
4263 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4264 {
4265         rtl8152_apply_firmware(tp, false);
4266         rtl_eee_enable(tp, tp->eee_en);
4267         r8152_aldps_en(tp, true);
4268         r8152b_enable_fc(tp);
4269
4270         set_bit(PHY_RESET, &tp->flags);
4271 }
4272
4273 static void wait_oob_link_list_ready(struct r8152 *tp)
4274 {
4275         u32 ocp_data;
4276         int i;
4277
4278         for (i = 0; i < 1000; i++) {
4279                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4280                 if (ocp_data & LINK_LIST_READY)
4281                         break;
4282                 usleep_range(1000, 2000);
4283         }
4284 }
4285
4286 static void r8152b_exit_oob(struct r8152 *tp)
4287 {
4288         u32 ocp_data;
4289
4290         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4291         ocp_data &= ~RCR_ACPT_ALL;
4292         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4293
4294         rxdy_gated_en(tp, true);
4295         r8153_teredo_off(tp);
4296         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4297         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4298
4299         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4300         ocp_data &= ~NOW_IS_OOB;
4301         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4302
4303         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4304         ocp_data &= ~MCU_BORW_EN;
4305         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4306
4307         wait_oob_link_list_ready(tp);
4308
4309         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4310         ocp_data |= RE_INIT_LL;
4311         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4312
4313         wait_oob_link_list_ready(tp);
4314
4315         rtl8152_nic_reset(tp);
4316
4317         /* rx share fifo credit full threshold */
4318         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4319
4320         if (tp->udev->speed == USB_SPEED_FULL ||
4321             tp->udev->speed == USB_SPEED_LOW) {
4322                 /* rx share fifo credit near full threshold */
4323                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4324                                 RXFIFO_THR2_FULL);
4325                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4326                                 RXFIFO_THR3_FULL);
4327         } else {
4328                 /* rx share fifo credit near full threshold */
4329                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4330                                 RXFIFO_THR2_HIGH);
4331                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4332                                 RXFIFO_THR3_HIGH);
4333         }
4334
4335         /* TX share fifo free credit full threshold */
4336         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4337
4338         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4339         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4340         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4341                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4342
4343         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4344
4345         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4346
4347         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4348         ocp_data |= TCR0_AUTO_FIFO;
4349         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4350 }
4351
4352 static void r8152b_enter_oob(struct r8152 *tp)
4353 {
4354         u32 ocp_data;
4355
4356         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4357         ocp_data &= ~NOW_IS_OOB;
4358         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4359
4360         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4361         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4362         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4363
4364         rtl_disable(tp);
4365
4366         wait_oob_link_list_ready(tp);
4367
4368         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4369         ocp_data |= RE_INIT_LL;
4370         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4371
4372         wait_oob_link_list_ready(tp);
4373
4374         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4375
4376         rtl_rx_vlan_en(tp, true);
4377
4378         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4379         ocp_data |= ALDPS_PROXY_MODE;
4380         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4381
4382         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4383         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4384         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4385
4386         rxdy_gated_en(tp, false);
4387
4388         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4389         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4390         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4391 }
4392
4393 static int r8153_pre_firmware_1(struct r8152 *tp)
4394 {
4395         int i;
4396
4397         /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4398         for (i = 0; i < 104; i++) {
4399                 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4400
4401                 if (!(ocp_data & WTD1_EN))
4402                         break;
4403                 usleep_range(1000, 2000);
4404         }
4405
4406         return 0;
4407 }
4408
4409 static int r8153_post_firmware_1(struct r8152 *tp)
4410 {
4411         /* set USB_BP_4 to support USB_SPEED_SUPER only */
4412         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4413                 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4414
4415         /* reset UPHY timer to 36 ms */
4416         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4417
4418         return 0;
4419 }
4420
4421 static int r8153_pre_firmware_2(struct r8152 *tp)
4422 {
4423         u32 ocp_data;
4424
4425         r8153_pre_firmware_1(tp);
4426
4427         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4428         ocp_data &= ~FW_FIX_SUSPEND;
4429         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4430
4431         return 0;
4432 }
4433
4434 static int r8153_post_firmware_2(struct r8152 *tp)
4435 {
4436         u32 ocp_data;
4437
4438         /* enable bp0 if support USB_SPEED_SUPER only */
4439         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4440                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4441                 ocp_data |= BIT(0);
4442                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4443         }
4444
4445         /* reset UPHY timer to 36 ms */
4446         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4447
4448         /* enable U3P3 check, set the counter to 4 */
4449         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4450
4451         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4452         ocp_data |= FW_FIX_SUSPEND;
4453         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4454
4455         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4456         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4457         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4458
4459         return 0;
4460 }
4461
4462 static int r8153_post_firmware_3(struct r8152 *tp)
4463 {
4464         u32 ocp_data;
4465
4466         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4467         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4468         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4469
4470         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4471         ocp_data |= FW_IP_RESET_EN;
4472         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4473
4474         return 0;
4475 }
4476
4477 static int r8153b_pre_firmware_1(struct r8152 *tp)
4478 {
4479         /* enable fc timer and set timer to 1 second. */
4480         ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4481                        CTRL_TIMER_EN | (1000 / 8));
4482
4483         return 0;
4484 }
4485
4486 static int r8153b_post_firmware_1(struct r8152 *tp)
4487 {
4488         u32 ocp_data;
4489
4490         /* enable bp0 for RTL8153-BND */
4491         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4492         if (ocp_data & BND_MASK) {
4493                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4494                 ocp_data |= BIT(0);
4495                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4496         }
4497
4498         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4499         ocp_data |= FLOW_CTRL_PATCH_OPT;
4500         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4501
4502         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4503         ocp_data |= FC_PATCH_TASK;
4504         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4505
4506         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4507         ocp_data |= FW_IP_RESET_EN;
4508         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4509
4510         return 0;
4511 }
4512
4513 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4514 {
4515         u16 data;
4516
4517         data = ocp_reg_read(tp, OCP_POWER_CFG);
4518         if (enable) {
4519                 data |= EN_ALDPS;
4520                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4521         } else {
4522                 int i;
4523
4524                 data &= ~EN_ALDPS;
4525                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4526                 for (i = 0; i < 20; i++) {
4527                         usleep_range(1000, 2000);
4528                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4529                                 break;
4530                 }
4531         }
4532
4533         tp->ups_info.aldps = enable;
4534 }
4535
4536 static void r8153_hw_phy_cfg(struct r8152 *tp)
4537 {
4538         u32 ocp_data;
4539         u16 data;
4540
4541         /* disable ALDPS before updating the PHY parameters */
4542         r8153_aldps_en(tp, false);
4543
4544         /* disable EEE before updating the PHY parameters */
4545         rtl_eee_enable(tp, false);
4546
4547         rtl8152_apply_firmware(tp, false);
4548
4549         if (tp->version == RTL_VER_03) {
4550                 data = ocp_reg_read(tp, OCP_EEE_CFG);
4551                 data &= ~CTAP_SHORT_EN;
4552                 ocp_reg_write(tp, OCP_EEE_CFG, data);
4553         }
4554
4555         data = ocp_reg_read(tp, OCP_POWER_CFG);
4556         data |= EEE_CLKDIV_EN;
4557         ocp_reg_write(tp, OCP_POWER_CFG, data);
4558
4559         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4560         data |= EN_10M_BGOFF;
4561         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4562         data = ocp_reg_read(tp, OCP_POWER_CFG);
4563         data |= EN_10M_PLLOFF;
4564         ocp_reg_write(tp, OCP_POWER_CFG, data);
4565         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4566
4567         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4568         ocp_data |= PFM_PWM_SWITCH;
4569         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4570
4571         /* Enable LPF corner auto tune */
4572         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4573
4574         /* Adjust 10M Amplitude */
4575         sram_write(tp, SRAM_10M_AMP1, 0x00af);
4576         sram_write(tp, SRAM_10M_AMP2, 0x0208);
4577
4578         if (tp->eee_en)
4579                 rtl_eee_enable(tp, true);
4580
4581         r8153_aldps_en(tp, true);
4582         r8152b_enable_fc(tp);
4583
4584         switch (tp->version) {
4585         case RTL_VER_03:
4586         case RTL_VER_04:
4587                 break;
4588         case RTL_VER_05:
4589         case RTL_VER_06:
4590         default:
4591                 r8153_u2p3en(tp, true);
4592                 break;
4593         }
4594
4595         set_bit(PHY_RESET, &tp->flags);
4596 }
4597
4598 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4599 {
4600         u32 ocp_data;
4601
4602         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4603         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4604         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
4605         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4606
4607         return ocp_data;
4608 }
4609
4610 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4611 {
4612         u32 ocp_data;
4613         u16 data;
4614
4615         /* disable ALDPS before updating the PHY parameters */
4616         r8153_aldps_en(tp, false);
4617
4618         /* disable EEE before updating the PHY parameters */
4619         rtl_eee_enable(tp, false);
4620
4621         rtl8152_apply_firmware(tp, false);
4622
4623         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4624
4625         data = sram_read(tp, SRAM_GREEN_CFG);
4626         data |= R_TUNE_EN;
4627         sram_write(tp, SRAM_GREEN_CFG, data);
4628         data = ocp_reg_read(tp, OCP_NCTL_CFG);
4629         data |= PGA_RETURN_EN;
4630         ocp_reg_write(tp, OCP_NCTL_CFG, data);
4631
4632         /* ADC Bias Calibration:
4633          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4634          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4635          * ADC ioffset.
4636          */
4637         ocp_data = r8152_efuse_read(tp, 0x7d);
4638         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4639         if (data != 0xffff)
4640                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4641
4642         /* ups mode tx-link-pulse timing adjustment:
4643          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4644          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4645          */
4646         ocp_data = ocp_reg_read(tp, 0xc426);
4647         ocp_data &= 0x3fff;
4648         if (ocp_data) {
4649                 u32 swr_cnt_1ms_ini;
4650
4651                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4652                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4653                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4654                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4655         }
4656
4657         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4658         ocp_data |= PFM_PWM_SWITCH;
4659         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4660
4661         /* Advnace EEE */
4662         if (!rtl_phy_patch_request(tp, true, true)) {
4663                 data = ocp_reg_read(tp, OCP_POWER_CFG);
4664                 data |= EEE_CLKDIV_EN;
4665                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4666                 tp->ups_info.eee_ckdiv = true;
4667
4668                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4669                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4670                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4671                 tp->ups_info.eee_cmod_lv = true;
4672                 tp->ups_info._10m_ckdiv = true;
4673                 tp->ups_info.eee_plloff_giga = true;
4674
4675                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4676                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4677                 tp->ups_info._250m_ckdiv = true;
4678
4679                 rtl_phy_patch_request(tp, false, true);
4680         }
4681
4682         if (tp->eee_en)
4683                 rtl_eee_enable(tp, true);
4684
4685         r8153_aldps_en(tp, true);
4686         r8152b_enable_fc(tp);
4687
4688         set_bit(PHY_RESET, &tp->flags);
4689 }
4690
4691 static void r8153_first_init(struct r8152 *tp)
4692 {
4693         u32 ocp_data;
4694
4695         r8153_mac_clk_spd(tp, false);
4696         rxdy_gated_en(tp, true);
4697         r8153_teredo_off(tp);
4698
4699         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4700         ocp_data &= ~RCR_ACPT_ALL;
4701         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4702
4703         rtl8152_nic_reset(tp);
4704         rtl_reset_bmu(tp);
4705
4706         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4707         ocp_data &= ~NOW_IS_OOB;
4708         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4709
4710         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4711         ocp_data &= ~MCU_BORW_EN;
4712         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4713
4714         wait_oob_link_list_ready(tp);
4715
4716         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4717         ocp_data |= RE_INIT_LL;
4718         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4719
4720         wait_oob_link_list_ready(tp);
4721
4722         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4723
4724         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4725         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4726         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4727
4728         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4729         ocp_data |= TCR0_AUTO_FIFO;
4730         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4731
4732         rtl8152_nic_reset(tp);
4733
4734         /* rx share fifo credit full threshold */
4735         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4736         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4737         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4738         /* TX share fifo free credit full threshold */
4739         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4740 }
4741
4742 static void r8153_enter_oob(struct r8152 *tp)
4743 {
4744         u32 ocp_data;
4745
4746         r8153_mac_clk_spd(tp, true);
4747
4748         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4749         ocp_data &= ~NOW_IS_OOB;
4750         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4751
4752         rtl_disable(tp);
4753         rtl_reset_bmu(tp);
4754
4755         wait_oob_link_list_ready(tp);
4756
4757         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4758         ocp_data |= RE_INIT_LL;
4759         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4760
4761         wait_oob_link_list_ready(tp);
4762
4763         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4764         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4765
4766         switch (tp->version) {
4767         case RTL_VER_03:
4768         case RTL_VER_04:
4769         case RTL_VER_05:
4770         case RTL_VER_06:
4771                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4772                 ocp_data &= ~TEREDO_WAKE_MASK;
4773                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4774                 break;
4775
4776         case RTL_VER_08:
4777         case RTL_VER_09:
4778                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4779                  * type. Set it to zero. bits[7:0] are the W1C bits about
4780                  * the events. Set them to all 1 to clear them.
4781                  */
4782                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4783                 break;
4784
4785         default:
4786                 break;
4787         }
4788
4789         rtl_rx_vlan_en(tp, true);
4790
4791         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4792         ocp_data |= ALDPS_PROXY_MODE;
4793         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4794
4795         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4796         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4797         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4798
4799         rxdy_gated_en(tp, false);
4800
4801         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4802         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4803         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4804 }
4805
4806 static void rtl8153_disable(struct r8152 *tp)
4807 {
4808         r8153_aldps_en(tp, false);
4809         rtl_disable(tp);
4810         rtl_reset_bmu(tp);
4811         r8153_aldps_en(tp, true);
4812 }
4813
4814 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4815                              u32 advertising)
4816 {
4817         u16 bmcr;
4818         int ret = 0;
4819
4820         if (autoneg == AUTONEG_DISABLE) {
4821                 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4822                         return -EINVAL;
4823
4824                 switch (speed) {
4825                 case SPEED_10:
4826                         bmcr = BMCR_SPEED10;
4827                         if (duplex == DUPLEX_FULL) {
4828                                 bmcr |= BMCR_FULLDPLX;
4829                                 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4830                         } else {
4831                                 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4832                         }
4833                         break;
4834                 case SPEED_100:
4835                         bmcr = BMCR_SPEED100;
4836                         if (duplex == DUPLEX_FULL) {
4837                                 bmcr |= BMCR_FULLDPLX;
4838                                 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4839                         } else {
4840                                 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4841                         }
4842                         break;
4843                 case SPEED_1000:
4844                         if (tp->mii.supports_gmii) {
4845                                 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4846                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4847                                 break;
4848                         }
4849                         fallthrough;
4850                 default:
4851                         ret = -EINVAL;
4852                         goto out;
4853                 }
4854
4855                 if (duplex == DUPLEX_FULL)
4856                         tp->mii.full_duplex = 1;
4857                 else
4858                         tp->mii.full_duplex = 0;
4859
4860                 tp->mii.force_media = 1;
4861         } else {
4862                 u16 anar, tmp1;
4863                 u32 support;
4864
4865                 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4866                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4867
4868                 if (tp->mii.supports_gmii)
4869                         support |= RTL_ADVERTISED_1000_FULL;
4870
4871                 if (!(advertising & support))
4872                         return -EINVAL;
4873
4874                 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4875                 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4876                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
4877                 if (advertising & RTL_ADVERTISED_10_HALF) {
4878                         tmp1 |= ADVERTISE_10HALF;
4879                         tp->ups_info.speed_duplex = NWAY_10M_HALF;
4880                 }
4881                 if (advertising & RTL_ADVERTISED_10_FULL) {
4882                         tmp1 |= ADVERTISE_10FULL;
4883                         tp->ups_info.speed_duplex = NWAY_10M_FULL;
4884                 }
4885
4886                 if (advertising & RTL_ADVERTISED_100_HALF) {
4887                         tmp1 |= ADVERTISE_100HALF;
4888                         tp->ups_info.speed_duplex = NWAY_100M_HALF;
4889                 }
4890                 if (advertising & RTL_ADVERTISED_100_FULL) {
4891                         tmp1 |= ADVERTISE_100FULL;
4892                         tp->ups_info.speed_duplex = NWAY_100M_FULL;
4893                 }
4894
4895                 if (anar != tmp1) {
4896                         r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4897                         tp->mii.advertising = tmp1;
4898                 }
4899
4900                 if (tp->mii.supports_gmii) {
4901                         u16 gbcr;
4902
4903                         gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4904                         tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4905                                         ADVERTISE_1000HALF);
4906
4907                         if (advertising & RTL_ADVERTISED_1000_FULL) {
4908                                 tmp1 |= ADVERTISE_1000FULL;
4909                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4910                         }
4911
4912                         if (gbcr != tmp1)
4913                                 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4914                 }
4915
4916                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4917
4918                 tp->mii.force_media = 0;
4919         }
4920
4921         if (test_and_clear_bit(PHY_RESET, &tp->flags))
4922                 bmcr |= BMCR_RESET;
4923
4924         r8152_mdio_write(tp, MII_BMCR, bmcr);
4925
4926         if (bmcr & BMCR_RESET) {
4927                 int i;
4928
4929                 for (i = 0; i < 50; i++) {
4930                         msleep(20);
4931                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4932                                 break;
4933                 }
4934         }
4935
4936 out:
4937         return ret;
4938 }
4939
4940 static void rtl8152_up(struct r8152 *tp)
4941 {
4942         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4943                 return;
4944
4945         r8152_aldps_en(tp, false);
4946         r8152b_exit_oob(tp);
4947         r8152_aldps_en(tp, true);
4948 }
4949
4950 static void rtl8152_down(struct r8152 *tp)
4951 {
4952         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4953                 rtl_drop_queued_tx(tp);
4954                 return;
4955         }
4956
4957         r8152_power_cut_en(tp, false);
4958         r8152_aldps_en(tp, false);
4959         r8152b_enter_oob(tp);
4960         r8152_aldps_en(tp, true);
4961 }
4962
4963 static void rtl8153_up(struct r8152 *tp)
4964 {
4965         u32 ocp_data;
4966
4967         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4968                 return;
4969
4970         r8153_u1u2en(tp, false);
4971         r8153_u2p3en(tp, false);
4972         r8153_aldps_en(tp, false);
4973         r8153_first_init(tp);
4974
4975         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4976         ocp_data |= LANWAKE_CLR_EN;
4977         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4978
4979         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4980         ocp_data &= ~LANWAKE_PIN;
4981         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4982
4983         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4984         ocp_data &= ~DELAY_PHY_PWR_CHG;
4985         ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4986
4987         r8153_aldps_en(tp, true);
4988
4989         switch (tp->version) {
4990         case RTL_VER_03:
4991         case RTL_VER_04:
4992                 break;
4993         case RTL_VER_05:
4994         case RTL_VER_06:
4995         default:
4996                 r8153_u2p3en(tp, true);
4997                 break;
4998         }
4999
5000         r8153_u1u2en(tp, true);
5001 }
5002
5003 static void rtl8153_down(struct r8152 *tp)
5004 {
5005         u32 ocp_data;
5006
5007         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5008                 rtl_drop_queued_tx(tp);
5009                 return;
5010         }
5011
5012         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5013         ocp_data &= ~LANWAKE_CLR_EN;
5014         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5015
5016         r8153_u1u2en(tp, false);
5017         r8153_u2p3en(tp, false);
5018         r8153_power_cut_en(tp, false);
5019         r8153_aldps_en(tp, false);
5020         r8153_enter_oob(tp);
5021         r8153_aldps_en(tp, true);
5022 }
5023
5024 static void rtl8153b_up(struct r8152 *tp)
5025 {
5026         u32 ocp_data;
5027
5028         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5029                 return;
5030
5031         r8153b_u1u2en(tp, false);
5032         r8153_u2p3en(tp, false);
5033         r8153_aldps_en(tp, false);
5034
5035         r8153_first_init(tp);
5036         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5037
5038         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5039         ocp_data &= ~PLA_MCU_SPDWN_EN;
5040         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5041
5042         r8153_aldps_en(tp, true);
5043
5044         if (tp->udev->speed != USB_SPEED_HIGH)
5045                 r8153b_u1u2en(tp, true);
5046 }
5047
5048 static void rtl8153b_down(struct r8152 *tp)
5049 {
5050         u32 ocp_data;
5051
5052         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5053                 rtl_drop_queued_tx(tp);
5054                 return;
5055         }
5056
5057         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5058         ocp_data |= PLA_MCU_SPDWN_EN;
5059         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5060
5061         r8153b_u1u2en(tp, false);
5062         r8153_u2p3en(tp, false);
5063         r8153b_power_cut_en(tp, false);
5064         r8153_aldps_en(tp, false);
5065         r8153_enter_oob(tp);
5066         r8153_aldps_en(tp, true);
5067 }
5068
5069 static bool rtl8152_in_nway(struct r8152 *tp)
5070 {
5071         u16 nway_state;
5072
5073         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5074         tp->ocp_base = 0x2000;
5075         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
5076         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5077
5078         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5079         if (nway_state & 0xc000)
5080                 return false;
5081         else
5082                 return true;
5083 }
5084
5085 static bool rtl8153_in_nway(struct r8152 *tp)
5086 {
5087         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5088
5089         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5090                 return false;
5091         else
5092                 return true;
5093 }
5094
5095 static void set_carrier(struct r8152 *tp)
5096 {
5097         struct net_device *netdev = tp->netdev;
5098         struct napi_struct *napi = &tp->napi;
5099         u8 speed;
5100
5101         speed = rtl8152_get_speed(tp);
5102
5103         if (speed & LINK_STATUS) {
5104                 if (!netif_carrier_ok(netdev)) {
5105                         tp->rtl_ops.enable(tp);
5106                         netif_stop_queue(netdev);
5107                         napi_disable(napi);
5108                         netif_carrier_on(netdev);
5109                         rtl_start_rx(tp);
5110                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5111                         _rtl8152_set_rx_mode(netdev);
5112                         napi_enable(&tp->napi);
5113                         netif_wake_queue(netdev);
5114                         netif_info(tp, link, netdev, "carrier on\n");
5115                 } else if (netif_queue_stopped(netdev) &&
5116                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5117                         netif_wake_queue(netdev);
5118                 }
5119         } else {
5120                 if (netif_carrier_ok(netdev)) {
5121                         netif_carrier_off(netdev);
5122                         tasklet_disable(&tp->tx_tl);
5123                         napi_disable(napi);
5124                         tp->rtl_ops.disable(tp);
5125                         napi_enable(napi);
5126                         tasklet_enable(&tp->tx_tl);
5127                         netif_info(tp, link, netdev, "carrier off\n");
5128                 }
5129         }
5130 }
5131
5132 static void rtl_work_func_t(struct work_struct *work)
5133 {
5134         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5135
5136         /* If the device is unplugged or !netif_running(), the workqueue
5137          * doesn't need to wake the device, and could return directly.
5138          */
5139         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5140                 return;
5141
5142         if (usb_autopm_get_interface(tp->intf) < 0)
5143                 return;
5144
5145         if (!test_bit(WORK_ENABLE, &tp->flags))
5146                 goto out1;
5147
5148         if (!mutex_trylock(&tp->control)) {
5149                 schedule_delayed_work(&tp->schedule, 0);
5150                 goto out1;
5151         }
5152
5153         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5154                 set_carrier(tp);
5155
5156         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5157                 _rtl8152_set_rx_mode(tp->netdev);
5158
5159         /* don't schedule tasket before linking */
5160         if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5161             netif_carrier_ok(tp->netdev))
5162                 tasklet_schedule(&tp->tx_tl);
5163
5164         mutex_unlock(&tp->control);
5165
5166 out1:
5167         usb_autopm_put_interface(tp->intf);
5168 }
5169
5170 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5171 {
5172         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5173
5174         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5175                 return;
5176
5177         if (usb_autopm_get_interface(tp->intf) < 0)
5178                 return;
5179
5180         mutex_lock(&tp->control);
5181
5182         if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5183                 tp->rtl_fw.retry = false;
5184                 tp->rtl_fw.fw = NULL;
5185
5186                 /* Delay execution in case request_firmware() is not ready yet.
5187                  */
5188                 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5189                 goto ignore_once;
5190         }
5191
5192         tp->rtl_ops.hw_phy_cfg(tp);
5193
5194         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5195                           tp->advertising);
5196
5197 ignore_once:
5198         mutex_unlock(&tp->control);
5199
5200         usb_autopm_put_interface(tp->intf);
5201 }
5202
5203 #ifdef CONFIG_PM_SLEEP
5204 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5205                         void *data)
5206 {
5207         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5208
5209         switch (action) {
5210         case PM_HIBERNATION_PREPARE:
5211         case PM_SUSPEND_PREPARE:
5212                 usb_autopm_get_interface(tp->intf);
5213                 break;
5214
5215         case PM_POST_HIBERNATION:
5216         case PM_POST_SUSPEND:
5217                 usb_autopm_put_interface(tp->intf);
5218                 break;
5219
5220         case PM_POST_RESTORE:
5221         case PM_RESTORE_PREPARE:
5222         default:
5223                 break;
5224         }
5225
5226         return NOTIFY_DONE;
5227 }
5228 #endif
5229
5230 static int rtl8152_open(struct net_device *netdev)
5231 {
5232         struct r8152 *tp = netdev_priv(netdev);
5233         int res = 0;
5234
5235         if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5236                 cancel_delayed_work_sync(&tp->hw_phy_work);
5237                 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5238         }
5239
5240         res = alloc_all_mem(tp);
5241         if (res)
5242                 goto out;
5243
5244         res = usb_autopm_get_interface(tp->intf);
5245         if (res < 0)
5246                 goto out_free;
5247
5248         mutex_lock(&tp->control);
5249
5250         tp->rtl_ops.up(tp);
5251
5252         netif_carrier_off(netdev);
5253         netif_start_queue(netdev);
5254         set_bit(WORK_ENABLE, &tp->flags);
5255
5256         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5257         if (res) {
5258                 if (res == -ENODEV)
5259                         netif_device_detach(tp->netdev);
5260                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5261                            res);
5262                 goto out_unlock;
5263         }
5264         napi_enable(&tp->napi);
5265         tasklet_enable(&tp->tx_tl);
5266
5267         mutex_unlock(&tp->control);
5268
5269         usb_autopm_put_interface(tp->intf);
5270 #ifdef CONFIG_PM_SLEEP
5271         tp->pm_notifier.notifier_call = rtl_notifier;
5272         register_pm_notifier(&tp->pm_notifier);
5273 #endif
5274         return 0;
5275
5276 out_unlock:
5277         mutex_unlock(&tp->control);
5278         usb_autopm_put_interface(tp->intf);
5279 out_free:
5280         free_all_mem(tp);
5281 out:
5282         return res;
5283 }
5284
5285 static int rtl8152_close(struct net_device *netdev)
5286 {
5287         struct r8152 *tp = netdev_priv(netdev);
5288         int res = 0;
5289
5290 #ifdef CONFIG_PM_SLEEP
5291         unregister_pm_notifier(&tp->pm_notifier);
5292 #endif
5293         tasklet_disable(&tp->tx_tl);
5294         clear_bit(WORK_ENABLE, &tp->flags);
5295         usb_kill_urb(tp->intr_urb);
5296         cancel_delayed_work_sync(&tp->schedule);
5297         napi_disable(&tp->napi);
5298         netif_stop_queue(netdev);
5299
5300         res = usb_autopm_get_interface(tp->intf);
5301         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5302                 rtl_drop_queued_tx(tp);
5303                 rtl_stop_rx(tp);
5304         } else {
5305                 mutex_lock(&tp->control);
5306
5307                 tp->rtl_ops.down(tp);
5308
5309                 mutex_unlock(&tp->control);
5310
5311                 usb_autopm_put_interface(tp->intf);
5312         }
5313
5314         free_all_mem(tp);
5315
5316         return res;
5317 }
5318
5319 static void rtl_tally_reset(struct r8152 *tp)
5320 {
5321         u32 ocp_data;
5322
5323         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5324         ocp_data |= TALLY_RESET;
5325         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5326 }
5327
5328 static void r8152b_init(struct r8152 *tp)
5329 {
5330         u32 ocp_data;
5331         u16 data;
5332
5333         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5334                 return;
5335
5336         data = r8152_mdio_read(tp, MII_BMCR);
5337         if (data & BMCR_PDOWN) {
5338                 data &= ~BMCR_PDOWN;
5339                 r8152_mdio_write(tp, MII_BMCR, data);
5340         }
5341
5342         r8152_aldps_en(tp, false);
5343
5344         if (tp->version == RTL_VER_01) {
5345                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5346                 ocp_data &= ~LED_MODE_MASK;
5347                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5348         }
5349
5350         r8152_power_cut_en(tp, false);
5351
5352         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5353         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5354         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5355         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5356         ocp_data &= ~MCU_CLK_RATIO_MASK;
5357         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5358         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5359         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5360                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5361         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5362
5363         rtl_tally_reset(tp);
5364
5365         /* enable rx aggregation */
5366         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5367         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5368         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5369 }
5370
5371 static void r8153_init(struct r8152 *tp)
5372 {
5373         u32 ocp_data;
5374         u16 data;
5375         int i;
5376
5377         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5378                 return;
5379
5380         r8153_u1u2en(tp, false);
5381
5382         for (i = 0; i < 500; i++) {
5383                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5384                     AUTOLOAD_DONE)
5385                         break;
5386
5387                 msleep(20);
5388                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5389                         break;
5390         }
5391
5392         data = r8153_phy_status(tp, 0);
5393
5394         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5395             tp->version == RTL_VER_05)
5396                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5397
5398         data = r8152_mdio_read(tp, MII_BMCR);
5399         if (data & BMCR_PDOWN) {
5400                 data &= ~BMCR_PDOWN;
5401                 r8152_mdio_write(tp, MII_BMCR, data);
5402         }
5403
5404         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5405
5406         r8153_u2p3en(tp, false);
5407
5408         if (tp->version == RTL_VER_04) {
5409                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5410                 ocp_data &= ~pwd_dn_scale_mask;
5411                 ocp_data |= pwd_dn_scale(96);
5412                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5413
5414                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5415                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5416                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5417         } else if (tp->version == RTL_VER_05) {
5418                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5419                 ocp_data &= ~ECM_ALDPS;
5420                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5421
5422                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5423                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5424                         ocp_data &= ~DYNAMIC_BURST;
5425                 else
5426                         ocp_data |= DYNAMIC_BURST;
5427                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5428         } else if (tp->version == RTL_VER_06) {
5429                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5430                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5431                         ocp_data &= ~DYNAMIC_BURST;
5432                 else
5433                         ocp_data |= DYNAMIC_BURST;
5434                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5435
5436                 r8153_queue_wake(tp, false);
5437
5438                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5439                 if (rtl8152_get_speed(tp) & LINK_STATUS)
5440                         ocp_data |= CUR_LINK_OK;
5441                 else
5442                         ocp_data &= ~CUR_LINK_OK;
5443                 ocp_data |= POLL_LINK_CHG;
5444                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5445         }
5446
5447         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5448         ocp_data |= EP4_FULL_FC;
5449         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5450
5451         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5452         ocp_data &= ~TIMER11_EN;
5453         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5454
5455         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5456         ocp_data &= ~LED_MODE_MASK;
5457         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5458
5459         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5460         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5461                 ocp_data |= LPM_TIMER_500MS;
5462         else
5463                 ocp_data |= LPM_TIMER_500US;
5464         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5465
5466         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5467         ocp_data &= ~SEN_VAL_MASK;
5468         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5469         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5470
5471         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5472
5473         r8153_power_cut_en(tp, false);
5474         rtl_runtime_suspend_enable(tp, false);
5475         r8153_u1u2en(tp, true);
5476         r8153_mac_clk_spd(tp, false);
5477         usb_enable_lpm(tp->udev);
5478
5479         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5480         ocp_data |= LANWAKE_CLR_EN;
5481         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5482
5483         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5484         ocp_data &= ~LANWAKE_PIN;
5485         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5486
5487         /* rx aggregation */
5488         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5489         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5490         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5491                 ocp_data |= RX_AGG_DISABLE;
5492
5493         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5494
5495         rtl_tally_reset(tp);
5496
5497         switch (tp->udev->speed) {
5498         case USB_SPEED_SUPER:
5499         case USB_SPEED_SUPER_PLUS:
5500                 tp->coalesce = COALESCE_SUPER;
5501                 break;
5502         case USB_SPEED_HIGH:
5503                 tp->coalesce = COALESCE_HIGH;
5504                 break;
5505         default:
5506                 tp->coalesce = COALESCE_SLOW;
5507                 break;
5508         }
5509 }
5510
5511 static void r8153b_init(struct r8152 *tp)
5512 {
5513         u32 ocp_data;
5514         u16 data;
5515         int i;
5516
5517         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5518                 return;
5519
5520         r8153b_u1u2en(tp, false);
5521
5522         for (i = 0; i < 500; i++) {
5523                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5524                     AUTOLOAD_DONE)
5525                         break;
5526
5527                 msleep(20);
5528                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5529                         break;
5530         }
5531
5532         data = r8153_phy_status(tp, 0);
5533
5534         data = r8152_mdio_read(tp, MII_BMCR);
5535         if (data & BMCR_PDOWN) {
5536                 data &= ~BMCR_PDOWN;
5537                 r8152_mdio_write(tp, MII_BMCR, data);
5538         }
5539
5540         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5541
5542         r8153_u2p3en(tp, false);
5543
5544         /* MSC timer = 0xfff * 8ms = 32760 ms */
5545         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5546
5547         /* U1/U2/L1 idle timer. 500 us */
5548         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5549
5550         r8153b_power_cut_en(tp, false);
5551         r8153b_ups_en(tp, false);
5552         r8153_queue_wake(tp, false);
5553         rtl_runtime_suspend_enable(tp, false);
5554
5555         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5556         if (rtl8152_get_speed(tp) & LINK_STATUS)
5557                 ocp_data |= CUR_LINK_OK;
5558         else
5559                 ocp_data &= ~CUR_LINK_OK;
5560         ocp_data |= POLL_LINK_CHG;
5561         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5562
5563         if (tp->udev->speed != USB_SPEED_HIGH)
5564                 r8153b_u1u2en(tp, true);
5565         usb_enable_lpm(tp->udev);
5566
5567         /* MAC clock speed down */
5568         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5569         ocp_data |= MAC_CLK_SPDWN_EN;
5570         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5571
5572         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5573         ocp_data &= ~PLA_MCU_SPDWN_EN;
5574         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5575
5576         if (tp->version == RTL_VER_09) {
5577                 /* Disable Test IO for 32QFN */
5578                 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5579                         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5580                         ocp_data |= TEST_IO_OFF;
5581                         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5582                 }
5583         }
5584
5585         set_bit(GREEN_ETHERNET, &tp->flags);
5586
5587         /* rx aggregation */
5588         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5589         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5590         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5591
5592         rtl_tally_reset(tp);
5593
5594         tp->coalesce = 15000;   /* 15 us */
5595 }
5596
5597 static int rtl8152_pre_reset(struct usb_interface *intf)
5598 {
5599         struct r8152 *tp = usb_get_intfdata(intf);
5600         struct net_device *netdev;
5601
5602         if (!tp)
5603                 return 0;
5604
5605         netdev = tp->netdev;
5606         if (!netif_running(netdev))
5607                 return 0;
5608
5609         netif_stop_queue(netdev);
5610         tasklet_disable(&tp->tx_tl);
5611         clear_bit(WORK_ENABLE, &tp->flags);
5612         usb_kill_urb(tp->intr_urb);
5613         cancel_delayed_work_sync(&tp->schedule);
5614         napi_disable(&tp->napi);
5615         if (netif_carrier_ok(netdev)) {
5616                 mutex_lock(&tp->control);
5617                 tp->rtl_ops.disable(tp);
5618                 mutex_unlock(&tp->control);
5619         }
5620
5621         return 0;
5622 }
5623
5624 static int rtl8152_post_reset(struct usb_interface *intf)
5625 {
5626         struct r8152 *tp = usb_get_intfdata(intf);
5627         struct net_device *netdev;
5628         struct sockaddr sa;
5629
5630         if (!tp)
5631                 return 0;
5632
5633         /* reset the MAC adddress in case of policy change */
5634         if (determine_ethernet_addr(tp, &sa) >= 0) {
5635                 rtnl_lock();
5636                 dev_set_mac_address (tp->netdev, &sa, NULL);
5637                 rtnl_unlock();
5638         }
5639
5640         netdev = tp->netdev;
5641         if (!netif_running(netdev))
5642                 return 0;
5643
5644         set_bit(WORK_ENABLE, &tp->flags);
5645         if (netif_carrier_ok(netdev)) {
5646                 mutex_lock(&tp->control);
5647                 tp->rtl_ops.enable(tp);
5648                 rtl_start_rx(tp);
5649                 _rtl8152_set_rx_mode(netdev);
5650                 mutex_unlock(&tp->control);
5651         }
5652
5653         napi_enable(&tp->napi);
5654         tasklet_enable(&tp->tx_tl);
5655         netif_wake_queue(netdev);
5656         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5657
5658         if (!list_empty(&tp->rx_done))
5659                 napi_schedule(&tp->napi);
5660
5661         return 0;
5662 }
5663
5664 static bool delay_autosuspend(struct r8152 *tp)
5665 {
5666         bool sw_linking = !!netif_carrier_ok(tp->netdev);
5667         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5668
5669         /* This means a linking change occurs and the driver doesn't detect it,
5670          * yet. If the driver has disabled tx/rx and hw is linking on, the
5671          * device wouldn't wake up by receiving any packet.
5672          */
5673         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5674                 return true;
5675
5676         /* If the linking down is occurred by nway, the device may miss the
5677          * linking change event. And it wouldn't wake when linking on.
5678          */
5679         if (!sw_linking && tp->rtl_ops.in_nway(tp))
5680                 return true;
5681         else if (!skb_queue_empty(&tp->tx_queue))
5682                 return true;
5683         else
5684                 return false;
5685 }
5686
5687 static int rtl8152_runtime_resume(struct r8152 *tp)
5688 {
5689         struct net_device *netdev = tp->netdev;
5690
5691         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5692                 struct napi_struct *napi = &tp->napi;
5693
5694                 tp->rtl_ops.autosuspend_en(tp, false);
5695                 napi_disable(napi);
5696                 set_bit(WORK_ENABLE, &tp->flags);
5697
5698                 if (netif_carrier_ok(netdev)) {
5699                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
5700                                 rtl_start_rx(tp);
5701                         } else {
5702                                 netif_carrier_off(netdev);
5703                                 tp->rtl_ops.disable(tp);
5704                                 netif_info(tp, link, netdev, "linking down\n");
5705                         }
5706                 }
5707
5708                 napi_enable(napi);
5709                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5710                 smp_mb__after_atomic();
5711
5712                 if (!list_empty(&tp->rx_done))
5713                         napi_schedule(&tp->napi);
5714
5715                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5716         } else {
5717                 if (netdev->flags & IFF_UP)
5718                         tp->rtl_ops.autosuspend_en(tp, false);
5719
5720                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5721         }
5722
5723         return 0;
5724 }
5725
5726 static int rtl8152_system_resume(struct r8152 *tp)
5727 {
5728         struct net_device *netdev = tp->netdev;
5729
5730         netif_device_attach(netdev);
5731
5732         if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5733                 tp->rtl_ops.up(tp);
5734                 netif_carrier_off(netdev);
5735                 set_bit(WORK_ENABLE, &tp->flags);
5736                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5737         }
5738
5739         return 0;
5740 }
5741
5742 static int rtl8152_runtime_suspend(struct r8152 *tp)
5743 {
5744         struct net_device *netdev = tp->netdev;
5745         int ret = 0;
5746
5747         set_bit(SELECTIVE_SUSPEND, &tp->flags);
5748         smp_mb__after_atomic();
5749
5750         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5751                 u32 rcr = 0;
5752
5753                 if (netif_carrier_ok(netdev)) {
5754                         u32 ocp_data;
5755
5756                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5757                         ocp_data = rcr & ~RCR_ACPT_ALL;
5758                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5759                         rxdy_gated_en(tp, true);
5760                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5761                                                  PLA_OOB_CTRL);
5762                         if (!(ocp_data & RXFIFO_EMPTY)) {
5763                                 rxdy_gated_en(tp, false);
5764                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5765                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5766                                 smp_mb__after_atomic();
5767                                 ret = -EBUSY;
5768                                 goto out1;
5769                         }
5770                 }
5771
5772                 clear_bit(WORK_ENABLE, &tp->flags);
5773                 usb_kill_urb(tp->intr_urb);
5774
5775                 tp->rtl_ops.autosuspend_en(tp, true);
5776
5777                 if (netif_carrier_ok(netdev)) {
5778                         struct napi_struct *napi = &tp->napi;
5779
5780                         napi_disable(napi);
5781                         rtl_stop_rx(tp);
5782                         rxdy_gated_en(tp, false);
5783                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5784                         napi_enable(napi);
5785                 }
5786
5787                 if (delay_autosuspend(tp)) {
5788                         rtl8152_runtime_resume(tp);
5789                         ret = -EBUSY;
5790                 }
5791         }
5792
5793 out1:
5794         return ret;
5795 }
5796
5797 static int rtl8152_system_suspend(struct r8152 *tp)
5798 {
5799         struct net_device *netdev = tp->netdev;
5800
5801         netif_device_detach(netdev);
5802
5803         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5804                 struct napi_struct *napi = &tp->napi;
5805
5806                 clear_bit(WORK_ENABLE, &tp->flags);
5807                 usb_kill_urb(tp->intr_urb);
5808                 tasklet_disable(&tp->tx_tl);
5809                 napi_disable(napi);
5810                 cancel_delayed_work_sync(&tp->schedule);
5811                 tp->rtl_ops.down(tp);
5812                 napi_enable(napi);
5813                 tasklet_enable(&tp->tx_tl);
5814         }
5815
5816         return 0;
5817 }
5818
5819 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5820 {
5821         struct r8152 *tp = usb_get_intfdata(intf);
5822         int ret;
5823
5824         mutex_lock(&tp->control);
5825
5826         if (PMSG_IS_AUTO(message))
5827                 ret = rtl8152_runtime_suspend(tp);
5828         else
5829                 ret = rtl8152_system_suspend(tp);
5830
5831         mutex_unlock(&tp->control);
5832
5833         return ret;
5834 }
5835
5836 static int rtl8152_resume(struct usb_interface *intf)
5837 {
5838         struct r8152 *tp = usb_get_intfdata(intf);
5839         int ret;
5840
5841         mutex_lock(&tp->control);
5842
5843         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5844                 ret = rtl8152_runtime_resume(tp);
5845         else
5846                 ret = rtl8152_system_resume(tp);
5847
5848         mutex_unlock(&tp->control);
5849
5850         return ret;
5851 }
5852
5853 static int rtl8152_reset_resume(struct usb_interface *intf)
5854 {
5855         struct r8152 *tp = usb_get_intfdata(intf);
5856
5857         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5858         tp->rtl_ops.init(tp);
5859         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5860         set_ethernet_addr(tp);
5861         return rtl8152_resume(intf);
5862 }
5863
5864 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5865 {
5866         struct r8152 *tp = netdev_priv(dev);
5867
5868         if (usb_autopm_get_interface(tp->intf) < 0)
5869                 return;
5870
5871         if (!rtl_can_wakeup(tp)) {
5872                 wol->supported = 0;
5873                 wol->wolopts = 0;
5874         } else {
5875                 mutex_lock(&tp->control);
5876                 wol->supported = WAKE_ANY;
5877                 wol->wolopts = __rtl_get_wol(tp);
5878                 mutex_unlock(&tp->control);
5879         }
5880
5881         usb_autopm_put_interface(tp->intf);
5882 }
5883
5884 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5885 {
5886         struct r8152 *tp = netdev_priv(dev);
5887         int ret;
5888
5889         if (!rtl_can_wakeup(tp))
5890                 return -EOPNOTSUPP;
5891
5892         if (wol->wolopts & ~WAKE_ANY)
5893                 return -EINVAL;
5894
5895         ret = usb_autopm_get_interface(tp->intf);
5896         if (ret < 0)
5897                 goto out_set_wol;
5898
5899         mutex_lock(&tp->control);
5900
5901         __rtl_set_wol(tp, wol->wolopts);
5902         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5903
5904         mutex_unlock(&tp->control);
5905
5906         usb_autopm_put_interface(tp->intf);
5907
5908 out_set_wol:
5909         return ret;
5910 }
5911
5912 static u32 rtl8152_get_msglevel(struct net_device *dev)
5913 {
5914         struct r8152 *tp = netdev_priv(dev);
5915
5916         return tp->msg_enable;
5917 }
5918
5919 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5920 {
5921         struct r8152 *tp = netdev_priv(dev);
5922
5923         tp->msg_enable = value;
5924 }
5925
5926 static void rtl8152_get_drvinfo(struct net_device *netdev,
5927                                 struct ethtool_drvinfo *info)
5928 {
5929         struct r8152 *tp = netdev_priv(netdev);
5930
5931         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5932         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5933         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5934         if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5935                 strlcpy(info->fw_version, tp->rtl_fw.version,
5936                         sizeof(info->fw_version));
5937 }
5938
5939 static
5940 int rtl8152_get_link_ksettings(struct net_device *netdev,
5941                                struct ethtool_link_ksettings *cmd)
5942 {
5943         struct r8152 *tp = netdev_priv(netdev);
5944         int ret;
5945
5946         if (!tp->mii.mdio_read)
5947                 return -EOPNOTSUPP;
5948
5949         ret = usb_autopm_get_interface(tp->intf);
5950         if (ret < 0)
5951                 goto out;
5952
5953         mutex_lock(&tp->control);
5954
5955         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5956
5957         mutex_unlock(&tp->control);
5958
5959         usb_autopm_put_interface(tp->intf);
5960
5961 out:
5962         return ret;
5963 }
5964
5965 static int rtl8152_set_link_ksettings(struct net_device *dev,
5966                                       const struct ethtool_link_ksettings *cmd)
5967 {
5968         struct r8152 *tp = netdev_priv(dev);
5969         u32 advertising = 0;
5970         int ret;
5971
5972         ret = usb_autopm_get_interface(tp->intf);
5973         if (ret < 0)
5974                 goto out;
5975
5976         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5977                      cmd->link_modes.advertising))
5978                 advertising |= RTL_ADVERTISED_10_HALF;
5979
5980         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5981                      cmd->link_modes.advertising))
5982                 advertising |= RTL_ADVERTISED_10_FULL;
5983
5984         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5985                      cmd->link_modes.advertising))
5986                 advertising |= RTL_ADVERTISED_100_HALF;
5987
5988         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5989                      cmd->link_modes.advertising))
5990                 advertising |= RTL_ADVERTISED_100_FULL;
5991
5992         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5993                      cmd->link_modes.advertising))
5994                 advertising |= RTL_ADVERTISED_1000_HALF;
5995
5996         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5997                      cmd->link_modes.advertising))
5998                 advertising |= RTL_ADVERTISED_1000_FULL;
5999
6000         mutex_lock(&tp->control);
6001
6002         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
6003                                 cmd->base.duplex, advertising);
6004         if (!ret) {
6005                 tp->autoneg = cmd->base.autoneg;
6006                 tp->speed = cmd->base.speed;
6007                 tp->duplex = cmd->base.duplex;
6008                 tp->advertising = advertising;
6009         }
6010
6011         mutex_unlock(&tp->control);
6012
6013         usb_autopm_put_interface(tp->intf);
6014
6015 out:
6016         return ret;
6017 }
6018
6019 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6020         "tx_packets",
6021         "rx_packets",
6022         "tx_errors",
6023         "rx_errors",
6024         "rx_missed",
6025         "align_errors",
6026         "tx_single_collisions",
6027         "tx_multi_collisions",
6028         "rx_unicast",
6029         "rx_broadcast",
6030         "rx_multicast",
6031         "tx_aborted",
6032         "tx_underrun",
6033 };
6034
6035 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6036 {
6037         switch (sset) {
6038         case ETH_SS_STATS:
6039                 return ARRAY_SIZE(rtl8152_gstrings);
6040         default:
6041                 return -EOPNOTSUPP;
6042         }
6043 }
6044
6045 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6046                                       struct ethtool_stats *stats, u64 *data)
6047 {
6048         struct r8152 *tp = netdev_priv(dev);
6049         struct tally_counter tally;
6050
6051         if (usb_autopm_get_interface(tp->intf) < 0)
6052                 return;
6053
6054         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6055
6056         usb_autopm_put_interface(tp->intf);
6057
6058         data[0] = le64_to_cpu(tally.tx_packets);
6059         data[1] = le64_to_cpu(tally.rx_packets);
6060         data[2] = le64_to_cpu(tally.tx_errors);
6061         data[3] = le32_to_cpu(tally.rx_errors);
6062         data[4] = le16_to_cpu(tally.rx_missed);
6063         data[5] = le16_to_cpu(tally.align_errors);
6064         data[6] = le32_to_cpu(tally.tx_one_collision);
6065         data[7] = le32_to_cpu(tally.tx_multi_collision);
6066         data[8] = le64_to_cpu(tally.rx_unicast);
6067         data[9] = le64_to_cpu(tally.rx_broadcast);
6068         data[10] = le32_to_cpu(tally.rx_multicast);
6069         data[11] = le16_to_cpu(tally.tx_aborted);
6070         data[12] = le16_to_cpu(tally.tx_underrun);
6071 }
6072
6073 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6074 {
6075         switch (stringset) {
6076         case ETH_SS_STATS:
6077                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6078                 break;
6079         }
6080 }
6081
6082 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6083 {
6084         u32 lp, adv, supported = 0;
6085         u16 val;
6086
6087         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6088         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6089
6090         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6091         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6092
6093         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6094         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6095
6096         eee->eee_enabled = tp->eee_en;
6097         eee->eee_active = !!(supported & adv & lp);
6098         eee->supported = supported;
6099         eee->advertised = tp->eee_adv;
6100         eee->lp_advertised = lp;
6101
6102         return 0;
6103 }
6104
6105 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6106 {
6107         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6108
6109         tp->eee_en = eee->eee_enabled;
6110         tp->eee_adv = val;
6111
6112         rtl_eee_enable(tp, tp->eee_en);
6113
6114         return 0;
6115 }
6116
6117 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6118 {
6119         u32 lp, adv, supported = 0;
6120         u16 val;
6121
6122         val = ocp_reg_read(tp, OCP_EEE_ABLE);
6123         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6124
6125         val = ocp_reg_read(tp, OCP_EEE_ADV);
6126         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6127
6128         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6129         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6130
6131         eee->eee_enabled = tp->eee_en;
6132         eee->eee_active = !!(supported & adv & lp);
6133         eee->supported = supported;
6134         eee->advertised = tp->eee_adv;
6135         eee->lp_advertised = lp;
6136
6137         return 0;
6138 }
6139
6140 static int
6141 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6142 {
6143         struct r8152 *tp = netdev_priv(net);
6144         int ret;
6145
6146         ret = usb_autopm_get_interface(tp->intf);
6147         if (ret < 0)
6148                 goto out;
6149
6150         mutex_lock(&tp->control);
6151
6152         ret = tp->rtl_ops.eee_get(tp, edata);
6153
6154         mutex_unlock(&tp->control);
6155
6156         usb_autopm_put_interface(tp->intf);
6157
6158 out:
6159         return ret;
6160 }
6161
6162 static int
6163 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6164 {
6165         struct r8152 *tp = netdev_priv(net);
6166         int ret;
6167
6168         ret = usb_autopm_get_interface(tp->intf);
6169         if (ret < 0)
6170                 goto out;
6171
6172         mutex_lock(&tp->control);
6173
6174         ret = tp->rtl_ops.eee_set(tp, edata);
6175         if (!ret)
6176                 ret = mii_nway_restart(&tp->mii);
6177
6178         mutex_unlock(&tp->control);
6179
6180         usb_autopm_put_interface(tp->intf);
6181
6182 out:
6183         return ret;
6184 }
6185
6186 static int rtl8152_nway_reset(struct net_device *dev)
6187 {
6188         struct r8152 *tp = netdev_priv(dev);
6189         int ret;
6190
6191         ret = usb_autopm_get_interface(tp->intf);
6192         if (ret < 0)
6193                 goto out;
6194
6195         mutex_lock(&tp->control);
6196
6197         ret = mii_nway_restart(&tp->mii);
6198
6199         mutex_unlock(&tp->control);
6200
6201         usb_autopm_put_interface(tp->intf);
6202
6203 out:
6204         return ret;
6205 }
6206
6207 static int rtl8152_get_coalesce(struct net_device *netdev,
6208                                 struct ethtool_coalesce *coalesce)
6209 {
6210         struct r8152 *tp = netdev_priv(netdev);
6211
6212         switch (tp->version) {
6213         case RTL_VER_01:
6214         case RTL_VER_02:
6215         case RTL_VER_07:
6216                 return -EOPNOTSUPP;
6217         default:
6218                 break;
6219         }
6220
6221         coalesce->rx_coalesce_usecs = tp->coalesce;
6222
6223         return 0;
6224 }
6225
6226 static int rtl8152_set_coalesce(struct net_device *netdev,
6227                                 struct ethtool_coalesce *coalesce)
6228 {
6229         struct r8152 *tp = netdev_priv(netdev);
6230         int ret;
6231
6232         switch (tp->version) {
6233         case RTL_VER_01:
6234         case RTL_VER_02:
6235         case RTL_VER_07:
6236                 return -EOPNOTSUPP;
6237         default:
6238                 break;
6239         }
6240
6241         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6242                 return -EINVAL;
6243
6244         ret = usb_autopm_get_interface(tp->intf);
6245         if (ret < 0)
6246                 return ret;
6247
6248         mutex_lock(&tp->control);
6249
6250         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6251                 tp->coalesce = coalesce->rx_coalesce_usecs;
6252
6253                 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6254                         netif_stop_queue(netdev);
6255                         napi_disable(&tp->napi);
6256                         tp->rtl_ops.disable(tp);
6257                         tp->rtl_ops.enable(tp);
6258                         rtl_start_rx(tp);
6259                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6260                         _rtl8152_set_rx_mode(netdev);
6261                         napi_enable(&tp->napi);
6262                         netif_wake_queue(netdev);
6263                 }
6264         }
6265
6266         mutex_unlock(&tp->control);
6267
6268         usb_autopm_put_interface(tp->intf);
6269
6270         return ret;
6271 }
6272
6273 static int rtl8152_get_tunable(struct net_device *netdev,
6274                                const struct ethtool_tunable *tunable, void *d)
6275 {
6276         struct r8152 *tp = netdev_priv(netdev);
6277
6278         switch (tunable->id) {
6279         case ETHTOOL_RX_COPYBREAK:
6280                 *(u32 *)d = tp->rx_copybreak;
6281                 break;
6282         default:
6283                 return -EOPNOTSUPP;
6284         }
6285
6286         return 0;
6287 }
6288
6289 static int rtl8152_set_tunable(struct net_device *netdev,
6290                                const struct ethtool_tunable *tunable,
6291                                const void *d)
6292 {
6293         struct r8152 *tp = netdev_priv(netdev);
6294         u32 val;
6295
6296         switch (tunable->id) {
6297         case ETHTOOL_RX_COPYBREAK:
6298                 val = *(u32 *)d;
6299                 if (val < ETH_ZLEN) {
6300                         netif_err(tp, rx_err, netdev,
6301                                   "Invalid rx copy break value\n");
6302                         return -EINVAL;
6303                 }
6304
6305                 if (tp->rx_copybreak != val) {
6306                         if (netdev->flags & IFF_UP) {
6307                                 mutex_lock(&tp->control);
6308                                 napi_disable(&tp->napi);
6309                                 tp->rx_copybreak = val;
6310                                 napi_enable(&tp->napi);
6311                                 mutex_unlock(&tp->control);
6312                         } else {
6313                                 tp->rx_copybreak = val;
6314                         }
6315                 }
6316                 break;
6317         default:
6318                 return -EOPNOTSUPP;
6319         }
6320
6321         return 0;
6322 }
6323
6324 static void rtl8152_get_ringparam(struct net_device *netdev,
6325                                   struct ethtool_ringparam *ring)
6326 {
6327         struct r8152 *tp = netdev_priv(netdev);
6328
6329         ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6330         ring->rx_pending = tp->rx_pending;
6331 }
6332
6333 static int rtl8152_set_ringparam(struct net_device *netdev,
6334                                  struct ethtool_ringparam *ring)
6335 {
6336         struct r8152 *tp = netdev_priv(netdev);
6337
6338         if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6339                 return -EINVAL;
6340
6341         if (tp->rx_pending != ring->rx_pending) {
6342                 if (netdev->flags & IFF_UP) {
6343                         mutex_lock(&tp->control);
6344                         napi_disable(&tp->napi);
6345                         tp->rx_pending = ring->rx_pending;
6346                         napi_enable(&tp->napi);
6347                         mutex_unlock(&tp->control);
6348                 } else {
6349                         tp->rx_pending = ring->rx_pending;
6350                 }
6351         }
6352
6353         return 0;
6354 }
6355
6356 static const struct ethtool_ops ops = {
6357         .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6358         .get_drvinfo = rtl8152_get_drvinfo,
6359         .get_link = ethtool_op_get_link,
6360         .nway_reset = rtl8152_nway_reset,
6361         .get_msglevel = rtl8152_get_msglevel,
6362         .set_msglevel = rtl8152_set_msglevel,
6363         .get_wol = rtl8152_get_wol,
6364         .set_wol = rtl8152_set_wol,
6365         .get_strings = rtl8152_get_strings,
6366         .get_sset_count = rtl8152_get_sset_count,
6367         .get_ethtool_stats = rtl8152_get_ethtool_stats,
6368         .get_coalesce = rtl8152_get_coalesce,
6369         .set_coalesce = rtl8152_set_coalesce,
6370         .get_eee = rtl_ethtool_get_eee,
6371         .set_eee = rtl_ethtool_set_eee,
6372         .get_link_ksettings = rtl8152_get_link_ksettings,
6373         .set_link_ksettings = rtl8152_set_link_ksettings,
6374         .get_tunable = rtl8152_get_tunable,
6375         .set_tunable = rtl8152_set_tunable,
6376         .get_ringparam = rtl8152_get_ringparam,
6377         .set_ringparam = rtl8152_set_ringparam,
6378 };
6379
6380 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6381 {
6382         struct r8152 *tp = netdev_priv(netdev);
6383         struct mii_ioctl_data *data = if_mii(rq);
6384         int res;
6385
6386         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6387                 return -ENODEV;
6388
6389         res = usb_autopm_get_interface(tp->intf);
6390         if (res < 0)
6391                 goto out;
6392
6393         switch (cmd) {
6394         case SIOCGMIIPHY:
6395                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6396                 break;
6397
6398         case SIOCGMIIREG:
6399                 mutex_lock(&tp->control);
6400                 data->val_out = r8152_mdio_read(tp, data->reg_num);
6401                 mutex_unlock(&tp->control);
6402                 break;
6403
6404         case SIOCSMIIREG:
6405                 if (!capable(CAP_NET_ADMIN)) {
6406                         res = -EPERM;
6407                         break;
6408                 }
6409                 mutex_lock(&tp->control);
6410                 r8152_mdio_write(tp, data->reg_num, data->val_in);
6411                 mutex_unlock(&tp->control);
6412                 break;
6413
6414         default:
6415                 res = -EOPNOTSUPP;
6416         }
6417
6418         usb_autopm_put_interface(tp->intf);
6419
6420 out:
6421         return res;
6422 }
6423
6424 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6425 {
6426         struct r8152 *tp = netdev_priv(dev);
6427         int ret;
6428
6429         switch (tp->version) {
6430         case RTL_VER_01:
6431         case RTL_VER_02:
6432         case RTL_VER_07:
6433                 dev->mtu = new_mtu;
6434                 return 0;
6435         default:
6436                 break;
6437         }
6438
6439         ret = usb_autopm_get_interface(tp->intf);
6440         if (ret < 0)
6441                 return ret;
6442
6443         mutex_lock(&tp->control);
6444
6445         dev->mtu = new_mtu;
6446
6447         if (netif_running(dev)) {
6448                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6449
6450                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6451
6452                 if (netif_carrier_ok(dev))
6453                         r8153_set_rx_early_size(tp);
6454         }
6455
6456         mutex_unlock(&tp->control);
6457
6458         usb_autopm_put_interface(tp->intf);
6459
6460         return ret;
6461 }
6462
6463 static const struct net_device_ops rtl8152_netdev_ops = {
6464         .ndo_open               = rtl8152_open,
6465         .ndo_stop               = rtl8152_close,
6466         .ndo_do_ioctl           = rtl8152_ioctl,
6467         .ndo_start_xmit         = rtl8152_start_xmit,
6468         .ndo_tx_timeout         = rtl8152_tx_timeout,
6469         .ndo_set_features       = rtl8152_set_features,
6470         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
6471         .ndo_set_mac_address    = rtl8152_set_mac_address,
6472         .ndo_change_mtu         = rtl8152_change_mtu,
6473         .ndo_validate_addr      = eth_validate_addr,
6474         .ndo_features_check     = rtl8152_features_check,
6475 };
6476
6477 static void rtl8152_unload(struct r8152 *tp)
6478 {
6479         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6480                 return;
6481
6482         if (tp->version != RTL_VER_01)
6483                 r8152_power_cut_en(tp, true);
6484 }
6485
6486 static void rtl8153_unload(struct r8152 *tp)
6487 {
6488         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6489                 return;
6490
6491         r8153_power_cut_en(tp, false);
6492 }
6493
6494 static void rtl8153b_unload(struct r8152 *tp)
6495 {
6496         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6497                 return;
6498
6499         r8153b_power_cut_en(tp, false);
6500 }
6501
6502 static int rtl_ops_init(struct r8152 *tp)
6503 {
6504         struct rtl_ops *ops = &tp->rtl_ops;
6505         int ret = 0;
6506
6507         switch (tp->version) {
6508         case RTL_VER_01:
6509         case RTL_VER_02:
6510         case RTL_VER_07:
6511                 ops->init               = r8152b_init;
6512                 ops->enable             = rtl8152_enable;
6513                 ops->disable            = rtl8152_disable;
6514                 ops->up                 = rtl8152_up;
6515                 ops->down               = rtl8152_down;
6516                 ops->unload             = rtl8152_unload;
6517                 ops->eee_get            = r8152_get_eee;
6518                 ops->eee_set            = r8152_set_eee;
6519                 ops->in_nway            = rtl8152_in_nway;
6520                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
6521                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
6522                 tp->rx_buf_sz           = 16 * 1024;
6523                 tp->eee_en              = true;
6524                 tp->eee_adv             = MDIO_EEE_100TX;
6525                 break;
6526
6527         case RTL_VER_03:
6528         case RTL_VER_04:
6529         case RTL_VER_05:
6530         case RTL_VER_06:
6531                 ops->init               = r8153_init;
6532                 ops->enable             = rtl8153_enable;
6533                 ops->disable            = rtl8153_disable;
6534                 ops->up                 = rtl8153_up;
6535                 ops->down               = rtl8153_down;
6536                 ops->unload             = rtl8153_unload;
6537                 ops->eee_get            = r8153_get_eee;
6538                 ops->eee_set            = r8152_set_eee;
6539                 ops->in_nway            = rtl8153_in_nway;
6540                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
6541                 ops->autosuspend_en     = rtl8153_runtime_enable;
6542                 tp->rx_buf_sz           = 32 * 1024;
6543                 tp->eee_en              = true;
6544                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6545                 break;
6546
6547         case RTL_VER_08:
6548         case RTL_VER_09:
6549                 ops->init               = r8153b_init;
6550                 ops->enable             = rtl8153_enable;
6551                 ops->disable            = rtl8153_disable;
6552                 ops->up                 = rtl8153b_up;
6553                 ops->down               = rtl8153b_down;
6554                 ops->unload             = rtl8153b_unload;
6555                 ops->eee_get            = r8153_get_eee;
6556                 ops->eee_set            = r8152_set_eee;
6557                 ops->in_nway            = rtl8153_in_nway;
6558                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
6559                 ops->autosuspend_en     = rtl8153b_runtime_enable;
6560                 tp->rx_buf_sz           = 32 * 1024;
6561                 tp->eee_en              = true;
6562                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6563                 break;
6564
6565         default:
6566                 ret = -ENODEV;
6567                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6568                 break;
6569         }
6570
6571         return ret;
6572 }
6573
6574 #define FIRMWARE_8153A_2        "rtl_nic/rtl8153a-2.fw"
6575 #define FIRMWARE_8153A_3        "rtl_nic/rtl8153a-3.fw"
6576 #define FIRMWARE_8153A_4        "rtl_nic/rtl8153a-4.fw"
6577 #define FIRMWARE_8153B_2        "rtl_nic/rtl8153b-2.fw"
6578
6579 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6580 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6581 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6582 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6583
6584 static int rtl_fw_init(struct r8152 *tp)
6585 {
6586         struct rtl_fw *rtl_fw = &tp->rtl_fw;
6587
6588         switch (tp->version) {
6589         case RTL_VER_04:
6590                 rtl_fw->fw_name         = FIRMWARE_8153A_2;
6591                 rtl_fw->pre_fw          = r8153_pre_firmware_1;
6592                 rtl_fw->post_fw         = r8153_post_firmware_1;
6593                 break;
6594         case RTL_VER_05:
6595                 rtl_fw->fw_name         = FIRMWARE_8153A_3;
6596                 rtl_fw->pre_fw          = r8153_pre_firmware_2;
6597                 rtl_fw->post_fw         = r8153_post_firmware_2;
6598                 break;
6599         case RTL_VER_06:
6600                 rtl_fw->fw_name         = FIRMWARE_8153A_4;
6601                 rtl_fw->post_fw         = r8153_post_firmware_3;
6602                 break;
6603         case RTL_VER_09:
6604                 rtl_fw->fw_name         = FIRMWARE_8153B_2;
6605                 rtl_fw->pre_fw          = r8153b_pre_firmware_1;
6606                 rtl_fw->post_fw         = r8153b_post_firmware_1;
6607                 break;
6608         default:
6609                 break;
6610         }
6611
6612         return 0;
6613 }
6614
6615 u8 rtl8152_get_version(struct usb_interface *intf)
6616 {
6617         struct usb_device *udev = interface_to_usbdev(intf);
6618         u32 ocp_data = 0;
6619         __le32 *tmp;
6620         u8 version;
6621         int ret;
6622
6623         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6624         if (!tmp)
6625                 return 0;
6626
6627         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6628                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6629                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6630         if (ret > 0)
6631                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6632
6633         kfree(tmp);
6634
6635         switch (ocp_data) {
6636         case 0x4c00:
6637                 version = RTL_VER_01;
6638                 break;
6639         case 0x4c10:
6640                 version = RTL_VER_02;
6641                 break;
6642         case 0x5c00:
6643                 version = RTL_VER_03;
6644                 break;
6645         case 0x5c10:
6646                 version = RTL_VER_04;
6647                 break;
6648         case 0x5c20:
6649                 version = RTL_VER_05;
6650                 break;
6651         case 0x5c30:
6652                 version = RTL_VER_06;
6653                 break;
6654         case 0x4800:
6655                 version = RTL_VER_07;
6656                 break;
6657         case 0x6000:
6658                 version = RTL_VER_08;
6659                 break;
6660         case 0x6010:
6661                 version = RTL_VER_09;
6662                 break;
6663         default:
6664                 version = RTL_VER_UNKNOWN;
6665                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6666                 break;
6667         }
6668
6669         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6670
6671         return version;
6672 }
6673 EXPORT_SYMBOL_GPL(rtl8152_get_version);
6674
6675 static int rtl8152_probe(struct usb_interface *intf,
6676                          const struct usb_device_id *id)
6677 {
6678         struct usb_device *udev = interface_to_usbdev(intf);
6679         u8 version = rtl8152_get_version(intf);
6680         struct r8152 *tp;
6681         struct net_device *netdev;
6682         int ret;
6683
6684         if (version == RTL_VER_UNKNOWN)
6685                 return -ENODEV;
6686
6687         if (udev->actconfig->desc.bConfigurationValue != 1) {
6688                 usb_driver_set_configuration(udev, 1);
6689                 return -ENODEV;
6690         }
6691
6692         if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6693                 return -ENODEV;
6694
6695         usb_reset_device(udev);
6696         netdev = alloc_etherdev(sizeof(struct r8152));
6697         if (!netdev) {
6698                 dev_err(&intf->dev, "Out of memory\n");
6699                 return -ENOMEM;
6700         }
6701
6702         SET_NETDEV_DEV(netdev, &intf->dev);
6703         tp = netdev_priv(netdev);
6704         tp->msg_enable = 0x7FFF;
6705
6706         tp->udev = udev;
6707         tp->netdev = netdev;
6708         tp->intf = intf;
6709         tp->version = version;
6710
6711         switch (version) {
6712         case RTL_VER_01:
6713         case RTL_VER_02:
6714         case RTL_VER_07:
6715                 tp->mii.supports_gmii = 0;
6716                 break;
6717         default:
6718                 tp->mii.supports_gmii = 1;
6719                 break;
6720         }
6721
6722         ret = rtl_ops_init(tp);
6723         if (ret)
6724                 goto out;
6725
6726         rtl_fw_init(tp);
6727
6728         mutex_init(&tp->control);
6729         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6730         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6731         tasklet_setup(&tp->tx_tl, bottom_half);
6732         tasklet_disable(&tp->tx_tl);
6733
6734         netdev->netdev_ops = &rtl8152_netdev_ops;
6735         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6736
6737         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6738                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6739                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6740                             NETIF_F_HW_VLAN_CTAG_TX;
6741         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6742                               NETIF_F_TSO | NETIF_F_FRAGLIST |
6743                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6744                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6745         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6746                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6747                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6748
6749         if (tp->version == RTL_VER_01) {
6750                 netdev->features &= ~NETIF_F_RXCSUM;
6751                 netdev->hw_features &= ~NETIF_F_RXCSUM;
6752         }
6753
6754         if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6755                 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6756                 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6757                 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6758                         set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6759                 }
6760         }
6761
6762         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6763             (!strcmp(udev->serial, "000001000000") ||
6764              !strcmp(udev->serial, "000002000000"))) {
6765                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6766                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6767         }
6768
6769         netdev->ethtool_ops = &ops;
6770         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6771
6772         /* MTU range: 68 - 1500 or 9194 */
6773         netdev->min_mtu = ETH_MIN_MTU;
6774         switch (tp->version) {
6775         case RTL_VER_01:
6776         case RTL_VER_02:
6777                 netdev->max_mtu = ETH_DATA_LEN;
6778                 break;
6779         default:
6780                 netdev->max_mtu = RTL8153_MAX_MTU;
6781                 break;
6782         }
6783
6784         tp->mii.dev = netdev;
6785         tp->mii.mdio_read = read_mii_word;
6786         tp->mii.mdio_write = write_mii_word;
6787         tp->mii.phy_id_mask = 0x3f;
6788         tp->mii.reg_num_mask = 0x1f;
6789         tp->mii.phy_id = R8152_PHY_ID;
6790
6791         tp->autoneg = AUTONEG_ENABLE;
6792         tp->speed = SPEED_100;
6793         tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6794                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6795         if (tp->mii.supports_gmii) {
6796                 tp->speed = SPEED_1000;
6797                 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6798         }
6799         tp->duplex = DUPLEX_FULL;
6800
6801         tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6802         tp->rx_pending = 10 * RTL8152_MAX_RX;
6803
6804         intf->needs_remote_wakeup = 1;
6805
6806         if (!rtl_can_wakeup(tp))
6807                 __rtl_set_wol(tp, 0);
6808         else
6809                 tp->saved_wolopts = __rtl_get_wol(tp);
6810
6811         tp->rtl_ops.init(tp);
6812 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6813         /* Retry in case request_firmware() is not ready yet. */
6814         tp->rtl_fw.retry = true;
6815 #endif
6816         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6817         set_ethernet_addr(tp);
6818
6819         usb_set_intfdata(intf, tp);
6820         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6821
6822         ret = register_netdev(netdev);
6823         if (ret != 0) {
6824                 netif_err(tp, probe, netdev, "couldn't register the device\n");
6825                 goto out1;
6826         }
6827
6828         if (tp->saved_wolopts)
6829                 device_set_wakeup_enable(&udev->dev, true);
6830         else
6831                 device_set_wakeup_enable(&udev->dev, false);
6832
6833         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6834
6835         return 0;
6836
6837 out1:
6838         tasklet_kill(&tp->tx_tl);
6839         usb_set_intfdata(intf, NULL);
6840 out:
6841         free_netdev(netdev);
6842         return ret;
6843 }
6844
6845 static void rtl8152_disconnect(struct usb_interface *intf)
6846 {
6847         struct r8152 *tp = usb_get_intfdata(intf);
6848
6849         usb_set_intfdata(intf, NULL);
6850         if (tp) {
6851                 rtl_set_unplug(tp);
6852
6853                 unregister_netdev(tp->netdev);
6854                 tasklet_kill(&tp->tx_tl);
6855                 cancel_delayed_work_sync(&tp->hw_phy_work);
6856                 tp->rtl_ops.unload(tp);
6857                 rtl8152_release_firmware(tp);
6858                 free_netdev(tp->netdev);
6859         }
6860 }
6861
6862 #define REALTEK_USB_DEVICE(vend, prod)  \
6863         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6864                        USB_DEVICE_ID_MATCH_INT_CLASS, \
6865         .idVendor = (vend), \
6866         .idProduct = (prod), \
6867         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6868 }, \
6869 { \
6870         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6871                        USB_DEVICE_ID_MATCH_DEVICE, \
6872         .idVendor = (vend), \
6873         .idProduct = (prod), \
6874         .bInterfaceClass = USB_CLASS_COMM, \
6875         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6876         .bInterfaceProtocol = USB_CDC_PROTO_NONE
6877
6878 /* table of devices that work with this driver */
6879 static const struct usb_device_id rtl8152_table[] = {
6880         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6881         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6882         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6883         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6884         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6885         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6886         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6887         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6888         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6889         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6890         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6891         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6892         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6893         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6894         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e)},
6895         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6896         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6897         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6898         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6899         {}
6900 };
6901
6902 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6903
6904 static struct usb_driver rtl8152_driver = {
6905         .name =         MODULENAME,
6906         .id_table =     rtl8152_table,
6907         .probe =        rtl8152_probe,
6908         .disconnect =   rtl8152_disconnect,
6909         .suspend =      rtl8152_suspend,
6910         .resume =       rtl8152_resume,
6911         .reset_resume = rtl8152_reset_resume,
6912         .pre_reset =    rtl8152_pre_reset,
6913         .post_reset =   rtl8152_post_reset,
6914         .supports_autosuspend = 1,
6915         .disable_hub_initiated_lpm = 1,
6916 };
6917
6918 module_usb_driver(rtl8152_driver);
6919
6920 MODULE_AUTHOR(DRIVER_AUTHOR);
6921 MODULE_DESCRIPTION(DRIVER_DESC);
6922 MODULE_LICENSE("GPL");
6923 MODULE_VERSION(DRIVER_VERSION);