1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
30 /* Information for net-next */
31 #define NETNEXT_VERSION "11"
33 /* Information for net */
34 #define NET_VERSION "10"
36 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
41 #define R8152_PHY_ID 32
43 #define PLA_IDR 0xc000
44 #define PLA_RCR 0xc010
45 #define PLA_RMS 0xc016
46 #define PLA_RXFIFO_CTRL0 0xc0a0
47 #define PLA_RXFIFO_CTRL1 0xc0a4
48 #define PLA_RXFIFO_CTRL2 0xc0a8
49 #define PLA_DMY_REG0 0xc0b0
50 #define PLA_FMC 0xc0b4
51 #define PLA_CFG_WOL 0xc0b6
52 #define PLA_TEREDO_CFG 0xc0bc
53 #define PLA_TEREDO_WAKE_BASE 0xc0c4
54 #define PLA_MAR 0xcd00
55 #define PLA_BACKUP 0xd000
56 #define PLA_BDC_CR 0xd1a0
57 #define PLA_TEREDO_TIMER 0xd2cc
58 #define PLA_REALWOW_TIMER 0xd2e8
59 #define PLA_UPHY_TIMER 0xd388
60 #define PLA_SUSPEND_FLAG 0xd38a
61 #define PLA_INDICATE_FALG 0xd38c
62 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS 0xd398
65 #define PLA_EFUSE_DATA 0xdd00
66 #define PLA_EFUSE_CMD 0xdd02
67 #define PLA_LEDSEL 0xdd90
68 #define PLA_LED_FEATURE 0xdd92
69 #define PLA_PHYAR 0xde00
70 #define PLA_BOOT_CTRL 0xe004
71 #define PLA_GPHY_INTR_IMR 0xe022
72 #define PLA_EEE_CR 0xe040
73 #define PLA_EEEP_CR 0xe080
74 #define PLA_MAC_PWR_CTRL 0xe0c0
75 #define PLA_MAC_PWR_CTRL2 0xe0ca
76 #define PLA_MAC_PWR_CTRL3 0xe0cc
77 #define PLA_MAC_PWR_CTRL4 0xe0ce
78 #define PLA_WDT6_CTRL 0xe428
79 #define PLA_TCR0 0xe610
80 #define PLA_TCR1 0xe612
81 #define PLA_MTPS 0xe615
82 #define PLA_TXFIFO_CTRL 0xe618
83 #define PLA_RSTTALLY 0xe800
85 #define PLA_CRWECR 0xe81c
86 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
87 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
88 #define PLA_CONFIG5 0xe822
89 #define PLA_PHY_PWR 0xe84c
90 #define PLA_OOB_CTRL 0xe84f
91 #define PLA_CPCR 0xe854
92 #define PLA_MISC_0 0xe858
93 #define PLA_MISC_1 0xe85a
94 #define PLA_OCP_GPHY_BASE 0xe86c
95 #define PLA_TALLYCNT 0xe890
96 #define PLA_SFF_STS_7 0xe8de
97 #define PLA_PHYSTATUS 0xe908
98 #define PLA_BP_BA 0xfc26
99 #define PLA_BP_0 0xfc28
100 #define PLA_BP_1 0xfc2a
101 #define PLA_BP_2 0xfc2c
102 #define PLA_BP_3 0xfc2e
103 #define PLA_BP_4 0xfc30
104 #define PLA_BP_5 0xfc32
105 #define PLA_BP_6 0xfc34
106 #define PLA_BP_7 0xfc36
107 #define PLA_BP_EN 0xfc38
109 #define USB_USB2PHY 0xb41e
110 #define USB_SSPHYLINK2 0xb428
111 #define USB_U2P3_CTRL 0xb460
112 #define USB_CSR_DUMMY1 0xb464
113 #define USB_CSR_DUMMY2 0xb466
114 #define USB_DEV_STAT 0xb808
115 #define USB_CONNECT_TIMER 0xcbf8
116 #define USB_MSC_TIMER 0xcbfc
117 #define USB_BURST_SIZE 0xcfc0
118 #define USB_FW_FIX_EN0 0xcfca
119 #define USB_FW_FIX_EN1 0xcfcc
120 #define USB_LPM_CONFIG 0xcfd8
121 #define USB_CSTMR 0xcfef /* RTL8153A */
122 #define USB_FW_CTRL 0xd334 /* RTL8153B */
123 #define USB_FC_TIMER 0xd340
124 #define USB_USB_CTRL 0xd406
125 #define USB_PHY_CTRL 0xd408
126 #define USB_TX_AGG 0xd40a
127 #define USB_RX_BUF_TH 0xd40c
128 #define USB_USB_TIMER 0xd428
129 #define USB_RX_EARLY_TIMEOUT 0xd42c
130 #define USB_RX_EARLY_SIZE 0xd42e
131 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
132 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
133 #define USB_TX_DMA 0xd434
134 #define USB_UPT_RXDMA_OWN 0xd437
135 #define USB_TOLERANCE 0xd490
136 #define USB_LPM_CTRL 0xd41a
137 #define USB_BMU_RESET 0xd4b0
138 #define USB_U1U2_TIMER 0xd4da
139 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
140 #define USB_UPS_CTRL 0xd800
141 #define USB_POWER_CUT 0xd80a
142 #define USB_MISC_0 0xd81a
143 #define USB_MISC_1 0xd81f
144 #define USB_AFE_CTRL2 0xd824
145 #define USB_UPS_CFG 0xd842
146 #define USB_UPS_FLAGS 0xd848
147 #define USB_WDT1_CTRL 0xe404
148 #define USB_WDT11_CTRL 0xe43c
149 #define USB_BP_BA PLA_BP_BA
150 #define USB_BP_0 PLA_BP_0
151 #define USB_BP_1 PLA_BP_1
152 #define USB_BP_2 PLA_BP_2
153 #define USB_BP_3 PLA_BP_3
154 #define USB_BP_4 PLA_BP_4
155 #define USB_BP_5 PLA_BP_5
156 #define USB_BP_6 PLA_BP_6
157 #define USB_BP_7 PLA_BP_7
158 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
159 #define USB_BP_8 0xfc38 /* RTL8153B */
160 #define USB_BP_9 0xfc3a
161 #define USB_BP_10 0xfc3c
162 #define USB_BP_11 0xfc3e
163 #define USB_BP_12 0xfc40
164 #define USB_BP_13 0xfc42
165 #define USB_BP_14 0xfc44
166 #define USB_BP_15 0xfc46
167 #define USB_BP2_EN 0xfc48
170 #define OCP_ALDPS_CONFIG 0x2010
171 #define OCP_EEE_CONFIG1 0x2080
172 #define OCP_EEE_CONFIG2 0x2092
173 #define OCP_EEE_CONFIG3 0x2094
174 #define OCP_BASE_MII 0xa400
175 #define OCP_EEE_AR 0xa41a
176 #define OCP_EEE_DATA 0xa41c
177 #define OCP_PHY_STATUS 0xa420
178 #define OCP_NCTL_CFG 0xa42c
179 #define OCP_POWER_CFG 0xa430
180 #define OCP_EEE_CFG 0xa432
181 #define OCP_SRAM_ADDR 0xa436
182 #define OCP_SRAM_DATA 0xa438
183 #define OCP_DOWN_SPEED 0xa442
184 #define OCP_EEE_ABLE 0xa5c4
185 #define OCP_EEE_ADV 0xa5d0
186 #define OCP_EEE_LPABLE 0xa5d2
187 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
188 #define OCP_PHY_PATCH_STAT 0xb800
189 #define OCP_PHY_PATCH_CMD 0xb820
190 #define OCP_PHY_LOCK 0xb82e
191 #define OCP_ADC_IOFFSET 0xbcfc
192 #define OCP_ADC_CFG 0xbc06
193 #define OCP_SYSCLK_CFG 0xc416
196 #define SRAM_GREEN_CFG 0x8011
197 #define SRAM_LPF_CFG 0x8012
198 #define SRAM_10M_AMP1 0x8080
199 #define SRAM_10M_AMP2 0x8082
200 #define SRAM_IMPEDANCE 0x8084
201 #define SRAM_PHY_LOCK 0xb82e
204 #define RCR_AAP 0x00000001
205 #define RCR_APM 0x00000002
206 #define RCR_AM 0x00000004
207 #define RCR_AB 0x00000008
208 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
210 /* PLA_RXFIFO_CTRL0 */
211 #define RXFIFO_THR1_NORMAL 0x00080002
212 #define RXFIFO_THR1_OOB 0x01800003
214 /* PLA_RXFIFO_CTRL1 */
215 #define RXFIFO_THR2_FULL 0x00000060
216 #define RXFIFO_THR2_HIGH 0x00000038
217 #define RXFIFO_THR2_OOB 0x0000004a
218 #define RXFIFO_THR2_NORMAL 0x00a0
220 /* PLA_RXFIFO_CTRL2 */
221 #define RXFIFO_THR3_FULL 0x00000078
222 #define RXFIFO_THR3_HIGH 0x00000048
223 #define RXFIFO_THR3_OOB 0x0000005a
224 #define RXFIFO_THR3_NORMAL 0x0110
226 /* PLA_TXFIFO_CTRL */
227 #define TXFIFO_THR_NORMAL 0x00400008
228 #define TXFIFO_THR_NORMAL2 0x01000008
231 #define ECM_ALDPS 0x0002
234 #define FMC_FCR_MCU_EN 0x0001
237 #define EEEP_CR_EEEP_TX 0x0002
240 #define WDT6_SET_MODE 0x0010
243 #define TCR0_TX_EMPTY 0x0800
244 #define TCR0_AUTO_FIFO 0x0080
247 #define VERSION_MASK 0x7cf0
250 #define MTPS_JUMBO (12 * 1024 / 64)
251 #define MTPS_DEFAULT (6 * 1024 / 64)
254 #define TALLY_RESET 0x0001
262 #define CRWECR_NORAML 0x00
263 #define CRWECR_CONFIG 0xc0
266 #define NOW_IS_OOB 0x80
267 #define TXFIFO_EMPTY 0x20
268 #define RXFIFO_EMPTY 0x10
269 #define LINK_LIST_READY 0x02
270 #define DIS_MCU_CLROOB 0x01
271 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
274 #define RXDY_GATED_EN 0x0008
277 #define RE_INIT_LL 0x8000
278 #define MCU_BORW_EN 0x4000
281 #define CPCR_RX_VLAN 0x0040
284 #define MAGIC_EN 0x0001
287 #define TEREDO_SEL 0x8000
288 #define TEREDO_WAKE_MASK 0x7f00
289 #define TEREDO_RS_EVENT_MASK 0x00fe
290 #define OOB_TEREDO_EN 0x0001
293 #define ALDPS_PROXY_MODE 0x0001
296 #define EFUSE_READ_CMD BIT(15)
297 #define EFUSE_DATA_BIT16 BIT(7)
300 #define LINK_ON_WAKE_EN 0x0010
301 #define LINK_OFF_WAKE_EN 0x0008
304 #define BWF_EN 0x0040
305 #define MWF_EN 0x0020
306 #define UWF_EN 0x0010
307 #define LAN_WAKE_EN 0x0002
309 /* PLA_LED_FEATURE */
310 #define LED_MODE_MASK 0x0700
313 #define TX_10M_IDLE_EN 0x0080
314 #define PFM_PWM_SWITCH 0x0040
316 /* PLA_MAC_PWR_CTRL */
317 #define D3_CLK_GATED_EN 0x00004000
318 #define MCU_CLK_RATIO 0x07010f07
319 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
320 #define ALDPS_SPDWN_RATIO 0x0f87
322 /* PLA_MAC_PWR_CTRL2 */
323 #define EEE_SPDWN_RATIO 0x8007
324 #define MAC_CLK_SPDWN_EN BIT(15)
326 /* PLA_MAC_PWR_CTRL3 */
327 #define PKT_AVAIL_SPDWN_EN 0x0100
328 #define SUSPEND_SPDWN_EN 0x0004
329 #define U1U2_SPDWN_EN 0x0002
330 #define L1_SPDWN_EN 0x0001
332 /* PLA_MAC_PWR_CTRL4 */
333 #define PWRSAVE_SPDWN_EN 0x1000
334 #define RXDV_SPDWN_EN 0x0800
335 #define TX10MIDLE_EN 0x0100
336 #define TP100_SPDWN_EN 0x0020
337 #define TP500_SPDWN_EN 0x0010
338 #define TP1000_SPDWN_EN 0x0008
339 #define EEE_SPDWN_EN 0x0001
341 /* PLA_GPHY_INTR_IMR */
342 #define GPHY_STS_MSK 0x0001
343 #define SPEED_DOWN_MSK 0x0002
344 #define SPDWN_RXDV_MSK 0x0004
345 #define SPDWN_LINKCHG_MSK 0x0008
348 #define PHYAR_FLAG 0x80000000
351 #define EEE_RX_EN 0x0001
352 #define EEE_TX_EN 0x0002
355 #define AUTOLOAD_DONE 0x0002
357 /* PLA_SUSPEND_FLAG */
358 #define LINK_CHG_EVENT BIT(0)
360 /* PLA_INDICATE_FALG */
361 #define UPCOMING_RUNTIME_D3 BIT(0)
363 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
364 #define DEBUG_OE BIT(0)
365 #define DEBUG_LTSSM 0x0082
367 /* PLA_EXTRA_STATUS */
368 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
369 #define LINK_CHANGE_FLAG BIT(8)
372 #define USB2PHY_SUSPEND 0x0001
373 #define USB2PHY_L1 0x0002
376 #define pwd_dn_scale_mask 0x3ffe
377 #define pwd_dn_scale(x) ((x) << 1)
380 #define DYNAMIC_BURST 0x0001
383 #define EP4_FULL_FC 0x0001
386 #define STAT_SPEED_MASK 0x0006
387 #define STAT_SPEED_HIGH 0x0000
388 #define STAT_SPEED_FULL 0x0002
391 #define FW_FIX_SUSPEND BIT(14)
394 #define FW_IP_RESET_EN BIT(9)
397 #define LPM_U1U2_EN BIT(0)
400 #define TX_AGG_MAX_THRESHOLD 0x03
403 #define RX_THR_SUPPER 0x0c350180
404 #define RX_THR_HIGH 0x7a120180
405 #define RX_THR_SLOW 0xffff0180
406 #define RX_THR_B 0x00010001
409 #define TEST_MODE_DISABLE 0x00000001
410 #define TX_SIZE_ADJUST1 0x00000100
413 #define BMU_RESET_EP_IN 0x01
414 #define BMU_RESET_EP_OUT 0x02
416 /* USB_UPT_RXDMA_OWN */
417 #define OWN_UPDATE BIT(0)
418 #define OWN_CLEAR BIT(1)
421 #define FC_PATCH_TASK BIT(1)
424 #define POWER_CUT 0x0100
426 /* USB_PM_CTRL_STATUS */
427 #define RESUME_INDICATE 0x0001
430 #define FORCE_SUPER BIT(0)
433 #define FLOW_CTRL_PATCH_OPT BIT(1)
436 #define CTRL_TIMER_EN BIT(15)
439 #define RX_AGG_DISABLE 0x0010
440 #define RX_ZERO_EN 0x0080
443 #define U2P3_ENABLE 0x0001
446 #define PWR_EN 0x0001
447 #define PHASE2_EN 0x0008
448 #define UPS_EN BIT(4)
449 #define USP_PREWAKE BIT(5)
452 #define PCUT_STATUS 0x0001
454 /* USB_RX_EARLY_TIMEOUT */
455 #define COALESCE_SUPER 85000U
456 #define COALESCE_HIGH 250000U
457 #define COALESCE_SLOW 524280U
460 #define WTD1_EN BIT(0)
463 #define TIMER11_EN 0x0001
466 /* bit 4 ~ 5: fifo empty boundary */
467 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
468 /* bit 2 ~ 3: LMP timer */
469 #define LPM_TIMER_MASK 0x0c
470 #define LPM_TIMER_500MS 0x04 /* 500 ms */
471 #define LPM_TIMER_500US 0x0c /* 500 us */
472 #define ROK_EXIT_LPM 0x02
475 #define SEN_VAL_MASK 0xf800
476 #define SEN_VAL_NORMAL 0xa000
477 #define SEL_RXIDLE 0x0100
480 #define SAW_CNT_1MS_MASK 0x0fff
483 #define UPS_FLAGS_R_TUNE BIT(0)
484 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
485 #define UPS_FLAGS_250M_CKDIV BIT(2)
486 #define UPS_FLAGS_EN_ALDPS BIT(3)
487 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
488 #define ups_flags_speed(x) ((x) << 16)
489 #define UPS_FLAGS_EN_EEE BIT(20)
490 #define UPS_FLAGS_EN_500M_EEE BIT(21)
491 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
492 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
493 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
494 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
495 #define UPS_FLAGS_EN_GREEN BIT(26)
496 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
510 /* OCP_ALDPS_CONFIG */
511 #define ENPWRSAVE 0x8000
512 #define ENPDNPS 0x0200
513 #define LINKENA 0x0100
514 #define DIS_SDSAVE 0x0010
517 #define PHY_STAT_MASK 0x0007
518 #define PHY_STAT_EXT_INIT 2
519 #define PHY_STAT_LAN_ON 3
520 #define PHY_STAT_PWRDN 5
523 #define PGA_RETURN_EN BIT(1)
526 #define EEE_CLKDIV_EN 0x8000
527 #define EN_ALDPS 0x0004
528 #define EN_10M_PLLOFF 0x0001
530 /* OCP_EEE_CONFIG1 */
531 #define RG_TXLPI_MSK_HFDUP 0x8000
532 #define RG_MATCLR_EN 0x4000
533 #define EEE_10_CAP 0x2000
534 #define EEE_NWAY_EN 0x1000
535 #define TX_QUIET_EN 0x0200
536 #define RX_QUIET_EN 0x0100
537 #define sd_rise_time_mask 0x0070
538 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
539 #define RG_RXLPI_MSK_HFDUP 0x0008
540 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
542 /* OCP_EEE_CONFIG2 */
543 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
544 #define RG_DACQUIET_EN 0x0400
545 #define RG_LDVQUIET_EN 0x0200
546 #define RG_CKRSEL 0x0020
547 #define RG_EEEPRG_EN 0x0010
549 /* OCP_EEE_CONFIG3 */
550 #define fast_snr_mask 0xff80
551 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
552 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
553 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
556 /* bit[15:14] function */
557 #define FUN_ADDR 0x0000
558 #define FUN_DATA 0x4000
559 /* bit[4:0] device addr */
562 #define CTAP_SHORT_EN 0x0040
563 #define EEE10_EN 0x0010
566 #define EN_EEE_CMODE BIT(14)
567 #define EN_EEE_1000 BIT(13)
568 #define EN_EEE_100 BIT(12)
569 #define EN_10M_CLKDIV BIT(11)
570 #define EN_10M_BGOFF 0x0080
573 #define TXDIS_STATE 0x01
574 #define ABD_STATE 0x02
576 /* OCP_PHY_PATCH_STAT */
577 #define PATCH_READY BIT(6)
579 /* OCP_PHY_PATCH_CMD */
580 #define PATCH_REQUEST BIT(4)
583 #define PATCH_LOCK BIT(0)
586 #define CKADSEL_L 0x0100
587 #define ADC_EN 0x0080
588 #define EN_EMI_L 0x0040
591 #define clk_div_expo(x) (min(x, 5) << 8)
594 #define GREEN_ETH_EN BIT(15)
595 #define R_TUNE_EN BIT(11)
598 #define LPF_AUTO_TUNE 0x8000
601 #define GDAC_IB_UPALL 0x0008
604 #define AMP_DN 0x0200
607 #define RX_DRIVING_MASK 0x6000
610 #define PHY_PATCH_LOCK 0x0001
613 #define AD_MASK 0xfee0
614 #define BND_MASK 0x0004
615 #define BD_MASK 0x0001
617 #define PASS_THRU_MASK 0x1
619 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
621 enum rtl_register_content {
629 #define RTL8152_MAX_TX 4
630 #define RTL8152_MAX_RX 10
635 #define RTL8152_RX_MAX_PENDING 4096
636 #define RTL8152_RXFG_HEADSZ 256
638 #define INTR_LINK 0x0004
640 #define RTL8152_REQT_READ 0xc0
641 #define RTL8152_REQT_WRITE 0x40
642 #define RTL8152_REQ_GET_REGS 0x05
643 #define RTL8152_REQ_SET_REGS 0x05
645 #define BYTE_EN_DWORD 0xff
646 #define BYTE_EN_WORD 0x33
647 #define BYTE_EN_BYTE 0x11
648 #define BYTE_EN_SIX_BYTES 0x3f
649 #define BYTE_EN_START_MASK 0x0f
650 #define BYTE_EN_END_MASK 0xf0
652 #define RTL8153_MAX_PACKET 9216 /* 9K */
653 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
655 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
656 #define RTL8153_RMS RTL8153_MAX_PACKET
657 #define RTL8152_TX_TIMEOUT (5 * HZ)
658 #define RTL8152_NAPI_WEIGHT 64
659 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
660 sizeof(struct rx_desc) + RX_ALIGN)
675 /* Define these values to match your device */
676 #define VENDOR_ID_REALTEK 0x0bda
677 #define VENDOR_ID_MICROSOFT 0x045e
678 #define VENDOR_ID_SAMSUNG 0x04e8
679 #define VENDOR_ID_LENOVO 0x17ef
680 #define VENDOR_ID_LINKSYS 0x13b1
681 #define VENDOR_ID_NVIDIA 0x0955
682 #define VENDOR_ID_TPLINK 0x2357
684 #define MCU_TYPE_PLA 0x0100
685 #define MCU_TYPE_USB 0x0000
687 struct tally_counter {
694 __le32 tx_one_collision;
695 __le32 tx_multi_collision;
705 #define RX_LEN_MASK 0x7fff
708 #define RD_UDP_CS BIT(23)
709 #define RD_TCP_CS BIT(22)
710 #define RD_IPV6_CS BIT(20)
711 #define RD_IPV4_CS BIT(19)
714 #define IPF BIT(23) /* IP checksum fail */
715 #define UDPF BIT(22) /* UDP checksum fail */
716 #define TCPF BIT(21) /* TCP checksum fail */
717 #define RX_VLAN_TAG BIT(16)
726 #define TX_FS BIT(31) /* First segment of a packet */
727 #define TX_LS BIT(30) /* Final segment of a packet */
728 #define GTSENDV4 BIT(28)
729 #define GTSENDV6 BIT(27)
730 #define GTTCPHO_SHIFT 18
731 #define GTTCPHO_MAX 0x7fU
732 #define TX_LEN_MAX 0x3ffffU
735 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
736 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
737 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
738 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
740 #define MSS_MAX 0x7ffU
741 #define TCPHO_SHIFT 17
742 #define TCPHO_MAX 0x7ffU
743 #define TX_VLAN_TAG BIT(16)
749 struct list_head list, info_list;
751 struct r8152 *context;
757 struct list_head list;
759 struct r8152 *context;
768 struct usb_device *udev;
769 struct napi_struct napi;
770 struct usb_interface *intf;
771 struct net_device *netdev;
772 struct urb *intr_urb;
773 struct tx_agg tx_info[RTL8152_MAX_TX];
774 struct list_head rx_info, rx_used;
775 struct list_head rx_done, tx_free;
776 struct sk_buff_head tx_queue, rx_queue;
777 spinlock_t rx_lock, tx_lock;
778 struct delayed_work schedule, hw_phy_work;
779 struct mii_if_info mii;
780 struct mutex control; /* use for hw setting */
781 #ifdef CONFIG_PM_SLEEP
782 struct notifier_block pm_notifier;
784 struct tasklet_struct tx_tl;
787 void (*init)(struct r8152 *tp);
788 int (*enable)(struct r8152 *tp);
789 void (*disable)(struct r8152 *tp);
790 void (*up)(struct r8152 *tp);
791 void (*down)(struct r8152 *tp);
792 void (*unload)(struct r8152 *tp);
793 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
794 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
795 bool (*in_nway)(struct r8152 *tp);
796 void (*hw_phy_cfg)(struct r8152 *tp);
797 void (*autosuspend_en)(struct r8152 *tp, bool enable);
809 u32 eee_plloff_100:1;
810 u32 eee_plloff_giga:1;
814 u32 ctap_short_off:1;
817 #define RTL_VER_SIZE 32
821 const struct firmware *fw;
823 char version[RTL_VER_SIZE];
824 int (*pre_fw)(struct r8152 *tp);
825 int (*post_fw)(struct r8152 *tp);
853 * struct fw_block - block type and total length
854 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
855 * RTL_FW_USB and so on.
856 * @length: total length of the current block.
864 * struct fw_header - header of the firmware file
865 * @checksum: checksum of sha256 which is calculated from the whole file
866 * except the checksum field of the file. That is, calculate sha256
867 * from the version field to the end of the file.
868 * @version: version of this firmware.
869 * @blocks: the first firmware block of the file
873 char version[RTL_VER_SIZE];
874 struct fw_block blocks[0];
878 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
879 * The layout of the firmware block is:
880 * <struct fw_mac> + <info> + <firmware data>.
881 * @fw_offset: offset of the firmware binary data. The start address of
882 * the data would be the address of struct fw_mac + @fw_offset.
883 * @fw_reg: the register to load the firmware. Depends on chip.
884 * @bp_ba_addr: the register to write break point base address. Depends on
886 * @bp_ba_value: break point base address. Depends on chip.
887 * @bp_en_addr: the register to write break point enabled mask. Depends
889 * @bp_en_value: break point enabled mask. Depends on the firmware.
890 * @bp_start: the start register of break points. Depends on chip.
891 * @bp_num: the break point number which needs to be set for this firmware.
892 * Depends on the firmware.
893 * @bp: break points. Depends on firmware.
894 * @fw_ver_reg: the register to store the fw version.
895 * @fw_ver_data: the firmware version of the current type.
896 * @info: additional information for debugging, and is followed by the
897 * binary data of firmware.
900 struct fw_block blk_hdr;
909 __le16 bp[16]; /* any value determined by firmware */
917 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
918 * This is used to set patch key when loading the firmware of PHY.
919 * @key_reg: the register to write the patch key.
920 * @key_data: patch key.
922 struct fw_phy_patch_key {
923 struct fw_block blk_hdr;
930 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
931 * The layout of the firmware block is:
932 * <struct fw_phy_nc> + <info> + <firmware data>.
933 * @fw_offset: offset of the firmware binary data. The start address of
934 * the data would be the address of struct fw_phy_nc + @fw_offset.
935 * @fw_reg: the register to load the firmware. Depends on chip.
936 * @ba_reg: the register to write the base address. Depends on chip.
937 * @ba_data: base address. Depends on chip.
938 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
939 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
940 * @mode_reg: the regitster of switching the mode.
941 * @mod_pre: the mode needing to be set before loading the firmware.
942 * @mod_post: the mode to be set when finishing to load the firmware.
943 * @bp_start: the start register of break points. Depends on chip.
944 * @bp_num: the break point number which needs to be set for this firmware.
945 * Depends on the firmware.
946 * @bp: break points. Depends on firmware.
947 * @info: additional information for debugging, and is followed by the
948 * binary data of firmware.
951 struct fw_block blk_hdr;
956 __le16 patch_en_addr;
957 __le16 patch_en_value;
997 #define RTL_ADVERTISED_10_HALF BIT(0)
998 #define RTL_ADVERTISED_10_FULL BIT(1)
999 #define RTL_ADVERTISED_100_HALF BIT(2)
1000 #define RTL_ADVERTISED_100_FULL BIT(3)
1001 #define RTL_ADVERTISED_1000_HALF BIT(4)
1002 #define RTL_ADVERTISED_1000_FULL BIT(5)
1004 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1005 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1007 static const int multicast_filter_limit = 32;
1008 static unsigned int agg_buf_sz = 16384;
1010 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
1011 VLAN_ETH_HLEN - ETH_FCS_LEN)
1014 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1019 tmp = kmalloc(size, GFP_KERNEL);
1023 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1024 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1025 value, index, tmp, size, 500);
1027 memset(data, 0xff, size);
1029 memcpy(data, tmp, size);
1037 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1042 tmp = kmemdup(data, size, GFP_KERNEL);
1046 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1047 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1048 value, index, tmp, size, 500);
1055 static void rtl_set_unplug(struct r8152 *tp)
1057 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1058 set_bit(RTL8152_UNPLUG, &tp->flags);
1059 smp_mb__after_atomic();
1063 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1064 void *data, u16 type)
1069 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1072 /* both size and indix must be 4 bytes align */
1073 if ((size & 3) || !size || (index & 3) || !data)
1076 if ((u32)index + (u32)size > 0xffff)
1081 ret = get_registers(tp, index, type, limit, data);
1089 ret = get_registers(tp, index, type, size, data);
1106 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1107 u16 size, void *data, u16 type)
1110 u16 byteen_start, byteen_end, byen;
1113 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1116 /* both size and indix must be 4 bytes align */
1117 if ((size & 3) || !size || (index & 3) || !data)
1120 if ((u32)index + (u32)size > 0xffff)
1123 byteen_start = byteen & BYTE_EN_START_MASK;
1124 byteen_end = byteen & BYTE_EN_END_MASK;
1126 byen = byteen_start | (byteen_start << 4);
1127 ret = set_registers(tp, index, type | byen, 4, data);
1140 ret = set_registers(tp, index,
1141 type | BYTE_EN_DWORD,
1150 ret = set_registers(tp, index,
1151 type | BYTE_EN_DWORD,
1163 byen = byteen_end | (byteen_end >> 4);
1164 ret = set_registers(tp, index, type | byen, 4, data);
1177 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1179 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1183 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1185 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1189 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1191 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1194 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1198 generic_ocp_read(tp, index, sizeof(data), &data, type);
1200 return __le32_to_cpu(data);
1203 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1205 __le32 tmp = __cpu_to_le32(data);
1207 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1210 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1214 u16 byen = BYTE_EN_WORD;
1215 u8 shift = index & 2;
1220 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1222 data = __le32_to_cpu(tmp);
1223 data >>= (shift * 8);
1229 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1233 u16 byen = BYTE_EN_WORD;
1234 u8 shift = index & 2;
1240 mask <<= (shift * 8);
1241 data <<= (shift * 8);
1245 tmp = __cpu_to_le32(data);
1247 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1250 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1254 u8 shift = index & 3;
1258 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1260 data = __le32_to_cpu(tmp);
1261 data >>= (shift * 8);
1267 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1271 u16 byen = BYTE_EN_BYTE;
1272 u8 shift = index & 3;
1278 mask <<= (shift * 8);
1279 data <<= (shift * 8);
1283 tmp = __cpu_to_le32(data);
1285 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1288 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1290 u16 ocp_base, ocp_index;
1292 ocp_base = addr & 0xf000;
1293 if (ocp_base != tp->ocp_base) {
1294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1295 tp->ocp_base = ocp_base;
1298 ocp_index = (addr & 0x0fff) | 0xb000;
1299 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1302 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1304 u16 ocp_base, ocp_index;
1306 ocp_base = addr & 0xf000;
1307 if (ocp_base != tp->ocp_base) {
1308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1309 tp->ocp_base = ocp_base;
1312 ocp_index = (addr & 0x0fff) | 0xb000;
1313 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1316 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1318 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1321 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1323 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1326 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1328 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1329 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1332 static u16 sram_read(struct r8152 *tp, u16 addr)
1334 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1335 return ocp_reg_read(tp, OCP_SRAM_DATA);
1338 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1340 struct r8152 *tp = netdev_priv(netdev);
1343 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1346 if (phy_id != R8152_PHY_ID)
1349 ret = r8152_mdio_read(tp, reg);
1355 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1357 struct r8152 *tp = netdev_priv(netdev);
1359 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1362 if (phy_id != R8152_PHY_ID)
1365 r8152_mdio_write(tp, reg, val);
1369 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1371 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1373 struct r8152 *tp = netdev_priv(netdev);
1374 struct sockaddr *addr = p;
1375 int ret = -EADDRNOTAVAIL;
1377 if (!is_valid_ether_addr(addr->sa_data))
1380 ret = usb_autopm_get_interface(tp->intf);
1384 mutex_lock(&tp->control);
1386 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1388 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1389 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1390 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1392 mutex_unlock(&tp->control);
1394 usb_autopm_put_interface(tp->intf);
1399 /* Devices containing proper chips can support a persistent
1400 * host system provided MAC address.
1401 * Examples of this are Dell TB15 and Dell WD15 docks
1403 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1406 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1407 union acpi_object *obj;
1410 unsigned char buf[6];
1412 /* test for -AD variant of RTL8153 */
1413 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1414 if ((ocp_data & AD_MASK) == 0x1000) {
1415 /* test for MAC address pass-through bit */
1416 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1417 if ((ocp_data & PASS_THRU_MASK) != 1) {
1418 netif_dbg(tp, probe, tp->netdev,
1419 "No efuse for RTL8153-AD MAC pass through\n");
1423 /* test for RTL8153-BND and RTL8153-BD */
1424 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1425 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1426 netif_dbg(tp, probe, tp->netdev,
1427 "Invalid variant for MAC pass through\n");
1432 /* returns _AUXMAC_#AABBCCDDEEFF# */
1433 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1434 obj = (union acpi_object *)buffer.pointer;
1435 if (!ACPI_SUCCESS(status))
1437 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1438 netif_warn(tp, probe, tp->netdev,
1439 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1440 obj->type, obj->string.length);
1443 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1444 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1445 netif_warn(tp, probe, tp->netdev,
1446 "Invalid header when reading pass-thru MAC addr\n");
1449 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1450 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1451 netif_warn(tp, probe, tp->netdev,
1452 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1457 memcpy(sa->sa_data, buf, 6);
1458 netif_info(tp, probe, tp->netdev,
1459 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1466 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1468 struct net_device *dev = tp->netdev;
1471 sa->sa_family = dev->type;
1473 if (tp->version == RTL_VER_01) {
1474 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1476 /* if device doesn't support MAC pass through this will
1477 * be expected to be non-zero
1479 ret = vendor_mac_passthru_addr_read(tp, sa);
1481 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1485 netif_err(tp, probe, dev, "Get ether addr fail\n");
1486 } else if (!is_valid_ether_addr(sa->sa_data)) {
1487 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1489 eth_hw_addr_random(dev);
1490 ether_addr_copy(sa->sa_data, dev->dev_addr);
1491 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1499 static int set_ethernet_addr(struct r8152 *tp)
1501 struct net_device *dev = tp->netdev;
1505 ret = determine_ethernet_addr(tp, &sa);
1509 if (tp->version == RTL_VER_01)
1510 ether_addr_copy(dev->dev_addr, sa.sa_data);
1512 ret = rtl8152_set_mac_address(dev, &sa);
1517 static void read_bulk_callback(struct urb *urb)
1519 struct net_device *netdev;
1520 int status = urb->status;
1523 unsigned long flags;
1533 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1536 if (!test_bit(WORK_ENABLE, &tp->flags))
1539 netdev = tp->netdev;
1541 /* When link down, the driver would cancel all bulks. */
1542 /* This avoid the re-submitting bulk */
1543 if (!netif_carrier_ok(netdev))
1546 usb_mark_last_busy(tp->udev);
1550 if (urb->actual_length < ETH_ZLEN)
1553 spin_lock_irqsave(&tp->rx_lock, flags);
1554 list_add_tail(&agg->list, &tp->rx_done);
1555 spin_unlock_irqrestore(&tp->rx_lock, flags);
1556 napi_schedule(&tp->napi);
1560 netif_device_detach(tp->netdev);
1563 return; /* the urb is in unlink state */
1565 if (net_ratelimit())
1566 netdev_warn(netdev, "maybe reset is needed?\n");
1569 if (net_ratelimit())
1570 netdev_warn(netdev, "Rx status %d\n", status);
1574 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1577 static void write_bulk_callback(struct urb *urb)
1579 struct net_device_stats *stats;
1580 struct net_device *netdev;
1583 unsigned long flags;
1584 int status = urb->status;
1594 netdev = tp->netdev;
1595 stats = &netdev->stats;
1597 if (net_ratelimit())
1598 netdev_warn(netdev, "Tx status %d\n", status);
1599 stats->tx_errors += agg->skb_num;
1601 stats->tx_packets += agg->skb_num;
1602 stats->tx_bytes += agg->skb_len;
1605 spin_lock_irqsave(&tp->tx_lock, flags);
1606 list_add_tail(&agg->list, &tp->tx_free);
1607 spin_unlock_irqrestore(&tp->tx_lock, flags);
1609 usb_autopm_put_interface_async(tp->intf);
1611 if (!netif_carrier_ok(netdev))
1614 if (!test_bit(WORK_ENABLE, &tp->flags))
1617 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1620 if (!skb_queue_empty(&tp->tx_queue))
1621 tasklet_schedule(&tp->tx_tl);
1624 static void intr_callback(struct urb *urb)
1628 int status = urb->status;
1635 if (!test_bit(WORK_ENABLE, &tp->flags))
1638 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1642 case 0: /* success */
1644 case -ECONNRESET: /* unlink */
1646 netif_device_detach(tp->netdev);
1650 netif_info(tp, intr, tp->netdev,
1651 "Stop submitting intr, status %d\n", status);
1654 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1656 /* -EPIPE: should clear the halt */
1658 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1662 d = urb->transfer_buffer;
1663 if (INTR_LINK & __le16_to_cpu(d[0])) {
1664 if (!netif_carrier_ok(tp->netdev)) {
1665 set_bit(RTL8152_LINK_CHG, &tp->flags);
1666 schedule_delayed_work(&tp->schedule, 0);
1669 if (netif_carrier_ok(tp->netdev)) {
1670 netif_stop_queue(tp->netdev);
1671 set_bit(RTL8152_LINK_CHG, &tp->flags);
1672 schedule_delayed_work(&tp->schedule, 0);
1677 res = usb_submit_urb(urb, GFP_ATOMIC);
1678 if (res == -ENODEV) {
1680 netif_device_detach(tp->netdev);
1682 netif_err(tp, intr, tp->netdev,
1683 "can't resubmit intr, status %d\n", res);
1687 static inline void *rx_agg_align(void *data)
1689 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1692 static inline void *tx_agg_align(void *data)
1694 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1697 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1699 list_del(&agg->info_list);
1701 usb_free_urb(agg->urb);
1702 put_page(agg->page);
1705 atomic_dec(&tp->rx_count);
1708 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1710 struct net_device *netdev = tp->netdev;
1711 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1712 unsigned int order = get_order(tp->rx_buf_sz);
1713 struct rx_agg *rx_agg;
1714 unsigned long flags;
1716 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1720 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1724 rx_agg->buffer = page_address(rx_agg->page);
1726 rx_agg->urb = usb_alloc_urb(0, mflags);
1730 rx_agg->context = tp;
1732 INIT_LIST_HEAD(&rx_agg->list);
1733 INIT_LIST_HEAD(&rx_agg->info_list);
1734 spin_lock_irqsave(&tp->rx_lock, flags);
1735 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1736 spin_unlock_irqrestore(&tp->rx_lock, flags);
1738 atomic_inc(&tp->rx_count);
1743 __free_pages(rx_agg->page, order);
1749 static void free_all_mem(struct r8152 *tp)
1751 struct rx_agg *agg, *agg_next;
1752 unsigned long flags;
1755 spin_lock_irqsave(&tp->rx_lock, flags);
1757 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1758 free_rx_agg(tp, agg);
1760 spin_unlock_irqrestore(&tp->rx_lock, flags);
1762 WARN_ON(atomic_read(&tp->rx_count));
1764 for (i = 0; i < RTL8152_MAX_TX; i++) {
1765 usb_free_urb(tp->tx_info[i].urb);
1766 tp->tx_info[i].urb = NULL;
1768 kfree(tp->tx_info[i].buffer);
1769 tp->tx_info[i].buffer = NULL;
1770 tp->tx_info[i].head = NULL;
1773 usb_free_urb(tp->intr_urb);
1774 tp->intr_urb = NULL;
1776 kfree(tp->intr_buff);
1777 tp->intr_buff = NULL;
1780 static int alloc_all_mem(struct r8152 *tp)
1782 struct net_device *netdev = tp->netdev;
1783 struct usb_interface *intf = tp->intf;
1784 struct usb_host_interface *alt = intf->cur_altsetting;
1785 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1788 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1790 spin_lock_init(&tp->rx_lock);
1791 spin_lock_init(&tp->tx_lock);
1792 INIT_LIST_HEAD(&tp->rx_info);
1793 INIT_LIST_HEAD(&tp->tx_free);
1794 INIT_LIST_HEAD(&tp->rx_done);
1795 skb_queue_head_init(&tp->tx_queue);
1796 skb_queue_head_init(&tp->rx_queue);
1797 atomic_set(&tp->rx_count, 0);
1799 for (i = 0; i < RTL8152_MAX_RX; i++) {
1800 if (!alloc_rx_agg(tp, GFP_KERNEL))
1804 for (i = 0; i < RTL8152_MAX_TX; i++) {
1808 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1812 if (buf != tx_agg_align(buf)) {
1814 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1820 urb = usb_alloc_urb(0, GFP_KERNEL);
1826 INIT_LIST_HEAD(&tp->tx_info[i].list);
1827 tp->tx_info[i].context = tp;
1828 tp->tx_info[i].urb = urb;
1829 tp->tx_info[i].buffer = buf;
1830 tp->tx_info[i].head = tx_agg_align(buf);
1832 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1835 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1839 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1843 tp->intr_interval = (int)ep_intr->desc.bInterval;
1844 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1845 tp->intr_buff, INTBUFSIZE, intr_callback,
1846 tp, tp->intr_interval);
1855 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1857 struct tx_agg *agg = NULL;
1858 unsigned long flags;
1860 if (list_empty(&tp->tx_free))
1863 spin_lock_irqsave(&tp->tx_lock, flags);
1864 if (!list_empty(&tp->tx_free)) {
1865 struct list_head *cursor;
1867 cursor = tp->tx_free.next;
1868 list_del_init(cursor);
1869 agg = list_entry(cursor, struct tx_agg, list);
1871 spin_unlock_irqrestore(&tp->tx_lock, flags);
1876 /* r8152_csum_workaround()
1877 * The hw limits the value of the transport offset. When the offset is out of
1878 * range, calculate the checksum by sw.
1880 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1881 struct sk_buff_head *list)
1883 if (skb_shinfo(skb)->gso_size) {
1884 netdev_features_t features = tp->netdev->features;
1885 struct sk_buff_head seg_list;
1886 struct sk_buff *segs, *nskb;
1888 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1889 segs = skb_gso_segment(skb, features);
1890 if (IS_ERR(segs) || !segs)
1893 __skb_queue_head_init(&seg_list);
1899 __skb_queue_tail(&seg_list, nskb);
1902 skb_queue_splice(&seg_list, list);
1904 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1905 if (skb_checksum_help(skb) < 0)
1908 __skb_queue_head(list, skb);
1910 struct net_device_stats *stats;
1913 stats = &tp->netdev->stats;
1914 stats->tx_dropped++;
1919 /* msdn_giant_send_check()
1920 * According to the document of microsoft, the TCP Pseudo Header excludes the
1921 * packet length for IPv6 TCP large packets.
1923 static int msdn_giant_send_check(struct sk_buff *skb)
1925 const struct ipv6hdr *ipv6h;
1929 ret = skb_cow_head(skb, 0);
1933 ipv6h = ipv6_hdr(skb);
1937 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1942 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1944 if (skb_vlan_tag_present(skb)) {
1947 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1948 desc->opts2 |= cpu_to_le32(opts2);
1952 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1954 u32 opts2 = le32_to_cpu(desc->opts2);
1956 if (opts2 & RX_VLAN_TAG)
1957 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1958 swab16(opts2 & 0xffff));
1961 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1962 struct sk_buff *skb, u32 len, u32 transport_offset)
1964 u32 mss = skb_shinfo(skb)->gso_size;
1965 u32 opts1, opts2 = 0;
1966 int ret = TX_CSUM_SUCCESS;
1968 WARN_ON_ONCE(len > TX_LEN_MAX);
1970 opts1 = len | TX_FS | TX_LS;
1973 if (transport_offset > GTTCPHO_MAX) {
1974 netif_warn(tp, tx_err, tp->netdev,
1975 "Invalid transport offset 0x%x for TSO\n",
1981 switch (vlan_get_protocol(skb)) {
1982 case htons(ETH_P_IP):
1986 case htons(ETH_P_IPV6):
1987 if (msdn_giant_send_check(skb)) {
1999 opts1 |= transport_offset << GTTCPHO_SHIFT;
2000 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2001 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2004 if (transport_offset > TCPHO_MAX) {
2005 netif_warn(tp, tx_err, tp->netdev,
2006 "Invalid transport offset 0x%x\n",
2012 switch (vlan_get_protocol(skb)) {
2013 case htons(ETH_P_IP):
2015 ip_protocol = ip_hdr(skb)->protocol;
2018 case htons(ETH_P_IPV6):
2020 ip_protocol = ipv6_hdr(skb)->nexthdr;
2024 ip_protocol = IPPROTO_RAW;
2028 if (ip_protocol == IPPROTO_TCP)
2030 else if (ip_protocol == IPPROTO_UDP)
2035 opts2 |= transport_offset << TCPHO_SHIFT;
2038 desc->opts2 = cpu_to_le32(opts2);
2039 desc->opts1 = cpu_to_le32(opts1);
2045 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2047 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2051 __skb_queue_head_init(&skb_head);
2052 spin_lock(&tx_queue->lock);
2053 skb_queue_splice_init(tx_queue, &skb_head);
2054 spin_unlock(&tx_queue->lock);
2056 tx_data = agg->head;
2059 remain = agg_buf_sz;
2061 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2062 struct tx_desc *tx_desc;
2063 struct sk_buff *skb;
2067 skb = __skb_dequeue(&skb_head);
2071 len = skb->len + sizeof(*tx_desc);
2074 __skb_queue_head(&skb_head, skb);
2078 tx_data = tx_agg_align(tx_data);
2079 tx_desc = (struct tx_desc *)tx_data;
2081 offset = (u32)skb_transport_offset(skb);
2083 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2084 r8152_csum_workaround(tp, skb, &skb_head);
2088 rtl_tx_vlan_tag(tx_desc, skb);
2090 tx_data += sizeof(*tx_desc);
2093 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2094 struct net_device_stats *stats = &tp->netdev->stats;
2096 stats->tx_dropped++;
2097 dev_kfree_skb_any(skb);
2098 tx_data -= sizeof(*tx_desc);
2103 agg->skb_len += len;
2104 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2106 dev_kfree_skb_any(skb);
2108 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2110 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2114 if (!skb_queue_empty(&skb_head)) {
2115 spin_lock(&tx_queue->lock);
2116 skb_queue_splice(&skb_head, tx_queue);
2117 spin_unlock(&tx_queue->lock);
2120 netif_tx_lock(tp->netdev);
2122 if (netif_queue_stopped(tp->netdev) &&
2123 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2124 netif_wake_queue(tp->netdev);
2126 netif_tx_unlock(tp->netdev);
2128 ret = usb_autopm_get_interface_async(tp->intf);
2132 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2133 agg->head, (int)(tx_data - (u8 *)agg->head),
2134 (usb_complete_t)write_bulk_callback, agg);
2136 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2138 usb_autopm_put_interface_async(tp->intf);
2144 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2146 u8 checksum = CHECKSUM_NONE;
2149 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2152 opts2 = le32_to_cpu(rx_desc->opts2);
2153 opts3 = le32_to_cpu(rx_desc->opts3);
2155 if (opts2 & RD_IPV4_CS) {
2157 checksum = CHECKSUM_NONE;
2158 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2159 checksum = CHECKSUM_UNNECESSARY;
2160 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2161 checksum = CHECKSUM_UNNECESSARY;
2162 } else if (opts2 & RD_IPV6_CS) {
2163 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2164 checksum = CHECKSUM_UNNECESSARY;
2165 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2166 checksum = CHECKSUM_UNNECESSARY;
2173 static inline bool rx_count_exceed(struct r8152 *tp)
2175 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2178 static inline int agg_offset(struct rx_agg *agg, void *addr)
2180 return (int)(addr - agg->buffer);
2183 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2185 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2186 unsigned long flags;
2188 spin_lock_irqsave(&tp->rx_lock, flags);
2190 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2191 if (page_count(agg->page) == 1) {
2193 list_del_init(&agg->list);
2197 if (rx_count_exceed(tp)) {
2198 list_del_init(&agg->list);
2199 free_rx_agg(tp, agg);
2205 spin_unlock_irqrestore(&tp->rx_lock, flags);
2207 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2208 agg_free = alloc_rx_agg(tp, mflags);
2213 static int rx_bottom(struct r8152 *tp, int budget)
2215 unsigned long flags;
2216 struct list_head *cursor, *next, rx_queue;
2217 int ret = 0, work_done = 0;
2218 struct napi_struct *napi = &tp->napi;
2220 if (!skb_queue_empty(&tp->rx_queue)) {
2221 while (work_done < budget) {
2222 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2223 struct net_device *netdev = tp->netdev;
2224 struct net_device_stats *stats = &netdev->stats;
2225 unsigned int pkt_len;
2231 napi_gro_receive(napi, skb);
2233 stats->rx_packets++;
2234 stats->rx_bytes += pkt_len;
2238 if (list_empty(&tp->rx_done))
2241 INIT_LIST_HEAD(&rx_queue);
2242 spin_lock_irqsave(&tp->rx_lock, flags);
2243 list_splice_init(&tp->rx_done, &rx_queue);
2244 spin_unlock_irqrestore(&tp->rx_lock, flags);
2246 list_for_each_safe(cursor, next, &rx_queue) {
2247 struct rx_desc *rx_desc;
2248 struct rx_agg *agg, *agg_free;
2253 list_del_init(cursor);
2255 agg = list_entry(cursor, struct rx_agg, list);
2257 if (urb->actual_length < ETH_ZLEN)
2260 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2262 rx_desc = agg->buffer;
2263 rx_data = agg->buffer;
2264 len_used += sizeof(struct rx_desc);
2266 while (urb->actual_length > len_used) {
2267 struct net_device *netdev = tp->netdev;
2268 struct net_device_stats *stats = &netdev->stats;
2269 unsigned int pkt_len, rx_frag_head_sz;
2270 struct sk_buff *skb;
2272 /* limite the skb numbers for rx_queue */
2273 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2276 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2277 if (pkt_len < ETH_ZLEN)
2280 len_used += pkt_len;
2281 if (urb->actual_length < len_used)
2284 pkt_len -= ETH_FCS_LEN;
2285 rx_data += sizeof(struct rx_desc);
2287 if (!agg_free || tp->rx_copybreak > pkt_len)
2288 rx_frag_head_sz = pkt_len;
2290 rx_frag_head_sz = tp->rx_copybreak;
2292 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2294 stats->rx_dropped++;
2298 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2299 memcpy(skb->data, rx_data, rx_frag_head_sz);
2300 skb_put(skb, rx_frag_head_sz);
2301 pkt_len -= rx_frag_head_sz;
2302 rx_data += rx_frag_head_sz;
2304 skb_add_rx_frag(skb, 0, agg->page,
2305 agg_offset(agg, rx_data),
2307 SKB_DATA_ALIGN(pkt_len));
2308 get_page(agg->page);
2311 skb->protocol = eth_type_trans(skb, netdev);
2312 rtl_rx_vlan_tag(rx_desc, skb);
2313 if (work_done < budget) {
2315 stats->rx_packets++;
2316 stats->rx_bytes += skb->len;
2317 napi_gro_receive(napi, skb);
2319 __skb_queue_tail(&tp->rx_queue, skb);
2323 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2324 rx_desc = (struct rx_desc *)rx_data;
2325 len_used = agg_offset(agg, rx_data);
2326 len_used += sizeof(struct rx_desc);
2329 WARN_ON(!agg_free && page_count(agg->page) > 1);
2332 spin_lock_irqsave(&tp->rx_lock, flags);
2333 if (page_count(agg->page) == 1) {
2334 list_add(&agg_free->list, &tp->rx_used);
2336 list_add_tail(&agg->list, &tp->rx_used);
2340 spin_unlock_irqrestore(&tp->rx_lock, flags);
2345 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2347 urb->actual_length = 0;
2348 list_add_tail(&agg->list, next);
2352 if (!list_empty(&rx_queue)) {
2353 spin_lock_irqsave(&tp->rx_lock, flags);
2354 list_splice_tail(&rx_queue, &tp->rx_done);
2355 spin_unlock_irqrestore(&tp->rx_lock, flags);
2362 static void tx_bottom(struct r8152 *tp)
2367 struct net_device *netdev = tp->netdev;
2370 if (skb_queue_empty(&tp->tx_queue))
2373 agg = r8152_get_tx_agg(tp);
2377 res = r8152_tx_agg_fill(tp, agg);
2381 if (res == -ENODEV) {
2383 netif_device_detach(netdev);
2385 struct net_device_stats *stats = &netdev->stats;
2386 unsigned long flags;
2388 netif_warn(tp, tx_err, netdev,
2389 "failed tx_urb %d\n", res);
2390 stats->tx_dropped += agg->skb_num;
2392 spin_lock_irqsave(&tp->tx_lock, flags);
2393 list_add_tail(&agg->list, &tp->tx_free);
2394 spin_unlock_irqrestore(&tp->tx_lock, flags);
2399 static void bottom_half(unsigned long data)
2403 tp = (struct r8152 *)data;
2405 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2408 if (!test_bit(WORK_ENABLE, &tp->flags))
2411 /* When link down, the driver would cancel all bulks. */
2412 /* This avoid the re-submitting bulk */
2413 if (!netif_carrier_ok(tp->netdev))
2416 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2421 static int r8152_poll(struct napi_struct *napi, int budget)
2423 struct r8152 *tp = container_of(napi, struct r8152, napi);
2426 work_done = rx_bottom(tp, budget);
2428 if (work_done < budget) {
2429 if (!napi_complete_done(napi, work_done))
2431 if (!list_empty(&tp->rx_done))
2432 napi_schedule(napi);
2440 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2444 /* The rx would be stopped, so skip submitting */
2445 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2446 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2449 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2450 agg->buffer, tp->rx_buf_sz,
2451 (usb_complete_t)read_bulk_callback, agg);
2453 ret = usb_submit_urb(agg->urb, mem_flags);
2454 if (ret == -ENODEV) {
2456 netif_device_detach(tp->netdev);
2458 struct urb *urb = agg->urb;
2459 unsigned long flags;
2461 urb->actual_length = 0;
2462 spin_lock_irqsave(&tp->rx_lock, flags);
2463 list_add_tail(&agg->list, &tp->rx_done);
2464 spin_unlock_irqrestore(&tp->rx_lock, flags);
2466 netif_err(tp, rx_err, tp->netdev,
2467 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2469 napi_schedule(&tp->napi);
2475 static void rtl_drop_queued_tx(struct r8152 *tp)
2477 struct net_device_stats *stats = &tp->netdev->stats;
2478 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2479 struct sk_buff *skb;
2481 if (skb_queue_empty(tx_queue))
2484 __skb_queue_head_init(&skb_head);
2485 spin_lock_bh(&tx_queue->lock);
2486 skb_queue_splice_init(tx_queue, &skb_head);
2487 spin_unlock_bh(&tx_queue->lock);
2489 while ((skb = __skb_dequeue(&skb_head))) {
2491 stats->tx_dropped++;
2495 static void rtl8152_tx_timeout(struct net_device *netdev)
2497 struct r8152 *tp = netdev_priv(netdev);
2499 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2501 usb_queue_reset_device(tp->intf);
2504 static void rtl8152_set_rx_mode(struct net_device *netdev)
2506 struct r8152 *tp = netdev_priv(netdev);
2508 if (netif_carrier_ok(netdev)) {
2509 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2510 schedule_delayed_work(&tp->schedule, 0);
2514 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2516 struct r8152 *tp = netdev_priv(netdev);
2517 u32 mc_filter[2]; /* Multicast hash filter */
2521 netif_stop_queue(netdev);
2522 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2523 ocp_data &= ~RCR_ACPT_ALL;
2524 ocp_data |= RCR_AB | RCR_APM;
2526 if (netdev->flags & IFF_PROMISC) {
2527 /* Unconditionally log net taps. */
2528 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2529 ocp_data |= RCR_AM | RCR_AAP;
2530 mc_filter[1] = 0xffffffff;
2531 mc_filter[0] = 0xffffffff;
2532 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2533 (netdev->flags & IFF_ALLMULTI)) {
2534 /* Too many to filter perfectly -- accept all multicasts. */
2536 mc_filter[1] = 0xffffffff;
2537 mc_filter[0] = 0xffffffff;
2539 struct netdev_hw_addr *ha;
2543 netdev_for_each_mc_addr(ha, netdev) {
2544 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2546 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2551 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2552 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2554 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2555 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2556 netif_wake_queue(netdev);
2559 static netdev_features_t
2560 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2561 netdev_features_t features)
2563 u32 mss = skb_shinfo(skb)->gso_size;
2564 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2565 int offset = skb_transport_offset(skb);
2567 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2568 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2569 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2570 features &= ~NETIF_F_GSO_MASK;
2575 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2576 struct net_device *netdev)
2578 struct r8152 *tp = netdev_priv(netdev);
2580 skb_tx_timestamp(skb);
2582 skb_queue_tail(&tp->tx_queue, skb);
2584 if (!list_empty(&tp->tx_free)) {
2585 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2586 set_bit(SCHEDULE_TASKLET, &tp->flags);
2587 schedule_delayed_work(&tp->schedule, 0);
2589 usb_mark_last_busy(tp->udev);
2590 tasklet_schedule(&tp->tx_tl);
2592 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2593 netif_stop_queue(netdev);
2596 return NETDEV_TX_OK;
2599 static void r8152b_reset_packet_filter(struct r8152 *tp)
2603 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2604 ocp_data &= ~FMC_FCR_MCU_EN;
2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2606 ocp_data |= FMC_FCR_MCU_EN;
2607 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2610 static void rtl8152_nic_reset(struct r8152 *tp)
2614 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2616 for (i = 0; i < 1000; i++) {
2617 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2619 usleep_range(100, 400);
2623 static void set_tx_qlen(struct r8152 *tp)
2625 struct net_device *netdev = tp->netdev;
2627 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2628 sizeof(struct tx_desc));
2631 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2633 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2636 static void rtl_set_eee_plus(struct r8152 *tp)
2641 speed = rtl8152_get_speed(tp);
2642 if (speed & _10bps) {
2643 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2644 ocp_data |= EEEP_CR_EEEP_TX;
2645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2647 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2648 ocp_data &= ~EEEP_CR_EEEP_TX;
2649 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2653 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2657 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2659 ocp_data |= RXDY_GATED_EN;
2661 ocp_data &= ~RXDY_GATED_EN;
2662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2665 static int rtl_start_rx(struct r8152 *tp)
2667 struct rx_agg *agg, *agg_next;
2668 struct list_head tmp_list;
2669 unsigned long flags;
2672 INIT_LIST_HEAD(&tmp_list);
2674 spin_lock_irqsave(&tp->rx_lock, flags);
2676 INIT_LIST_HEAD(&tp->rx_done);
2677 INIT_LIST_HEAD(&tp->rx_used);
2679 list_splice_init(&tp->rx_info, &tmp_list);
2681 spin_unlock_irqrestore(&tp->rx_lock, flags);
2683 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2684 INIT_LIST_HEAD(&agg->list);
2686 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2687 if (++i > RTL8152_MAX_RX) {
2688 spin_lock_irqsave(&tp->rx_lock, flags);
2689 list_add_tail(&agg->list, &tp->rx_used);
2690 spin_unlock_irqrestore(&tp->rx_lock, flags);
2691 } else if (unlikely(ret < 0)) {
2692 spin_lock_irqsave(&tp->rx_lock, flags);
2693 list_add_tail(&agg->list, &tp->rx_done);
2694 spin_unlock_irqrestore(&tp->rx_lock, flags);
2696 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2700 spin_lock_irqsave(&tp->rx_lock, flags);
2701 WARN_ON(!list_empty(&tp->rx_info));
2702 list_splice(&tmp_list, &tp->rx_info);
2703 spin_unlock_irqrestore(&tp->rx_lock, flags);
2708 static int rtl_stop_rx(struct r8152 *tp)
2710 struct rx_agg *agg, *agg_next;
2711 struct list_head tmp_list;
2712 unsigned long flags;
2714 INIT_LIST_HEAD(&tmp_list);
2716 /* The usb_kill_urb() couldn't be used in atomic.
2717 * Therefore, move the list of rx_info to a tmp one.
2718 * Then, list_for_each_entry_safe could be used without
2722 spin_lock_irqsave(&tp->rx_lock, flags);
2723 list_splice_init(&tp->rx_info, &tmp_list);
2724 spin_unlock_irqrestore(&tp->rx_lock, flags);
2726 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2727 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2728 * equal to 1, so the other ones could be freed safely.
2730 if (page_count(agg->page) > 1)
2731 free_rx_agg(tp, agg);
2733 usb_kill_urb(agg->urb);
2736 /* Move back the list of temp to the rx_info */
2737 spin_lock_irqsave(&tp->rx_lock, flags);
2738 WARN_ON(!list_empty(&tp->rx_info));
2739 list_splice(&tmp_list, &tp->rx_info);
2740 spin_unlock_irqrestore(&tp->rx_lock, flags);
2742 while (!skb_queue_empty(&tp->rx_queue))
2743 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2748 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2750 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2751 OWN_UPDATE | OWN_CLEAR);
2754 static int rtl_enable(struct r8152 *tp)
2758 r8152b_reset_packet_filter(tp);
2760 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2761 ocp_data |= CR_RE | CR_TE;
2762 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2764 switch (tp->version) {
2767 r8153b_rx_agg_chg_indicate(tp);
2773 rxdy_gated_en(tp, false);
2778 static int rtl8152_enable(struct r8152 *tp)
2780 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2784 rtl_set_eee_plus(tp);
2786 return rtl_enable(tp);
2789 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2791 u32 ocp_data = tp->coalesce / 8;
2793 switch (tp->version) {
2798 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2804 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2805 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2807 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2809 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2818 static void r8153_set_rx_early_size(struct r8152 *tp)
2820 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2822 switch (tp->version) {
2827 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2832 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2841 static int rtl8153_enable(struct r8152 *tp)
2843 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2847 rtl_set_eee_plus(tp);
2848 r8153_set_rx_early_timeout(tp);
2849 r8153_set_rx_early_size(tp);
2851 return rtl_enable(tp);
2854 static void rtl_disable(struct r8152 *tp)
2859 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2860 rtl_drop_queued_tx(tp);
2864 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2865 ocp_data &= ~RCR_ACPT_ALL;
2866 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2868 rtl_drop_queued_tx(tp);
2870 for (i = 0; i < RTL8152_MAX_TX; i++)
2871 usb_kill_urb(tp->tx_info[i].urb);
2873 rxdy_gated_en(tp, true);
2875 for (i = 0; i < 1000; i++) {
2876 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2877 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2879 usleep_range(1000, 2000);
2882 for (i = 0; i < 1000; i++) {
2883 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2885 usleep_range(1000, 2000);
2890 rtl8152_nic_reset(tp);
2893 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2897 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2899 ocp_data |= POWER_CUT;
2901 ocp_data &= ~POWER_CUT;
2902 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2904 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2905 ocp_data &= ~RESUME_INDICATE;
2906 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2909 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2913 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2915 ocp_data |= CPCR_RX_VLAN;
2917 ocp_data &= ~CPCR_RX_VLAN;
2918 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2921 static int rtl8152_set_features(struct net_device *dev,
2922 netdev_features_t features)
2924 netdev_features_t changed = features ^ dev->features;
2925 struct r8152 *tp = netdev_priv(dev);
2928 ret = usb_autopm_get_interface(tp->intf);
2932 mutex_lock(&tp->control);
2934 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2935 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2936 rtl_rx_vlan_en(tp, true);
2938 rtl_rx_vlan_en(tp, false);
2941 mutex_unlock(&tp->control);
2943 usb_autopm_put_interface(tp->intf);
2949 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2951 static u32 __rtl_get_wol(struct r8152 *tp)
2956 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2957 if (ocp_data & LINK_ON_WAKE_EN)
2958 wolopts |= WAKE_PHY;
2960 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2961 if (ocp_data & UWF_EN)
2962 wolopts |= WAKE_UCAST;
2963 if (ocp_data & BWF_EN)
2964 wolopts |= WAKE_BCAST;
2965 if (ocp_data & MWF_EN)
2966 wolopts |= WAKE_MCAST;
2968 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2969 if (ocp_data & MAGIC_EN)
2970 wolopts |= WAKE_MAGIC;
2975 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2979 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2981 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2982 ocp_data &= ~LINK_ON_WAKE_EN;
2983 if (wolopts & WAKE_PHY)
2984 ocp_data |= LINK_ON_WAKE_EN;
2985 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2987 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2988 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2989 if (wolopts & WAKE_UCAST)
2991 if (wolopts & WAKE_BCAST)
2993 if (wolopts & WAKE_MCAST)
2995 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2997 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2999 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3000 ocp_data &= ~MAGIC_EN;
3001 if (wolopts & WAKE_MAGIC)
3002 ocp_data |= MAGIC_EN;
3003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3005 if (wolopts & WAKE_ANY)
3006 device_set_wakeup_enable(&tp->udev->dev, true);
3008 device_set_wakeup_enable(&tp->udev->dev, false);
3011 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3013 /* MAC clock speed down */
3015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3017 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3019 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3020 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3021 U1U2_SPDWN_EN | L1_SPDWN_EN);
3022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3023 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3024 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3029 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3034 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3039 memset(u1u2, 0xff, sizeof(u1u2));
3041 memset(u1u2, 0x00, sizeof(u1u2));
3043 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3046 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3050 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3052 ocp_data |= LPM_U1U2_EN;
3054 ocp_data &= ~LPM_U1U2_EN;
3056 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3059 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3065 ocp_data |= U2P3_ENABLE;
3067 ocp_data &= ~U2P3_ENABLE;
3068 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3071 static void r8153b_ups_flags(struct r8152 *tp)
3075 if (tp->ups_info.green)
3076 ups_flags |= UPS_FLAGS_EN_GREEN;
3078 if (tp->ups_info.aldps)
3079 ups_flags |= UPS_FLAGS_EN_ALDPS;
3081 if (tp->ups_info.eee)
3082 ups_flags |= UPS_FLAGS_EN_EEE;
3084 if (tp->ups_info.flow_control)
3085 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3087 if (tp->ups_info.eee_ckdiv)
3088 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3090 if (tp->ups_info.eee_cmod_lv)
3091 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3093 if (tp->ups_info._10m_ckdiv)
3094 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3096 if (tp->ups_info.eee_plloff_100)
3097 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3099 if (tp->ups_info.eee_plloff_giga)
3100 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3102 if (tp->ups_info._250m_ckdiv)
3103 ups_flags |= UPS_FLAGS_250M_CKDIV;
3105 if (tp->ups_info.ctap_short_off)
3106 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3108 switch (tp->ups_info.speed_duplex) {
3110 ups_flags |= ups_flags_speed(1);
3113 ups_flags |= ups_flags_speed(2);
3115 case NWAY_100M_HALF:
3116 ups_flags |= ups_flags_speed(3);
3118 case NWAY_100M_FULL:
3119 ups_flags |= ups_flags_speed(4);
3121 case NWAY_1000M_FULL:
3122 ups_flags |= ups_flags_speed(5);
3124 case FORCE_10M_HALF:
3125 ups_flags |= ups_flags_speed(6);
3127 case FORCE_10M_FULL:
3128 ups_flags |= ups_flags_speed(7);
3130 case FORCE_100M_HALF:
3131 ups_flags |= ups_flags_speed(8);
3133 case FORCE_100M_FULL:
3134 ups_flags |= ups_flags_speed(9);
3140 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3143 static void r8153b_green_en(struct r8152 *tp, bool enable)
3148 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3149 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3150 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3152 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3153 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3154 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3157 data = sram_read(tp, SRAM_GREEN_CFG);
3158 data |= GREEN_ETH_EN;
3159 sram_write(tp, SRAM_GREEN_CFG, data);
3161 tp->ups_info.green = enable;
3164 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3169 for (i = 0; i < 500; i++) {
3170 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3171 data &= PHY_STAT_MASK;
3173 if (data == desired)
3175 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3176 data == PHY_STAT_EXT_INIT) {
3186 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3188 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3191 r8153b_ups_flags(tp);
3193 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3194 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3196 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3198 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3202 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3203 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3205 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3206 ocp_data &= ~BIT(0);
3207 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3209 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3210 ocp_data &= ~PCUT_STATUS;
3211 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3213 data = r8153_phy_status(tp, 0);
3216 case PHY_STAT_PWRDN:
3217 case PHY_STAT_EXT_INIT:
3219 test_bit(GREEN_ETHERNET, &tp->flags));
3221 data = r8152_mdio_read(tp, MII_BMCR);
3222 data &= ~BMCR_PDOWN;
3224 r8152_mdio_write(tp, MII_BMCR, data);
3226 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3230 if (data != PHY_STAT_LAN_ON)
3231 netif_warn(tp, link, tp->netdev,
3238 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3242 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3244 ocp_data |= PWR_EN | PHASE2_EN;
3246 ocp_data &= ~(PWR_EN | PHASE2_EN);
3247 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3249 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3250 ocp_data &= ~PCUT_STATUS;
3251 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3254 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3258 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3260 ocp_data |= PWR_EN | PHASE2_EN;
3262 ocp_data &= ~PWR_EN;
3263 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3265 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3266 ocp_data &= ~PCUT_STATUS;
3267 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3270 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3274 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3276 ocp_data |= UPCOMING_RUNTIME_D3;
3278 ocp_data &= ~UPCOMING_RUNTIME_D3;
3279 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3281 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3282 ocp_data &= ~LINK_CHG_EVENT;
3283 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3285 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3286 ocp_data &= ~LINK_CHANGE_FLAG;
3287 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3290 static bool rtl_can_wakeup(struct r8152 *tp)
3292 struct usb_device *udev = tp->udev;
3294 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3297 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3302 __rtl_set_wol(tp, WAKE_ANY);
3304 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3307 ocp_data |= LINK_OFF_WAKE_EN;
3308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3310 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3314 __rtl_set_wol(tp, tp->saved_wolopts);
3316 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3318 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3319 ocp_data &= ~LINK_OFF_WAKE_EN;
3320 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3322 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3326 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3329 r8153_u1u2en(tp, false);
3330 r8153_u2p3en(tp, false);
3331 r8153_mac_clk_spd(tp, true);
3332 rtl_runtime_suspend_enable(tp, true);
3334 rtl_runtime_suspend_enable(tp, false);
3335 r8153_mac_clk_spd(tp, false);
3337 switch (tp->version) {
3344 r8153_u2p3en(tp, true);
3348 r8153_u1u2en(tp, true);
3352 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3355 r8153_queue_wake(tp, true);
3356 r8153b_u1u2en(tp, false);
3357 r8153_u2p3en(tp, false);
3358 rtl_runtime_suspend_enable(tp, true);
3359 r8153b_ups_en(tp, true);
3361 r8153b_ups_en(tp, false);
3362 r8153_queue_wake(tp, false);
3363 rtl_runtime_suspend_enable(tp, false);
3364 r8153_u2p3en(tp, true);
3365 r8153b_u1u2en(tp, true);
3369 static void r8153_teredo_off(struct r8152 *tp)
3373 switch (tp->version) {
3381 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3382 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3389 /* The bit 0 ~ 7 are relative with teredo settings. They are
3390 * W1C (write 1 to clear), so set all 1 to disable it.
3392 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3399 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3400 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3401 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3404 static void rtl_reset_bmu(struct r8152 *tp)
3408 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3409 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3410 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3411 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3412 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3415 /* Clear the bp to stop the firmware before loading a new one */
3416 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3418 switch (tp->version) {
3427 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3432 if (type == MCU_TYPE_USB) {
3433 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3435 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3436 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3437 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3438 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3439 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3440 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3441 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3442 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3444 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3449 ocp_write_word(tp, type, PLA_BP_0, 0);
3450 ocp_write_word(tp, type, PLA_BP_1, 0);
3451 ocp_write_word(tp, type, PLA_BP_2, 0);
3452 ocp_write_word(tp, type, PLA_BP_3, 0);
3453 ocp_write_word(tp, type, PLA_BP_4, 0);
3454 ocp_write_word(tp, type, PLA_BP_5, 0);
3455 ocp_write_word(tp, type, PLA_BP_6, 0);
3456 ocp_write_word(tp, type, PLA_BP_7, 0);
3458 /* wait 3 ms to make sure the firmware is stopped */
3459 usleep_range(3000, 6000);
3460 ocp_write_word(tp, type, PLA_BP_BA, 0);
3463 static int r8153_patch_request(struct r8152 *tp, bool request)
3468 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3470 data |= PATCH_REQUEST;
3472 data &= ~PATCH_REQUEST;
3473 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3475 for (i = 0; request && i < 5000; i++) {
3476 usleep_range(1000, 2000);
3477 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3481 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3482 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3483 r8153_patch_request(tp, false);
3490 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3492 if (r8153_patch_request(tp, true)) {
3493 dev_err(&tp->intf->dev, "patch request fail\n");
3497 sram_write(tp, key_addr, patch_key);
3498 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3503 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3507 sram_write(tp, 0x0000, 0x0000);
3509 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3510 data &= ~PATCH_LOCK;
3511 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3513 sram_write(tp, key_addr, 0x0000);
3515 r8153_patch_request(tp, false);
3517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3522 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3525 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3528 switch (tp->version) {
3534 patch_en_addr = 0xa01a;
3542 fw_offset = __le16_to_cpu(phy->fw_offset);
3543 if (fw_offset < sizeof(*phy)) {
3544 dev_err(&tp->intf->dev, "fw_offset too small\n");
3548 length = __le32_to_cpu(phy->blk_hdr.length);
3549 if (length < fw_offset) {
3550 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3554 length -= __le16_to_cpu(phy->fw_offset);
3555 if (!length || (length & 1)) {
3556 dev_err(&tp->intf->dev, "invalid block length\n");
3560 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3561 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3565 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3566 dev_err(&tp->intf->dev, "invalid base address register\n");
3570 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3571 dev_err(&tp->intf->dev,
3572 "invalid patch mode enabled register\n");
3576 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3577 dev_err(&tp->intf->dev,
3578 "invalid register to switch the mode\n");
3582 if (__le16_to_cpu(phy->bp_start) != bp_start) {
3583 dev_err(&tp->intf->dev,
3584 "invalid start register of break point\n");
3588 if (__le16_to_cpu(phy->bp_num) > 4) {
3589 dev_err(&tp->intf->dev, "invalid break point number\n");
3598 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3600 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3605 type = __le32_to_cpu(mac->blk_hdr.type);
3606 if (type == RTL_FW_PLA) {
3607 switch (tp->version) {
3612 bp_ba_addr = PLA_BP_BA;
3614 bp_start = PLA_BP_0;
3624 bp_ba_addr = PLA_BP_BA;
3625 bp_en_addr = PLA_BP_EN;
3626 bp_start = PLA_BP_0;
3632 } else if (type == RTL_FW_USB) {
3633 switch (tp->version) {
3639 bp_ba_addr = USB_BP_BA;
3640 bp_en_addr = USB_BP_EN;
3641 bp_start = USB_BP_0;
3647 bp_ba_addr = USB_BP_BA;
3648 bp_en_addr = USB_BP2_EN;
3649 bp_start = USB_BP_0;
3662 fw_offset = __le16_to_cpu(mac->fw_offset);
3663 if (fw_offset < sizeof(*mac)) {
3664 dev_err(&tp->intf->dev, "fw_offset too small\n");
3668 length = __le32_to_cpu(mac->blk_hdr.length);
3669 if (length < fw_offset) {
3670 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3674 length -= fw_offset;
3675 if (length < 4 || (length & 3)) {
3676 dev_err(&tp->intf->dev, "invalid block length\n");
3680 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3681 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3685 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3686 dev_err(&tp->intf->dev, "invalid base address register\n");
3690 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3691 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3695 if (__le16_to_cpu(mac->bp_start) != bp_start) {
3696 dev_err(&tp->intf->dev,
3697 "invalid start register of break point\n");
3701 if (__le16_to_cpu(mac->bp_num) > max_bp) {
3702 dev_err(&tp->intf->dev, "invalid break point number\n");
3706 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3708 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3718 /* Verify the checksum for the firmware file. It is calculated from the version
3719 * field to the end of the file. Compare the result with the checksum field to
3720 * make sure the file is correct.
3722 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3723 struct fw_header *fw_hdr, size_t size)
3725 unsigned char checksum[sizeof(fw_hdr->checksum)];
3726 struct crypto_shash *alg;
3727 struct shash_desc *sdesc;
3731 alg = crypto_alloc_shash("sha256", 0, 0);
3737 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3739 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3740 crypto_shash_digestsize(alg));
3744 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3745 sdesc = kmalloc(len, GFP_KERNEL);
3752 len = size - sizeof(fw_hdr->checksum);
3753 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3758 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3759 dev_err(&tp->intf->dev, "checksum fail\n");
3764 crypto_free_shash(alg);
3769 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3771 const struct firmware *fw = rtl_fw->fw;
3772 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3773 struct fw_mac *pla = NULL, *usb = NULL;
3774 struct fw_phy_patch_key *start = NULL;
3775 struct fw_phy_nc *phy_nc = NULL;
3776 struct fw_block *stop = NULL;
3780 if (fw->size < sizeof(*fw_hdr)) {
3781 dev_err(&tp->intf->dev, "file too small\n");
3785 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3791 for (i = sizeof(*fw_hdr); i < fw->size;) {
3792 struct fw_block *block = (struct fw_block *)&fw->data[i];
3795 if ((i + sizeof(*block)) > fw->size)
3798 type = __le32_to_cpu(block->type);
3801 if (__le32_to_cpu(block->length) != sizeof(*block))
3806 dev_err(&tp->intf->dev,
3807 "multiple PLA firmware encountered");
3811 pla = (struct fw_mac *)block;
3812 if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3813 dev_err(&tp->intf->dev,
3814 "check PLA firmware failed\n");
3820 dev_err(&tp->intf->dev,
3821 "multiple USB firmware encountered");
3825 usb = (struct fw_mac *)block;
3826 if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3827 dev_err(&tp->intf->dev,
3828 "check USB firmware failed\n");
3832 case RTL_FW_PHY_START:
3833 if (start || phy_nc || stop) {
3834 dev_err(&tp->intf->dev,
3835 "check PHY_START fail\n");
3839 if (__le32_to_cpu(block->length) != sizeof(*start)) {
3840 dev_err(&tp->intf->dev,
3841 "Invalid length for PHY_START\n");
3845 start = (struct fw_phy_patch_key *)block;
3847 case RTL_FW_PHY_STOP:
3848 if (stop || !start) {
3849 dev_err(&tp->intf->dev,
3850 "Check PHY_STOP fail\n");
3854 if (__le32_to_cpu(block->length) != sizeof(*block)) {
3855 dev_err(&tp->intf->dev,
3856 "Invalid length for PHY_STOP\n");
3863 if (!start || stop) {
3864 dev_err(&tp->intf->dev,
3865 "check PHY_NC fail\n");
3870 dev_err(&tp->intf->dev,
3871 "multiple PHY NC encountered\n");
3875 phy_nc = (struct fw_phy_nc *)block;
3876 if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3877 dev_err(&tp->intf->dev,
3878 "check PHY NC firmware failed\n");
3884 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3890 i += ALIGN(__le32_to_cpu(block->length), 8);
3894 if ((phy_nc || start) && !stop) {
3895 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3904 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3906 u16 mode_reg, bp_index;
3910 mode_reg = __le16_to_cpu(phy->mode_reg);
3911 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3912 sram_write(tp, __le16_to_cpu(phy->ba_reg),
3913 __le16_to_cpu(phy->ba_data));
3915 length = __le32_to_cpu(phy->blk_hdr.length);
3916 length -= __le16_to_cpu(phy->fw_offset);
3918 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3920 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3921 for (i = 0; i < num; i++)
3922 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3924 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3925 __le16_to_cpu(phy->patch_en_value));
3927 bp_index = __le16_to_cpu(phy->bp_start);
3928 num = __le16_to_cpu(phy->bp_num);
3929 for (i = 0; i < num; i++) {
3930 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3934 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3936 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3939 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3941 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3946 switch (__le32_to_cpu(mac->blk_hdr.type)) {
3948 type = MCU_TYPE_PLA;
3951 type = MCU_TYPE_USB;
3957 rtl_clear_bp(tp, type);
3959 /* Enable backup/restore of MACDBG. This is required after clearing PLA
3960 * break points and before applying the PLA firmware.
3962 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3963 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3964 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3965 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3968 length = __le32_to_cpu(mac->blk_hdr.length);
3969 length -= __le16_to_cpu(mac->fw_offset);
3972 data += __le16_to_cpu(mac->fw_offset);
3974 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3977 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3978 __le16_to_cpu(mac->bp_ba_value));
3980 bp_index = __le16_to_cpu(mac->bp_start);
3981 bp_num = __le16_to_cpu(mac->bp_num);
3982 for (i = 0; i < bp_num; i++) {
3983 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3987 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3989 ocp_write_word(tp, type, bp_en_addr,
3990 __le16_to_cpu(mac->bp_en_value));
3992 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
3994 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
3997 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4000 static void rtl8152_apply_firmware(struct r8152 *tp)
4002 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4003 const struct firmware *fw = rtl_fw->fw;
4004 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4005 struct fw_phy_patch_key *key;
4009 if (IS_ERR_OR_NULL(rtl_fw->fw))
4015 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4016 struct fw_block *block = (struct fw_block *)&fw->data[i];
4018 switch (__le32_to_cpu(block->type)) {
4023 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4025 case RTL_FW_PHY_START:
4026 key = (struct fw_phy_patch_key *)block;
4027 key_addr = __le16_to_cpu(key->key_reg);
4028 r8153_pre_ram_code(tp, key_addr,
4029 __le16_to_cpu(key->key_data));
4031 case RTL_FW_PHY_STOP:
4033 r8153_post_ram_code(tp, key_addr);
4036 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4042 i += ALIGN(__le32_to_cpu(block->length), 8);
4046 if (rtl_fw->post_fw)
4047 rtl_fw->post_fw(tp);
4049 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4050 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4053 static void rtl8152_release_firmware(struct r8152 *tp)
4055 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4057 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4058 release_firmware(rtl_fw->fw);
4063 static int rtl8152_request_firmware(struct r8152 *tp)
4065 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4068 if (rtl_fw->fw || !rtl_fw->fw_name) {
4069 dev_info(&tp->intf->dev, "skip request firmware\n");
4074 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4078 rc = rtl8152_check_firmware(tp, rtl_fw);
4080 release_firmware(rtl_fw->fw);
4084 rtl_fw->fw = ERR_PTR(rc);
4086 dev_warn(&tp->intf->dev,
4087 "unable to load firmware patch %s (%ld)\n",
4088 rtl_fw->fw_name, rc);
4094 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4097 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4098 LINKENA | DIS_SDSAVE);
4100 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4106 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4108 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4109 ocp_reg_write(tp, OCP_EEE_DATA, reg);
4110 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4113 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4117 r8152_mmd_indirect(tp, dev, reg);
4118 data = ocp_reg_read(tp, OCP_EEE_DATA);
4119 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4124 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4126 r8152_mmd_indirect(tp, dev, reg);
4127 ocp_reg_write(tp, OCP_EEE_DATA, data);
4128 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4131 static void r8152_eee_en(struct r8152 *tp, bool enable)
4133 u16 config1, config2, config3;
4136 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4137 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4138 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4139 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4142 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4143 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4144 config1 |= sd_rise_time(1);
4145 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4146 config3 |= fast_snr(42);
4148 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4149 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4151 config1 |= sd_rise_time(7);
4152 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4153 config3 |= fast_snr(511);
4156 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4157 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4158 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4159 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4162 static void r8153_eee_en(struct r8152 *tp, bool enable)
4167 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4168 config = ocp_reg_read(tp, OCP_EEE_CFG);
4171 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4174 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4175 config &= ~EEE10_EN;
4178 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4179 ocp_reg_write(tp, OCP_EEE_CFG, config);
4181 tp->ups_info.eee = enable;
4184 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4186 switch (tp->version) {
4191 r8152_eee_en(tp, true);
4192 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4195 r8152_eee_en(tp, false);
4196 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4206 r8153_eee_en(tp, true);
4207 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4209 r8153_eee_en(tp, false);
4210 ocp_reg_write(tp, OCP_EEE_ADV, 0);
4218 static void r8152b_enable_fc(struct r8152 *tp)
4222 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4223 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4224 r8152_mdio_write(tp, MII_ADVERTISE, anar);
4226 tp->ups_info.flow_control = true;
4229 static void rtl8152_disable(struct r8152 *tp)
4231 r8152_aldps_en(tp, false);
4233 r8152_aldps_en(tp, true);
4236 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4238 rtl8152_apply_firmware(tp);
4239 rtl_eee_enable(tp, tp->eee_en);
4240 r8152_aldps_en(tp, true);
4241 r8152b_enable_fc(tp);
4243 set_bit(PHY_RESET, &tp->flags);
4246 static void wait_oob_link_list_ready(struct r8152 *tp)
4251 for (i = 0; i < 1000; i++) {
4252 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4253 if (ocp_data & LINK_LIST_READY)
4255 usleep_range(1000, 2000);
4259 static void r8152b_exit_oob(struct r8152 *tp)
4263 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4264 ocp_data &= ~RCR_ACPT_ALL;
4265 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4267 rxdy_gated_en(tp, true);
4268 r8153_teredo_off(tp);
4269 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4270 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4272 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4273 ocp_data &= ~NOW_IS_OOB;
4274 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4276 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4277 ocp_data &= ~MCU_BORW_EN;
4278 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4280 wait_oob_link_list_ready(tp);
4282 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4283 ocp_data |= RE_INIT_LL;
4284 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4286 wait_oob_link_list_ready(tp);
4288 rtl8152_nic_reset(tp);
4290 /* rx share fifo credit full threshold */
4291 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4293 if (tp->udev->speed == USB_SPEED_FULL ||
4294 tp->udev->speed == USB_SPEED_LOW) {
4295 /* rx share fifo credit near full threshold */
4296 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4298 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4301 /* rx share fifo credit near full threshold */
4302 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4304 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4308 /* TX share fifo free credit full threshold */
4309 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4311 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4312 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4313 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4314 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4316 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4318 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4320 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4321 ocp_data |= TCR0_AUTO_FIFO;
4322 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4325 static void r8152b_enter_oob(struct r8152 *tp)
4329 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4330 ocp_data &= ~NOW_IS_OOB;
4331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4333 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4334 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4335 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4339 wait_oob_link_list_ready(tp);
4341 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4342 ocp_data |= RE_INIT_LL;
4343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4345 wait_oob_link_list_ready(tp);
4347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4349 rtl_rx_vlan_en(tp, true);
4351 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4352 ocp_data |= ALDPS_PROXY_MODE;
4353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4355 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4356 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4357 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4359 rxdy_gated_en(tp, false);
4361 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4362 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4363 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4366 static int r8153_pre_firmware_1(struct r8152 *tp)
4370 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4371 for (i = 0; i < 104; i++) {
4372 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4374 if (!(ocp_data & WTD1_EN))
4376 usleep_range(1000, 2000);
4382 static int r8153_post_firmware_1(struct r8152 *tp)
4384 /* set USB_BP_4 to support USB_SPEED_SUPER only */
4385 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4386 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4388 /* reset UPHY timer to 36 ms */
4389 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4394 static int r8153_pre_firmware_2(struct r8152 *tp)
4398 r8153_pre_firmware_1(tp);
4400 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4401 ocp_data &= ~FW_FIX_SUSPEND;
4402 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4407 static int r8153_post_firmware_2(struct r8152 *tp)
4411 /* enable bp0 if support USB_SPEED_SUPER only */
4412 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4413 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4418 /* reset UPHY timer to 36 ms */
4419 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4421 /* enable U3P3 check, set the counter to 4 */
4422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4424 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4425 ocp_data |= FW_FIX_SUSPEND;
4426 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4428 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4429 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4430 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4435 static int r8153_post_firmware_3(struct r8152 *tp)
4439 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4440 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4441 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4443 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4444 ocp_data |= FW_IP_RESET_EN;
4445 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4450 static int r8153b_pre_firmware_1(struct r8152 *tp)
4452 /* enable fc timer and set timer to 1 second. */
4453 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4454 CTRL_TIMER_EN | (1000 / 8));
4459 static int r8153b_post_firmware_1(struct r8152 *tp)
4463 /* enable bp0 for RTL8153-BND */
4464 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4465 if (ocp_data & BND_MASK) {
4466 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4468 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4471 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4472 ocp_data |= FLOW_CTRL_PATCH_OPT;
4473 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4475 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4476 ocp_data |= FC_PATCH_TASK;
4477 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4480 ocp_data |= FW_IP_RESET_EN;
4481 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4486 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4490 data = ocp_reg_read(tp, OCP_POWER_CFG);
4493 ocp_reg_write(tp, OCP_POWER_CFG, data);
4498 ocp_reg_write(tp, OCP_POWER_CFG, data);
4499 for (i = 0; i < 20; i++) {
4500 usleep_range(1000, 2000);
4501 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4506 tp->ups_info.aldps = enable;
4509 static void r8153_hw_phy_cfg(struct r8152 *tp)
4514 /* disable ALDPS before updating the PHY parameters */
4515 r8153_aldps_en(tp, false);
4517 /* disable EEE before updating the PHY parameters */
4518 rtl_eee_enable(tp, false);
4520 rtl8152_apply_firmware(tp);
4522 if (tp->version == RTL_VER_03) {
4523 data = ocp_reg_read(tp, OCP_EEE_CFG);
4524 data &= ~CTAP_SHORT_EN;
4525 ocp_reg_write(tp, OCP_EEE_CFG, data);
4528 data = ocp_reg_read(tp, OCP_POWER_CFG);
4529 data |= EEE_CLKDIV_EN;
4530 ocp_reg_write(tp, OCP_POWER_CFG, data);
4532 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4533 data |= EN_10M_BGOFF;
4534 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4535 data = ocp_reg_read(tp, OCP_POWER_CFG);
4536 data |= EN_10M_PLLOFF;
4537 ocp_reg_write(tp, OCP_POWER_CFG, data);
4538 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4541 ocp_data |= PFM_PWM_SWITCH;
4542 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4544 /* Enable LPF corner auto tune */
4545 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4547 /* Adjust 10M Amplitude */
4548 sram_write(tp, SRAM_10M_AMP1, 0x00af);
4549 sram_write(tp, SRAM_10M_AMP2, 0x0208);
4552 rtl_eee_enable(tp, true);
4554 r8153_aldps_en(tp, true);
4555 r8152b_enable_fc(tp);
4557 switch (tp->version) {
4564 r8153_u2p3en(tp, true);
4568 set_bit(PHY_RESET, &tp->flags);
4571 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4576 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4577 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
4578 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4583 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4588 /* disable ALDPS before updating the PHY parameters */
4589 r8153_aldps_en(tp, false);
4591 /* disable EEE before updating the PHY parameters */
4592 rtl_eee_enable(tp, false);
4594 rtl8152_apply_firmware(tp);
4596 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4598 data = sram_read(tp, SRAM_GREEN_CFG);
4600 sram_write(tp, SRAM_GREEN_CFG, data);
4601 data = ocp_reg_read(tp, OCP_NCTL_CFG);
4602 data |= PGA_RETURN_EN;
4603 ocp_reg_write(tp, OCP_NCTL_CFG, data);
4605 /* ADC Bias Calibration:
4606 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4607 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4610 ocp_data = r8152_efuse_read(tp, 0x7d);
4611 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4613 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4615 /* ups mode tx-link-pulse timing adjustment:
4616 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4617 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4619 ocp_data = ocp_reg_read(tp, 0xc426);
4622 u32 swr_cnt_1ms_ini;
4624 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4625 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4626 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4627 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4630 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4631 ocp_data |= PFM_PWM_SWITCH;
4632 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4635 if (!r8153_patch_request(tp, true)) {
4636 data = ocp_reg_read(tp, OCP_POWER_CFG);
4637 data |= EEE_CLKDIV_EN;
4638 ocp_reg_write(tp, OCP_POWER_CFG, data);
4639 tp->ups_info.eee_ckdiv = true;
4641 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4642 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4643 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4644 tp->ups_info.eee_cmod_lv = true;
4645 tp->ups_info._10m_ckdiv = true;
4646 tp->ups_info.eee_plloff_giga = true;
4648 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4649 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4650 tp->ups_info._250m_ckdiv = true;
4652 r8153_patch_request(tp, false);
4656 rtl_eee_enable(tp, true);
4658 r8153_aldps_en(tp, true);
4659 r8152b_enable_fc(tp);
4660 r8153_u2p3en(tp, true);
4662 set_bit(PHY_RESET, &tp->flags);
4665 static void r8153_first_init(struct r8152 *tp)
4669 r8153_mac_clk_spd(tp, false);
4670 rxdy_gated_en(tp, true);
4671 r8153_teredo_off(tp);
4673 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4674 ocp_data &= ~RCR_ACPT_ALL;
4675 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4677 rtl8152_nic_reset(tp);
4680 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4681 ocp_data &= ~NOW_IS_OOB;
4682 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4684 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4685 ocp_data &= ~MCU_BORW_EN;
4686 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4688 wait_oob_link_list_ready(tp);
4690 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4691 ocp_data |= RE_INIT_LL;
4692 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4694 wait_oob_link_list_ready(tp);
4696 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4698 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4699 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4700 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4703 ocp_data |= TCR0_AUTO_FIFO;
4704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4706 rtl8152_nic_reset(tp);
4708 /* rx share fifo credit full threshold */
4709 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4710 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4711 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4712 /* TX share fifo free credit full threshold */
4713 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4716 static void r8153_enter_oob(struct r8152 *tp)
4720 r8153_mac_clk_spd(tp, true);
4722 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4723 ocp_data &= ~NOW_IS_OOB;
4724 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4729 wait_oob_link_list_ready(tp);
4731 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4732 ocp_data |= RE_INIT_LL;
4733 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4735 wait_oob_link_list_ready(tp);
4737 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4738 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4740 switch (tp->version) {
4745 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4746 ocp_data &= ~TEREDO_WAKE_MASK;
4747 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4752 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4753 * type. Set it to zero. bits[7:0] are the W1C bits about
4754 * the events. Set them to all 1 to clear them.
4756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4763 rtl_rx_vlan_en(tp, true);
4765 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4766 ocp_data |= ALDPS_PROXY_MODE;
4767 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4769 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4770 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4771 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4773 rxdy_gated_en(tp, false);
4775 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4776 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4777 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4780 static void rtl8153_disable(struct r8152 *tp)
4782 r8153_aldps_en(tp, false);
4785 r8153_aldps_en(tp, true);
4788 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4794 if (autoneg == AUTONEG_DISABLE) {
4795 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4800 bmcr = BMCR_SPEED10;
4801 if (duplex == DUPLEX_FULL) {
4802 bmcr |= BMCR_FULLDPLX;
4803 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4805 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4809 bmcr = BMCR_SPEED100;
4810 if (duplex == DUPLEX_FULL) {
4811 bmcr |= BMCR_FULLDPLX;
4812 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4814 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4818 if (tp->mii.supports_gmii) {
4819 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4820 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4829 if (duplex == DUPLEX_FULL)
4830 tp->mii.full_duplex = 1;
4832 tp->mii.full_duplex = 0;
4834 tp->mii.force_media = 1;
4839 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4840 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4842 if (tp->mii.supports_gmii)
4843 support |= RTL_ADVERTISED_1000_FULL;
4845 if (!(advertising & support))
4848 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4849 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4850 ADVERTISE_100HALF | ADVERTISE_100FULL);
4851 if (advertising & RTL_ADVERTISED_10_HALF) {
4852 tmp1 |= ADVERTISE_10HALF;
4853 tp->ups_info.speed_duplex = NWAY_10M_HALF;
4855 if (advertising & RTL_ADVERTISED_10_FULL) {
4856 tmp1 |= ADVERTISE_10FULL;
4857 tp->ups_info.speed_duplex = NWAY_10M_FULL;
4860 if (advertising & RTL_ADVERTISED_100_HALF) {
4861 tmp1 |= ADVERTISE_100HALF;
4862 tp->ups_info.speed_duplex = NWAY_100M_HALF;
4864 if (advertising & RTL_ADVERTISED_100_FULL) {
4865 tmp1 |= ADVERTISE_100FULL;
4866 tp->ups_info.speed_duplex = NWAY_100M_FULL;
4870 r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4871 tp->mii.advertising = tmp1;
4874 if (tp->mii.supports_gmii) {
4877 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4878 tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4879 ADVERTISE_1000HALF);
4881 if (advertising & RTL_ADVERTISED_1000_FULL) {
4882 tmp1 |= ADVERTISE_1000FULL;
4883 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4887 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4890 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4892 tp->mii.force_media = 0;
4895 if (test_and_clear_bit(PHY_RESET, &tp->flags))
4898 r8152_mdio_write(tp, MII_BMCR, bmcr);
4900 if (bmcr & BMCR_RESET) {
4903 for (i = 0; i < 50; i++) {
4905 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4914 static void rtl8152_up(struct r8152 *tp)
4916 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4919 r8152_aldps_en(tp, false);
4920 r8152b_exit_oob(tp);
4921 r8152_aldps_en(tp, true);
4924 static void rtl8152_down(struct r8152 *tp)
4926 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4927 rtl_drop_queued_tx(tp);
4931 r8152_power_cut_en(tp, false);
4932 r8152_aldps_en(tp, false);
4933 r8152b_enter_oob(tp);
4934 r8152_aldps_en(tp, true);
4937 static void rtl8153_up(struct r8152 *tp)
4939 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4942 r8153_u1u2en(tp, false);
4943 r8153_u2p3en(tp, false);
4944 r8153_aldps_en(tp, false);
4945 r8153_first_init(tp);
4946 r8153_aldps_en(tp, true);
4948 switch (tp->version) {
4955 r8153_u2p3en(tp, true);
4959 r8153_u1u2en(tp, true);
4962 static void rtl8153_down(struct r8152 *tp)
4964 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4965 rtl_drop_queued_tx(tp);
4969 r8153_u1u2en(tp, false);
4970 r8153_u2p3en(tp, false);
4971 r8153_power_cut_en(tp, false);
4972 r8153_aldps_en(tp, false);
4973 r8153_enter_oob(tp);
4974 r8153_aldps_en(tp, true);
4977 static void rtl8153b_up(struct r8152 *tp)
4979 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4982 r8153b_u1u2en(tp, false);
4983 r8153_u2p3en(tp, false);
4984 r8153_aldps_en(tp, false);
4986 r8153_first_init(tp);
4987 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
4989 r8153_aldps_en(tp, true);
4990 r8153_u2p3en(tp, true);
4991 r8153b_u1u2en(tp, true);
4994 static void rtl8153b_down(struct r8152 *tp)
4996 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4997 rtl_drop_queued_tx(tp);
5001 r8153b_u1u2en(tp, false);
5002 r8153_u2p3en(tp, false);
5003 r8153b_power_cut_en(tp, false);
5004 r8153_aldps_en(tp, false);
5005 r8153_enter_oob(tp);
5006 r8153_aldps_en(tp, true);
5009 static bool rtl8152_in_nway(struct r8152 *tp)
5013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5014 tp->ocp_base = 0x2000;
5015 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
5016 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5018 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5019 if (nway_state & 0xc000)
5025 static bool rtl8153_in_nway(struct r8152 *tp)
5027 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5029 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5035 static void set_carrier(struct r8152 *tp)
5037 struct net_device *netdev = tp->netdev;
5038 struct napi_struct *napi = &tp->napi;
5041 speed = rtl8152_get_speed(tp);
5043 if (speed & LINK_STATUS) {
5044 if (!netif_carrier_ok(netdev)) {
5045 tp->rtl_ops.enable(tp);
5046 netif_stop_queue(netdev);
5048 netif_carrier_on(netdev);
5050 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5051 _rtl8152_set_rx_mode(netdev);
5052 napi_enable(&tp->napi);
5053 netif_wake_queue(netdev);
5054 netif_info(tp, link, netdev, "carrier on\n");
5055 } else if (netif_queue_stopped(netdev) &&
5056 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5057 netif_wake_queue(netdev);
5060 if (netif_carrier_ok(netdev)) {
5061 netif_carrier_off(netdev);
5062 tasklet_disable(&tp->tx_tl);
5064 tp->rtl_ops.disable(tp);
5066 tasklet_enable(&tp->tx_tl);
5067 netif_info(tp, link, netdev, "carrier off\n");
5072 static void rtl_work_func_t(struct work_struct *work)
5074 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5076 /* If the device is unplugged or !netif_running(), the workqueue
5077 * doesn't need to wake the device, and could return directly.
5079 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5082 if (usb_autopm_get_interface(tp->intf) < 0)
5085 if (!test_bit(WORK_ENABLE, &tp->flags))
5088 if (!mutex_trylock(&tp->control)) {
5089 schedule_delayed_work(&tp->schedule, 0);
5093 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5096 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5097 _rtl8152_set_rx_mode(tp->netdev);
5099 /* don't schedule tasket before linking */
5100 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5101 netif_carrier_ok(tp->netdev))
5102 tasklet_schedule(&tp->tx_tl);
5104 mutex_unlock(&tp->control);
5107 usb_autopm_put_interface(tp->intf);
5110 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5112 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5114 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5117 if (usb_autopm_get_interface(tp->intf) < 0)
5120 mutex_lock(&tp->control);
5122 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5123 tp->rtl_fw.retry = false;
5124 tp->rtl_fw.fw = NULL;
5126 /* Delay execution in case request_firmware() is not ready yet.
5128 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5132 tp->rtl_ops.hw_phy_cfg(tp);
5134 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5138 mutex_unlock(&tp->control);
5140 usb_autopm_put_interface(tp->intf);
5143 #ifdef CONFIG_PM_SLEEP
5144 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5147 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5150 case PM_HIBERNATION_PREPARE:
5151 case PM_SUSPEND_PREPARE:
5152 usb_autopm_get_interface(tp->intf);
5155 case PM_POST_HIBERNATION:
5156 case PM_POST_SUSPEND:
5157 usb_autopm_put_interface(tp->intf);
5160 case PM_POST_RESTORE:
5161 case PM_RESTORE_PREPARE:
5170 static int rtl8152_open(struct net_device *netdev)
5172 struct r8152 *tp = netdev_priv(netdev);
5175 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5176 cancel_delayed_work_sync(&tp->hw_phy_work);
5177 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5180 res = alloc_all_mem(tp);
5184 res = usb_autopm_get_interface(tp->intf);
5188 mutex_lock(&tp->control);
5192 netif_carrier_off(netdev);
5193 netif_start_queue(netdev);
5194 set_bit(WORK_ENABLE, &tp->flags);
5196 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5199 netif_device_detach(tp->netdev);
5200 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5204 napi_enable(&tp->napi);
5205 tasklet_enable(&tp->tx_tl);
5207 mutex_unlock(&tp->control);
5209 usb_autopm_put_interface(tp->intf);
5210 #ifdef CONFIG_PM_SLEEP
5211 tp->pm_notifier.notifier_call = rtl_notifier;
5212 register_pm_notifier(&tp->pm_notifier);
5217 mutex_unlock(&tp->control);
5218 usb_autopm_put_interface(tp->intf);
5225 static int rtl8152_close(struct net_device *netdev)
5227 struct r8152 *tp = netdev_priv(netdev);
5230 #ifdef CONFIG_PM_SLEEP
5231 unregister_pm_notifier(&tp->pm_notifier);
5233 tasklet_disable(&tp->tx_tl);
5234 napi_disable(&tp->napi);
5235 clear_bit(WORK_ENABLE, &tp->flags);
5236 usb_kill_urb(tp->intr_urb);
5237 cancel_delayed_work_sync(&tp->schedule);
5238 netif_stop_queue(netdev);
5240 res = usb_autopm_get_interface(tp->intf);
5241 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5242 rtl_drop_queued_tx(tp);
5245 mutex_lock(&tp->control);
5247 tp->rtl_ops.down(tp);
5249 mutex_unlock(&tp->control);
5251 usb_autopm_put_interface(tp->intf);
5259 static void rtl_tally_reset(struct r8152 *tp)
5263 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5264 ocp_data |= TALLY_RESET;
5265 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5268 static void r8152b_init(struct r8152 *tp)
5273 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5276 data = r8152_mdio_read(tp, MII_BMCR);
5277 if (data & BMCR_PDOWN) {
5278 data &= ~BMCR_PDOWN;
5279 r8152_mdio_write(tp, MII_BMCR, data);
5282 r8152_aldps_en(tp, false);
5284 if (tp->version == RTL_VER_01) {
5285 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5286 ocp_data &= ~LED_MODE_MASK;
5287 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5290 r8152_power_cut_en(tp, false);
5292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5293 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5295 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5296 ocp_data &= ~MCU_CLK_RATIO_MASK;
5297 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5298 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5299 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5300 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5301 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5303 rtl_tally_reset(tp);
5305 /* enable rx aggregation */
5306 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5307 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5308 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5311 static void r8153_init(struct r8152 *tp)
5317 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5320 r8153_u1u2en(tp, false);
5322 for (i = 0; i < 500; i++) {
5323 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5329 data = r8153_phy_status(tp, 0);
5331 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5332 tp->version == RTL_VER_05)
5333 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5335 data = r8152_mdio_read(tp, MII_BMCR);
5336 if (data & BMCR_PDOWN) {
5337 data &= ~BMCR_PDOWN;
5338 r8152_mdio_write(tp, MII_BMCR, data);
5341 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5343 r8153_u2p3en(tp, false);
5345 if (tp->version == RTL_VER_04) {
5346 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5347 ocp_data &= ~pwd_dn_scale_mask;
5348 ocp_data |= pwd_dn_scale(96);
5349 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5351 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5352 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5353 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5354 } else if (tp->version == RTL_VER_05) {
5355 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5356 ocp_data &= ~ECM_ALDPS;
5357 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5359 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5360 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5361 ocp_data &= ~DYNAMIC_BURST;
5363 ocp_data |= DYNAMIC_BURST;
5364 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5365 } else if (tp->version == RTL_VER_06) {
5366 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5367 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5368 ocp_data &= ~DYNAMIC_BURST;
5370 ocp_data |= DYNAMIC_BURST;
5371 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5374 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5375 ocp_data |= EP4_FULL_FC;
5376 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5378 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5379 ocp_data &= ~TIMER11_EN;
5380 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5383 ocp_data &= ~LED_MODE_MASK;
5384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5386 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5387 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5388 ocp_data |= LPM_TIMER_500MS;
5390 ocp_data |= LPM_TIMER_500US;
5391 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5393 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5394 ocp_data &= ~SEN_VAL_MASK;
5395 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5396 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5398 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5400 r8153_power_cut_en(tp, false);
5401 r8153_u1u2en(tp, true);
5402 r8153_mac_clk_spd(tp, false);
5403 usb_enable_lpm(tp->udev);
5405 /* rx aggregation */
5406 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5407 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5408 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5409 ocp_data |= RX_AGG_DISABLE;
5411 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5413 rtl_tally_reset(tp);
5415 switch (tp->udev->speed) {
5416 case USB_SPEED_SUPER:
5417 case USB_SPEED_SUPER_PLUS:
5418 tp->coalesce = COALESCE_SUPER;
5420 case USB_SPEED_HIGH:
5421 tp->coalesce = COALESCE_HIGH;
5424 tp->coalesce = COALESCE_SLOW;
5429 static void r8153b_init(struct r8152 *tp)
5435 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5438 r8153b_u1u2en(tp, false);
5440 for (i = 0; i < 500; i++) {
5441 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5447 data = r8153_phy_status(tp, 0);
5449 data = r8152_mdio_read(tp, MII_BMCR);
5450 if (data & BMCR_PDOWN) {
5451 data &= ~BMCR_PDOWN;
5452 r8152_mdio_write(tp, MII_BMCR, data);
5455 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5457 r8153_u2p3en(tp, false);
5459 /* MSC timer = 0xfff * 8ms = 32760 ms */
5460 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5462 /* U1/U2/L1 idle timer. 500 us */
5463 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5465 r8153b_power_cut_en(tp, false);
5466 r8153b_ups_en(tp, false);
5467 r8153_queue_wake(tp, false);
5468 rtl_runtime_suspend_enable(tp, false);
5469 r8153b_u1u2en(tp, true);
5470 usb_enable_lpm(tp->udev);
5472 /* MAC clock speed down */
5473 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5474 ocp_data |= MAC_CLK_SPDWN_EN;
5475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5477 set_bit(GREEN_ETHERNET, &tp->flags);
5479 /* rx aggregation */
5480 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5481 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5482 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5484 rtl_tally_reset(tp);
5486 tp->coalesce = 15000; /* 15 us */
5489 static int rtl8152_pre_reset(struct usb_interface *intf)
5491 struct r8152 *tp = usb_get_intfdata(intf);
5492 struct net_device *netdev;
5497 netdev = tp->netdev;
5498 if (!netif_running(netdev))
5501 netif_stop_queue(netdev);
5502 tasklet_disable(&tp->tx_tl);
5503 napi_disable(&tp->napi);
5504 clear_bit(WORK_ENABLE, &tp->flags);
5505 usb_kill_urb(tp->intr_urb);
5506 cancel_delayed_work_sync(&tp->schedule);
5507 if (netif_carrier_ok(netdev)) {
5508 mutex_lock(&tp->control);
5509 tp->rtl_ops.disable(tp);
5510 mutex_unlock(&tp->control);
5516 static int rtl8152_post_reset(struct usb_interface *intf)
5518 struct r8152 *tp = usb_get_intfdata(intf);
5519 struct net_device *netdev;
5525 /* reset the MAC adddress in case of policy change */
5526 if (determine_ethernet_addr(tp, &sa) >= 0) {
5528 dev_set_mac_address (tp->netdev, &sa, NULL);
5532 netdev = tp->netdev;
5533 if (!netif_running(netdev))
5536 set_bit(WORK_ENABLE, &tp->flags);
5537 if (netif_carrier_ok(netdev)) {
5538 mutex_lock(&tp->control);
5539 tp->rtl_ops.enable(tp);
5541 _rtl8152_set_rx_mode(netdev);
5542 mutex_unlock(&tp->control);
5545 napi_enable(&tp->napi);
5546 tasklet_enable(&tp->tx_tl);
5547 netif_wake_queue(netdev);
5548 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5550 if (!list_empty(&tp->rx_done))
5551 napi_schedule(&tp->napi);
5556 static bool delay_autosuspend(struct r8152 *tp)
5558 bool sw_linking = !!netif_carrier_ok(tp->netdev);
5559 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5561 /* This means a linking change occurs and the driver doesn't detect it,
5562 * yet. If the driver has disabled tx/rx and hw is linking on, the
5563 * device wouldn't wake up by receiving any packet.
5565 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5568 /* If the linking down is occurred by nway, the device may miss the
5569 * linking change event. And it wouldn't wake when linking on.
5571 if (!sw_linking && tp->rtl_ops.in_nway(tp))
5573 else if (!skb_queue_empty(&tp->tx_queue))
5579 static int rtl8152_runtime_resume(struct r8152 *tp)
5581 struct net_device *netdev = tp->netdev;
5583 if (netif_running(netdev) && netdev->flags & IFF_UP) {
5584 struct napi_struct *napi = &tp->napi;
5586 tp->rtl_ops.autosuspend_en(tp, false);
5588 set_bit(WORK_ENABLE, &tp->flags);
5590 if (netif_carrier_ok(netdev)) {
5591 if (rtl8152_get_speed(tp) & LINK_STATUS) {
5594 netif_carrier_off(netdev);
5595 tp->rtl_ops.disable(tp);
5596 netif_info(tp, link, netdev, "linking down\n");
5601 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5602 smp_mb__after_atomic();
5604 if (!list_empty(&tp->rx_done))
5605 napi_schedule(&tp->napi);
5607 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5609 if (netdev->flags & IFF_UP)
5610 tp->rtl_ops.autosuspend_en(tp, false);
5612 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5618 static int rtl8152_system_resume(struct r8152 *tp)
5620 struct net_device *netdev = tp->netdev;
5622 netif_device_attach(netdev);
5624 if (netif_running(netdev) && netdev->flags & IFF_UP) {
5626 netif_carrier_off(netdev);
5627 set_bit(WORK_ENABLE, &tp->flags);
5628 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5634 static int rtl8152_runtime_suspend(struct r8152 *tp)
5636 struct net_device *netdev = tp->netdev;
5639 set_bit(SELECTIVE_SUSPEND, &tp->flags);
5640 smp_mb__after_atomic();
5642 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5645 if (netif_carrier_ok(netdev)) {
5648 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5649 ocp_data = rcr & ~RCR_ACPT_ALL;
5650 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5651 rxdy_gated_en(tp, true);
5652 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5654 if (!(ocp_data & RXFIFO_EMPTY)) {
5655 rxdy_gated_en(tp, false);
5656 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5657 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5658 smp_mb__after_atomic();
5664 clear_bit(WORK_ENABLE, &tp->flags);
5665 usb_kill_urb(tp->intr_urb);
5667 tp->rtl_ops.autosuspend_en(tp, true);
5669 if (netif_carrier_ok(netdev)) {
5670 struct napi_struct *napi = &tp->napi;
5674 rxdy_gated_en(tp, false);
5675 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5679 if (delay_autosuspend(tp)) {
5680 rtl8152_runtime_resume(tp);
5689 static int rtl8152_system_suspend(struct r8152 *tp)
5691 struct net_device *netdev = tp->netdev;
5693 netif_device_detach(netdev);
5695 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5696 struct napi_struct *napi = &tp->napi;
5698 clear_bit(WORK_ENABLE, &tp->flags);
5699 usb_kill_urb(tp->intr_urb);
5700 tasklet_disable(&tp->tx_tl);
5702 cancel_delayed_work_sync(&tp->schedule);
5703 tp->rtl_ops.down(tp);
5705 tasklet_enable(&tp->tx_tl);
5711 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5713 struct r8152 *tp = usb_get_intfdata(intf);
5716 mutex_lock(&tp->control);
5718 if (PMSG_IS_AUTO(message))
5719 ret = rtl8152_runtime_suspend(tp);
5721 ret = rtl8152_system_suspend(tp);
5723 mutex_unlock(&tp->control);
5728 static int rtl8152_resume(struct usb_interface *intf)
5730 struct r8152 *tp = usb_get_intfdata(intf);
5733 mutex_lock(&tp->control);
5735 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5736 ret = rtl8152_runtime_resume(tp);
5738 ret = rtl8152_system_resume(tp);
5740 mutex_unlock(&tp->control);
5745 static int rtl8152_reset_resume(struct usb_interface *intf)
5747 struct r8152 *tp = usb_get_intfdata(intf);
5749 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5750 tp->rtl_ops.init(tp);
5751 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5752 set_ethernet_addr(tp);
5753 return rtl8152_resume(intf);
5756 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5758 struct r8152 *tp = netdev_priv(dev);
5760 if (usb_autopm_get_interface(tp->intf) < 0)
5763 if (!rtl_can_wakeup(tp)) {
5767 mutex_lock(&tp->control);
5768 wol->supported = WAKE_ANY;
5769 wol->wolopts = __rtl_get_wol(tp);
5770 mutex_unlock(&tp->control);
5773 usb_autopm_put_interface(tp->intf);
5776 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5778 struct r8152 *tp = netdev_priv(dev);
5781 if (!rtl_can_wakeup(tp))
5784 if (wol->wolopts & ~WAKE_ANY)
5787 ret = usb_autopm_get_interface(tp->intf);
5791 mutex_lock(&tp->control);
5793 __rtl_set_wol(tp, wol->wolopts);
5794 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5796 mutex_unlock(&tp->control);
5798 usb_autopm_put_interface(tp->intf);
5804 static u32 rtl8152_get_msglevel(struct net_device *dev)
5806 struct r8152 *tp = netdev_priv(dev);
5808 return tp->msg_enable;
5811 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5813 struct r8152 *tp = netdev_priv(dev);
5815 tp->msg_enable = value;
5818 static void rtl8152_get_drvinfo(struct net_device *netdev,
5819 struct ethtool_drvinfo *info)
5821 struct r8152 *tp = netdev_priv(netdev);
5823 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5824 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5825 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5826 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5827 strlcpy(info->fw_version, tp->rtl_fw.version,
5828 sizeof(info->fw_version));
5832 int rtl8152_get_link_ksettings(struct net_device *netdev,
5833 struct ethtool_link_ksettings *cmd)
5835 struct r8152 *tp = netdev_priv(netdev);
5838 if (!tp->mii.mdio_read)
5841 ret = usb_autopm_get_interface(tp->intf);
5845 mutex_lock(&tp->control);
5847 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5849 mutex_unlock(&tp->control);
5851 usb_autopm_put_interface(tp->intf);
5857 static int rtl8152_set_link_ksettings(struct net_device *dev,
5858 const struct ethtool_link_ksettings *cmd)
5860 struct r8152 *tp = netdev_priv(dev);
5861 u32 advertising = 0;
5864 ret = usb_autopm_get_interface(tp->intf);
5868 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5869 cmd->link_modes.advertising))
5870 advertising |= RTL_ADVERTISED_10_HALF;
5872 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5873 cmd->link_modes.advertising))
5874 advertising |= RTL_ADVERTISED_10_FULL;
5876 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5877 cmd->link_modes.advertising))
5878 advertising |= RTL_ADVERTISED_100_HALF;
5880 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5881 cmd->link_modes.advertising))
5882 advertising |= RTL_ADVERTISED_100_FULL;
5884 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5885 cmd->link_modes.advertising))
5886 advertising |= RTL_ADVERTISED_1000_HALF;
5888 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5889 cmd->link_modes.advertising))
5890 advertising |= RTL_ADVERTISED_1000_FULL;
5892 mutex_lock(&tp->control);
5894 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5895 cmd->base.duplex, advertising);
5897 tp->autoneg = cmd->base.autoneg;
5898 tp->speed = cmd->base.speed;
5899 tp->duplex = cmd->base.duplex;
5900 tp->advertising = advertising;
5903 mutex_unlock(&tp->control);
5905 usb_autopm_put_interface(tp->intf);
5911 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
5918 "tx_single_collisions",
5919 "tx_multi_collisions",
5927 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
5931 return ARRAY_SIZE(rtl8152_gstrings);
5937 static void rtl8152_get_ethtool_stats(struct net_device *dev,
5938 struct ethtool_stats *stats, u64 *data)
5940 struct r8152 *tp = netdev_priv(dev);
5941 struct tally_counter tally;
5943 if (usb_autopm_get_interface(tp->intf) < 0)
5946 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
5948 usb_autopm_put_interface(tp->intf);
5950 data[0] = le64_to_cpu(tally.tx_packets);
5951 data[1] = le64_to_cpu(tally.rx_packets);
5952 data[2] = le64_to_cpu(tally.tx_errors);
5953 data[3] = le32_to_cpu(tally.rx_errors);
5954 data[4] = le16_to_cpu(tally.rx_missed);
5955 data[5] = le16_to_cpu(tally.align_errors);
5956 data[6] = le32_to_cpu(tally.tx_one_collision);
5957 data[7] = le32_to_cpu(tally.tx_multi_collision);
5958 data[8] = le64_to_cpu(tally.rx_unicast);
5959 data[9] = le64_to_cpu(tally.rx_broadcast);
5960 data[10] = le32_to_cpu(tally.rx_multicast);
5961 data[11] = le16_to_cpu(tally.tx_aborted);
5962 data[12] = le16_to_cpu(tally.tx_underrun);
5965 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5967 switch (stringset) {
5969 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
5974 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
5976 u32 lp, adv, supported = 0;
5979 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
5980 supported = mmd_eee_cap_to_ethtool_sup_t(val);
5982 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
5983 adv = mmd_eee_adv_to_ethtool_adv_t(val);
5985 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
5986 lp = mmd_eee_adv_to_ethtool_adv_t(val);
5988 eee->eee_enabled = tp->eee_en;
5989 eee->eee_active = !!(supported & adv & lp);
5990 eee->supported = supported;
5991 eee->advertised = tp->eee_adv;
5992 eee->lp_advertised = lp;
5997 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
5999 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6001 tp->eee_en = eee->eee_enabled;
6004 rtl_eee_enable(tp, tp->eee_en);
6009 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6011 u32 lp, adv, supported = 0;
6014 val = ocp_reg_read(tp, OCP_EEE_ABLE);
6015 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6017 val = ocp_reg_read(tp, OCP_EEE_ADV);
6018 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6020 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6021 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6023 eee->eee_enabled = tp->eee_en;
6024 eee->eee_active = !!(supported & adv & lp);
6025 eee->supported = supported;
6026 eee->advertised = tp->eee_adv;
6027 eee->lp_advertised = lp;
6033 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6035 struct r8152 *tp = netdev_priv(net);
6038 ret = usb_autopm_get_interface(tp->intf);
6042 mutex_lock(&tp->control);
6044 ret = tp->rtl_ops.eee_get(tp, edata);
6046 mutex_unlock(&tp->control);
6048 usb_autopm_put_interface(tp->intf);
6055 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6057 struct r8152 *tp = netdev_priv(net);
6060 ret = usb_autopm_get_interface(tp->intf);
6064 mutex_lock(&tp->control);
6066 ret = tp->rtl_ops.eee_set(tp, edata);
6068 ret = mii_nway_restart(&tp->mii);
6070 mutex_unlock(&tp->control);
6072 usb_autopm_put_interface(tp->intf);
6078 static int rtl8152_nway_reset(struct net_device *dev)
6080 struct r8152 *tp = netdev_priv(dev);
6083 ret = usb_autopm_get_interface(tp->intf);
6087 mutex_lock(&tp->control);
6089 ret = mii_nway_restart(&tp->mii);
6091 mutex_unlock(&tp->control);
6093 usb_autopm_put_interface(tp->intf);
6099 static int rtl8152_get_coalesce(struct net_device *netdev,
6100 struct ethtool_coalesce *coalesce)
6102 struct r8152 *tp = netdev_priv(netdev);
6104 switch (tp->version) {
6113 coalesce->rx_coalesce_usecs = tp->coalesce;
6118 static int rtl8152_set_coalesce(struct net_device *netdev,
6119 struct ethtool_coalesce *coalesce)
6121 struct r8152 *tp = netdev_priv(netdev);
6124 switch (tp->version) {
6133 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6136 ret = usb_autopm_get_interface(tp->intf);
6140 mutex_lock(&tp->control);
6142 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6143 tp->coalesce = coalesce->rx_coalesce_usecs;
6145 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6146 netif_stop_queue(netdev);
6147 napi_disable(&tp->napi);
6148 tp->rtl_ops.disable(tp);
6149 tp->rtl_ops.enable(tp);
6151 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6152 _rtl8152_set_rx_mode(netdev);
6153 napi_enable(&tp->napi);
6154 netif_wake_queue(netdev);
6158 mutex_unlock(&tp->control);
6160 usb_autopm_put_interface(tp->intf);
6165 static int rtl8152_get_tunable(struct net_device *netdev,
6166 const struct ethtool_tunable *tunable, void *d)
6168 struct r8152 *tp = netdev_priv(netdev);
6170 switch (tunable->id) {
6171 case ETHTOOL_RX_COPYBREAK:
6172 *(u32 *)d = tp->rx_copybreak;
6181 static int rtl8152_set_tunable(struct net_device *netdev,
6182 const struct ethtool_tunable *tunable,
6185 struct r8152 *tp = netdev_priv(netdev);
6188 switch (tunable->id) {
6189 case ETHTOOL_RX_COPYBREAK:
6191 if (val < ETH_ZLEN) {
6192 netif_err(tp, rx_err, netdev,
6193 "Invalid rx copy break value\n");
6197 if (tp->rx_copybreak != val) {
6198 napi_disable(&tp->napi);
6199 tp->rx_copybreak = val;
6200 napi_enable(&tp->napi);
6210 static void rtl8152_get_ringparam(struct net_device *netdev,
6211 struct ethtool_ringparam *ring)
6213 struct r8152 *tp = netdev_priv(netdev);
6215 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6216 ring->rx_pending = tp->rx_pending;
6219 static int rtl8152_set_ringparam(struct net_device *netdev,
6220 struct ethtool_ringparam *ring)
6222 struct r8152 *tp = netdev_priv(netdev);
6224 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6227 if (tp->rx_pending != ring->rx_pending) {
6228 napi_disable(&tp->napi);
6229 tp->rx_pending = ring->rx_pending;
6230 napi_enable(&tp->napi);
6236 static const struct ethtool_ops ops = {
6237 .get_drvinfo = rtl8152_get_drvinfo,
6238 .get_link = ethtool_op_get_link,
6239 .nway_reset = rtl8152_nway_reset,
6240 .get_msglevel = rtl8152_get_msglevel,
6241 .set_msglevel = rtl8152_set_msglevel,
6242 .get_wol = rtl8152_get_wol,
6243 .set_wol = rtl8152_set_wol,
6244 .get_strings = rtl8152_get_strings,
6245 .get_sset_count = rtl8152_get_sset_count,
6246 .get_ethtool_stats = rtl8152_get_ethtool_stats,
6247 .get_coalesce = rtl8152_get_coalesce,
6248 .set_coalesce = rtl8152_set_coalesce,
6249 .get_eee = rtl_ethtool_get_eee,
6250 .set_eee = rtl_ethtool_set_eee,
6251 .get_link_ksettings = rtl8152_get_link_ksettings,
6252 .set_link_ksettings = rtl8152_set_link_ksettings,
6253 .get_tunable = rtl8152_get_tunable,
6254 .set_tunable = rtl8152_set_tunable,
6255 .get_ringparam = rtl8152_get_ringparam,
6256 .set_ringparam = rtl8152_set_ringparam,
6259 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6261 struct r8152 *tp = netdev_priv(netdev);
6262 struct mii_ioctl_data *data = if_mii(rq);
6265 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6268 res = usb_autopm_get_interface(tp->intf);
6274 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6278 mutex_lock(&tp->control);
6279 data->val_out = r8152_mdio_read(tp, data->reg_num);
6280 mutex_unlock(&tp->control);
6284 if (!capable(CAP_NET_ADMIN)) {
6288 mutex_lock(&tp->control);
6289 r8152_mdio_write(tp, data->reg_num, data->val_in);
6290 mutex_unlock(&tp->control);
6297 usb_autopm_put_interface(tp->intf);
6303 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6305 struct r8152 *tp = netdev_priv(dev);
6308 switch (tp->version) {
6318 ret = usb_autopm_get_interface(tp->intf);
6322 mutex_lock(&tp->control);
6326 if (netif_running(dev)) {
6327 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6331 if (netif_carrier_ok(dev))
6332 r8153_set_rx_early_size(tp);
6335 mutex_unlock(&tp->control);
6337 usb_autopm_put_interface(tp->intf);
6342 static const struct net_device_ops rtl8152_netdev_ops = {
6343 .ndo_open = rtl8152_open,
6344 .ndo_stop = rtl8152_close,
6345 .ndo_do_ioctl = rtl8152_ioctl,
6346 .ndo_start_xmit = rtl8152_start_xmit,
6347 .ndo_tx_timeout = rtl8152_tx_timeout,
6348 .ndo_set_features = rtl8152_set_features,
6349 .ndo_set_rx_mode = rtl8152_set_rx_mode,
6350 .ndo_set_mac_address = rtl8152_set_mac_address,
6351 .ndo_change_mtu = rtl8152_change_mtu,
6352 .ndo_validate_addr = eth_validate_addr,
6353 .ndo_features_check = rtl8152_features_check,
6356 static void rtl8152_unload(struct r8152 *tp)
6358 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6361 if (tp->version != RTL_VER_01)
6362 r8152_power_cut_en(tp, true);
6365 static void rtl8153_unload(struct r8152 *tp)
6367 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6370 r8153_power_cut_en(tp, false);
6373 static void rtl8153b_unload(struct r8152 *tp)
6375 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6378 r8153b_power_cut_en(tp, false);
6381 static int rtl_ops_init(struct r8152 *tp)
6383 struct rtl_ops *ops = &tp->rtl_ops;
6386 switch (tp->version) {
6390 ops->init = r8152b_init;
6391 ops->enable = rtl8152_enable;
6392 ops->disable = rtl8152_disable;
6393 ops->up = rtl8152_up;
6394 ops->down = rtl8152_down;
6395 ops->unload = rtl8152_unload;
6396 ops->eee_get = r8152_get_eee;
6397 ops->eee_set = r8152_set_eee;
6398 ops->in_nway = rtl8152_in_nway;
6399 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
6400 ops->autosuspend_en = rtl_runtime_suspend_enable;
6401 tp->rx_buf_sz = 16 * 1024;
6403 tp->eee_adv = MDIO_EEE_100TX;
6410 ops->init = r8153_init;
6411 ops->enable = rtl8153_enable;
6412 ops->disable = rtl8153_disable;
6413 ops->up = rtl8153_up;
6414 ops->down = rtl8153_down;
6415 ops->unload = rtl8153_unload;
6416 ops->eee_get = r8153_get_eee;
6417 ops->eee_set = r8152_set_eee;
6418 ops->in_nway = rtl8153_in_nway;
6419 ops->hw_phy_cfg = r8153_hw_phy_cfg;
6420 ops->autosuspend_en = rtl8153_runtime_enable;
6421 tp->rx_buf_sz = 32 * 1024;
6423 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6428 ops->init = r8153b_init;
6429 ops->enable = rtl8153_enable;
6430 ops->disable = rtl8153_disable;
6431 ops->up = rtl8153b_up;
6432 ops->down = rtl8153b_down;
6433 ops->unload = rtl8153b_unload;
6434 ops->eee_get = r8153_get_eee;
6435 ops->eee_set = r8152_set_eee;
6436 ops->in_nway = rtl8153_in_nway;
6437 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
6438 ops->autosuspend_en = rtl8153b_runtime_enable;
6439 tp->rx_buf_sz = 32 * 1024;
6441 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6446 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6453 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
6454 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
6455 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
6456 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
6458 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6459 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6460 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6461 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6463 static int rtl_fw_init(struct r8152 *tp)
6465 struct rtl_fw *rtl_fw = &tp->rtl_fw;
6467 switch (tp->version) {
6469 rtl_fw->fw_name = FIRMWARE_8153A_2;
6470 rtl_fw->pre_fw = r8153_pre_firmware_1;
6471 rtl_fw->post_fw = r8153_post_firmware_1;
6474 rtl_fw->fw_name = FIRMWARE_8153A_3;
6475 rtl_fw->pre_fw = r8153_pre_firmware_2;
6476 rtl_fw->post_fw = r8153_post_firmware_2;
6479 rtl_fw->fw_name = FIRMWARE_8153A_4;
6480 rtl_fw->post_fw = r8153_post_firmware_3;
6483 rtl_fw->fw_name = FIRMWARE_8153B_2;
6484 rtl_fw->pre_fw = r8153b_pre_firmware_1;
6485 rtl_fw->post_fw = r8153b_post_firmware_1;
6494 static u8 rtl_get_version(struct usb_interface *intf)
6496 struct usb_device *udev = interface_to_usbdev(intf);
6502 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6506 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6507 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6508 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6510 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6516 version = RTL_VER_01;
6519 version = RTL_VER_02;
6522 version = RTL_VER_03;
6525 version = RTL_VER_04;
6528 version = RTL_VER_05;
6531 version = RTL_VER_06;
6534 version = RTL_VER_07;
6537 version = RTL_VER_08;
6540 version = RTL_VER_09;
6543 version = RTL_VER_UNKNOWN;
6544 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6548 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6553 static int rtl8152_probe(struct usb_interface *intf,
6554 const struct usb_device_id *id)
6556 struct usb_device *udev = interface_to_usbdev(intf);
6557 u8 version = rtl_get_version(intf);
6559 struct net_device *netdev;
6562 if (version == RTL_VER_UNKNOWN)
6565 if (udev->actconfig->desc.bConfigurationValue != 1) {
6566 usb_driver_set_configuration(udev, 1);
6570 usb_reset_device(udev);
6571 netdev = alloc_etherdev(sizeof(struct r8152));
6573 dev_err(&intf->dev, "Out of memory\n");
6577 SET_NETDEV_DEV(netdev, &intf->dev);
6578 tp = netdev_priv(netdev);
6579 tp->msg_enable = 0x7FFF;
6582 tp->netdev = netdev;
6584 tp->version = version;
6590 tp->mii.supports_gmii = 0;
6593 tp->mii.supports_gmii = 1;
6597 ret = rtl_ops_init(tp);
6603 mutex_init(&tp->control);
6604 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6605 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6606 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6607 tasklet_disable(&tp->tx_tl);
6609 netdev->netdev_ops = &rtl8152_netdev_ops;
6610 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6612 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6613 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6614 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6615 NETIF_F_HW_VLAN_CTAG_TX;
6616 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6617 NETIF_F_TSO | NETIF_F_FRAGLIST |
6618 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6619 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6620 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6621 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6622 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6624 if (tp->version == RTL_VER_01) {
6625 netdev->features &= ~NETIF_F_RXCSUM;
6626 netdev->hw_features &= ~NETIF_F_RXCSUM;
6629 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6630 (!strcmp(udev->serial, "000001000000") ||
6631 !strcmp(udev->serial, "000002000000"))) {
6632 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6633 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6636 netdev->ethtool_ops = &ops;
6637 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6639 /* MTU range: 68 - 1500 or 9194 */
6640 netdev->min_mtu = ETH_MIN_MTU;
6641 switch (tp->version) {
6644 netdev->max_mtu = ETH_DATA_LEN;
6647 netdev->max_mtu = RTL8153_MAX_MTU;
6651 tp->mii.dev = netdev;
6652 tp->mii.mdio_read = read_mii_word;
6653 tp->mii.mdio_write = write_mii_word;
6654 tp->mii.phy_id_mask = 0x3f;
6655 tp->mii.reg_num_mask = 0x1f;
6656 tp->mii.phy_id = R8152_PHY_ID;
6658 tp->autoneg = AUTONEG_ENABLE;
6659 tp->speed = SPEED_100;
6660 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6661 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6662 if (tp->mii.supports_gmii) {
6663 tp->speed = SPEED_1000;
6664 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6666 tp->duplex = DUPLEX_FULL;
6668 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6669 tp->rx_pending = 10 * RTL8152_MAX_RX;
6671 intf->needs_remote_wakeup = 1;
6673 tp->rtl_ops.init(tp);
6674 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6675 /* Retry in case request_firmware() is not ready yet. */
6676 tp->rtl_fw.retry = true;
6678 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6679 set_ethernet_addr(tp);
6681 usb_set_intfdata(intf, tp);
6682 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6684 ret = register_netdev(netdev);
6686 netif_err(tp, probe, netdev, "couldn't register the device\n");
6690 if (!rtl_can_wakeup(tp))
6691 __rtl_set_wol(tp, 0);
6693 tp->saved_wolopts = __rtl_get_wol(tp);
6694 if (tp->saved_wolopts)
6695 device_set_wakeup_enable(&udev->dev, true);
6697 device_set_wakeup_enable(&udev->dev, false);
6699 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6704 tasklet_kill(&tp->tx_tl);
6705 usb_set_intfdata(intf, NULL);
6707 free_netdev(netdev);
6711 static void rtl8152_disconnect(struct usb_interface *intf)
6713 struct r8152 *tp = usb_get_intfdata(intf);
6715 usb_set_intfdata(intf, NULL);
6719 unregister_netdev(tp->netdev);
6720 tasklet_kill(&tp->tx_tl);
6721 cancel_delayed_work_sync(&tp->hw_phy_work);
6722 tp->rtl_ops.unload(tp);
6723 rtl8152_release_firmware(tp);
6724 free_netdev(tp->netdev);
6728 #define REALTEK_USB_DEVICE(vend, prod) \
6729 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6730 USB_DEVICE_ID_MATCH_INT_CLASS, \
6731 .idVendor = (vend), \
6732 .idProduct = (prod), \
6733 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6736 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6737 USB_DEVICE_ID_MATCH_DEVICE, \
6738 .idVendor = (vend), \
6739 .idProduct = (prod), \
6740 .bInterfaceClass = USB_CLASS_COMM, \
6741 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6742 .bInterfaceProtocol = USB_CDC_PROTO_NONE
6744 /* table of devices that work with this driver */
6745 static const struct usb_device_id rtl8152_table[] = {
6746 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6747 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6748 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6749 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6750 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6751 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6752 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
6753 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
6754 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
6755 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6756 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6757 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
6758 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6759 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
6760 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
6764 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6766 static struct usb_driver rtl8152_driver = {
6768 .id_table = rtl8152_table,
6769 .probe = rtl8152_probe,
6770 .disconnect = rtl8152_disconnect,
6771 .suspend = rtl8152_suspend,
6772 .resume = rtl8152_resume,
6773 .reset_resume = rtl8152_reset_resume,
6774 .pre_reset = rtl8152_pre_reset,
6775 .post_reset = rtl8152_post_reset,
6776 .supports_autosuspend = 1,
6777 .disable_hub_initiated_lpm = 1,
6780 module_usb_driver(rtl8152_driver);
6782 MODULE_AUTHOR(DRIVER_AUTHOR);
6783 MODULE_DESCRIPTION(DRIVER_DESC);
6784 MODULE_LICENSE("GPL");
6785 MODULE_VERSION(DRIVER_VERSION);