1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "12"
34 /* Information for net */
35 #define NET_VERSION "11"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RCR1 0xc012
47 #define PLA_RMS 0xc016
48 #define PLA_RXFIFO_CTRL0 0xc0a0
49 #define PLA_RXFIFO_FULL 0xc0a2
50 #define PLA_RXFIFO_CTRL1 0xc0a4
51 #define PLA_RX_FIFO_FULL 0xc0a6
52 #define PLA_RXFIFO_CTRL2 0xc0a8
53 #define PLA_RX_FIFO_EMPTY 0xc0aa
54 #define PLA_DMY_REG0 0xc0b0
55 #define PLA_FMC 0xc0b4
56 #define PLA_CFG_WOL 0xc0b6
57 #define PLA_TEREDO_CFG 0xc0bc
58 #define PLA_TEREDO_WAKE_BASE 0xc0c4
59 #define PLA_MAR 0xcd00
60 #define PLA_BACKUP 0xd000
61 #define PLA_BDC_CR 0xd1a0
62 #define PLA_TEREDO_TIMER 0xd2cc
63 #define PLA_REALWOW_TIMER 0xd2e8
64 #define PLA_UPHY_TIMER 0xd388
65 #define PLA_SUSPEND_FLAG 0xd38a
66 #define PLA_INDICATE_FALG 0xd38c
67 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69 #define PLA_EXTRA_STATUS 0xd398
70 #define PLA_GPHY_CTRL 0xd3ae
71 #define PLA_POL_GPIO_CTRL 0xdc6a
72 #define PLA_EFUSE_DATA 0xdd00
73 #define PLA_EFUSE_CMD 0xdd02
74 #define PLA_LEDSEL 0xdd90
75 #define PLA_LED_FEATURE 0xdd92
76 #define PLA_PHYAR 0xde00
77 #define PLA_BOOT_CTRL 0xe004
78 #define PLA_LWAKE_CTRL_REG 0xe007
79 #define PLA_GPHY_INTR_IMR 0xe022
80 #define PLA_EEE_CR 0xe040
81 #define PLA_EEE_TXTWSYS 0xe04c
82 #define PLA_EEE_TXTWSYS_2P5G 0xe058
83 #define PLA_EEEP_CR 0xe080
84 #define PLA_MAC_PWR_CTRL 0xe0c0
85 #define PLA_MAC_PWR_CTRL2 0xe0ca
86 #define PLA_MAC_PWR_CTRL3 0xe0cc
87 #define PLA_MAC_PWR_CTRL4 0xe0ce
88 #define PLA_WDT6_CTRL 0xe428
89 #define PLA_TCR0 0xe610
90 #define PLA_TCR1 0xe612
91 #define PLA_MTPS 0xe615
92 #define PLA_TXFIFO_CTRL 0xe618
93 #define PLA_TXFIFO_FULL 0xe61a
94 #define PLA_RSTTALLY 0xe800
96 #define PLA_CRWECR 0xe81c
97 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99 #define PLA_CONFIG5 0xe822
100 #define PLA_PHY_PWR 0xe84c
101 #define PLA_OOB_CTRL 0xe84f
102 #define PLA_CPCR 0xe854
103 #define PLA_MISC_0 0xe858
104 #define PLA_MISC_1 0xe85a
105 #define PLA_OCP_GPHY_BASE 0xe86c
106 #define PLA_TALLYCNT 0xe890
107 #define PLA_SFF_STS_7 0xe8de
108 #define PLA_PHYSTATUS 0xe908
109 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
110 #define PLA_USB_CFG 0xe952
111 #define PLA_BP_BA 0xfc26
112 #define PLA_BP_0 0xfc28
113 #define PLA_BP_1 0xfc2a
114 #define PLA_BP_2 0xfc2c
115 #define PLA_BP_3 0xfc2e
116 #define PLA_BP_4 0xfc30
117 #define PLA_BP_5 0xfc32
118 #define PLA_BP_6 0xfc34
119 #define PLA_BP_7 0xfc36
120 #define PLA_BP_EN 0xfc38
122 #define USB_USB2PHY 0xb41e
123 #define USB_SSPHYLINK1 0xb426
124 #define USB_SSPHYLINK2 0xb428
125 #define USB_L1_CTRL 0xb45e
126 #define USB_U2P3_CTRL 0xb460
127 #define USB_CSR_DUMMY1 0xb464
128 #define USB_CSR_DUMMY2 0xb466
129 #define USB_DEV_STAT 0xb808
130 #define USB_CONNECT_TIMER 0xcbf8
131 #define USB_MSC_TIMER 0xcbfc
132 #define USB_BURST_SIZE 0xcfc0
133 #define USB_FW_FIX_EN0 0xcfca
134 #define USB_FW_FIX_EN1 0xcfcc
135 #define USB_LPM_CONFIG 0xcfd8
136 #define USB_ECM_OPTION 0xcfee
137 #define USB_CSTMR 0xcfef /* RTL8153A */
138 #define USB_MISC_2 0xcfff
139 #define USB_ECM_OP 0xd26b
140 #define USB_GPHY_CTRL 0xd284
141 #define USB_SPEED_OPTION 0xd32a
142 #define USB_FW_CTRL 0xd334 /* RTL8153B */
143 #define USB_FC_TIMER 0xd340
144 #define USB_USB_CTRL 0xd406
145 #define USB_PHY_CTRL 0xd408
146 #define USB_TX_AGG 0xd40a
147 #define USB_RX_BUF_TH 0xd40c
148 #define USB_USB_TIMER 0xd428
149 #define USB_RX_EARLY_TIMEOUT 0xd42c
150 #define USB_RX_EARLY_SIZE 0xd42e
151 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153 #define USB_TX_DMA 0xd434
154 #define USB_UPT_RXDMA_OWN 0xd437
155 #define USB_UPHY3_MDCMDIO 0xd480
156 #define USB_TOLERANCE 0xd490
157 #define USB_LPM_CTRL 0xd41a
158 #define USB_BMU_RESET 0xd4b0
159 #define USB_BMU_CONFIG 0xd4b4
160 #define USB_U1U2_TIMER 0xd4da
161 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
162 #define USB_RX_AGGR_NUM 0xd4ee
163 #define USB_UPS_CTRL 0xd800
164 #define USB_POWER_CUT 0xd80a
165 #define USB_MISC_0 0xd81a
166 #define USB_MISC_1 0xd81f
167 #define USB_AFE_CTRL2 0xd824
168 #define USB_UPHY_XTAL 0xd826
169 #define USB_UPS_CFG 0xd842
170 #define USB_UPS_FLAGS 0xd848
171 #define USB_WDT1_CTRL 0xe404
172 #define USB_WDT11_CTRL 0xe43c
173 #define USB_BP_BA PLA_BP_BA
174 #define USB_BP_0 PLA_BP_0
175 #define USB_BP_1 PLA_BP_1
176 #define USB_BP_2 PLA_BP_2
177 #define USB_BP_3 PLA_BP_3
178 #define USB_BP_4 PLA_BP_4
179 #define USB_BP_5 PLA_BP_5
180 #define USB_BP_6 PLA_BP_6
181 #define USB_BP_7 PLA_BP_7
182 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
183 #define USB_BP_8 0xfc38 /* RTL8153B */
184 #define USB_BP_9 0xfc3a
185 #define USB_BP_10 0xfc3c
186 #define USB_BP_11 0xfc3e
187 #define USB_BP_12 0xfc40
188 #define USB_BP_13 0xfc42
189 #define USB_BP_14 0xfc44
190 #define USB_BP_15 0xfc46
191 #define USB_BP2_EN 0xfc48
194 #define OCP_ALDPS_CONFIG 0x2010
195 #define OCP_EEE_CONFIG1 0x2080
196 #define OCP_EEE_CONFIG2 0x2092
197 #define OCP_EEE_CONFIG3 0x2094
198 #define OCP_BASE_MII 0xa400
199 #define OCP_EEE_AR 0xa41a
200 #define OCP_EEE_DATA 0xa41c
201 #define OCP_PHY_STATUS 0xa420
202 #define OCP_NCTL_CFG 0xa42c
203 #define OCP_POWER_CFG 0xa430
204 #define OCP_EEE_CFG 0xa432
205 #define OCP_SRAM_ADDR 0xa436
206 #define OCP_SRAM_DATA 0xa438
207 #define OCP_DOWN_SPEED 0xa442
208 #define OCP_EEE_ABLE 0xa5c4
209 #define OCP_EEE_ADV 0xa5d0
210 #define OCP_EEE_LPABLE 0xa5d2
211 #define OCP_10GBT_CTRL 0xa5d4
212 #define OCP_10GBT_STAT 0xa5d6
213 #define OCP_EEE_ADV2 0xa6d4
214 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215 #define OCP_PHY_PATCH_STAT 0xb800
216 #define OCP_PHY_PATCH_CMD 0xb820
217 #define OCP_PHY_LOCK 0xb82e
218 #define OCP_ADC_IOFFSET 0xbcfc
219 #define OCP_ADC_CFG 0xbc06
220 #define OCP_SYSCLK_CFG 0xc416
223 #define SRAM_GREEN_CFG 0x8011
224 #define SRAM_LPF_CFG 0x8012
225 #define SRAM_GPHY_FW_VER 0x801e
226 #define SRAM_10M_AMP1 0x8080
227 #define SRAM_10M_AMP2 0x8082
228 #define SRAM_IMPEDANCE 0x8084
229 #define SRAM_PHY_LOCK 0xb82e
232 #define RCR_AAP 0x00000001
233 #define RCR_APM 0x00000002
234 #define RCR_AM 0x00000004
235 #define RCR_AB 0x00000008
236 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237 #define SLOT_EN BIT(11)
240 #define OUTER_VLAN BIT(7)
241 #define INNER_VLAN BIT(6)
243 /* PLA_RXFIFO_CTRL0 */
244 #define RXFIFO_THR1_NORMAL 0x00080002
245 #define RXFIFO_THR1_OOB 0x01800003
247 /* PLA_RXFIFO_FULL */
248 #define RXFIFO_FULL_MASK 0xfff
250 /* PLA_RXFIFO_CTRL1 */
251 #define RXFIFO_THR2_FULL 0x00000060
252 #define RXFIFO_THR2_HIGH 0x00000038
253 #define RXFIFO_THR2_OOB 0x0000004a
254 #define RXFIFO_THR2_NORMAL 0x00a0
256 /* PLA_RXFIFO_CTRL2 */
257 #define RXFIFO_THR3_FULL 0x00000078
258 #define RXFIFO_THR3_HIGH 0x00000048
259 #define RXFIFO_THR3_OOB 0x0000005a
260 #define RXFIFO_THR3_NORMAL 0x0110
262 /* PLA_TXFIFO_CTRL */
263 #define TXFIFO_THR_NORMAL 0x00400008
264 #define TXFIFO_THR_NORMAL2 0x01000008
267 #define ECM_ALDPS 0x0002
270 #define FMC_FCR_MCU_EN 0x0001
273 #define EEEP_CR_EEEP_TX 0x0002
276 #define WDT6_SET_MODE 0x0010
279 #define TCR0_TX_EMPTY 0x0800
280 #define TCR0_AUTO_FIFO 0x0080
283 #define VERSION_MASK 0x7cf0
284 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
285 #define IFG_144NS BIT(9)
286 #define IFG_96NS (BIT(9) | BIT(8))
289 #define MTPS_JUMBO (12 * 1024 / 64)
290 #define MTPS_DEFAULT (6 * 1024 / 64)
293 #define TALLY_RESET 0x0001
301 #define CRWECR_NORAML 0x00
302 #define CRWECR_CONFIG 0xc0
305 #define NOW_IS_OOB 0x80
306 #define TXFIFO_EMPTY 0x20
307 #define RXFIFO_EMPTY 0x10
308 #define LINK_LIST_READY 0x02
309 #define DIS_MCU_CLROOB 0x01
310 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
313 #define RXDY_GATED_EN 0x0008
316 #define RE_INIT_LL 0x8000
317 #define MCU_BORW_EN 0x4000
320 #define FLOW_CTRL_EN BIT(0)
321 #define CPCR_RX_VLAN 0x0040
324 #define MAGIC_EN 0x0001
327 #define TEREDO_SEL 0x8000
328 #define TEREDO_WAKE_MASK 0x7f00
329 #define TEREDO_RS_EVENT_MASK 0x00fe
330 #define OOB_TEREDO_EN 0x0001
333 #define ALDPS_PROXY_MODE 0x0001
336 #define EFUSE_READ_CMD BIT(15)
337 #define EFUSE_DATA_BIT16 BIT(7)
340 #define LINK_ON_WAKE_EN 0x0010
341 #define LINK_OFF_WAKE_EN 0x0008
344 #define LANWAKE_CLR_EN BIT(0)
347 #define EN_XG_LIP BIT(1)
348 #define EN_G_LIP BIT(2)
351 #define BWF_EN 0x0040
352 #define MWF_EN 0x0020
353 #define UWF_EN 0x0010
354 #define LAN_WAKE_EN 0x0002
356 /* PLA_LED_FEATURE */
357 #define LED_MODE_MASK 0x0700
360 #define TX_10M_IDLE_EN 0x0080
361 #define PFM_PWM_SWITCH 0x0040
362 #define TEST_IO_OFF BIT(4)
364 /* PLA_MAC_PWR_CTRL */
365 #define D3_CLK_GATED_EN 0x00004000
366 #define MCU_CLK_RATIO 0x07010f07
367 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368 #define ALDPS_SPDWN_RATIO 0x0f87
370 /* PLA_MAC_PWR_CTRL2 */
371 #define EEE_SPDWN_RATIO 0x8007
372 #define MAC_CLK_SPDWN_EN BIT(15)
373 #define EEE_SPDWN_RATIO_MASK 0xff
375 /* PLA_MAC_PWR_CTRL3 */
376 #define PLA_MCU_SPDWN_EN BIT(14)
377 #define PKT_AVAIL_SPDWN_EN 0x0100
378 #define SUSPEND_SPDWN_EN 0x0004
379 #define U1U2_SPDWN_EN 0x0002
380 #define L1_SPDWN_EN 0x0001
382 /* PLA_MAC_PWR_CTRL4 */
383 #define PWRSAVE_SPDWN_EN 0x1000
384 #define RXDV_SPDWN_EN 0x0800
385 #define TX10MIDLE_EN 0x0100
386 #define IDLE_SPDWN_EN BIT(6)
387 #define TP100_SPDWN_EN 0x0020
388 #define TP500_SPDWN_EN 0x0010
389 #define TP1000_SPDWN_EN 0x0008
390 #define EEE_SPDWN_EN 0x0001
392 /* PLA_GPHY_INTR_IMR */
393 #define GPHY_STS_MSK 0x0001
394 #define SPEED_DOWN_MSK 0x0002
395 #define SPDWN_RXDV_MSK 0x0004
396 #define SPDWN_LINKCHG_MSK 0x0008
399 #define PHYAR_FLAG 0x80000000
402 #define EEE_RX_EN 0x0001
403 #define EEE_TX_EN 0x0002
406 #define AUTOLOAD_DONE 0x0002
408 /* PLA_LWAKE_CTRL_REG */
409 #define LANWAKE_PIN BIT(7)
411 /* PLA_SUSPEND_FLAG */
412 #define LINK_CHG_EVENT BIT(0)
414 /* PLA_INDICATE_FALG */
415 #define UPCOMING_RUNTIME_D3 BIT(0)
417 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418 #define DEBUG_OE BIT(0)
419 #define DEBUG_LTSSM 0x0082
421 /* PLA_EXTRA_STATUS */
422 #define CUR_LINK_OK BIT(15)
423 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
424 #define LINK_CHANGE_FLAG BIT(8)
425 #define POLL_LINK_CHG BIT(0)
428 #define GPHY_FLASH BIT(1)
430 /* PLA_POL_GPIO_CTRL */
431 #define DACK_DET_EN BIT(15)
432 #define POL_GPHY_PATCH BIT(4)
435 #define USB2PHY_SUSPEND 0x0001
436 #define USB2PHY_L1 0x0002
439 #define DELAY_PHY_PWR_CHG BIT(1)
442 #define pwd_dn_scale_mask 0x3ffe
443 #define pwd_dn_scale(x) ((x) << 1)
446 #define DYNAMIC_BURST 0x0001
449 #define EP4_FULL_FC 0x0001
452 #define STAT_SPEED_MASK 0x0006
453 #define STAT_SPEED_HIGH 0x0000
454 #define STAT_SPEED_FULL 0x0002
457 #define FW_FIX_SUSPEND BIT(14)
460 #define FW_IP_RESET_EN BIT(9)
463 #define LPM_U1U2_EN BIT(0)
466 #define TX_AGG_MAX_THRESHOLD 0x03
469 #define RX_THR_SUPPER 0x0c350180
470 #define RX_THR_HIGH 0x7a120180
471 #define RX_THR_SLOW 0xffff0180
472 #define RX_THR_B 0x00010001
475 #define TEST_MODE_DISABLE 0x00000001
476 #define TX_SIZE_ADJUST1 0x00000100
479 #define BMU_RESET_EP_IN 0x01
480 #define BMU_RESET_EP_OUT 0x02
483 #define ACT_ODMA BIT(1)
485 /* USB_UPT_RXDMA_OWN */
486 #define OWN_UPDATE BIT(0)
487 #define OWN_CLEAR BIT(1)
490 #define FC_PATCH_TASK BIT(1)
492 /* USB_RX_AGGR_NUM */
493 #define RX_AGGR_NUM_MASK 0x1ff
496 #define POWER_CUT 0x0100
498 /* USB_PM_CTRL_STATUS */
499 #define RESUME_INDICATE 0x0001
502 #define BYPASS_MAC_RESET BIT(5)
505 #define FORCE_SUPER BIT(0)
508 #define UPS_FORCE_PWR_DOWN BIT(0)
511 #define EN_ALL_SPEED BIT(0)
514 #define GPHY_PATCH_DONE BIT(2)
515 #define BYPASS_FLASH BIT(5)
516 #define BACKUP_RESTRORE BIT(6)
518 /* USB_SPEED_OPTION */
519 #define RG_PWRDN_EN BIT(8)
520 #define ALL_SPEED_OFF BIT(9)
523 #define FLOW_CTRL_PATCH_OPT BIT(1)
524 #define AUTO_SPEEDUP BIT(3)
525 #define FLOW_CTRL_PATCH_2 BIT(8)
528 #define CTRL_TIMER_EN BIT(15)
531 #define CDC_ECM_EN BIT(3)
532 #define RX_AGG_DISABLE 0x0010
533 #define RX_ZERO_EN 0x0080
536 #define U2P3_ENABLE 0x0001
537 #define RX_DETECT8 BIT(3)
540 #define PWR_EN 0x0001
541 #define PHASE2_EN 0x0008
542 #define UPS_EN BIT(4)
543 #define USP_PREWAKE BIT(5)
546 #define PCUT_STATUS 0x0001
548 /* USB_RX_EARLY_TIMEOUT */
549 #define COALESCE_SUPER 85000U
550 #define COALESCE_HIGH 250000U
551 #define COALESCE_SLOW 524280U
554 #define WTD1_EN BIT(0)
557 #define TIMER11_EN 0x0001
560 /* bit 4 ~ 5: fifo empty boundary */
561 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
562 /* bit 2 ~ 3: LMP timer */
563 #define LPM_TIMER_MASK 0x0c
564 #define LPM_TIMER_500MS 0x04 /* 500 ms */
565 #define LPM_TIMER_500US 0x0c /* 500 us */
566 #define ROK_EXIT_LPM 0x02
569 #define SEN_VAL_MASK 0xf800
570 #define SEN_VAL_NORMAL 0xa000
571 #define SEL_RXIDLE 0x0100
574 #define OOBS_POLLING BIT(8)
577 #define SAW_CNT_1MS_MASK 0x0fff
578 #define MID_REVERSE BIT(5) /* RTL8156A */
581 #define UPS_FLAGS_R_TUNE BIT(0)
582 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
583 #define UPS_FLAGS_250M_CKDIV BIT(2)
584 #define UPS_FLAGS_EN_ALDPS BIT(3)
585 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
586 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
587 #define ups_flags_speed(x) ((x) << 16)
588 #define UPS_FLAGS_EN_EEE BIT(20)
589 #define UPS_FLAGS_EN_500M_EEE BIT(21)
590 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
591 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
592 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
593 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
594 #define UPS_FLAGS_EN_GREEN BIT(26)
595 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
611 /* OCP_ALDPS_CONFIG */
612 #define ENPWRSAVE 0x8000
613 #define ENPDNPS 0x0200
614 #define LINKENA 0x0100
615 #define DIS_SDSAVE 0x0010
618 #define PHY_STAT_MASK 0x0007
619 #define PHY_STAT_EXT_INIT 2
620 #define PHY_STAT_LAN_ON 3
621 #define PHY_STAT_PWRDN 5
624 #define PGA_RETURN_EN BIT(1)
627 #define EEE_CLKDIV_EN 0x8000
628 #define EN_ALDPS 0x0004
629 #define EN_10M_PLLOFF 0x0001
631 /* OCP_EEE_CONFIG1 */
632 #define RG_TXLPI_MSK_HFDUP 0x8000
633 #define RG_MATCLR_EN 0x4000
634 #define EEE_10_CAP 0x2000
635 #define EEE_NWAY_EN 0x1000
636 #define TX_QUIET_EN 0x0200
637 #define RX_QUIET_EN 0x0100
638 #define sd_rise_time_mask 0x0070
639 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
640 #define RG_RXLPI_MSK_HFDUP 0x0008
641 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
643 /* OCP_EEE_CONFIG2 */
644 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645 #define RG_DACQUIET_EN 0x0400
646 #define RG_LDVQUIET_EN 0x0200
647 #define RG_CKRSEL 0x0020
648 #define RG_EEEPRG_EN 0x0010
650 /* OCP_EEE_CONFIG3 */
651 #define fast_snr_mask 0xff80
652 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
657 /* bit[15:14] function */
658 #define FUN_ADDR 0x0000
659 #define FUN_DATA 0x4000
660 /* bit[4:0] device addr */
663 #define CTAP_SHORT_EN 0x0040
664 #define EEE10_EN 0x0010
667 #define EN_EEE_CMODE BIT(14)
668 #define EN_EEE_1000 BIT(13)
669 #define EN_EEE_100 BIT(12)
670 #define EN_10M_CLKDIV BIT(11)
671 #define EN_10M_BGOFF 0x0080
674 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
677 #define TXDIS_STATE 0x01
678 #define ABD_STATE 0x02
680 /* OCP_PHY_PATCH_STAT */
681 #define PATCH_READY BIT(6)
683 /* OCP_PHY_PATCH_CMD */
684 #define PATCH_REQUEST BIT(4)
687 #define PATCH_LOCK BIT(0)
690 #define CKADSEL_L 0x0100
691 #define ADC_EN 0x0080
692 #define EN_EMI_L 0x0040
695 #define sysclk_div_expo(x) (min(x, 5) << 8)
696 #define clk_div_expo(x) (min(x, 5) << 4)
699 #define GREEN_ETH_EN BIT(15)
700 #define R_TUNE_EN BIT(11)
703 #define LPF_AUTO_TUNE 0x8000
706 #define GDAC_IB_UPALL 0x0008
709 #define AMP_DN 0x0200
712 #define RX_DRIVING_MASK 0x6000
715 #define PHY_PATCH_LOCK 0x0001
718 #define AD_MASK 0xfee0
719 #define BND_MASK 0x0004
720 #define BD_MASK 0x0001
722 #define PASS_THRU_MASK 0x1
724 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
726 enum rtl_register_content {
739 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
742 #define RTL8152_MAX_TX 4
743 #define RTL8152_MAX_RX 10
748 #define RTL8152_RX_MAX_PENDING 4096
749 #define RTL8152_RXFG_HEADSZ 256
751 #define INTR_LINK 0x0004
753 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754 #define RTL8153_RMS RTL8153_MAX_PACKET
755 #define RTL8152_TX_TIMEOUT (5 * HZ)
756 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
772 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
773 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
775 struct tally_counter {
782 __le32 tx_one_collision;
783 __le32 tx_multi_collision;
793 #define RX_LEN_MASK 0x7fff
796 #define RD_UDP_CS BIT(23)
797 #define RD_TCP_CS BIT(22)
798 #define RD_IPV6_CS BIT(20)
799 #define RD_IPV4_CS BIT(19)
802 #define IPF BIT(23) /* IP checksum fail */
803 #define UDPF BIT(22) /* UDP checksum fail */
804 #define TCPF BIT(21) /* TCP checksum fail */
805 #define RX_VLAN_TAG BIT(16)
814 #define TX_FS BIT(31) /* First segment of a packet */
815 #define TX_LS BIT(30) /* Final segment of a packet */
816 #define GTSENDV4 BIT(28)
817 #define GTSENDV6 BIT(27)
818 #define GTTCPHO_SHIFT 18
819 #define GTTCPHO_MAX 0x7fU
820 #define TX_LEN_MAX 0x3ffffU
823 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
824 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
825 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
826 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
828 #define MSS_MAX 0x7ffU
829 #define TCPHO_SHIFT 17
830 #define TCPHO_MAX 0x7ffU
831 #define TX_VLAN_TAG BIT(16)
837 struct list_head list, info_list;
839 struct r8152 *context;
845 struct list_head list;
847 struct r8152 *context;
856 struct usb_device *udev;
857 struct napi_struct napi;
858 struct usb_interface *intf;
859 struct net_device *netdev;
860 struct urb *intr_urb;
861 struct tx_agg tx_info[RTL8152_MAX_TX];
862 struct list_head rx_info, rx_used;
863 struct list_head rx_done, tx_free;
864 struct sk_buff_head tx_queue, rx_queue;
865 spinlock_t rx_lock, tx_lock;
866 struct delayed_work schedule, hw_phy_work;
867 struct mii_if_info mii;
868 struct mutex control; /* use for hw setting */
869 #ifdef CONFIG_PM_SLEEP
870 struct notifier_block pm_notifier;
872 struct tasklet_struct tx_tl;
875 void (*init)(struct r8152 *tp);
876 int (*enable)(struct r8152 *tp);
877 void (*disable)(struct r8152 *tp);
878 void (*up)(struct r8152 *tp);
879 void (*down)(struct r8152 *tp);
880 void (*unload)(struct r8152 *tp);
881 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
882 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
883 bool (*in_nway)(struct r8152 *tp);
884 void (*hw_phy_cfg)(struct r8152 *tp);
885 void (*autosuspend_en)(struct r8152 *tp, bool enable);
886 void (*change_mtu)(struct r8152 *tp);
899 u32 eee_plloff_100:1;
900 u32 eee_plloff_giga:1;
904 u32 ctap_short_off:1;
907 #define RTL_VER_SIZE 32
911 const struct firmware *fw;
913 char version[RTL_VER_SIZE];
914 int (*pre_fw)(struct r8152 *tp);
915 int (*post_fw)(struct r8152 *tp);
932 u32 fc_pause_on, fc_pause_off;
934 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
936 u32 support_2500full:1;
937 u32 lenovo_macpassthru:1;
938 u32 dell_tb_rx_agg_bug:1;
949 * struct fw_block - block type and total length
950 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
951 * RTL_FW_USB and so on.
952 * @length: total length of the current block.
960 * struct fw_header - header of the firmware file
961 * @checksum: checksum of sha256 which is calculated from the whole file
962 * except the checksum field of the file. That is, calculate sha256
963 * from the version field to the end of the file.
964 * @version: version of this firmware.
965 * @blocks: the first firmware block of the file
969 char version[RTL_VER_SIZE];
970 struct fw_block blocks[];
973 enum rtl8152_fw_flags {
987 enum rtl8152_fw_fixup_cmd {
999 struct fw_phy_speed_up {
1000 struct fw_block blk_hdr;
1009 struct fw_block blk_hdr;
1010 struct fw_phy_set ver;
1014 struct fw_phy_fixup {
1015 struct fw_block blk_hdr;
1016 struct fw_phy_set setting;
1021 struct fw_phy_union {
1022 struct fw_block blk_hdr;
1025 struct fw_phy_set pre_set[2];
1026 struct fw_phy_set bp[8];
1027 struct fw_phy_set bp_en;
1034 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1035 * The layout of the firmware block is:
1036 * <struct fw_mac> + <info> + <firmware data>.
1037 * @blk_hdr: firmware descriptor (type, length)
1038 * @fw_offset: offset of the firmware binary data. The start address of
1039 * the data would be the address of struct fw_mac + @fw_offset.
1040 * @fw_reg: the register to load the firmware. Depends on chip.
1041 * @bp_ba_addr: the register to write break point base address. Depends on
1043 * @bp_ba_value: break point base address. Depends on chip.
1044 * @bp_en_addr: the register to write break point enabled mask. Depends
1046 * @bp_en_value: break point enabled mask. Depends on the firmware.
1047 * @bp_start: the start register of break points. Depends on chip.
1048 * @bp_num: the break point number which needs to be set for this firmware.
1049 * Depends on the firmware.
1050 * @bp: break points. Depends on firmware.
1051 * @reserved: reserved space (unused)
1052 * @fw_ver_reg: the register to store the fw version.
1053 * @fw_ver_data: the firmware version of the current type.
1054 * @info: additional information for debugging, and is followed by the
1055 * binary data of firmware.
1058 struct fw_block blk_hdr;
1067 __le16 bp[16]; /* any value determined by firmware */
1075 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1076 * This is used to set patch key when loading the firmware of PHY.
1077 * @blk_hdr: firmware descriptor (type, length)
1078 * @key_reg: the register to write the patch key.
1079 * @key_data: patch key.
1080 * @reserved: reserved space (unused)
1082 struct fw_phy_patch_key {
1083 struct fw_block blk_hdr;
1090 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1091 * The layout of the firmware block is:
1092 * <struct fw_phy_nc> + <info> + <firmware data>.
1093 * @blk_hdr: firmware descriptor (type, length)
1094 * @fw_offset: offset of the firmware binary data. The start address of
1095 * the data would be the address of struct fw_phy_nc + @fw_offset.
1096 * @fw_reg: the register to load the firmware. Depends on chip.
1097 * @ba_reg: the register to write the base address. Depends on chip.
1098 * @ba_data: base address. Depends on chip.
1099 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1100 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1101 * @mode_reg: the regitster of switching the mode.
1102 * @mode_pre: the mode needing to be set before loading the firmware.
1103 * @mode_post: the mode to be set when finishing to load the firmware.
1104 * @reserved: reserved space (unused)
1105 * @bp_start: the start register of break points. Depends on chip.
1106 * @bp_num: the break point number which needs to be set for this firmware.
1107 * Depends on the firmware.
1108 * @bp: break points. Depends on firmware.
1109 * @info: additional information for debugging, and is followed by the
1110 * binary data of firmware.
1113 struct fw_block blk_hdr;
1118 __le16 patch_en_addr;
1119 __le16 patch_en_value;
1138 RTL_FW_PHY_UNION_NC,
1139 RTL_FW_PHY_UNION_NC1,
1140 RTL_FW_PHY_UNION_NC2,
1141 RTL_FW_PHY_UNION_UC2,
1142 RTL_FW_PHY_UNION_UC,
1143 RTL_FW_PHY_UNION_MISC,
1144 RTL_FW_PHY_SPEED_UP,
1149 RTL_VER_UNKNOWN = 0,
1172 TX_CSUM_SUCCESS = 0,
1177 #define RTL_ADVERTISED_10_HALF BIT(0)
1178 #define RTL_ADVERTISED_10_FULL BIT(1)
1179 #define RTL_ADVERTISED_100_HALF BIT(2)
1180 #define RTL_ADVERTISED_100_FULL BIT(3)
1181 #define RTL_ADVERTISED_1000_HALF BIT(4)
1182 #define RTL_ADVERTISED_1000_FULL BIT(5)
1183 #define RTL_ADVERTISED_2500_FULL BIT(6)
1185 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1186 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1188 static const int multicast_filter_limit = 32;
1189 static unsigned int agg_buf_sz = 16384;
1191 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1194 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1199 tmp = kmalloc(size, GFP_KERNEL);
1203 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
1204 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1205 value, index, tmp, size, 500);
1207 memset(data, 0xff, size);
1209 memcpy(data, tmp, size);
1217 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1222 tmp = kmemdup(data, size, GFP_KERNEL);
1226 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
1227 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1228 value, index, tmp, size, 500);
1235 static void rtl_set_unplug(struct r8152 *tp)
1237 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1238 set_bit(RTL8152_UNPLUG, &tp->flags);
1239 smp_mb__after_atomic();
1243 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1244 void *data, u16 type)
1249 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1252 /* both size and indix must be 4 bytes align */
1253 if ((size & 3) || !size || (index & 3) || !data)
1256 if ((u32)index + (u32)size > 0xffff)
1261 ret = get_registers(tp, index, type, limit, data);
1269 ret = get_registers(tp, index, type, size, data);
1286 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1287 u16 size, void *data, u16 type)
1290 u16 byteen_start, byteen_end, byen;
1293 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1296 /* both size and indix must be 4 bytes align */
1297 if ((size & 3) || !size || (index & 3) || !data)
1300 if ((u32)index + (u32)size > 0xffff)
1303 byteen_start = byteen & BYTE_EN_START_MASK;
1304 byteen_end = byteen & BYTE_EN_END_MASK;
1306 byen = byteen_start | (byteen_start << 4);
1307 ret = set_registers(tp, index, type | byen, 4, data);
1320 ret = set_registers(tp, index,
1321 type | BYTE_EN_DWORD,
1330 ret = set_registers(tp, index,
1331 type | BYTE_EN_DWORD,
1343 byen = byteen_end | (byteen_end >> 4);
1344 ret = set_registers(tp, index, type | byen, 4, data);
1357 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1359 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1363 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1365 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1369 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1371 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1374 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1378 generic_ocp_read(tp, index, sizeof(data), &data, type);
1380 return __le32_to_cpu(data);
1383 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1385 __le32 tmp = __cpu_to_le32(data);
1387 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1390 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1394 u16 byen = BYTE_EN_WORD;
1395 u8 shift = index & 2;
1400 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1402 data = __le32_to_cpu(tmp);
1403 data >>= (shift * 8);
1409 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1413 u16 byen = BYTE_EN_WORD;
1414 u8 shift = index & 2;
1420 mask <<= (shift * 8);
1421 data <<= (shift * 8);
1425 tmp = __cpu_to_le32(data);
1427 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1430 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1434 u8 shift = index & 3;
1438 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1440 data = __le32_to_cpu(tmp);
1441 data >>= (shift * 8);
1447 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1451 u16 byen = BYTE_EN_BYTE;
1452 u8 shift = index & 3;
1458 mask <<= (shift * 8);
1459 data <<= (shift * 8);
1463 tmp = __cpu_to_le32(data);
1465 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1468 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1470 u16 ocp_base, ocp_index;
1472 ocp_base = addr & 0xf000;
1473 if (ocp_base != tp->ocp_base) {
1474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1475 tp->ocp_base = ocp_base;
1478 ocp_index = (addr & 0x0fff) | 0xb000;
1479 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1482 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1484 u16 ocp_base, ocp_index;
1486 ocp_base = addr & 0xf000;
1487 if (ocp_base != tp->ocp_base) {
1488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1489 tp->ocp_base = ocp_base;
1492 ocp_index = (addr & 0x0fff) | 0xb000;
1493 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1496 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1498 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1501 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1503 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1506 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1508 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1509 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1512 static u16 sram_read(struct r8152 *tp, u16 addr)
1514 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1515 return ocp_reg_read(tp, OCP_SRAM_DATA);
1518 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1520 struct r8152 *tp = netdev_priv(netdev);
1523 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1526 if (phy_id != R8152_PHY_ID)
1529 ret = r8152_mdio_read(tp, reg);
1535 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1537 struct r8152 *tp = netdev_priv(netdev);
1539 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1542 if (phy_id != R8152_PHY_ID)
1545 r8152_mdio_write(tp, reg, val);
1549 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1552 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1555 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1558 struct r8152 *tp = netdev_priv(netdev);
1559 struct sockaddr *addr = p;
1560 int ret = -EADDRNOTAVAIL;
1562 if (!is_valid_ether_addr(addr->sa_data))
1566 ret = usb_autopm_get_interface(tp->intf);
1571 mutex_lock(&tp->control);
1573 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1575 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1576 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1577 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1579 mutex_unlock(&tp->control);
1582 usb_autopm_put_interface(tp->intf);
1587 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1589 return __rtl8152_set_mac_address(netdev, p, false);
1592 /* Devices containing proper chips can support a persistent
1593 * host system provided MAC address.
1594 * Examples of this are Dell TB15 and Dell WD15 docks
1596 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1599 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1600 union acpi_object *obj;
1603 unsigned char buf[6];
1605 acpi_object_type mac_obj_type;
1608 if (tp->lenovo_macpassthru) {
1609 mac_obj_name = "\\MACA";
1610 mac_obj_type = ACPI_TYPE_STRING;
1613 /* test for -AD variant of RTL8153 */
1614 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1615 if ((ocp_data & AD_MASK) == 0x1000) {
1616 /* test for MAC address pass-through bit */
1617 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1618 if ((ocp_data & PASS_THRU_MASK) != 1) {
1619 netif_dbg(tp, probe, tp->netdev,
1620 "No efuse for RTL8153-AD MAC pass through\n");
1624 /* test for RTL8153-BND and RTL8153-BD */
1625 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1626 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1627 netif_dbg(tp, probe, tp->netdev,
1628 "Invalid variant for MAC pass through\n");
1633 mac_obj_name = "\\_SB.AMAC";
1634 mac_obj_type = ACPI_TYPE_BUFFER;
1638 /* returns _AUXMAC_#AABBCCDDEEFF# */
1639 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1640 obj = (union acpi_object *)buffer.pointer;
1641 if (!ACPI_SUCCESS(status))
1643 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1644 netif_warn(tp, probe, tp->netdev,
1645 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1646 obj->type, obj->string.length);
1650 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1651 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1652 netif_warn(tp, probe, tp->netdev,
1653 "Invalid header when reading pass-thru MAC addr\n");
1656 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1657 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1658 netif_warn(tp, probe, tp->netdev,
1659 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1664 memcpy(sa->sa_data, buf, 6);
1665 netif_info(tp, probe, tp->netdev,
1666 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1673 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1675 struct net_device *dev = tp->netdev;
1678 sa->sa_family = dev->type;
1680 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1682 if (tp->version == RTL_VER_01) {
1683 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1685 /* if device doesn't support MAC pass through this will
1686 * be expected to be non-zero
1688 ret = vendor_mac_passthru_addr_read(tp, sa);
1690 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1696 netif_err(tp, probe, dev, "Get ether addr fail\n");
1697 } else if (!is_valid_ether_addr(sa->sa_data)) {
1698 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1700 eth_hw_addr_random(dev);
1701 ether_addr_copy(sa->sa_data, dev->dev_addr);
1702 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1710 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1712 struct net_device *dev = tp->netdev;
1716 ret = determine_ethernet_addr(tp, &sa);
1720 if (tp->version == RTL_VER_01)
1721 ether_addr_copy(dev->dev_addr, sa.sa_data);
1723 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1728 static void read_bulk_callback(struct urb *urb)
1730 struct net_device *netdev;
1731 int status = urb->status;
1734 unsigned long flags;
1744 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1747 if (!test_bit(WORK_ENABLE, &tp->flags))
1750 netdev = tp->netdev;
1752 /* When link down, the driver would cancel all bulks. */
1753 /* This avoid the re-submitting bulk */
1754 if (!netif_carrier_ok(netdev))
1757 usb_mark_last_busy(tp->udev);
1761 if (urb->actual_length < ETH_ZLEN)
1764 spin_lock_irqsave(&tp->rx_lock, flags);
1765 list_add_tail(&agg->list, &tp->rx_done);
1766 spin_unlock_irqrestore(&tp->rx_lock, flags);
1767 napi_schedule(&tp->napi);
1771 netif_device_detach(tp->netdev);
1774 return; /* the urb is in unlink state */
1776 if (net_ratelimit())
1777 netdev_warn(netdev, "maybe reset is needed?\n");
1780 if (net_ratelimit())
1781 netdev_warn(netdev, "Rx status %d\n", status);
1785 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1788 static void write_bulk_callback(struct urb *urb)
1790 struct net_device_stats *stats;
1791 struct net_device *netdev;
1794 unsigned long flags;
1795 int status = urb->status;
1805 netdev = tp->netdev;
1806 stats = &netdev->stats;
1808 if (net_ratelimit())
1809 netdev_warn(netdev, "Tx status %d\n", status);
1810 stats->tx_errors += agg->skb_num;
1812 stats->tx_packets += agg->skb_num;
1813 stats->tx_bytes += agg->skb_len;
1816 spin_lock_irqsave(&tp->tx_lock, flags);
1817 list_add_tail(&agg->list, &tp->tx_free);
1818 spin_unlock_irqrestore(&tp->tx_lock, flags);
1820 usb_autopm_put_interface_async(tp->intf);
1822 if (!netif_carrier_ok(netdev))
1825 if (!test_bit(WORK_ENABLE, &tp->flags))
1828 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1831 if (!skb_queue_empty(&tp->tx_queue))
1832 tasklet_schedule(&tp->tx_tl);
1835 static void intr_callback(struct urb *urb)
1839 int status = urb->status;
1846 if (!test_bit(WORK_ENABLE, &tp->flags))
1849 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1853 case 0: /* success */
1855 case -ECONNRESET: /* unlink */
1857 netif_device_detach(tp->netdev);
1861 netif_info(tp, intr, tp->netdev,
1862 "Stop submitting intr, status %d\n", status);
1865 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1867 /* -EPIPE: should clear the halt */
1869 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1873 d = urb->transfer_buffer;
1874 if (INTR_LINK & __le16_to_cpu(d[0])) {
1875 if (!netif_carrier_ok(tp->netdev)) {
1876 set_bit(RTL8152_LINK_CHG, &tp->flags);
1877 schedule_delayed_work(&tp->schedule, 0);
1880 if (netif_carrier_ok(tp->netdev)) {
1881 netif_stop_queue(tp->netdev);
1882 set_bit(RTL8152_LINK_CHG, &tp->flags);
1883 schedule_delayed_work(&tp->schedule, 0);
1888 res = usb_submit_urb(urb, GFP_ATOMIC);
1889 if (res == -ENODEV) {
1891 netif_device_detach(tp->netdev);
1893 netif_err(tp, intr, tp->netdev,
1894 "can't resubmit intr, status %d\n", res);
1898 static inline void *rx_agg_align(void *data)
1900 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1903 static inline void *tx_agg_align(void *data)
1905 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1908 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1910 list_del(&agg->info_list);
1912 usb_free_urb(agg->urb);
1913 put_page(agg->page);
1916 atomic_dec(&tp->rx_count);
1919 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1921 struct net_device *netdev = tp->netdev;
1922 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1923 unsigned int order = get_order(tp->rx_buf_sz);
1924 struct rx_agg *rx_agg;
1925 unsigned long flags;
1927 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1931 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1935 rx_agg->buffer = page_address(rx_agg->page);
1937 rx_agg->urb = usb_alloc_urb(0, mflags);
1941 rx_agg->context = tp;
1943 INIT_LIST_HEAD(&rx_agg->list);
1944 INIT_LIST_HEAD(&rx_agg->info_list);
1945 spin_lock_irqsave(&tp->rx_lock, flags);
1946 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1947 spin_unlock_irqrestore(&tp->rx_lock, flags);
1949 atomic_inc(&tp->rx_count);
1954 __free_pages(rx_agg->page, order);
1960 static void free_all_mem(struct r8152 *tp)
1962 struct rx_agg *agg, *agg_next;
1963 unsigned long flags;
1966 spin_lock_irqsave(&tp->rx_lock, flags);
1968 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1969 free_rx_agg(tp, agg);
1971 spin_unlock_irqrestore(&tp->rx_lock, flags);
1973 WARN_ON(atomic_read(&tp->rx_count));
1975 for (i = 0; i < RTL8152_MAX_TX; i++) {
1976 usb_free_urb(tp->tx_info[i].urb);
1977 tp->tx_info[i].urb = NULL;
1979 kfree(tp->tx_info[i].buffer);
1980 tp->tx_info[i].buffer = NULL;
1981 tp->tx_info[i].head = NULL;
1984 usb_free_urb(tp->intr_urb);
1985 tp->intr_urb = NULL;
1987 kfree(tp->intr_buff);
1988 tp->intr_buff = NULL;
1991 static int alloc_all_mem(struct r8152 *tp)
1993 struct net_device *netdev = tp->netdev;
1994 struct usb_interface *intf = tp->intf;
1995 struct usb_host_interface *alt = intf->cur_altsetting;
1996 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1999 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2001 spin_lock_init(&tp->rx_lock);
2002 spin_lock_init(&tp->tx_lock);
2003 INIT_LIST_HEAD(&tp->rx_info);
2004 INIT_LIST_HEAD(&tp->tx_free);
2005 INIT_LIST_HEAD(&tp->rx_done);
2006 skb_queue_head_init(&tp->tx_queue);
2007 skb_queue_head_init(&tp->rx_queue);
2008 atomic_set(&tp->rx_count, 0);
2010 for (i = 0; i < RTL8152_MAX_RX; i++) {
2011 if (!alloc_rx_agg(tp, GFP_KERNEL))
2015 for (i = 0; i < RTL8152_MAX_TX; i++) {
2019 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2023 if (buf != tx_agg_align(buf)) {
2025 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2031 urb = usb_alloc_urb(0, GFP_KERNEL);
2037 INIT_LIST_HEAD(&tp->tx_info[i].list);
2038 tp->tx_info[i].context = tp;
2039 tp->tx_info[i].urb = urb;
2040 tp->tx_info[i].buffer = buf;
2041 tp->tx_info[i].head = tx_agg_align(buf);
2043 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2046 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2050 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2054 tp->intr_interval = (int)ep_intr->desc.bInterval;
2055 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2056 tp->intr_buff, INTBUFSIZE, intr_callback,
2057 tp, tp->intr_interval);
2066 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2068 struct tx_agg *agg = NULL;
2069 unsigned long flags;
2071 if (list_empty(&tp->tx_free))
2074 spin_lock_irqsave(&tp->tx_lock, flags);
2075 if (!list_empty(&tp->tx_free)) {
2076 struct list_head *cursor;
2078 cursor = tp->tx_free.next;
2079 list_del_init(cursor);
2080 agg = list_entry(cursor, struct tx_agg, list);
2082 spin_unlock_irqrestore(&tp->tx_lock, flags);
2087 /* r8152_csum_workaround()
2088 * The hw limits the value of the transport offset. When the offset is out of
2089 * range, calculate the checksum by sw.
2091 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2092 struct sk_buff_head *list)
2094 if (skb_shinfo(skb)->gso_size) {
2095 netdev_features_t features = tp->netdev->features;
2096 struct sk_buff *segs, *seg, *next;
2097 struct sk_buff_head seg_list;
2099 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2100 segs = skb_gso_segment(skb, features);
2101 if (IS_ERR(segs) || !segs)
2104 __skb_queue_head_init(&seg_list);
2106 skb_list_walk_safe(segs, seg, next) {
2107 skb_mark_not_on_list(seg);
2108 __skb_queue_tail(&seg_list, seg);
2111 skb_queue_splice(&seg_list, list);
2113 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2114 if (skb_checksum_help(skb) < 0)
2117 __skb_queue_head(list, skb);
2119 struct net_device_stats *stats;
2122 stats = &tp->netdev->stats;
2123 stats->tx_dropped++;
2128 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2130 if (skb_vlan_tag_present(skb)) {
2133 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2134 desc->opts2 |= cpu_to_le32(opts2);
2138 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2140 u32 opts2 = le32_to_cpu(desc->opts2);
2142 if (opts2 & RX_VLAN_TAG)
2143 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2144 swab16(opts2 & 0xffff));
2147 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2148 struct sk_buff *skb, u32 len, u32 transport_offset)
2150 u32 mss = skb_shinfo(skb)->gso_size;
2151 u32 opts1, opts2 = 0;
2152 int ret = TX_CSUM_SUCCESS;
2154 WARN_ON_ONCE(len > TX_LEN_MAX);
2156 opts1 = len | TX_FS | TX_LS;
2159 if (transport_offset > GTTCPHO_MAX) {
2160 netif_warn(tp, tx_err, tp->netdev,
2161 "Invalid transport offset 0x%x for TSO\n",
2167 switch (vlan_get_protocol(skb)) {
2168 case htons(ETH_P_IP):
2172 case htons(ETH_P_IPV6):
2173 if (skb_cow_head(skb, 0)) {
2177 tcp_v6_gso_csum_prep(skb);
2186 opts1 |= transport_offset << GTTCPHO_SHIFT;
2187 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2188 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2191 if (transport_offset > TCPHO_MAX) {
2192 netif_warn(tp, tx_err, tp->netdev,
2193 "Invalid transport offset 0x%x\n",
2199 switch (vlan_get_protocol(skb)) {
2200 case htons(ETH_P_IP):
2202 ip_protocol = ip_hdr(skb)->protocol;
2205 case htons(ETH_P_IPV6):
2207 ip_protocol = ipv6_hdr(skb)->nexthdr;
2211 ip_protocol = IPPROTO_RAW;
2215 if (ip_protocol == IPPROTO_TCP)
2217 else if (ip_protocol == IPPROTO_UDP)
2222 opts2 |= transport_offset << TCPHO_SHIFT;
2225 desc->opts2 = cpu_to_le32(opts2);
2226 desc->opts1 = cpu_to_le32(opts1);
2232 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2234 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2238 __skb_queue_head_init(&skb_head);
2239 spin_lock(&tx_queue->lock);
2240 skb_queue_splice_init(tx_queue, &skb_head);
2241 spin_unlock(&tx_queue->lock);
2243 tx_data = agg->head;
2246 remain = agg_buf_sz;
2248 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2249 struct tx_desc *tx_desc;
2250 struct sk_buff *skb;
2254 skb = __skb_dequeue(&skb_head);
2258 len = skb->len + sizeof(*tx_desc);
2261 __skb_queue_head(&skb_head, skb);
2265 tx_data = tx_agg_align(tx_data);
2266 tx_desc = (struct tx_desc *)tx_data;
2268 offset = (u32)skb_transport_offset(skb);
2270 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2271 r8152_csum_workaround(tp, skb, &skb_head);
2275 rtl_tx_vlan_tag(tx_desc, skb);
2277 tx_data += sizeof(*tx_desc);
2280 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2281 struct net_device_stats *stats = &tp->netdev->stats;
2283 stats->tx_dropped++;
2284 dev_kfree_skb_any(skb);
2285 tx_data -= sizeof(*tx_desc);
2290 agg->skb_len += len;
2291 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2293 dev_kfree_skb_any(skb);
2295 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2297 if (tp->dell_tb_rx_agg_bug)
2301 if (!skb_queue_empty(&skb_head)) {
2302 spin_lock(&tx_queue->lock);
2303 skb_queue_splice(&skb_head, tx_queue);
2304 spin_unlock(&tx_queue->lock);
2307 netif_tx_lock(tp->netdev);
2309 if (netif_queue_stopped(tp->netdev) &&
2310 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2311 netif_wake_queue(tp->netdev);
2313 netif_tx_unlock(tp->netdev);
2315 ret = usb_autopm_get_interface_async(tp->intf);
2319 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2320 agg->head, (int)(tx_data - (u8 *)agg->head),
2321 (usb_complete_t)write_bulk_callback, agg);
2323 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2325 usb_autopm_put_interface_async(tp->intf);
2331 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2333 u8 checksum = CHECKSUM_NONE;
2336 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2339 opts2 = le32_to_cpu(rx_desc->opts2);
2340 opts3 = le32_to_cpu(rx_desc->opts3);
2342 if (opts2 & RD_IPV4_CS) {
2344 checksum = CHECKSUM_NONE;
2345 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2346 checksum = CHECKSUM_UNNECESSARY;
2347 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2348 checksum = CHECKSUM_UNNECESSARY;
2349 } else if (opts2 & RD_IPV6_CS) {
2350 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2351 checksum = CHECKSUM_UNNECESSARY;
2352 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2353 checksum = CHECKSUM_UNNECESSARY;
2360 static inline bool rx_count_exceed(struct r8152 *tp)
2362 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2365 static inline int agg_offset(struct rx_agg *agg, void *addr)
2367 return (int)(addr - agg->buffer);
2370 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2372 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2373 unsigned long flags;
2375 spin_lock_irqsave(&tp->rx_lock, flags);
2377 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2378 if (page_count(agg->page) == 1) {
2380 list_del_init(&agg->list);
2384 if (rx_count_exceed(tp)) {
2385 list_del_init(&agg->list);
2386 free_rx_agg(tp, agg);
2392 spin_unlock_irqrestore(&tp->rx_lock, flags);
2394 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2395 agg_free = alloc_rx_agg(tp, mflags);
2400 static int rx_bottom(struct r8152 *tp, int budget)
2402 unsigned long flags;
2403 struct list_head *cursor, *next, rx_queue;
2404 int ret = 0, work_done = 0;
2405 struct napi_struct *napi = &tp->napi;
2407 if (!skb_queue_empty(&tp->rx_queue)) {
2408 while (work_done < budget) {
2409 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2410 struct net_device *netdev = tp->netdev;
2411 struct net_device_stats *stats = &netdev->stats;
2412 unsigned int pkt_len;
2418 napi_gro_receive(napi, skb);
2420 stats->rx_packets++;
2421 stats->rx_bytes += pkt_len;
2425 if (list_empty(&tp->rx_done))
2428 INIT_LIST_HEAD(&rx_queue);
2429 spin_lock_irqsave(&tp->rx_lock, flags);
2430 list_splice_init(&tp->rx_done, &rx_queue);
2431 spin_unlock_irqrestore(&tp->rx_lock, flags);
2433 list_for_each_safe(cursor, next, &rx_queue) {
2434 struct rx_desc *rx_desc;
2435 struct rx_agg *agg, *agg_free;
2440 list_del_init(cursor);
2442 agg = list_entry(cursor, struct rx_agg, list);
2444 if (urb->actual_length < ETH_ZLEN)
2447 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2449 rx_desc = agg->buffer;
2450 rx_data = agg->buffer;
2451 len_used += sizeof(struct rx_desc);
2453 while (urb->actual_length > len_used) {
2454 struct net_device *netdev = tp->netdev;
2455 struct net_device_stats *stats = &netdev->stats;
2456 unsigned int pkt_len, rx_frag_head_sz;
2457 struct sk_buff *skb;
2459 /* limit the skb numbers for rx_queue */
2460 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2463 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2464 if (pkt_len < ETH_ZLEN)
2467 len_used += pkt_len;
2468 if (urb->actual_length < len_used)
2471 pkt_len -= ETH_FCS_LEN;
2472 rx_data += sizeof(struct rx_desc);
2474 if (!agg_free || tp->rx_copybreak > pkt_len)
2475 rx_frag_head_sz = pkt_len;
2477 rx_frag_head_sz = tp->rx_copybreak;
2479 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2481 stats->rx_dropped++;
2485 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2486 memcpy(skb->data, rx_data, rx_frag_head_sz);
2487 skb_put(skb, rx_frag_head_sz);
2488 pkt_len -= rx_frag_head_sz;
2489 rx_data += rx_frag_head_sz;
2491 skb_add_rx_frag(skb, 0, agg->page,
2492 agg_offset(agg, rx_data),
2494 SKB_DATA_ALIGN(pkt_len));
2495 get_page(agg->page);
2498 skb->protocol = eth_type_trans(skb, netdev);
2499 rtl_rx_vlan_tag(rx_desc, skb);
2500 if (work_done < budget) {
2502 stats->rx_packets++;
2503 stats->rx_bytes += skb->len;
2504 napi_gro_receive(napi, skb);
2506 __skb_queue_tail(&tp->rx_queue, skb);
2510 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2511 rx_desc = (struct rx_desc *)rx_data;
2512 len_used = agg_offset(agg, rx_data);
2513 len_used += sizeof(struct rx_desc);
2516 WARN_ON(!agg_free && page_count(agg->page) > 1);
2519 spin_lock_irqsave(&tp->rx_lock, flags);
2520 if (page_count(agg->page) == 1) {
2521 list_add(&agg_free->list, &tp->rx_used);
2523 list_add_tail(&agg->list, &tp->rx_used);
2527 spin_unlock_irqrestore(&tp->rx_lock, flags);
2532 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2534 urb->actual_length = 0;
2535 list_add_tail(&agg->list, next);
2539 if (!list_empty(&rx_queue)) {
2540 spin_lock_irqsave(&tp->rx_lock, flags);
2541 list_splice_tail(&rx_queue, &tp->rx_done);
2542 spin_unlock_irqrestore(&tp->rx_lock, flags);
2549 static void tx_bottom(struct r8152 *tp)
2554 struct net_device *netdev = tp->netdev;
2557 if (skb_queue_empty(&tp->tx_queue))
2560 agg = r8152_get_tx_agg(tp);
2564 res = r8152_tx_agg_fill(tp, agg);
2568 if (res == -ENODEV) {
2570 netif_device_detach(netdev);
2572 struct net_device_stats *stats = &netdev->stats;
2573 unsigned long flags;
2575 netif_warn(tp, tx_err, netdev,
2576 "failed tx_urb %d\n", res);
2577 stats->tx_dropped += agg->skb_num;
2579 spin_lock_irqsave(&tp->tx_lock, flags);
2580 list_add_tail(&agg->list, &tp->tx_free);
2581 spin_unlock_irqrestore(&tp->tx_lock, flags);
2586 static void bottom_half(struct tasklet_struct *t)
2588 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2590 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2593 if (!test_bit(WORK_ENABLE, &tp->flags))
2596 /* When link down, the driver would cancel all bulks. */
2597 /* This avoid the re-submitting bulk */
2598 if (!netif_carrier_ok(tp->netdev))
2601 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2606 static int r8152_poll(struct napi_struct *napi, int budget)
2608 struct r8152 *tp = container_of(napi, struct r8152, napi);
2611 work_done = rx_bottom(tp, budget);
2613 if (work_done < budget) {
2614 if (!napi_complete_done(napi, work_done))
2616 if (!list_empty(&tp->rx_done))
2617 napi_schedule(napi);
2625 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2629 /* The rx would be stopped, so skip submitting */
2630 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2631 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2634 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2635 agg->buffer, tp->rx_buf_sz,
2636 (usb_complete_t)read_bulk_callback, agg);
2638 ret = usb_submit_urb(agg->urb, mem_flags);
2639 if (ret == -ENODEV) {
2641 netif_device_detach(tp->netdev);
2643 struct urb *urb = agg->urb;
2644 unsigned long flags;
2646 urb->actual_length = 0;
2647 spin_lock_irqsave(&tp->rx_lock, flags);
2648 list_add_tail(&agg->list, &tp->rx_done);
2649 spin_unlock_irqrestore(&tp->rx_lock, flags);
2651 netif_err(tp, rx_err, tp->netdev,
2652 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2654 napi_schedule(&tp->napi);
2660 static void rtl_drop_queued_tx(struct r8152 *tp)
2662 struct net_device_stats *stats = &tp->netdev->stats;
2663 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2664 struct sk_buff *skb;
2666 if (skb_queue_empty(tx_queue))
2669 __skb_queue_head_init(&skb_head);
2670 spin_lock_bh(&tx_queue->lock);
2671 skb_queue_splice_init(tx_queue, &skb_head);
2672 spin_unlock_bh(&tx_queue->lock);
2674 while ((skb = __skb_dequeue(&skb_head))) {
2676 stats->tx_dropped++;
2680 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2682 struct r8152 *tp = netdev_priv(netdev);
2684 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2686 usb_queue_reset_device(tp->intf);
2689 static void rtl8152_set_rx_mode(struct net_device *netdev)
2691 struct r8152 *tp = netdev_priv(netdev);
2693 if (netif_carrier_ok(netdev)) {
2694 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2695 schedule_delayed_work(&tp->schedule, 0);
2699 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2701 struct r8152 *tp = netdev_priv(netdev);
2702 u32 mc_filter[2]; /* Multicast hash filter */
2706 netif_stop_queue(netdev);
2707 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2708 ocp_data &= ~RCR_ACPT_ALL;
2709 ocp_data |= RCR_AB | RCR_APM;
2711 if (netdev->flags & IFF_PROMISC) {
2712 /* Unconditionally log net taps. */
2713 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2714 ocp_data |= RCR_AM | RCR_AAP;
2715 mc_filter[1] = 0xffffffff;
2716 mc_filter[0] = 0xffffffff;
2717 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2718 (netdev->flags & IFF_ALLMULTI)) {
2719 /* Too many to filter perfectly -- accept all multicasts. */
2721 mc_filter[1] = 0xffffffff;
2722 mc_filter[0] = 0xffffffff;
2724 struct netdev_hw_addr *ha;
2728 netdev_for_each_mc_addr(ha, netdev) {
2729 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2731 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2736 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2737 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2739 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2740 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2741 netif_wake_queue(netdev);
2744 static netdev_features_t
2745 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2746 netdev_features_t features)
2748 u32 mss = skb_shinfo(skb)->gso_size;
2749 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2750 int offset = skb_transport_offset(skb);
2752 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2753 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2754 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2755 features &= ~NETIF_F_GSO_MASK;
2760 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2761 struct net_device *netdev)
2763 struct r8152 *tp = netdev_priv(netdev);
2765 skb_tx_timestamp(skb);
2767 skb_queue_tail(&tp->tx_queue, skb);
2769 if (!list_empty(&tp->tx_free)) {
2770 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2771 set_bit(SCHEDULE_TASKLET, &tp->flags);
2772 schedule_delayed_work(&tp->schedule, 0);
2774 usb_mark_last_busy(tp->udev);
2775 tasklet_schedule(&tp->tx_tl);
2777 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2778 netif_stop_queue(netdev);
2781 return NETDEV_TX_OK;
2784 static void r8152b_reset_packet_filter(struct r8152 *tp)
2788 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2789 ocp_data &= ~FMC_FCR_MCU_EN;
2790 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2791 ocp_data |= FMC_FCR_MCU_EN;
2792 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2795 static void rtl8152_nic_reset(struct r8152 *tp)
2800 switch (tp->version) {
2804 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2806 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2808 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2809 ocp_data &= ~BMU_RESET_EP_IN;
2810 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2812 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2813 ocp_data |= CDC_ECM_EN;
2814 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2816 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2818 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2820 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2821 ocp_data |= BMU_RESET_EP_IN;
2822 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2824 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2825 ocp_data &= ~CDC_ECM_EN;
2826 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2832 for (i = 0; i < 1000; i++) {
2833 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2835 usleep_range(100, 400);
2841 static void set_tx_qlen(struct r8152 *tp)
2843 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2846 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2848 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2851 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2855 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2857 ocp_data |= EEEP_CR_EEEP_TX;
2859 ocp_data &= ~EEEP_CR_EEEP_TX;
2860 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2863 static void rtl_set_eee_plus(struct r8152 *tp)
2865 if (rtl8152_get_speed(tp) & _10bps)
2866 rtl_eee_plus_en(tp, true);
2868 rtl_eee_plus_en(tp, false);
2871 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2877 ocp_data |= RXDY_GATED_EN;
2879 ocp_data &= ~RXDY_GATED_EN;
2880 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2883 static int rtl_start_rx(struct r8152 *tp)
2885 struct rx_agg *agg, *agg_next;
2886 struct list_head tmp_list;
2887 unsigned long flags;
2890 INIT_LIST_HEAD(&tmp_list);
2892 spin_lock_irqsave(&tp->rx_lock, flags);
2894 INIT_LIST_HEAD(&tp->rx_done);
2895 INIT_LIST_HEAD(&tp->rx_used);
2897 list_splice_init(&tp->rx_info, &tmp_list);
2899 spin_unlock_irqrestore(&tp->rx_lock, flags);
2901 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2902 INIT_LIST_HEAD(&agg->list);
2904 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2905 if (++i > RTL8152_MAX_RX) {
2906 spin_lock_irqsave(&tp->rx_lock, flags);
2907 list_add_tail(&agg->list, &tp->rx_used);
2908 spin_unlock_irqrestore(&tp->rx_lock, flags);
2909 } else if (unlikely(ret < 0)) {
2910 spin_lock_irqsave(&tp->rx_lock, flags);
2911 list_add_tail(&agg->list, &tp->rx_done);
2912 spin_unlock_irqrestore(&tp->rx_lock, flags);
2914 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2918 spin_lock_irqsave(&tp->rx_lock, flags);
2919 WARN_ON(!list_empty(&tp->rx_info));
2920 list_splice(&tmp_list, &tp->rx_info);
2921 spin_unlock_irqrestore(&tp->rx_lock, flags);
2926 static int rtl_stop_rx(struct r8152 *tp)
2928 struct rx_agg *agg, *agg_next;
2929 struct list_head tmp_list;
2930 unsigned long flags;
2932 INIT_LIST_HEAD(&tmp_list);
2934 /* The usb_kill_urb() couldn't be used in atomic.
2935 * Therefore, move the list of rx_info to a tmp one.
2936 * Then, list_for_each_entry_safe could be used without
2940 spin_lock_irqsave(&tp->rx_lock, flags);
2941 list_splice_init(&tp->rx_info, &tmp_list);
2942 spin_unlock_irqrestore(&tp->rx_lock, flags);
2944 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2945 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2946 * equal to 1, so the other ones could be freed safely.
2948 if (page_count(agg->page) > 1)
2949 free_rx_agg(tp, agg);
2951 usb_kill_urb(agg->urb);
2954 /* Move back the list of temp to the rx_info */
2955 spin_lock_irqsave(&tp->rx_lock, flags);
2956 WARN_ON(!list_empty(&tp->rx_info));
2957 list_splice(&tmp_list, &tp->rx_info);
2958 spin_unlock_irqrestore(&tp->rx_lock, flags);
2960 while (!skb_queue_empty(&tp->rx_queue))
2961 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2966 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
2970 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2971 ocp_data &= ~IFG_MASK;
2972 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
2973 ocp_data |= IFG_144NS;
2974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2976 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2977 ocp_data &= ~TX10MIDLE_EN;
2978 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2980 ocp_data |= IFG_96NS;
2981 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2983 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2984 ocp_data |= TX10MIDLE_EN;
2985 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2989 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2991 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2992 OWN_UPDATE | OWN_CLEAR);
2995 static int rtl_enable(struct r8152 *tp)
2999 r8152b_reset_packet_filter(tp);
3001 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3002 ocp_data |= CR_RE | CR_TE;
3003 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3005 switch (tp->version) {
3009 r8153b_rx_agg_chg_indicate(tp);
3015 rxdy_gated_en(tp, false);
3020 static int rtl8152_enable(struct r8152 *tp)
3022 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3026 rtl_set_eee_plus(tp);
3028 return rtl_enable(tp);
3031 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3033 u32 ocp_data = tp->coalesce / 8;
3035 switch (tp->version) {
3040 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3047 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3048 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3050 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3052 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3061 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3063 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3065 r8153b_rx_agg_chg_indicate(tp);
3073 static void r8153_set_rx_early_size(struct r8152 *tp)
3075 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3077 switch (tp->version) {
3082 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3088 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3097 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3099 r8153b_rx_agg_chg_indicate(tp);
3107 static int rtl8153_enable(struct r8152 *tp)
3111 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3115 rtl_set_eee_plus(tp);
3116 r8153_set_rx_early_timeout(tp);
3117 r8153_set_rx_early_size(tp);
3119 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3121 switch (tp->version) {
3124 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3125 ocp_data &= ~FC_PATCH_TASK;
3126 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3127 usleep_range(1000, 2000);
3128 ocp_data |= FC_PATCH_TASK;
3129 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3135 return rtl_enable(tp);
3138 static void rtl_disable(struct r8152 *tp)
3143 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3144 rtl_drop_queued_tx(tp);
3148 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3149 ocp_data &= ~RCR_ACPT_ALL;
3150 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3152 rtl_drop_queued_tx(tp);
3154 for (i = 0; i < RTL8152_MAX_TX; i++)
3155 usb_kill_urb(tp->tx_info[i].urb);
3157 rxdy_gated_en(tp, true);
3159 for (i = 0; i < 1000; i++) {
3160 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3161 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3163 usleep_range(1000, 2000);
3166 for (i = 0; i < 1000; i++) {
3167 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3169 usleep_range(1000, 2000);
3174 rtl8152_nic_reset(tp);
3177 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3181 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3183 ocp_data |= POWER_CUT;
3185 ocp_data &= ~POWER_CUT;
3186 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3188 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3189 ocp_data &= ~RESUME_INDICATE;
3190 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3193 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3197 switch (tp->version) {
3208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3210 ocp_data |= CPCR_RX_VLAN;
3212 ocp_data &= ~CPCR_RX_VLAN;
3213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3223 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3225 ocp_data |= OUTER_VLAN | INNER_VLAN;
3227 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3228 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3233 static int rtl8152_set_features(struct net_device *dev,
3234 netdev_features_t features)
3236 netdev_features_t changed = features ^ dev->features;
3237 struct r8152 *tp = netdev_priv(dev);
3240 ret = usb_autopm_get_interface(tp->intf);
3244 mutex_lock(&tp->control);
3246 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3247 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3248 rtl_rx_vlan_en(tp, true);
3250 rtl_rx_vlan_en(tp, false);
3253 mutex_unlock(&tp->control);
3255 usb_autopm_put_interface(tp->intf);
3261 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3263 static u32 __rtl_get_wol(struct r8152 *tp)
3268 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3269 if (ocp_data & LINK_ON_WAKE_EN)
3270 wolopts |= WAKE_PHY;
3272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3273 if (ocp_data & UWF_EN)
3274 wolopts |= WAKE_UCAST;
3275 if (ocp_data & BWF_EN)
3276 wolopts |= WAKE_BCAST;
3277 if (ocp_data & MWF_EN)
3278 wolopts |= WAKE_MCAST;
3280 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3281 if (ocp_data & MAGIC_EN)
3282 wolopts |= WAKE_MAGIC;
3287 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3291 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3294 ocp_data &= ~LINK_ON_WAKE_EN;
3295 if (wolopts & WAKE_PHY)
3296 ocp_data |= LINK_ON_WAKE_EN;
3297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3299 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3300 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3301 if (wolopts & WAKE_UCAST)
3303 if (wolopts & WAKE_BCAST)
3305 if (wolopts & WAKE_MCAST)
3307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3309 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3311 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3312 ocp_data &= ~MAGIC_EN;
3313 if (wolopts & WAKE_MAGIC)
3314 ocp_data |= MAGIC_EN;
3315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3317 if (wolopts & WAKE_ANY)
3318 device_set_wakeup_enable(&tp->udev->dev, true);
3320 device_set_wakeup_enable(&tp->udev->dev, false);
3323 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3325 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3327 /* MAC clock speed down */
3329 ocp_data |= MAC_CLK_SPDWN_EN;
3331 ocp_data &= ~MAC_CLK_SPDWN_EN;
3333 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3336 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3340 /* MAC clock speed down */
3342 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3346 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3347 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3348 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3349 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3351 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3352 ocp_data &= ~MAC_CLK_SPDWN_EN;
3353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3357 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3362 memset(u1u2, 0xff, sizeof(u1u2));
3364 memset(u1u2, 0x00, sizeof(u1u2));
3366 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3369 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3373 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3375 ocp_data |= LPM_U1U2_EN;
3377 ocp_data &= ~LPM_U1U2_EN;
3379 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3382 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3386 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3388 ocp_data |= U2P3_ENABLE;
3390 ocp_data &= ~U2P3_ENABLE;
3391 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3394 static void r8153b_ups_flags(struct r8152 *tp)
3398 if (tp->ups_info.green)
3399 ups_flags |= UPS_FLAGS_EN_GREEN;
3401 if (tp->ups_info.aldps)
3402 ups_flags |= UPS_FLAGS_EN_ALDPS;
3404 if (tp->ups_info.eee)
3405 ups_flags |= UPS_FLAGS_EN_EEE;
3407 if (tp->ups_info.flow_control)
3408 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3410 if (tp->ups_info.eee_ckdiv)
3411 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3413 if (tp->ups_info.eee_cmod_lv)
3414 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3416 if (tp->ups_info.r_tune)
3417 ups_flags |= UPS_FLAGS_R_TUNE;
3419 if (tp->ups_info._10m_ckdiv)
3420 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3422 if (tp->ups_info.eee_plloff_100)
3423 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3425 if (tp->ups_info.eee_plloff_giga)
3426 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3428 if (tp->ups_info._250m_ckdiv)
3429 ups_flags |= UPS_FLAGS_250M_CKDIV;
3431 if (tp->ups_info.ctap_short_off)
3432 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3434 switch (tp->ups_info.speed_duplex) {
3436 ups_flags |= ups_flags_speed(1);
3439 ups_flags |= ups_flags_speed(2);
3441 case NWAY_100M_HALF:
3442 ups_flags |= ups_flags_speed(3);
3444 case NWAY_100M_FULL:
3445 ups_flags |= ups_flags_speed(4);
3447 case NWAY_1000M_FULL:
3448 ups_flags |= ups_flags_speed(5);
3450 case FORCE_10M_HALF:
3451 ups_flags |= ups_flags_speed(6);
3453 case FORCE_10M_FULL:
3454 ups_flags |= ups_flags_speed(7);
3456 case FORCE_100M_HALF:
3457 ups_flags |= ups_flags_speed(8);
3459 case FORCE_100M_FULL:
3460 ups_flags |= ups_flags_speed(9);
3466 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3469 static void r8156_ups_flags(struct r8152 *tp)
3473 if (tp->ups_info.green)
3474 ups_flags |= UPS_FLAGS_EN_GREEN;
3476 if (tp->ups_info.aldps)
3477 ups_flags |= UPS_FLAGS_EN_ALDPS;
3479 if (tp->ups_info.eee)
3480 ups_flags |= UPS_FLAGS_EN_EEE;
3482 if (tp->ups_info.flow_control)
3483 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3485 if (tp->ups_info.eee_ckdiv)
3486 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3488 if (tp->ups_info._10m_ckdiv)
3489 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3491 if (tp->ups_info.eee_plloff_100)
3492 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3494 if (tp->ups_info.eee_plloff_giga)
3495 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3497 if (tp->ups_info._250m_ckdiv)
3498 ups_flags |= UPS_FLAGS_250M_CKDIV;
3500 switch (tp->ups_info.speed_duplex) {
3501 case FORCE_10M_HALF:
3502 ups_flags |= ups_flags_speed(0);
3504 case FORCE_10M_FULL:
3505 ups_flags |= ups_flags_speed(1);
3507 case FORCE_100M_HALF:
3508 ups_flags |= ups_flags_speed(2);
3510 case FORCE_100M_FULL:
3511 ups_flags |= ups_flags_speed(3);
3514 ups_flags |= ups_flags_speed(4);
3517 ups_flags |= ups_flags_speed(5);
3519 case NWAY_100M_HALF:
3520 ups_flags |= ups_flags_speed(6);
3522 case NWAY_100M_FULL:
3523 ups_flags |= ups_flags_speed(7);
3525 case NWAY_1000M_FULL:
3526 ups_flags |= ups_flags_speed(8);
3528 case NWAY_2500M_FULL:
3529 ups_flags |= ups_flags_speed(9);
3535 switch (tp->ups_info.lite_mode) {
3537 ups_flags |= 0 << 5;
3540 ups_flags |= 2 << 5;
3544 ups_flags |= 1 << 5;
3548 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3551 static void rtl_green_en(struct r8152 *tp, bool enable)
3555 data = sram_read(tp, SRAM_GREEN_CFG);
3557 data |= GREEN_ETH_EN;
3559 data &= ~GREEN_ETH_EN;
3560 sram_write(tp, SRAM_GREEN_CFG, data);
3562 tp->ups_info.green = enable;
3565 static void r8153b_green_en(struct r8152 *tp, bool enable)
3568 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3569 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3570 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3572 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3573 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3574 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3577 rtl_green_en(tp, true);
3580 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3585 for (i = 0; i < 500; i++) {
3586 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3587 data &= PHY_STAT_MASK;
3589 if (data == desired)
3591 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3592 data == PHY_STAT_EXT_INIT) {
3597 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3604 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3606 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3609 r8153b_ups_flags(tp);
3611 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3612 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3614 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3615 ocp_data |= UPS_FORCE_PWR_DOWN;
3616 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3618 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3619 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3621 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3622 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3623 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3625 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3628 for (i = 0; i < 500; i++) {
3629 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3635 tp->rtl_ops.hw_phy_cfg(tp);
3637 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3638 tp->duplex, tp->advertising);
3643 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3645 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3648 r8153b_ups_flags(tp);
3650 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3651 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3653 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3654 ocp_data |= UPS_FORCE_PWR_DOWN;
3655 ocp_data &= ~BIT(7);
3656 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3658 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3659 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3661 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3662 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3663 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3665 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3668 for (i = 0; i < 500; i++) {
3669 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3675 tp->rtl_ops.hw_phy_cfg(tp);
3677 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3678 tp->duplex, tp->advertising);
3681 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3683 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3685 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3687 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3691 static void r8156_ups_en(struct r8152 *tp, bool enable)
3693 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3696 r8156_ups_flags(tp);
3698 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3699 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3701 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3702 ocp_data |= UPS_FORCE_PWR_DOWN;
3703 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3705 switch (tp->version) {
3708 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3709 ocp_data &= ~OOBS_POLLING;
3710 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3716 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3717 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3719 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3720 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3721 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3723 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3724 tp->rtl_ops.hw_phy_cfg(tp);
3726 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3727 tp->duplex, tp->advertising);
3732 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3736 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3738 ocp_data |= PWR_EN | PHASE2_EN;
3740 ocp_data &= ~(PWR_EN | PHASE2_EN);
3741 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3743 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3744 ocp_data &= ~PCUT_STATUS;
3745 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3748 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3752 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3754 ocp_data |= PWR_EN | PHASE2_EN;
3756 ocp_data &= ~PWR_EN;
3757 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3759 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3760 ocp_data &= ~PCUT_STATUS;
3761 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3764 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3768 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3770 ocp_data |= UPCOMING_RUNTIME_D3;
3772 ocp_data &= ~UPCOMING_RUNTIME_D3;
3773 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3775 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3776 ocp_data &= ~LINK_CHG_EVENT;
3777 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3779 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3780 ocp_data &= ~LINK_CHANGE_FLAG;
3781 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3784 static bool rtl_can_wakeup(struct r8152 *tp)
3786 struct usb_device *udev = tp->udev;
3788 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3791 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3796 __rtl_set_wol(tp, WAKE_ANY);
3798 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3800 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3801 ocp_data |= LINK_OFF_WAKE_EN;
3802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3804 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3808 __rtl_set_wol(tp, tp->saved_wolopts);
3810 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3812 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3813 ocp_data &= ~LINK_OFF_WAKE_EN;
3814 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3820 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3823 r8153_u1u2en(tp, false);
3824 r8153_u2p3en(tp, false);
3825 rtl_runtime_suspend_enable(tp, true);
3827 rtl_runtime_suspend_enable(tp, false);
3829 switch (tp->version) {
3836 r8153_u2p3en(tp, true);
3840 r8153_u1u2en(tp, true);
3844 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3847 r8153_queue_wake(tp, true);
3848 r8153b_u1u2en(tp, false);
3849 r8153_u2p3en(tp, false);
3850 rtl_runtime_suspend_enable(tp, true);
3851 r8153b_ups_en(tp, true);
3853 r8153b_ups_en(tp, false);
3854 r8153_queue_wake(tp, false);
3855 rtl_runtime_suspend_enable(tp, false);
3856 if (tp->udev->speed >= USB_SPEED_SUPER)
3857 r8153b_u1u2en(tp, true);
3861 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3864 r8153_queue_wake(tp, true);
3865 r8153b_u1u2en(tp, false);
3866 r8153_u2p3en(tp, false);
3867 rtl_runtime_suspend_enable(tp, true);
3868 r8153c_ups_en(tp, true);
3870 r8153c_ups_en(tp, false);
3871 r8153_queue_wake(tp, false);
3872 rtl_runtime_suspend_enable(tp, false);
3873 r8153b_u1u2en(tp, true);
3877 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3880 r8153_queue_wake(tp, true);
3881 r8153b_u1u2en(tp, false);
3882 r8153_u2p3en(tp, false);
3883 rtl_runtime_suspend_enable(tp, true);
3885 r8153_queue_wake(tp, false);
3886 rtl_runtime_suspend_enable(tp, false);
3887 r8153_u2p3en(tp, true);
3888 if (tp->udev->speed >= USB_SPEED_SUPER)
3889 r8153b_u1u2en(tp, true);
3893 static void r8153_teredo_off(struct r8152 *tp)
3897 switch (tp->version) {
3905 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3906 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3908 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3921 /* The bit 0 ~ 7 are relative with teredo settings. They are
3922 * W1C (write 1 to clear), so set all 1 to disable it.
3924 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3928 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3929 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3930 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3933 static void rtl_reset_bmu(struct r8152 *tp)
3937 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3938 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3939 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3940 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3941 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3944 /* Clear the bp to stop the firmware before loading a new one */
3945 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3947 switch (tp->version) {
3956 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3959 ocp_write_word(tp, type, USB_BP2_EN, 0);
3961 ocp_write_word(tp, type, USB_BP_8, 0);
3962 ocp_write_word(tp, type, USB_BP_9, 0);
3963 ocp_write_word(tp, type, USB_BP_10, 0);
3964 ocp_write_word(tp, type, USB_BP_11, 0);
3965 ocp_write_word(tp, type, USB_BP_12, 0);
3966 ocp_write_word(tp, type, USB_BP_13, 0);
3967 ocp_write_word(tp, type, USB_BP_14, 0);
3968 ocp_write_word(tp, type, USB_BP_15, 0);
3978 if (type == MCU_TYPE_USB) {
3979 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3981 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3982 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3983 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3984 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3985 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3986 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3987 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3988 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3990 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3995 ocp_write_word(tp, type, PLA_BP_0, 0);
3996 ocp_write_word(tp, type, PLA_BP_1, 0);
3997 ocp_write_word(tp, type, PLA_BP_2, 0);
3998 ocp_write_word(tp, type, PLA_BP_3, 0);
3999 ocp_write_word(tp, type, PLA_BP_4, 0);
4000 ocp_write_word(tp, type, PLA_BP_5, 0);
4001 ocp_write_word(tp, type, PLA_BP_6, 0);
4002 ocp_write_word(tp, type, PLA_BP_7, 0);
4004 /* wait 3 ms to make sure the firmware is stopped */
4005 usleep_range(3000, 6000);
4006 ocp_write_word(tp, type, PLA_BP_BA, 0);
4009 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4014 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4016 data |= PATCH_REQUEST;
4019 data &= ~PATCH_REQUEST;
4020 check = PATCH_READY;
4022 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4024 for (i = 0; wait && i < 5000; i++) {
4027 usleep_range(1000, 2000);
4028 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4029 if ((ocp_data & PATCH_READY) ^ check)
4033 if (request && wait &&
4034 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4035 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4036 rtl_phy_patch_request(tp, false, false);
4043 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4045 if (patch_key && key_addr) {
4046 sram_write(tp, key_addr, patch_key);
4047 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4048 } else if (key_addr) {
4051 sram_write(tp, 0x0000, 0x0000);
4053 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4054 data &= ~PATCH_LOCK;
4055 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4057 sram_write(tp, key_addr, 0x0000);
4064 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4066 if (rtl_phy_patch_request(tp, true, wait))
4069 rtl_patch_key_set(tp, key_addr, patch_key);
4074 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4076 rtl_patch_key_set(tp, key_addr, 0);
4078 rtl_phy_patch_request(tp, false, wait);
4080 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4085 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4091 switch (tp->version) {
4112 fw_offset = __le16_to_cpu(phy->fw_offset);
4113 length = __le32_to_cpu(phy->blk_hdr.length);
4114 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4115 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4119 length -= fw_offset;
4121 dev_err(&tp->intf->dev, "invalid block length\n");
4125 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4126 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4135 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4139 switch (tp->version) {
4150 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4151 dev_err(&tp->intf->dev, "invalid block length\n");
4155 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4156 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4165 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4169 switch (tp->version) {
4180 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4181 dev_err(&tp->intf->dev, "invalid block length\n");
4185 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4186 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4187 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4196 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4202 switch (tp->version) {
4213 fw_offset = __le16_to_cpu(phy->fw_offset);
4214 length = __le32_to_cpu(phy->blk_hdr.length);
4215 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4216 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4220 length -= fw_offset;
4222 dev_err(&tp->intf->dev, "invalid block length\n");
4226 if (phy->pre_num > 2) {
4227 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4231 if (phy->bp_num > 8) {
4232 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4241 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4244 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4247 switch (tp->version) {
4253 patch_en_addr = 0xa01a;
4261 fw_offset = __le16_to_cpu(phy->fw_offset);
4262 if (fw_offset < sizeof(*phy)) {
4263 dev_err(&tp->intf->dev, "fw_offset too small\n");
4267 length = __le32_to_cpu(phy->blk_hdr.length);
4268 if (length < fw_offset) {
4269 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4273 length -= __le16_to_cpu(phy->fw_offset);
4274 if (!length || (length & 1)) {
4275 dev_err(&tp->intf->dev, "invalid block length\n");
4279 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4280 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4284 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4285 dev_err(&tp->intf->dev, "invalid base address register\n");
4289 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4290 dev_err(&tp->intf->dev,
4291 "invalid patch mode enabled register\n");
4295 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4296 dev_err(&tp->intf->dev,
4297 "invalid register to switch the mode\n");
4301 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4302 dev_err(&tp->intf->dev,
4303 "invalid start register of break point\n");
4307 if (__le16_to_cpu(phy->bp_num) > 4) {
4308 dev_err(&tp->intf->dev, "invalid break point number\n");
4317 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4319 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4324 type = __le32_to_cpu(mac->blk_hdr.type);
4325 if (type == RTL_FW_PLA) {
4326 switch (tp->version) {
4331 bp_ba_addr = PLA_BP_BA;
4333 bp_start = PLA_BP_0;
4347 bp_ba_addr = PLA_BP_BA;
4348 bp_en_addr = PLA_BP_EN;
4349 bp_start = PLA_BP_0;
4354 bp_ba_addr = PLA_BP_BA;
4355 bp_en_addr = USB_BP2_EN;
4356 bp_start = PLA_BP_0;
4362 } else if (type == RTL_FW_USB) {
4363 switch (tp->version) {
4369 bp_ba_addr = USB_BP_BA;
4370 bp_en_addr = USB_BP_EN;
4371 bp_start = USB_BP_0;
4382 bp_ba_addr = USB_BP_BA;
4383 bp_en_addr = USB_BP2_EN;
4384 bp_start = USB_BP_0;
4397 fw_offset = __le16_to_cpu(mac->fw_offset);
4398 if (fw_offset < sizeof(*mac)) {
4399 dev_err(&tp->intf->dev, "fw_offset too small\n");
4403 length = __le32_to_cpu(mac->blk_hdr.length);
4404 if (length < fw_offset) {
4405 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4409 length -= fw_offset;
4410 if (length < 4 || (length & 3)) {
4411 dev_err(&tp->intf->dev, "invalid block length\n");
4415 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4416 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4420 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4421 dev_err(&tp->intf->dev, "invalid base address register\n");
4425 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4426 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4430 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4431 dev_err(&tp->intf->dev,
4432 "invalid start register of break point\n");
4436 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4437 dev_err(&tp->intf->dev, "invalid break point number\n");
4441 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4443 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4453 /* Verify the checksum for the firmware file. It is calculated from the version
4454 * field to the end of the file. Compare the result with the checksum field to
4455 * make sure the file is correct.
4457 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4458 struct fw_header *fw_hdr, size_t size)
4460 unsigned char checksum[sizeof(fw_hdr->checksum)];
4461 struct crypto_shash *alg;
4462 struct shash_desc *sdesc;
4466 alg = crypto_alloc_shash("sha256", 0, 0);
4472 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4474 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4475 crypto_shash_digestsize(alg));
4479 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4480 sdesc = kmalloc(len, GFP_KERNEL);
4487 len = size - sizeof(fw_hdr->checksum);
4488 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4493 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4494 dev_err(&tp->intf->dev, "checksum fail\n");
4499 crypto_free_shash(alg);
4504 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4506 const struct firmware *fw = rtl_fw->fw;
4507 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4508 unsigned long fw_flags = 0;
4512 if (fw->size < sizeof(*fw_hdr)) {
4513 dev_err(&tp->intf->dev, "file too small\n");
4517 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4523 for (i = sizeof(*fw_hdr); i < fw->size;) {
4524 struct fw_block *block = (struct fw_block *)&fw->data[i];
4527 if ((i + sizeof(*block)) > fw->size)
4530 type = __le32_to_cpu(block->type);
4533 if (__le32_to_cpu(block->length) != sizeof(*block))
4537 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4538 dev_err(&tp->intf->dev,
4539 "multiple PLA firmware encountered");
4543 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4544 dev_err(&tp->intf->dev,
4545 "check PLA firmware failed\n");
4548 __set_bit(FW_FLAGS_PLA, &fw_flags);
4551 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4552 dev_err(&tp->intf->dev,
4553 "multiple USB firmware encountered");
4557 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4558 dev_err(&tp->intf->dev,
4559 "check USB firmware failed\n");
4562 __set_bit(FW_FLAGS_USB, &fw_flags);
4564 case RTL_FW_PHY_START:
4565 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4566 test_bit(FW_FLAGS_NC, &fw_flags) ||
4567 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4568 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4569 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4570 test_bit(FW_FLAGS_UC, &fw_flags) ||
4571 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4572 dev_err(&tp->intf->dev,
4573 "check PHY_START fail\n");
4577 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4578 dev_err(&tp->intf->dev,
4579 "Invalid length for PHY_START\n");
4582 __set_bit(FW_FLAGS_START, &fw_flags);
4584 case RTL_FW_PHY_STOP:
4585 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4586 !test_bit(FW_FLAGS_START, &fw_flags)) {
4587 dev_err(&tp->intf->dev,
4588 "Check PHY_STOP fail\n");
4592 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4593 dev_err(&tp->intf->dev,
4594 "Invalid length for PHY_STOP\n");
4597 __set_bit(FW_FLAGS_STOP, &fw_flags);
4600 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4601 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4602 dev_err(&tp->intf->dev,
4603 "check PHY_NC fail\n");
4607 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4608 dev_err(&tp->intf->dev,
4609 "multiple PHY NC encountered\n");
4613 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4614 dev_err(&tp->intf->dev,
4615 "check PHY NC firmware failed\n");
4618 __set_bit(FW_FLAGS_NC, &fw_flags);
4620 case RTL_FW_PHY_UNION_NC:
4621 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4622 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4623 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4624 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4625 test_bit(FW_FLAGS_UC, &fw_flags) ||
4626 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4627 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4631 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4632 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4636 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4637 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4640 __set_bit(FW_FLAGS_NC, &fw_flags);
4642 case RTL_FW_PHY_UNION_NC1:
4643 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4644 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4645 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4646 test_bit(FW_FLAGS_UC, &fw_flags) ||
4647 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4648 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4652 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4653 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4657 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4658 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4661 __set_bit(FW_FLAGS_NC1, &fw_flags);
4663 case RTL_FW_PHY_UNION_NC2:
4664 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4665 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4666 test_bit(FW_FLAGS_UC, &fw_flags) ||
4667 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4668 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4672 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4673 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4677 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4678 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4681 __set_bit(FW_FLAGS_NC2, &fw_flags);
4683 case RTL_FW_PHY_UNION_UC2:
4684 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4685 test_bit(FW_FLAGS_UC, &fw_flags) ||
4686 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4687 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4691 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4692 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4696 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4697 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4700 __set_bit(FW_FLAGS_UC2, &fw_flags);
4702 case RTL_FW_PHY_UNION_UC:
4703 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4704 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4705 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4709 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4710 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4714 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4715 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4718 __set_bit(FW_FLAGS_UC, &fw_flags);
4720 case RTL_FW_PHY_UNION_MISC:
4721 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4722 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4726 case RTL_FW_PHY_FIXUP:
4727 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4728 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4732 case RTL_FW_PHY_SPEED_UP:
4733 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4734 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4738 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4739 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4742 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4744 case RTL_FW_PHY_VER:
4745 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4746 test_bit(FW_FLAGS_NC, &fw_flags) ||
4747 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4748 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4749 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4750 test_bit(FW_FLAGS_UC, &fw_flags) ||
4751 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4752 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4756 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4757 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4761 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4762 dev_err(&tp->intf->dev, "check PHY version failed\n");
4765 __set_bit(FW_FLAGS_VER, &fw_flags);
4768 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4774 i += ALIGN(__le32_to_cpu(block->length), 8);
4778 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4779 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4788 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4793 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4794 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4798 len = __le32_to_cpu(phy->blk_hdr.length);
4799 len -= __le16_to_cpu(phy->fw_offset);
4800 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4802 if (rtl_phy_patch_request(tp, true, wait))
4814 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4815 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4816 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4818 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4823 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4824 ocp_data |= POL_GPHY_PATCH;
4825 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4827 for (i = 0; i < 1000; i++) {
4828 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4833 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4838 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4839 rtl_phy_patch_request(tp, false, wait);
4841 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4842 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4844 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4847 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4851 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4852 ver = __le16_to_cpu(phy_ver->ver.data);
4854 if (sram_read(tp, ver_addr) >= ver) {
4855 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4859 sram_write(tp, ver_addr, ver);
4861 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4866 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4870 addr = __le16_to_cpu(fix->setting.addr);
4871 data = ocp_reg_read(tp, addr);
4873 switch (__le16_to_cpu(fix->bit_cmd)) {
4875 data &= __le16_to_cpu(fix->setting.data);
4878 data |= __le16_to_cpu(fix->setting.data);
4881 data &= ~__le16_to_cpu(fix->setting.data);
4884 data ^= __le16_to_cpu(fix->setting.data);
4890 ocp_reg_write(tp, addr, data);
4892 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4895 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4902 for (i = 0; i < num; i++)
4903 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4904 __le16_to_cpu(phy->pre_set[i].data));
4906 length = __le32_to_cpu(phy->blk_hdr.length);
4907 length -= __le16_to_cpu(phy->fw_offset);
4909 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4911 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4912 for (i = 0; i < num; i++)
4913 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4916 for (i = 0; i < num; i++)
4917 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4919 if (phy->bp_num && phy->bp_en.addr)
4920 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4922 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4925 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4927 u16 mode_reg, bp_index;
4931 mode_reg = __le16_to_cpu(phy->mode_reg);
4932 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4933 sram_write(tp, __le16_to_cpu(phy->ba_reg),
4934 __le16_to_cpu(phy->ba_data));
4936 length = __le32_to_cpu(phy->blk_hdr.length);
4937 length -= __le16_to_cpu(phy->fw_offset);
4939 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4941 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4942 for (i = 0; i < num; i++)
4943 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4945 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4946 __le16_to_cpu(phy->patch_en_value));
4948 bp_index = __le16_to_cpu(phy->bp_start);
4949 num = __le16_to_cpu(phy->bp_num);
4950 for (i = 0; i < num; i++) {
4951 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4955 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4957 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4960 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4962 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
4967 switch (__le32_to_cpu(mac->blk_hdr.type)) {
4969 type = MCU_TYPE_PLA;
4972 type = MCU_TYPE_USB;
4978 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4979 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
4980 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
4984 rtl_clear_bp(tp, type);
4986 /* Enable backup/restore of MACDBG. This is required after clearing PLA
4987 * break points and before applying the PLA firmware.
4989 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
4990 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
4991 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
4992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
4995 length = __le32_to_cpu(mac->blk_hdr.length);
4996 length -= __le16_to_cpu(mac->fw_offset);
4999 data += __le16_to_cpu(mac->fw_offset);
5001 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5004 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5005 __le16_to_cpu(mac->bp_ba_value));
5007 bp_index = __le16_to_cpu(mac->bp_start);
5008 bp_num = __le16_to_cpu(mac->bp_num);
5009 for (i = 0; i < bp_num; i++) {
5010 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
5014 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5016 ocp_write_word(tp, type, bp_en_addr,
5017 __le16_to_cpu(mac->bp_en_value));
5020 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5023 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5026 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5028 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5029 const struct firmware *fw;
5030 struct fw_header *fw_hdr;
5031 struct fw_phy_patch_key *key;
5033 int i, patch_phy = 1;
5035 if (IS_ERR_OR_NULL(rtl_fw->fw))
5039 fw_hdr = (struct fw_header *)fw->data;
5044 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5045 struct fw_block *block = (struct fw_block *)&fw->data[i];
5047 switch (__le32_to_cpu(block->type)) {
5052 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5054 case RTL_FW_PHY_START:
5057 key = (struct fw_phy_patch_key *)block;
5058 key_addr = __le16_to_cpu(key->key_reg);
5059 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5061 case RTL_FW_PHY_STOP:
5065 rtl_post_ram_code(tp, key_addr, !power_cut);
5068 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5070 case RTL_FW_PHY_VER:
5071 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5073 case RTL_FW_PHY_UNION_NC:
5074 case RTL_FW_PHY_UNION_NC1:
5075 case RTL_FW_PHY_UNION_NC2:
5076 case RTL_FW_PHY_UNION_UC2:
5077 case RTL_FW_PHY_UNION_UC:
5078 case RTL_FW_PHY_UNION_MISC:
5080 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5082 case RTL_FW_PHY_FIXUP:
5084 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5086 case RTL_FW_PHY_SPEED_UP:
5087 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5093 i += ALIGN(__le32_to_cpu(block->length), 8);
5097 if (rtl_fw->post_fw)
5098 rtl_fw->post_fw(tp);
5100 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5101 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5104 static void rtl8152_release_firmware(struct r8152 *tp)
5106 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5108 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5109 release_firmware(rtl_fw->fw);
5114 static int rtl8152_request_firmware(struct r8152 *tp)
5116 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5119 if (rtl_fw->fw || !rtl_fw->fw_name) {
5120 dev_info(&tp->intf->dev, "skip request firmware\n");
5125 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5129 rc = rtl8152_check_firmware(tp, rtl_fw);
5131 release_firmware(rtl_fw->fw);
5135 rtl_fw->fw = ERR_PTR(rc);
5137 dev_warn(&tp->intf->dev,
5138 "unable to load firmware patch %s (%ld)\n",
5139 rtl_fw->fw_name, rc);
5145 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5148 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5149 LINKENA | DIS_SDSAVE);
5151 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5157 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5159 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5160 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5161 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5164 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5168 r8152_mmd_indirect(tp, dev, reg);
5169 data = ocp_reg_read(tp, OCP_EEE_DATA);
5170 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5175 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5177 r8152_mmd_indirect(tp, dev, reg);
5178 ocp_reg_write(tp, OCP_EEE_DATA, data);
5179 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5182 static void r8152_eee_en(struct r8152 *tp, bool enable)
5184 u16 config1, config2, config3;
5187 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5188 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5189 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5190 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5193 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5194 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5195 config1 |= sd_rise_time(1);
5196 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5197 config3 |= fast_snr(42);
5199 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5200 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5202 config1 |= sd_rise_time(7);
5203 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5204 config3 |= fast_snr(511);
5207 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5208 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5209 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5210 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5213 static void r8153_eee_en(struct r8152 *tp, bool enable)
5218 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5219 config = ocp_reg_read(tp, OCP_EEE_CFG);
5222 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5225 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5226 config &= ~EEE10_EN;
5229 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5230 ocp_reg_write(tp, OCP_EEE_CFG, config);
5232 tp->ups_info.eee = enable;
5235 static void r8156_eee_en(struct r8152 *tp, bool enable)
5239 r8153_eee_en(tp, enable);
5241 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5244 config |= MDIO_EEE_2_5GT;
5246 config &= ~MDIO_EEE_2_5GT;
5248 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5251 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5253 switch (tp->version) {
5258 r8152_eee_en(tp, true);
5259 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5262 r8152_eee_en(tp, false);
5263 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5274 r8153_eee_en(tp, true);
5275 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5277 r8153_eee_en(tp, false);
5278 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5287 r8156_eee_en(tp, true);
5288 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5290 r8156_eee_en(tp, false);
5291 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5299 static void r8152b_enable_fc(struct r8152 *tp)
5303 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5304 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5305 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5307 tp->ups_info.flow_control = true;
5310 static void rtl8152_disable(struct r8152 *tp)
5312 r8152_aldps_en(tp, false);
5314 r8152_aldps_en(tp, true);
5317 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5319 rtl8152_apply_firmware(tp, false);
5320 rtl_eee_enable(tp, tp->eee_en);
5321 r8152_aldps_en(tp, true);
5322 r8152b_enable_fc(tp);
5324 set_bit(PHY_RESET, &tp->flags);
5327 static void wait_oob_link_list_ready(struct r8152 *tp)
5332 for (i = 0; i < 1000; i++) {
5333 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5334 if (ocp_data & LINK_LIST_READY)
5336 usleep_range(1000, 2000);
5340 static void r8156b_wait_loading_flash(struct r8152 *tp)
5342 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5343 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5346 for (i = 0; i < 100; i++) {
5347 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5349 usleep_range(1000, 2000);
5354 static void r8152b_exit_oob(struct r8152 *tp)
5358 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5359 ocp_data &= ~RCR_ACPT_ALL;
5360 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5362 rxdy_gated_en(tp, true);
5363 r8153_teredo_off(tp);
5364 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5365 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5367 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5368 ocp_data &= ~NOW_IS_OOB;
5369 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5372 ocp_data &= ~MCU_BORW_EN;
5373 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5375 wait_oob_link_list_ready(tp);
5377 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5378 ocp_data |= RE_INIT_LL;
5379 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5381 wait_oob_link_list_ready(tp);
5383 rtl8152_nic_reset(tp);
5385 /* rx share fifo credit full threshold */
5386 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5388 if (tp->udev->speed == USB_SPEED_FULL ||
5389 tp->udev->speed == USB_SPEED_LOW) {
5390 /* rx share fifo credit near full threshold */
5391 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5393 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5396 /* rx share fifo credit near full threshold */
5397 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5399 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5403 /* TX share fifo free credit full threshold */
5404 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5406 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5407 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5408 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5409 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5411 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5413 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5415 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5416 ocp_data |= TCR0_AUTO_FIFO;
5417 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5420 static void r8152b_enter_oob(struct r8152 *tp)
5424 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5425 ocp_data &= ~NOW_IS_OOB;
5426 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5429 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5430 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5434 wait_oob_link_list_ready(tp);
5436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5437 ocp_data |= RE_INIT_LL;
5438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5440 wait_oob_link_list_ready(tp);
5442 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5444 rtl_rx_vlan_en(tp, true);
5446 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5447 ocp_data |= ALDPS_PROXY_MODE;
5448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5450 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5451 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5452 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5454 rxdy_gated_en(tp, false);
5456 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5457 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5458 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5461 static int r8153_pre_firmware_1(struct r8152 *tp)
5465 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5466 for (i = 0; i < 104; i++) {
5467 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5469 if (!(ocp_data & WTD1_EN))
5471 usleep_range(1000, 2000);
5477 static int r8153_post_firmware_1(struct r8152 *tp)
5479 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5480 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5481 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5483 /* reset UPHY timer to 36 ms */
5484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5489 static int r8153_pre_firmware_2(struct r8152 *tp)
5493 r8153_pre_firmware_1(tp);
5495 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5496 ocp_data &= ~FW_FIX_SUSPEND;
5497 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5502 static int r8153_post_firmware_2(struct r8152 *tp)
5506 /* enable bp0 if support USB_SPEED_SUPER only */
5507 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5508 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5510 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5513 /* reset UPHY timer to 36 ms */
5514 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5516 /* enable U3P3 check, set the counter to 4 */
5517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5519 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5520 ocp_data |= FW_FIX_SUSPEND;
5521 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5523 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5524 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5525 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5530 static int r8153_post_firmware_3(struct r8152 *tp)
5534 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5535 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5536 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5538 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5539 ocp_data |= FW_IP_RESET_EN;
5540 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5545 static int r8153b_pre_firmware_1(struct r8152 *tp)
5547 /* enable fc timer and set timer to 1 second. */
5548 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5549 CTRL_TIMER_EN | (1000 / 8));
5554 static int r8153b_post_firmware_1(struct r8152 *tp)
5558 /* enable bp0 for RTL8153-BND */
5559 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5560 if (ocp_data & BND_MASK) {
5561 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5563 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5566 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5567 ocp_data |= FLOW_CTRL_PATCH_OPT;
5568 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5570 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5571 ocp_data |= FC_PATCH_TASK;
5572 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5574 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5575 ocp_data |= FW_IP_RESET_EN;
5576 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5581 static int r8153c_post_firmware_1(struct r8152 *tp)
5585 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5586 ocp_data |= FLOW_CTRL_PATCH_2;
5587 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5589 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5590 ocp_data |= FC_PATCH_TASK;
5591 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5596 static int r8156a_post_firmware_1(struct r8152 *tp)
5600 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5601 ocp_data |= FW_IP_RESET_EN;
5602 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5604 /* Modify U3PHY parameter for compatibility issue */
5605 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5606 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5611 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5615 data = ocp_reg_read(tp, OCP_POWER_CFG);
5618 ocp_reg_write(tp, OCP_POWER_CFG, data);
5623 ocp_reg_write(tp, OCP_POWER_CFG, data);
5624 for (i = 0; i < 20; i++) {
5625 usleep_range(1000, 2000);
5626 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5631 tp->ups_info.aldps = enable;
5634 static void r8153_hw_phy_cfg(struct r8152 *tp)
5639 /* disable ALDPS before updating the PHY parameters */
5640 r8153_aldps_en(tp, false);
5642 /* disable EEE before updating the PHY parameters */
5643 rtl_eee_enable(tp, false);
5645 rtl8152_apply_firmware(tp, false);
5647 if (tp->version == RTL_VER_03) {
5648 data = ocp_reg_read(tp, OCP_EEE_CFG);
5649 data &= ~CTAP_SHORT_EN;
5650 ocp_reg_write(tp, OCP_EEE_CFG, data);
5653 data = ocp_reg_read(tp, OCP_POWER_CFG);
5654 data |= EEE_CLKDIV_EN;
5655 ocp_reg_write(tp, OCP_POWER_CFG, data);
5657 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5658 data |= EN_10M_BGOFF;
5659 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5660 data = ocp_reg_read(tp, OCP_POWER_CFG);
5661 data |= EN_10M_PLLOFF;
5662 ocp_reg_write(tp, OCP_POWER_CFG, data);
5663 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5665 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5666 ocp_data |= PFM_PWM_SWITCH;
5667 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5669 /* Enable LPF corner auto tune */
5670 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5672 /* Adjust 10M Amplitude */
5673 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5674 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5677 rtl_eee_enable(tp, true);
5679 r8153_aldps_en(tp, true);
5680 r8152b_enable_fc(tp);
5682 switch (tp->version) {
5689 r8153_u2p3en(tp, true);
5693 set_bit(PHY_RESET, &tp->flags);
5696 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5700 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5701 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5702 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5703 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5708 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5713 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5714 if (ocp_data & PCUT_STATUS) {
5715 ocp_data &= ~PCUT_STATUS;
5716 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5719 /* disable ALDPS before updating the PHY parameters */
5720 r8153_aldps_en(tp, false);
5722 /* disable EEE before updating the PHY parameters */
5723 rtl_eee_enable(tp, false);
5725 /* U1/U2/L1 idle timer. 500 us */
5726 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5728 data = r8153_phy_status(tp, 0);
5731 case PHY_STAT_PWRDN:
5732 case PHY_STAT_EXT_INIT:
5733 rtl8152_apply_firmware(tp, true);
5735 data = r8152_mdio_read(tp, MII_BMCR);
5736 data &= ~BMCR_PDOWN;
5737 r8152_mdio_write(tp, MII_BMCR, data);
5739 case PHY_STAT_LAN_ON:
5741 rtl8152_apply_firmware(tp, false);
5745 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5747 data = sram_read(tp, SRAM_GREEN_CFG);
5749 sram_write(tp, SRAM_GREEN_CFG, data);
5750 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5751 data |= PGA_RETURN_EN;
5752 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5754 /* ADC Bias Calibration:
5755 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5756 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5759 ocp_data = r8152_efuse_read(tp, 0x7d);
5760 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5762 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5764 /* ups mode tx-link-pulse timing adjustment:
5765 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5766 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5768 ocp_data = ocp_reg_read(tp, 0xc426);
5771 u32 swr_cnt_1ms_ini;
5773 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5774 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5775 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5776 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5779 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5780 ocp_data |= PFM_PWM_SWITCH;
5781 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5784 if (!rtl_phy_patch_request(tp, true, true)) {
5785 data = ocp_reg_read(tp, OCP_POWER_CFG);
5786 data |= EEE_CLKDIV_EN;
5787 ocp_reg_write(tp, OCP_POWER_CFG, data);
5788 tp->ups_info.eee_ckdiv = true;
5790 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5791 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5792 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5793 tp->ups_info.eee_cmod_lv = true;
5794 tp->ups_info._10m_ckdiv = true;
5795 tp->ups_info.eee_plloff_giga = true;
5797 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5798 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5799 tp->ups_info._250m_ckdiv = true;
5801 rtl_phy_patch_request(tp, false, true);
5805 rtl_eee_enable(tp, true);
5807 r8153_aldps_en(tp, true);
5808 r8152b_enable_fc(tp);
5810 set_bit(PHY_RESET, &tp->flags);
5813 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5815 r8153b_hw_phy_cfg(tp);
5817 tp->ups_info.r_tune = true;
5820 static void rtl8153_change_mtu(struct r8152 *tp)
5822 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5823 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5826 static void r8153_first_init(struct r8152 *tp)
5830 rxdy_gated_en(tp, true);
5831 r8153_teredo_off(tp);
5833 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5834 ocp_data &= ~RCR_ACPT_ALL;
5835 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5837 rtl8152_nic_reset(tp);
5840 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5841 ocp_data &= ~NOW_IS_OOB;
5842 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5844 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5845 ocp_data &= ~MCU_BORW_EN;
5846 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5848 wait_oob_link_list_ready(tp);
5850 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5851 ocp_data |= RE_INIT_LL;
5852 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5854 wait_oob_link_list_ready(tp);
5856 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5858 rtl8153_change_mtu(tp);
5860 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5861 ocp_data |= TCR0_AUTO_FIFO;
5862 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5864 rtl8152_nic_reset(tp);
5866 /* rx share fifo credit full threshold */
5867 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5868 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5869 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5870 /* TX share fifo free credit full threshold */
5871 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5874 static void r8153_enter_oob(struct r8152 *tp)
5878 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5879 ocp_data &= ~NOW_IS_OOB;
5880 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5885 wait_oob_link_list_ready(tp);
5887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5888 ocp_data |= RE_INIT_LL;
5889 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5891 wait_oob_link_list_ready(tp);
5893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5895 switch (tp->version) {
5900 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5901 ocp_data &= ~TEREDO_WAKE_MASK;
5902 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5908 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5909 * type. Set it to zero. bits[7:0] are the W1C bits about
5910 * the events. Set them to all 1 to clear them.
5912 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5919 rtl_rx_vlan_en(tp, true);
5921 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5922 ocp_data |= ALDPS_PROXY_MODE;
5923 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5925 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5926 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5927 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5929 rxdy_gated_en(tp, false);
5931 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5932 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5933 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5936 static void rtl8153_disable(struct r8152 *tp)
5938 r8153_aldps_en(tp, false);
5941 r8153_aldps_en(tp, true);
5944 static int rtl8156_enable(struct r8152 *tp)
5949 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5953 rtl_set_eee_plus(tp);
5954 r8153_set_rx_early_timeout(tp);
5955 r8153_set_rx_early_size(tp);
5957 speed = rtl8152_get_speed(tp);
5958 rtl_set_ifg(tp, speed);
5960 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5961 if (speed & _2500bps)
5962 ocp_data &= ~IDLE_SPDWN_EN;
5964 ocp_data |= IDLE_SPDWN_EN;
5965 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5967 if (speed & _1000bps)
5968 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
5969 else if (speed & _500bps)
5970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
5972 if (tp->udev->speed == USB_SPEED_HIGH) {
5973 /* USB 0xb45e[3:0] l1_nyet_hird */
5974 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
5976 if (is_flow_control(speed))
5980 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
5983 return rtl_enable(tp);
5986 static int rtl8156b_enable(struct r8152 *tp)
5991 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5995 rtl_set_eee_plus(tp);
5997 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
5998 ocp_data &= ~RX_AGGR_NUM_MASK;
5999 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6001 r8153_set_rx_early_timeout(tp);
6002 r8153_set_rx_early_size(tp);
6004 speed = rtl8152_get_speed(tp);
6005 rtl_set_ifg(tp, speed);
6007 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6008 if (speed & _2500bps)
6009 ocp_data &= ~IDLE_SPDWN_EN;
6011 ocp_data |= IDLE_SPDWN_EN;
6012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6014 if (tp->udev->speed == USB_SPEED_HIGH) {
6015 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6017 if (is_flow_control(speed))
6021 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6024 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6025 ocp_data &= ~FC_PATCH_TASK;
6026 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6027 usleep_range(1000, 2000);
6028 ocp_data |= FC_PATCH_TASK;
6029 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6031 return rtl_enable(tp);
6034 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6040 if (autoneg == AUTONEG_DISABLE) {
6041 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6046 bmcr = BMCR_SPEED10;
6047 if (duplex == DUPLEX_FULL) {
6048 bmcr |= BMCR_FULLDPLX;
6049 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6051 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6055 bmcr = BMCR_SPEED100;
6056 if (duplex == DUPLEX_FULL) {
6057 bmcr |= BMCR_FULLDPLX;
6058 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6060 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6064 if (tp->mii.supports_gmii) {
6065 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6066 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6075 if (duplex == DUPLEX_FULL)
6076 tp->mii.full_duplex = 1;
6078 tp->mii.full_duplex = 0;
6080 tp->mii.force_media = 1;
6085 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6086 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6088 if (tp->mii.supports_gmii) {
6089 support |= RTL_ADVERTISED_1000_FULL;
6091 if (tp->support_2500full)
6092 support |= RTL_ADVERTISED_2500_FULL;
6095 if (!(advertising & support))
6098 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6099 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6100 ADVERTISE_100HALF | ADVERTISE_100FULL);
6101 if (advertising & RTL_ADVERTISED_10_HALF) {
6102 new1 |= ADVERTISE_10HALF;
6103 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6105 if (advertising & RTL_ADVERTISED_10_FULL) {
6106 new1 |= ADVERTISE_10FULL;
6107 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6110 if (advertising & RTL_ADVERTISED_100_HALF) {
6111 new1 |= ADVERTISE_100HALF;
6112 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6114 if (advertising & RTL_ADVERTISED_100_FULL) {
6115 new1 |= ADVERTISE_100FULL;
6116 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6120 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6121 tp->mii.advertising = new1;
6124 if (tp->mii.supports_gmii) {
6125 orig = r8152_mdio_read(tp, MII_CTRL1000);
6126 new1 = orig & ~(ADVERTISE_1000FULL |
6127 ADVERTISE_1000HALF);
6129 if (advertising & RTL_ADVERTISED_1000_FULL) {
6130 new1 |= ADVERTISE_1000FULL;
6131 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6135 r8152_mdio_write(tp, MII_CTRL1000, new1);
6138 if (tp->support_2500full) {
6139 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6140 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6142 if (advertising & RTL_ADVERTISED_2500_FULL) {
6143 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6144 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6148 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6151 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6153 tp->mii.force_media = 0;
6156 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6159 r8152_mdio_write(tp, MII_BMCR, bmcr);
6161 if (bmcr & BMCR_RESET) {
6164 for (i = 0; i < 50; i++) {
6166 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6175 static void rtl8152_up(struct r8152 *tp)
6177 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6180 r8152_aldps_en(tp, false);
6181 r8152b_exit_oob(tp);
6182 r8152_aldps_en(tp, true);
6185 static void rtl8152_down(struct r8152 *tp)
6187 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6188 rtl_drop_queued_tx(tp);
6192 r8152_power_cut_en(tp, false);
6193 r8152_aldps_en(tp, false);
6194 r8152b_enter_oob(tp);
6195 r8152_aldps_en(tp, true);
6198 static void rtl8153_up(struct r8152 *tp)
6202 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6205 r8153_u1u2en(tp, false);
6206 r8153_u2p3en(tp, false);
6207 r8153_aldps_en(tp, false);
6208 r8153_first_init(tp);
6210 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6211 ocp_data |= LANWAKE_CLR_EN;
6212 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6214 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6215 ocp_data &= ~LANWAKE_PIN;
6216 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6218 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6219 ocp_data &= ~DELAY_PHY_PWR_CHG;
6220 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6222 r8153_aldps_en(tp, true);
6224 switch (tp->version) {
6231 r8153_u2p3en(tp, true);
6235 r8153_u1u2en(tp, true);
6238 static void rtl8153_down(struct r8152 *tp)
6242 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6243 rtl_drop_queued_tx(tp);
6247 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6248 ocp_data &= ~LANWAKE_CLR_EN;
6249 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6251 r8153_u1u2en(tp, false);
6252 r8153_u2p3en(tp, false);
6253 r8153_power_cut_en(tp, false);
6254 r8153_aldps_en(tp, false);
6255 r8153_enter_oob(tp);
6256 r8153_aldps_en(tp, true);
6259 static void rtl8153b_up(struct r8152 *tp)
6263 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6266 r8153b_u1u2en(tp, false);
6267 r8153_u2p3en(tp, false);
6268 r8153_aldps_en(tp, false);
6270 r8153_first_init(tp);
6271 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6274 ocp_data &= ~PLA_MCU_SPDWN_EN;
6275 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6277 r8153_aldps_en(tp, true);
6279 if (tp->udev->speed >= USB_SPEED_SUPER)
6280 r8153b_u1u2en(tp, true);
6283 static void rtl8153b_down(struct r8152 *tp)
6287 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6288 rtl_drop_queued_tx(tp);
6292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6293 ocp_data |= PLA_MCU_SPDWN_EN;
6294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6296 r8153b_u1u2en(tp, false);
6297 r8153_u2p3en(tp, false);
6298 r8153b_power_cut_en(tp, false);
6299 r8153_aldps_en(tp, false);
6300 r8153_enter_oob(tp);
6301 r8153_aldps_en(tp, true);
6304 static void rtl8153c_change_mtu(struct r8152 *tp)
6306 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6307 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6311 /* Adjust the tx fifo free credit full threshold, otherwise
6312 * the fifo would be too small to send a jumbo frame packet.
6314 if (tp->netdev->mtu < 8000)
6315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6320 static void rtl8153c_up(struct r8152 *tp)
6324 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6327 r8153b_u1u2en(tp, false);
6328 r8153_u2p3en(tp, false);
6329 r8153_aldps_en(tp, false);
6331 rxdy_gated_en(tp, true);
6332 r8153_teredo_off(tp);
6334 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6335 ocp_data &= ~RCR_ACPT_ALL;
6336 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6338 rtl8152_nic_reset(tp);
6341 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6342 ocp_data &= ~NOW_IS_OOB;
6343 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6345 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6346 ocp_data &= ~MCU_BORW_EN;
6347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6349 wait_oob_link_list_ready(tp);
6351 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6352 ocp_data |= RE_INIT_LL;
6353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6355 wait_oob_link_list_ready(tp);
6357 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6359 rtl8153c_change_mtu(tp);
6361 rtl8152_nic_reset(tp);
6363 /* rx share fifo credit full threshold */
6364 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6365 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6366 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6369 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6371 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6373 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6375 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6377 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6379 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6380 ocp_data &= ~PLA_MCU_SPDWN_EN;
6381 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6383 r8153_aldps_en(tp, true);
6384 r8153b_u1u2en(tp, true);
6387 static inline u32 fc_pause_on_auto(struct r8152 *tp)
6389 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6392 static inline u32 fc_pause_off_auto(struct r8152 *tp)
6394 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6397 static void r8156_fc_parameter(struct r8152 *tp)
6399 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6400 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6402 switch (tp->version) {
6405 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
6406 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
6411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6412 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6419 static void rtl8156_change_mtu(struct r8152 *tp)
6421 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6424 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6425 r8156_fc_parameter(tp);
6427 /* TX share fifo free credit full threshold */
6428 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6429 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6430 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6433 static void rtl8156_up(struct r8152 *tp)
6437 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6440 r8153b_u1u2en(tp, false);
6441 r8153_u2p3en(tp, false);
6442 r8153_aldps_en(tp, false);
6444 rxdy_gated_en(tp, true);
6445 r8153_teredo_off(tp);
6447 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6448 ocp_data &= ~RCR_ACPT_ALL;
6449 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6451 rtl8152_nic_reset(tp);
6454 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6455 ocp_data &= ~NOW_IS_OOB;
6456 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6458 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6459 ocp_data &= ~MCU_BORW_EN;
6460 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6462 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6464 rtl8156_change_mtu(tp);
6466 switch (tp->version) {
6470 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6471 ocp_data |= ACT_ODMA;
6472 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6478 /* share FIFO settings */
6479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6480 ocp_data &= ~RXFIFO_FULL_MASK;
6482 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6484 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6485 ocp_data &= ~PLA_MCU_SPDWN_EN;
6486 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6488 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6489 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6490 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6492 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6494 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6495 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6496 __rtl_set_wol(tp, tp->saved_wolopts);
6499 r8153_aldps_en(tp, true);
6500 r8153_u2p3en(tp, true);
6502 if (tp->udev->speed >= USB_SPEED_SUPER)
6503 r8153b_u1u2en(tp, true);
6506 static void rtl8156_down(struct r8152 *tp)
6510 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6511 rtl_drop_queued_tx(tp);
6515 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6516 ocp_data |= PLA_MCU_SPDWN_EN;
6517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6519 r8153b_u1u2en(tp, false);
6520 r8153_u2p3en(tp, false);
6521 r8153b_power_cut_en(tp, false);
6522 r8153_aldps_en(tp, false);
6524 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6525 ocp_data &= ~NOW_IS_OOB;
6526 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6531 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6532 * type. Set it to zero. bits[7:0] are the W1C bits about
6533 * the events. Set them to all 1 to clear them.
6535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6537 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6538 ocp_data |= NOW_IS_OOB;
6539 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6541 rtl_rx_vlan_en(tp, true);
6542 rxdy_gated_en(tp, false);
6544 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6545 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6546 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6548 r8153_aldps_en(tp, true);
6551 static bool rtl8152_in_nway(struct r8152 *tp)
6555 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6556 tp->ocp_base = 0x2000;
6557 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6558 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6560 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6561 if (nway_state & 0xc000)
6567 static bool rtl8153_in_nway(struct r8152 *tp)
6569 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6571 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6577 static void set_carrier(struct r8152 *tp)
6579 struct net_device *netdev = tp->netdev;
6580 struct napi_struct *napi = &tp->napi;
6583 speed = rtl8152_get_speed(tp);
6585 if (speed & LINK_STATUS) {
6586 if (!netif_carrier_ok(netdev)) {
6587 tp->rtl_ops.enable(tp);
6588 netif_stop_queue(netdev);
6590 netif_carrier_on(netdev);
6592 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6593 _rtl8152_set_rx_mode(netdev);
6595 netif_wake_queue(netdev);
6596 netif_info(tp, link, netdev, "carrier on\n");
6597 } else if (netif_queue_stopped(netdev) &&
6598 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6599 netif_wake_queue(netdev);
6602 if (netif_carrier_ok(netdev)) {
6603 netif_carrier_off(netdev);
6604 tasklet_disable(&tp->tx_tl);
6606 tp->rtl_ops.disable(tp);
6608 tasklet_enable(&tp->tx_tl);
6609 netif_info(tp, link, netdev, "carrier off\n");
6614 static void rtl_work_func_t(struct work_struct *work)
6616 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6618 /* If the device is unplugged or !netif_running(), the workqueue
6619 * doesn't need to wake the device, and could return directly.
6621 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6624 if (usb_autopm_get_interface(tp->intf) < 0)
6627 if (!test_bit(WORK_ENABLE, &tp->flags))
6630 if (!mutex_trylock(&tp->control)) {
6631 schedule_delayed_work(&tp->schedule, 0);
6635 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6638 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6639 _rtl8152_set_rx_mode(tp->netdev);
6641 /* don't schedule tasket before linking */
6642 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6643 netif_carrier_ok(tp->netdev))
6644 tasklet_schedule(&tp->tx_tl);
6646 mutex_unlock(&tp->control);
6649 usb_autopm_put_interface(tp->intf);
6652 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6654 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6656 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6659 if (usb_autopm_get_interface(tp->intf) < 0)
6662 mutex_lock(&tp->control);
6664 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6665 tp->rtl_fw.retry = false;
6666 tp->rtl_fw.fw = NULL;
6668 /* Delay execution in case request_firmware() is not ready yet.
6670 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6674 tp->rtl_ops.hw_phy_cfg(tp);
6676 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6680 mutex_unlock(&tp->control);
6682 usb_autopm_put_interface(tp->intf);
6685 #ifdef CONFIG_PM_SLEEP
6686 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6689 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6692 case PM_HIBERNATION_PREPARE:
6693 case PM_SUSPEND_PREPARE:
6694 usb_autopm_get_interface(tp->intf);
6697 case PM_POST_HIBERNATION:
6698 case PM_POST_SUSPEND:
6699 usb_autopm_put_interface(tp->intf);
6702 case PM_POST_RESTORE:
6703 case PM_RESTORE_PREPARE:
6712 static int rtl8152_open(struct net_device *netdev)
6714 struct r8152 *tp = netdev_priv(netdev);
6717 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6718 cancel_delayed_work_sync(&tp->hw_phy_work);
6719 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6722 res = alloc_all_mem(tp);
6726 res = usb_autopm_get_interface(tp->intf);
6730 mutex_lock(&tp->control);
6734 netif_carrier_off(netdev);
6735 netif_start_queue(netdev);
6736 set_bit(WORK_ENABLE, &tp->flags);
6738 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6741 netif_device_detach(tp->netdev);
6742 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6746 napi_enable(&tp->napi);
6747 tasklet_enable(&tp->tx_tl);
6749 mutex_unlock(&tp->control);
6751 usb_autopm_put_interface(tp->intf);
6752 #ifdef CONFIG_PM_SLEEP
6753 tp->pm_notifier.notifier_call = rtl_notifier;
6754 register_pm_notifier(&tp->pm_notifier);
6759 mutex_unlock(&tp->control);
6760 usb_autopm_put_interface(tp->intf);
6767 static int rtl8152_close(struct net_device *netdev)
6769 struct r8152 *tp = netdev_priv(netdev);
6772 #ifdef CONFIG_PM_SLEEP
6773 unregister_pm_notifier(&tp->pm_notifier);
6775 tasklet_disable(&tp->tx_tl);
6776 clear_bit(WORK_ENABLE, &tp->flags);
6777 usb_kill_urb(tp->intr_urb);
6778 cancel_delayed_work_sync(&tp->schedule);
6779 napi_disable(&tp->napi);
6780 netif_stop_queue(netdev);
6782 res = usb_autopm_get_interface(tp->intf);
6783 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6784 rtl_drop_queued_tx(tp);
6787 mutex_lock(&tp->control);
6789 tp->rtl_ops.down(tp);
6791 mutex_unlock(&tp->control);
6795 usb_autopm_put_interface(tp->intf);
6802 static void rtl_tally_reset(struct r8152 *tp)
6806 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6807 ocp_data |= TALLY_RESET;
6808 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6811 static void r8152b_init(struct r8152 *tp)
6816 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6819 data = r8152_mdio_read(tp, MII_BMCR);
6820 if (data & BMCR_PDOWN) {
6821 data &= ~BMCR_PDOWN;
6822 r8152_mdio_write(tp, MII_BMCR, data);
6825 r8152_aldps_en(tp, false);
6827 if (tp->version == RTL_VER_01) {
6828 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6829 ocp_data &= ~LED_MODE_MASK;
6830 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6833 r8152_power_cut_en(tp, false);
6835 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6836 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6837 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6838 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6839 ocp_data &= ~MCU_CLK_RATIO_MASK;
6840 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6841 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6842 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6843 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6844 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6846 rtl_tally_reset(tp);
6848 /* enable rx aggregation */
6849 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6850 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6851 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6854 static void r8153_init(struct r8152 *tp)
6860 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6863 r8153_u1u2en(tp, false);
6865 for (i = 0; i < 500; i++) {
6866 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6871 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6875 data = r8153_phy_status(tp, 0);
6877 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6878 tp->version == RTL_VER_05)
6879 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6881 data = r8152_mdio_read(tp, MII_BMCR);
6882 if (data & BMCR_PDOWN) {
6883 data &= ~BMCR_PDOWN;
6884 r8152_mdio_write(tp, MII_BMCR, data);
6887 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6889 r8153_u2p3en(tp, false);
6891 if (tp->version == RTL_VER_04) {
6892 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6893 ocp_data &= ~pwd_dn_scale_mask;
6894 ocp_data |= pwd_dn_scale(96);
6895 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6897 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6898 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6899 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6900 } else if (tp->version == RTL_VER_05) {
6901 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6902 ocp_data &= ~ECM_ALDPS;
6903 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6905 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6906 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6907 ocp_data &= ~DYNAMIC_BURST;
6909 ocp_data |= DYNAMIC_BURST;
6910 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6911 } else if (tp->version == RTL_VER_06) {
6912 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6913 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6914 ocp_data &= ~DYNAMIC_BURST;
6916 ocp_data |= DYNAMIC_BURST;
6917 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6919 r8153_queue_wake(tp, false);
6921 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6922 if (rtl8152_get_speed(tp) & LINK_STATUS)
6923 ocp_data |= CUR_LINK_OK;
6925 ocp_data &= ~CUR_LINK_OK;
6926 ocp_data |= POLL_LINK_CHG;
6927 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6930 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6931 ocp_data |= EP4_FULL_FC;
6932 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
6934 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6935 ocp_data &= ~TIMER11_EN;
6936 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
6938 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6939 ocp_data &= ~LED_MODE_MASK;
6940 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6942 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
6943 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
6944 ocp_data |= LPM_TIMER_500MS;
6946 ocp_data |= LPM_TIMER_500US;
6947 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
6949 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
6950 ocp_data &= ~SEN_VAL_MASK;
6951 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
6952 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
6954 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
6956 r8153_power_cut_en(tp, false);
6957 rtl_runtime_suspend_enable(tp, false);
6958 r8153_mac_clk_speed_down(tp, false);
6959 r8153_u1u2en(tp, true);
6960 usb_enable_lpm(tp->udev);
6962 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6963 ocp_data |= LANWAKE_CLR_EN;
6964 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6966 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6967 ocp_data &= ~LANWAKE_PIN;
6968 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6970 /* rx aggregation */
6971 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6972 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6973 if (tp->dell_tb_rx_agg_bug)
6974 ocp_data |= RX_AGG_DISABLE;
6976 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6978 rtl_tally_reset(tp);
6980 switch (tp->udev->speed) {
6981 case USB_SPEED_SUPER:
6982 case USB_SPEED_SUPER_PLUS:
6983 tp->coalesce = COALESCE_SUPER;
6985 case USB_SPEED_HIGH:
6986 tp->coalesce = COALESCE_HIGH;
6989 tp->coalesce = COALESCE_SLOW;
6994 static void r8153b_init(struct r8152 *tp)
7000 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7003 r8153b_u1u2en(tp, false);
7005 for (i = 0; i < 500; i++) {
7006 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7011 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7015 data = r8153_phy_status(tp, 0);
7017 data = r8152_mdio_read(tp, MII_BMCR);
7018 if (data & BMCR_PDOWN) {
7019 data &= ~BMCR_PDOWN;
7020 r8152_mdio_write(tp, MII_BMCR, data);
7023 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7025 r8153_u2p3en(tp, false);
7027 /* MSC timer = 0xfff * 8ms = 32760 ms */
7028 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7030 r8153b_power_cut_en(tp, false);
7031 r8153b_ups_en(tp, false);
7032 r8153_queue_wake(tp, false);
7033 rtl_runtime_suspend_enable(tp, false);
7035 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7036 if (rtl8152_get_speed(tp) & LINK_STATUS)
7037 ocp_data |= CUR_LINK_OK;
7039 ocp_data &= ~CUR_LINK_OK;
7040 ocp_data |= POLL_LINK_CHG;
7041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7043 if (tp->udev->speed >= USB_SPEED_SUPER)
7044 r8153b_u1u2en(tp, true);
7046 usb_enable_lpm(tp->udev);
7048 /* MAC clock speed down */
7049 r8153_mac_clk_speed_down(tp, true);
7051 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7052 ocp_data &= ~PLA_MCU_SPDWN_EN;
7053 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7055 if (tp->version == RTL_VER_09) {
7056 /* Disable Test IO for 32QFN */
7057 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7058 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7059 ocp_data |= TEST_IO_OFF;
7060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7064 set_bit(GREEN_ETHERNET, &tp->flags);
7066 /* rx aggregation */
7067 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7068 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7069 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7071 rtl_tally_reset(tp);
7073 tp->coalesce = 15000; /* 15 us */
7076 static void r8153c_init(struct r8152 *tp)
7082 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7085 r8153b_u1u2en(tp, false);
7087 /* Disable spi_en */
7088 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7089 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7090 ocp_data &= ~BIT(3);
7091 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7092 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7094 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7096 for (i = 0; i < 500; i++) {
7097 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7102 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7106 data = r8153_phy_status(tp, 0);
7108 data = r8152_mdio_read(tp, MII_BMCR);
7109 if (data & BMCR_PDOWN) {
7110 data &= ~BMCR_PDOWN;
7111 r8152_mdio_write(tp, MII_BMCR, data);
7114 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7116 r8153_u2p3en(tp, false);
7118 /* MSC timer = 0xfff * 8ms = 32760 ms */
7119 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7121 r8153b_power_cut_en(tp, false);
7122 r8153c_ups_en(tp, false);
7123 r8153_queue_wake(tp, false);
7124 rtl_runtime_suspend_enable(tp, false);
7126 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7127 if (rtl8152_get_speed(tp) & LINK_STATUS)
7128 ocp_data |= CUR_LINK_OK;
7130 ocp_data &= ~CUR_LINK_OK;
7132 ocp_data |= POLL_LINK_CHG;
7133 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7135 r8153b_u1u2en(tp, true);
7137 usb_enable_lpm(tp->udev);
7139 /* MAC clock speed down */
7140 r8153_mac_clk_speed_down(tp, true);
7142 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7143 ocp_data &= ~BIT(7);
7144 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7146 set_bit(GREEN_ETHERNET, &tp->flags);
7148 /* rx aggregation */
7149 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7150 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7151 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7153 rtl_tally_reset(tp);
7155 tp->coalesce = 15000; /* 15 us */
7158 static void r8156_hw_phy_cfg(struct r8152 *tp)
7163 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7164 if (ocp_data & PCUT_STATUS) {
7165 ocp_data &= ~PCUT_STATUS;
7166 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7169 data = r8153_phy_status(tp, 0);
7171 case PHY_STAT_EXT_INIT:
7172 rtl8152_apply_firmware(tp, true);
7174 data = ocp_reg_read(tp, 0xa468);
7175 data &= ~(BIT(3) | BIT(1));
7176 ocp_reg_write(tp, 0xa468, data);
7178 case PHY_STAT_LAN_ON:
7179 case PHY_STAT_PWRDN:
7181 rtl8152_apply_firmware(tp, false);
7185 /* disable ALDPS before updating the PHY parameters */
7186 r8153_aldps_en(tp, false);
7188 /* disable EEE before updating the PHY parameters */
7189 rtl_eee_enable(tp, false);
7191 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7192 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7194 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7195 ocp_data |= PFM_PWM_SWITCH;
7196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7198 switch (tp->version) {
7200 data = ocp_reg_read(tp, 0xad40);
7202 data |= BIT(7) | BIT(2);
7203 ocp_reg_write(tp, 0xad40, data);
7205 data = ocp_reg_read(tp, 0xad4e);
7207 ocp_reg_write(tp, 0xad4e, data);
7208 data = ocp_reg_read(tp, 0xad16);
7211 ocp_reg_write(tp, 0xad16, data);
7212 data = ocp_reg_read(tp, 0xad32);
7215 ocp_reg_write(tp, 0xad32, data);
7216 data = ocp_reg_read(tp, 0xac08);
7217 data &= ~(BIT(12) | BIT(8));
7218 ocp_reg_write(tp, 0xac08, data);
7219 data = ocp_reg_read(tp, 0xac8a);
7220 data |= BIT(12) | BIT(13) | BIT(14);
7222 ocp_reg_write(tp, 0xac8a, data);
7223 data = ocp_reg_read(tp, 0xad18);
7225 ocp_reg_write(tp, 0xad18, data);
7226 data = ocp_reg_read(tp, 0xad1a);
7228 ocp_reg_write(tp, 0xad1a, data);
7229 data = ocp_reg_read(tp, 0xad1c);
7231 ocp_reg_write(tp, 0xad1c, data);
7233 data = sram_read(tp, 0x80ea);
7236 sram_write(tp, 0x80ea, data);
7237 data = sram_read(tp, 0x80eb);
7240 sram_write(tp, 0x80eb, data);
7241 data = sram_read(tp, 0x80f8);
7244 sram_write(tp, 0x80f8, data);
7245 data = sram_read(tp, 0x80f1);
7248 sram_write(tp, 0x80f1, data);
7250 data = sram_read(tp, 0x80fe);
7253 sram_write(tp, 0x80fe, data);
7254 data = sram_read(tp, 0x8102);
7257 sram_write(tp, 0x8102, data);
7258 data = sram_read(tp, 0x8015);
7261 sram_write(tp, 0x8015, data);
7262 data = sram_read(tp, 0x8100);
7265 sram_write(tp, 0x8100, data);
7266 data = sram_read(tp, 0x8014);
7269 sram_write(tp, 0x8014, data);
7270 data = sram_read(tp, 0x8016);
7273 sram_write(tp, 0x8016, data);
7274 data = sram_read(tp, 0x80dc);
7277 sram_write(tp, 0x80dc, data);
7278 data = sram_read(tp, 0x80df);
7280 sram_write(tp, 0x80df, data);
7281 data = sram_read(tp, 0x80e1);
7283 sram_write(tp, 0x80e1, data);
7285 data = ocp_reg_read(tp, 0xbf06);
7288 ocp_reg_write(tp, 0xbf06, data);
7290 sram_write(tp, 0x819f, 0xddb6);
7292 ocp_reg_write(tp, 0xbc34, 0x5555);
7293 data = ocp_reg_read(tp, 0xbf0a);
7296 ocp_reg_write(tp, 0xbf0a, data);
7298 data = ocp_reg_read(tp, 0xbd2c);
7300 ocp_reg_write(tp, 0xbd2c, data);
7303 data = ocp_reg_read(tp, 0xad16);
7305 ocp_reg_write(tp, 0xad16, data);
7306 data = ocp_reg_read(tp, 0xad32);
7309 ocp_reg_write(tp, 0xad32, data);
7310 data = ocp_reg_read(tp, 0xac08);
7311 data &= ~(BIT(12) | BIT(8));
7312 ocp_reg_write(tp, 0xac08, data);
7313 data = ocp_reg_read(tp, 0xacc0);
7316 ocp_reg_write(tp, 0xacc0, data);
7317 data = ocp_reg_read(tp, 0xad40);
7319 data |= BIT(6) | BIT(2);
7320 ocp_reg_write(tp, 0xad40, data);
7321 data = ocp_reg_read(tp, 0xac14);
7323 ocp_reg_write(tp, 0xac14, data);
7324 data = ocp_reg_read(tp, 0xac80);
7325 data &= ~(BIT(8) | BIT(9));
7326 ocp_reg_write(tp, 0xac80, data);
7327 data = ocp_reg_read(tp, 0xac5e);
7330 ocp_reg_write(tp, 0xac5e, data);
7331 ocp_reg_write(tp, 0xad4c, 0x00a8);
7332 ocp_reg_write(tp, 0xac5c, 0x01ff);
7333 data = ocp_reg_read(tp, 0xac8a);
7335 data |= BIT(4) | BIT(5);
7336 ocp_reg_write(tp, 0xac8a, data);
7337 ocp_reg_write(tp, 0xb87c, 0x8157);
7338 data = ocp_reg_read(tp, 0xb87e);
7341 ocp_reg_write(tp, 0xb87e, data);
7342 ocp_reg_write(tp, 0xb87c, 0x8159);
7343 data = ocp_reg_read(tp, 0xb87e);
7346 ocp_reg_write(tp, 0xb87e, data);
7349 ocp_reg_write(tp, 0xb87c, 0x80a2);
7350 ocp_reg_write(tp, 0xb87e, 0x0153);
7351 ocp_reg_write(tp, 0xb87c, 0x809c);
7352 ocp_reg_write(tp, 0xb87e, 0x0153);
7355 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7357 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7358 ocp_data |= EN_XG_LIP | EN_G_LIP;
7359 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7361 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7362 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7364 if (rtl_phy_patch_request(tp, true, true))
7368 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7369 ocp_data |= EEE_SPDWN_EN;
7370 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7372 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7373 data &= ~(EN_EEE_100 | EN_EEE_1000);
7374 data |= EN_10M_CLKDIV;
7375 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7376 tp->ups_info._10m_ckdiv = true;
7377 tp->ups_info.eee_plloff_100 = false;
7378 tp->ups_info.eee_plloff_giga = false;
7380 data = ocp_reg_read(tp, OCP_POWER_CFG);
7381 data &= ~EEE_CLKDIV_EN;
7382 ocp_reg_write(tp, OCP_POWER_CFG, data);
7383 tp->ups_info.eee_ckdiv = false;
7385 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7386 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7387 tp->ups_info._250m_ckdiv = false;
7389 rtl_phy_patch_request(tp, false, true);
7391 /* enable ADC Ibias Cal */
7392 data = ocp_reg_read(tp, 0xd068);
7394 ocp_reg_write(tp, 0xd068, data);
7396 /* enable Thermal Sensor */
7397 data = sram_read(tp, 0x81a2);
7399 sram_write(tp, 0x81a2, data);
7400 data = ocp_reg_read(tp, 0xb54c);
7403 ocp_reg_write(tp, 0xb54c, data);
7405 /* Nway 2.5G Lite */
7406 data = ocp_reg_read(tp, 0xa454);
7408 ocp_reg_write(tp, 0xa454, data);
7410 /* CS DSP solution */
7411 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7412 data |= RTL_ADV2_5G_F_R;
7413 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7414 data = ocp_reg_read(tp, 0xad4e);
7416 ocp_reg_write(tp, 0xad4e, data);
7417 data = ocp_reg_read(tp, 0xa86a);
7419 ocp_reg_write(tp, 0xa86a, data);
7422 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7423 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7426 data = ocp_reg_read(tp, 0xd068);
7428 data |= 0x1; /* p0 */
7429 ocp_reg_write(tp, 0xd068, data);
7430 swap_a = ocp_reg_read(tp, 0xd06a);
7432 data |= 0x18; /* p3 */
7433 ocp_reg_write(tp, 0xd068, data);
7434 swap_b = ocp_reg_read(tp, 0xd06a);
7435 data &= ~0x18; /* p0 */
7436 ocp_reg_write(tp, 0xd068, data);
7437 ocp_reg_write(tp, 0xd06a,
7438 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7439 data |= 0x18; /* p3 */
7440 ocp_reg_write(tp, 0xd068, data);
7441 ocp_reg_write(tp, 0xd06a,
7442 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7444 data |= 0x08; /* p1 */
7445 ocp_reg_write(tp, 0xd068, data);
7446 swap_a = ocp_reg_read(tp, 0xd06a);
7448 data |= 0x10; /* p2 */
7449 ocp_reg_write(tp, 0xd068, data);
7450 swap_b = ocp_reg_read(tp, 0xd06a);
7452 data |= 0x08; /* p1 */
7453 ocp_reg_write(tp, 0xd068, data);
7454 ocp_reg_write(tp, 0xd06a,
7455 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7457 data |= 0x10; /* p2 */
7458 ocp_reg_write(tp, 0xd068, data);
7459 ocp_reg_write(tp, 0xd06a,
7460 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7461 swap_a = ocp_reg_read(tp, 0xbd5a);
7462 swap_b = ocp_reg_read(tp, 0xbd5c);
7463 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7464 ((swap_b & 0x1f) << 8) |
7465 ((swap_b >> 8) & 0x1f));
7466 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7467 ((swap_a & 0x1f) << 8) |
7468 ((swap_a >> 8) & 0x1f));
7469 swap_a = ocp_reg_read(tp, 0xbc18);
7470 swap_b = ocp_reg_read(tp, 0xbc1a);
7471 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7472 ((swap_b & 0x1f) << 8) |
7473 ((swap_b >> 8) & 0x1f));
7474 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7475 ((swap_a & 0x1f) << 8) |
7476 ((swap_a >> 8) & 0x1f));
7483 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7485 data = ocp_reg_read(tp, 0xa428);
7487 ocp_reg_write(tp, 0xa428, data);
7488 data = ocp_reg_read(tp, 0xa5ea);
7490 ocp_reg_write(tp, 0xa5ea, data);
7491 tp->ups_info.lite_mode = 0;
7494 rtl_eee_enable(tp, true);
7496 r8153_aldps_en(tp, true);
7497 r8152b_enable_fc(tp);
7498 r8153_u2p3en(tp, true);
7500 set_bit(PHY_RESET, &tp->flags);
7503 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7508 switch (tp->version) {
7510 ocp_reg_write(tp, 0xbf86, 0x9000);
7511 data = ocp_reg_read(tp, 0xc402);
7513 ocp_reg_write(tp, 0xc402, data);
7515 ocp_reg_write(tp, 0xc402, data);
7516 ocp_reg_write(tp, 0xbd86, 0x1010);
7517 ocp_reg_write(tp, 0xbd88, 0x1010);
7518 data = ocp_reg_read(tp, 0xbd4e);
7519 data &= ~(BIT(10) | BIT(11));
7521 ocp_reg_write(tp, 0xbd4e, data);
7522 data = ocp_reg_read(tp, 0xbf46);
7525 ocp_reg_write(tp, 0xbf46, data);
7529 r8156b_wait_loading_flash(tp);
7535 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7536 if (ocp_data & PCUT_STATUS) {
7537 ocp_data &= ~PCUT_STATUS;
7538 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7541 data = r8153_phy_status(tp, 0);
7543 case PHY_STAT_EXT_INIT:
7544 rtl8152_apply_firmware(tp, true);
7546 data = ocp_reg_read(tp, 0xa466);
7548 ocp_reg_write(tp, 0xa466, data);
7550 data = ocp_reg_read(tp, 0xa468);
7551 data &= ~(BIT(3) | BIT(1));
7552 ocp_reg_write(tp, 0xa468, data);
7554 case PHY_STAT_LAN_ON:
7555 case PHY_STAT_PWRDN:
7557 rtl8152_apply_firmware(tp, false);
7561 data = r8152_mdio_read(tp, MII_BMCR);
7562 if (data & BMCR_PDOWN) {
7563 data &= ~BMCR_PDOWN;
7564 r8152_mdio_write(tp, MII_BMCR, data);
7567 /* disable ALDPS before updating the PHY parameters */
7568 r8153_aldps_en(tp, false);
7570 /* disable EEE before updating the PHY parameters */
7571 rtl_eee_enable(tp, false);
7573 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7574 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7576 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7577 ocp_data |= PFM_PWM_SWITCH;
7578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7580 switch (tp->version) {
7582 data = ocp_reg_read(tp, 0xbc08);
7583 data |= BIT(3) | BIT(2);
7584 ocp_reg_write(tp, 0xbc08, data);
7586 data = sram_read(tp, 0x8fff);
7589 sram_write(tp, 0x8fff, data);
7591 data = ocp_reg_read(tp, 0xacda);
7593 ocp_reg_write(tp, 0xacda, data);
7594 data = ocp_reg_read(tp, 0xacde);
7596 ocp_reg_write(tp, 0xacde, data);
7597 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7598 ocp_reg_write(tp, 0xac46, 0xb7b4);
7599 ocp_reg_write(tp, 0xac50, 0x0fbc);
7600 ocp_reg_write(tp, 0xac3c, 0x9240);
7601 ocp_reg_write(tp, 0xac4e, 0x0db4);
7602 ocp_reg_write(tp, 0xacc6, 0x0707);
7603 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7604 ocp_reg_write(tp, 0xad08, 0x0007);
7606 ocp_reg_write(tp, 0xb87c, 0x8560);
7607 ocp_reg_write(tp, 0xb87e, 0x19cc);
7608 ocp_reg_write(tp, 0xb87c, 0x8562);
7609 ocp_reg_write(tp, 0xb87e, 0x19cc);
7610 ocp_reg_write(tp, 0xb87c, 0x8564);
7611 ocp_reg_write(tp, 0xb87e, 0x19cc);
7612 ocp_reg_write(tp, 0xb87c, 0x8566);
7613 ocp_reg_write(tp, 0xb87e, 0x147d);
7614 ocp_reg_write(tp, 0xb87c, 0x8568);
7615 ocp_reg_write(tp, 0xb87e, 0x147d);
7616 ocp_reg_write(tp, 0xb87c, 0x856a);
7617 ocp_reg_write(tp, 0xb87e, 0x147d);
7618 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7619 ocp_reg_write(tp, 0xb87e, 0x0907);
7620 ocp_reg_write(tp, 0xb87c, 0x80d6);
7621 ocp_reg_write(tp, 0xb87e, 0x2801);
7622 ocp_reg_write(tp, 0xb87c, 0x80f2);
7623 ocp_reg_write(tp, 0xb87e, 0x2801);
7624 ocp_reg_write(tp, 0xb87c, 0x80f4);
7625 ocp_reg_write(tp, 0xb87e, 0x6077);
7626 ocp_reg_write(tp, 0xb506, 0x01e7);
7628 ocp_reg_write(tp, 0xb87c, 0x8013);
7629 ocp_reg_write(tp, 0xb87e, 0x0700);
7630 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7631 ocp_reg_write(tp, 0xb87e, 0x2801);
7632 ocp_reg_write(tp, 0xb87c, 0x8fba);
7633 ocp_reg_write(tp, 0xb87e, 0x0100);
7634 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7635 ocp_reg_write(tp, 0xb87e, 0x1900);
7636 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7637 ocp_reg_write(tp, 0xb87e, 0xe100);
7638 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7639 ocp_reg_write(tp, 0xb87e, 0x0800);
7640 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7641 ocp_reg_write(tp, 0xb87e, 0xe500);
7642 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7643 ocp_reg_write(tp, 0xb87e, 0x0f00);
7644 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7645 ocp_reg_write(tp, 0xb87e, 0xf100);
7646 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7647 ocp_reg_write(tp, 0xb87e, 0x0400);
7648 ocp_reg_write(tp, 0xb87c, 0x8fca);
7649 ocp_reg_write(tp, 0xb87e, 0xf300);
7650 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7651 ocp_reg_write(tp, 0xb87e, 0xfd00);
7652 ocp_reg_write(tp, 0xb87c, 0x8fce);
7653 ocp_reg_write(tp, 0xb87e, 0xff00);
7654 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7655 ocp_reg_write(tp, 0xb87e, 0xfb00);
7656 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7657 ocp_reg_write(tp, 0xb87e, 0x0100);
7658 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7659 ocp_reg_write(tp, 0xb87e, 0xf400);
7660 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7661 ocp_reg_write(tp, 0xb87e, 0xff00);
7662 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7663 ocp_reg_write(tp, 0xb87e, 0xf600);
7665 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7666 ocp_data |= EN_XG_LIP | EN_G_LIP;
7667 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7668 ocp_reg_write(tp, 0xb87c, 0x813d);
7669 ocp_reg_write(tp, 0xb87e, 0x390e);
7670 ocp_reg_write(tp, 0xb87c, 0x814f);
7671 ocp_reg_write(tp, 0xb87e, 0x790e);
7672 ocp_reg_write(tp, 0xb87c, 0x80b0);
7673 ocp_reg_write(tp, 0xb87e, 0x0f31);
7674 data = ocp_reg_read(tp, 0xbf4c);
7676 ocp_reg_write(tp, 0xbf4c, data);
7677 data = ocp_reg_read(tp, 0xbcca);
7678 data |= BIT(9) | BIT(8);
7679 ocp_reg_write(tp, 0xbcca, data);
7680 ocp_reg_write(tp, 0xb87c, 0x8141);
7681 ocp_reg_write(tp, 0xb87e, 0x320e);
7682 ocp_reg_write(tp, 0xb87c, 0x8153);
7683 ocp_reg_write(tp, 0xb87e, 0x720e);
7684 ocp_reg_write(tp, 0xb87c, 0x8529);
7685 ocp_reg_write(tp, 0xb87e, 0x050e);
7686 data = ocp_reg_read(tp, OCP_EEE_CFG);
7687 data &= ~CTAP_SHORT_EN;
7688 ocp_reg_write(tp, OCP_EEE_CFG, data);
7690 sram_write(tp, 0x816c, 0xc4a0);
7691 sram_write(tp, 0x8170, 0xc4a0);
7692 sram_write(tp, 0x8174, 0x04a0);
7693 sram_write(tp, 0x8178, 0x04a0);
7694 sram_write(tp, 0x817c, 0x0719);
7695 sram_write(tp, 0x8ff4, 0x0400);
7696 sram_write(tp, 0x8ff1, 0x0404);
7698 ocp_reg_write(tp, 0xbf4a, 0x001b);
7699 ocp_reg_write(tp, 0xb87c, 0x8033);
7700 ocp_reg_write(tp, 0xb87e, 0x7c13);
7701 ocp_reg_write(tp, 0xb87c, 0x8037);
7702 ocp_reg_write(tp, 0xb87e, 0x7c13);
7703 ocp_reg_write(tp, 0xb87c, 0x803b);
7704 ocp_reg_write(tp, 0xb87e, 0xfc32);
7705 ocp_reg_write(tp, 0xb87c, 0x803f);
7706 ocp_reg_write(tp, 0xb87e, 0x7c13);
7707 ocp_reg_write(tp, 0xb87c, 0x8043);
7708 ocp_reg_write(tp, 0xb87e, 0x7c13);
7709 ocp_reg_write(tp, 0xb87c, 0x8047);
7710 ocp_reg_write(tp, 0xb87e, 0x7c13);
7712 ocp_reg_write(tp, 0xb87c, 0x8145);
7713 ocp_reg_write(tp, 0xb87e, 0x370e);
7714 ocp_reg_write(tp, 0xb87c, 0x8157);
7715 ocp_reg_write(tp, 0xb87e, 0x770e);
7716 ocp_reg_write(tp, 0xb87c, 0x8169);
7717 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7718 ocp_reg_write(tp, 0xb87c, 0x817b);
7719 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7721 data = sram_read(tp, 0x8217);
7724 sram_write(tp, 0x8217, data);
7725 data = sram_read(tp, 0x821a);
7728 sram_write(tp, 0x821a, data);
7729 sram_write(tp, 0x80da, 0x0403);
7730 data = sram_read(tp, 0x80dc);
7733 sram_write(tp, 0x80dc, data);
7734 sram_write(tp, 0x80b3, 0x0384);
7735 sram_write(tp, 0x80b7, 0x2007);
7736 data = sram_read(tp, 0x80ba);
7739 sram_write(tp, 0x80ba, data);
7740 sram_write(tp, 0x80b5, 0xf009);
7741 data = sram_read(tp, 0x80bd);
7744 sram_write(tp, 0x80bd, data);
7745 sram_write(tp, 0x80c7, 0xf083);
7746 sram_write(tp, 0x80dd, 0x03f0);
7747 data = sram_read(tp, 0x80df);
7750 sram_write(tp, 0x80df, data);
7751 sram_write(tp, 0x80cb, 0x2007);
7752 data = sram_read(tp, 0x80ce);
7755 sram_write(tp, 0x80ce, data);
7756 sram_write(tp, 0x80c9, 0x8009);
7757 data = sram_read(tp, 0x80d1);
7760 sram_write(tp, 0x80d1, data);
7761 sram_write(tp, 0x80a3, 0x200a);
7762 sram_write(tp, 0x80a5, 0xf0ad);
7763 sram_write(tp, 0x809f, 0x6073);
7764 sram_write(tp, 0x80a1, 0x000b);
7765 data = sram_read(tp, 0x80a9);
7768 sram_write(tp, 0x80a9, data);
7770 if (rtl_phy_patch_request(tp, true, true))
7773 data = ocp_reg_read(tp, 0xb896);
7775 ocp_reg_write(tp, 0xb896, data);
7776 data = ocp_reg_read(tp, 0xb892);
7778 ocp_reg_write(tp, 0xb892, data);
7779 ocp_reg_write(tp, 0xb88e, 0xc23e);
7780 ocp_reg_write(tp, 0xb890, 0x0000);
7781 ocp_reg_write(tp, 0xb88e, 0xc240);
7782 ocp_reg_write(tp, 0xb890, 0x0103);
7783 ocp_reg_write(tp, 0xb88e, 0xc242);
7784 ocp_reg_write(tp, 0xb890, 0x0507);
7785 ocp_reg_write(tp, 0xb88e, 0xc244);
7786 ocp_reg_write(tp, 0xb890, 0x090b);
7787 ocp_reg_write(tp, 0xb88e, 0xc246);
7788 ocp_reg_write(tp, 0xb890, 0x0c0e);
7789 ocp_reg_write(tp, 0xb88e, 0xc248);
7790 ocp_reg_write(tp, 0xb890, 0x1012);
7791 ocp_reg_write(tp, 0xb88e, 0xc24a);
7792 ocp_reg_write(tp, 0xb890, 0x1416);
7793 data = ocp_reg_read(tp, 0xb896);
7795 ocp_reg_write(tp, 0xb896, data);
7797 rtl_phy_patch_request(tp, false, true);
7799 data = ocp_reg_read(tp, 0xa86a);
7801 ocp_reg_write(tp, 0xa86a, data);
7802 data = ocp_reg_read(tp, 0xa6f0);
7804 ocp_reg_write(tp, 0xa6f0, data);
7806 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7807 ocp_reg_write(tp, 0xbfa2, 0x4100);
7808 ocp_reg_write(tp, 0xbfa4, 0xe868);
7809 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7810 ocp_reg_write(tp, 0xb54c, 0x3c18);
7811 data = ocp_reg_read(tp, 0xbfa4);
7813 ocp_reg_write(tp, 0xbfa4, data);
7814 data = sram_read(tp, 0x817d);
7816 sram_write(tp, 0x817d, data);
7820 data = ocp_reg_read(tp, 0xac46);
7823 ocp_reg_write(tp, 0xac46, data);
7824 data = ocp_reg_read(tp, 0xad30);
7827 ocp_reg_write(tp, 0xad30, data);
7831 ocp_reg_write(tp, 0xb87c, 0x80f5);
7832 ocp_reg_write(tp, 0xb87e, 0x760e);
7833 ocp_reg_write(tp, 0xb87c, 0x8107);
7834 ocp_reg_write(tp, 0xb87e, 0x360e);
7835 ocp_reg_write(tp, 0xb87c, 0x8551);
7836 data = ocp_reg_read(tp, 0xb87e);
7839 ocp_reg_write(tp, 0xb87e, data);
7841 /* ADC_PGA parameter */
7842 data = ocp_reg_read(tp, 0xbf00);
7845 ocp_reg_write(tp, 0xbf00, data);
7846 data = ocp_reg_read(tp, 0xbf46);
7849 ocp_reg_write(tp, 0xbf46, data);
7851 /* Green Table-PGA, 1G full viterbi */
7852 sram_write(tp, 0x8044, 0x2417);
7853 sram_write(tp, 0x804a, 0x2417);
7854 sram_write(tp, 0x8050, 0x2417);
7855 sram_write(tp, 0x8056, 0x2417);
7856 sram_write(tp, 0x805c, 0x2417);
7857 sram_write(tp, 0x8062, 0x2417);
7858 sram_write(tp, 0x8068, 0x2417);
7859 sram_write(tp, 0x806e, 0x2417);
7860 sram_write(tp, 0x8074, 0x2417);
7861 sram_write(tp, 0x807a, 0x2417);
7864 data = ocp_reg_read(tp, 0xbf84);
7867 ocp_reg_write(tp, 0xbf84, data);
7873 if (rtl_phy_patch_request(tp, true, true))
7876 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7877 ocp_data |= EEE_SPDWN_EN;
7878 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7880 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7881 data &= ~(EN_EEE_100 | EN_EEE_1000);
7882 data |= EN_10M_CLKDIV;
7883 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7884 tp->ups_info._10m_ckdiv = true;
7885 tp->ups_info.eee_plloff_100 = false;
7886 tp->ups_info.eee_plloff_giga = false;
7888 data = ocp_reg_read(tp, OCP_POWER_CFG);
7889 data &= ~EEE_CLKDIV_EN;
7890 ocp_reg_write(tp, OCP_POWER_CFG, data);
7891 tp->ups_info.eee_ckdiv = false;
7893 rtl_phy_patch_request(tp, false, true);
7895 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7897 data = ocp_reg_read(tp, 0xa428);
7899 ocp_reg_write(tp, 0xa428, data);
7900 data = ocp_reg_read(tp, 0xa5ea);
7902 ocp_reg_write(tp, 0xa5ea, data);
7903 tp->ups_info.lite_mode = 0;
7906 rtl_eee_enable(tp, true);
7908 r8153_aldps_en(tp, true);
7909 r8152b_enable_fc(tp);
7910 r8153_u2p3en(tp, true);
7912 set_bit(PHY_RESET, &tp->flags);
7915 static void r8156_init(struct r8152 *tp)
7921 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7924 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7925 ocp_data &= ~EN_ALL_SPEED;
7926 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7928 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7930 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7931 ocp_data |= BYPASS_MAC_RESET;
7932 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7934 r8153b_u1u2en(tp, false);
7936 for (i = 0; i < 500; i++) {
7937 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7942 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7946 data = r8153_phy_status(tp, 0);
7947 if (data == PHY_STAT_EXT_INIT) {
7948 data = ocp_reg_read(tp, 0xa468);
7949 data &= ~(BIT(3) | BIT(1));
7950 ocp_reg_write(tp, 0xa468, data);
7953 data = r8152_mdio_read(tp, MII_BMCR);
7954 if (data & BMCR_PDOWN) {
7955 data &= ~BMCR_PDOWN;
7956 r8152_mdio_write(tp, MII_BMCR, data);
7959 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7960 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7962 r8153_u2p3en(tp, false);
7964 /* MSC timer = 0xfff * 8ms = 32760 ms */
7965 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7967 /* U1/U2/L1 idle timer. 500 us */
7968 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
7970 r8153b_power_cut_en(tp, false);
7971 r8156_ups_en(tp, false);
7972 r8153_queue_wake(tp, false);
7973 rtl_runtime_suspend_enable(tp, false);
7975 if (tp->udev->speed >= USB_SPEED_SUPER)
7976 r8153b_u1u2en(tp, true);
7978 usb_enable_lpm(tp->udev);
7980 r8156_mac_clk_spd(tp, true);
7982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7983 ocp_data &= ~PLA_MCU_SPDWN_EN;
7984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7987 if (rtl8152_get_speed(tp) & LINK_STATUS)
7988 ocp_data |= CUR_LINK_OK;
7990 ocp_data &= ~CUR_LINK_OK;
7991 ocp_data |= POLL_LINK_CHG;
7992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7994 set_bit(GREEN_ETHERNET, &tp->flags);
7996 /* rx aggregation */
7997 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7998 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7999 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8001 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8002 ocp_data |= ACT_ODMA;
8003 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8005 rtl_tally_reset(tp);
8007 tp->coalesce = 15000; /* 15 us */
8010 static void r8156b_init(struct r8152 *tp)
8016 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8019 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8020 ocp_data &= ~EN_ALL_SPEED;
8021 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8023 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8025 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8026 ocp_data |= BYPASS_MAC_RESET;
8027 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8029 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8030 ocp_data |= RX_DETECT8;
8031 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8033 r8153b_u1u2en(tp, false);
8035 switch (tp->version) {
8038 r8156b_wait_loading_flash(tp);
8044 for (i = 0; i < 500; i++) {
8045 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8050 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8054 data = r8153_phy_status(tp, 0);
8055 if (data == PHY_STAT_EXT_INIT) {
8056 data = ocp_reg_read(tp, 0xa468);
8057 data &= ~(BIT(3) | BIT(1));
8058 ocp_reg_write(tp, 0xa468, data);
8060 data = ocp_reg_read(tp, 0xa466);
8062 ocp_reg_write(tp, 0xa466, data);
8065 data = r8152_mdio_read(tp, MII_BMCR);
8066 if (data & BMCR_PDOWN) {
8067 data &= ~BMCR_PDOWN;
8068 r8152_mdio_write(tp, MII_BMCR, data);
8071 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8073 r8153_u2p3en(tp, false);
8075 /* MSC timer = 0xfff * 8ms = 32760 ms */
8076 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8078 /* U1/U2/L1 idle timer. 500 us */
8079 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8081 r8153b_power_cut_en(tp, false);
8082 r8156_ups_en(tp, false);
8083 r8153_queue_wake(tp, false);
8084 rtl_runtime_suspend_enable(tp, false);
8086 if (tp->udev->speed >= USB_SPEED_SUPER)
8087 r8153b_u1u2en(tp, true);
8089 usb_enable_lpm(tp->udev);
8091 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8092 ocp_data &= ~SLOT_EN;
8093 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8095 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8096 ocp_data |= FLOW_CTRL_EN;
8097 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8099 /* enable fc timer and set timer to 600 ms. */
8100 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8101 CTRL_TIMER_EN | (600 / 8));
8103 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8104 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8105 ocp_data |= FLOW_CTRL_PATCH_2;
8106 ocp_data &= ~AUTO_SPEEDUP;
8107 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8109 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8110 ocp_data |= FC_PATCH_TASK;
8111 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8113 r8156_mac_clk_spd(tp, true);
8115 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8116 ocp_data &= ~PLA_MCU_SPDWN_EN;
8117 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8119 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8120 if (rtl8152_get_speed(tp) & LINK_STATUS)
8121 ocp_data |= CUR_LINK_OK;
8123 ocp_data &= ~CUR_LINK_OK;
8124 ocp_data |= POLL_LINK_CHG;
8125 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8127 set_bit(GREEN_ETHERNET, &tp->flags);
8129 /* rx aggregation */
8130 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8131 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8132 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8134 rtl_tally_reset(tp);
8136 tp->coalesce = 15000; /* 15 us */
8139 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8141 struct usb_host_interface *alt = intf->cur_altsetting;
8142 struct usb_endpoint_descriptor *in, *out, *intr;
8144 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8145 dev_err(&intf->dev, "Expected endpoints are not found\n");
8149 /* Check Rx endpoint address */
8150 if (usb_endpoint_num(in) != 1) {
8151 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8155 /* Check Tx endpoint address */
8156 if (usb_endpoint_num(out) != 2) {
8157 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8161 /* Check interrupt endpoint address */
8162 if (usb_endpoint_num(intr) != 3) {
8163 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8170 static bool rtl_vendor_mode(struct usb_interface *intf)
8172 struct usb_host_interface *alt = intf->cur_altsetting;
8173 struct usb_device *udev;
8174 struct usb_host_config *c;
8177 if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
8178 return rtl_check_vendor_ok(intf);
8180 /* The vendor mode is not always config #1, so to find it out. */
8181 udev = interface_to_usbdev(intf);
8183 num_configs = udev->descriptor.bNumConfigurations;
8184 if (num_configs < 2)
8187 for (i = 0; i < num_configs; (i++, c++)) {
8188 struct usb_interface_descriptor *desc = NULL;
8190 if (c->desc.bNumInterfaces > 0)
8191 desc = &c->intf_cache[0]->altsetting->desc;
8195 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
8196 usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
8201 if (i == num_configs)
8202 dev_err(&intf->dev, "Unexpected Device\n");
8207 static int rtl8152_pre_reset(struct usb_interface *intf)
8209 struct r8152 *tp = usb_get_intfdata(intf);
8210 struct net_device *netdev;
8215 netdev = tp->netdev;
8216 if (!netif_running(netdev))
8219 netif_stop_queue(netdev);
8220 tasklet_disable(&tp->tx_tl);
8221 clear_bit(WORK_ENABLE, &tp->flags);
8222 usb_kill_urb(tp->intr_urb);
8223 cancel_delayed_work_sync(&tp->schedule);
8224 napi_disable(&tp->napi);
8225 if (netif_carrier_ok(netdev)) {
8226 mutex_lock(&tp->control);
8227 tp->rtl_ops.disable(tp);
8228 mutex_unlock(&tp->control);
8234 static int rtl8152_post_reset(struct usb_interface *intf)
8236 struct r8152 *tp = usb_get_intfdata(intf);
8237 struct net_device *netdev;
8243 /* reset the MAC address in case of policy change */
8244 if (determine_ethernet_addr(tp, &sa) >= 0) {
8246 dev_set_mac_address (tp->netdev, &sa, NULL);
8250 netdev = tp->netdev;
8251 if (!netif_running(netdev))
8254 set_bit(WORK_ENABLE, &tp->flags);
8255 if (netif_carrier_ok(netdev)) {
8256 mutex_lock(&tp->control);
8257 tp->rtl_ops.enable(tp);
8259 _rtl8152_set_rx_mode(netdev);
8260 mutex_unlock(&tp->control);
8263 napi_enable(&tp->napi);
8264 tasklet_enable(&tp->tx_tl);
8265 netif_wake_queue(netdev);
8266 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8268 if (!list_empty(&tp->rx_done))
8269 napi_schedule(&tp->napi);
8274 static bool delay_autosuspend(struct r8152 *tp)
8276 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8277 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8279 /* This means a linking change occurs and the driver doesn't detect it,
8280 * yet. If the driver has disabled tx/rx and hw is linking on, the
8281 * device wouldn't wake up by receiving any packet.
8283 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8286 /* If the linking down is occurred by nway, the device may miss the
8287 * linking change event. And it wouldn't wake when linking on.
8289 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8291 else if (!skb_queue_empty(&tp->tx_queue))
8297 static int rtl8152_runtime_resume(struct r8152 *tp)
8299 struct net_device *netdev = tp->netdev;
8301 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8302 struct napi_struct *napi = &tp->napi;
8304 tp->rtl_ops.autosuspend_en(tp, false);
8306 set_bit(WORK_ENABLE, &tp->flags);
8308 if (netif_carrier_ok(netdev)) {
8309 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8312 netif_carrier_off(netdev);
8313 tp->rtl_ops.disable(tp);
8314 netif_info(tp, link, netdev, "linking down\n");
8319 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8320 smp_mb__after_atomic();
8322 if (!list_empty(&tp->rx_done))
8323 napi_schedule(&tp->napi);
8325 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8327 if (netdev->flags & IFF_UP)
8328 tp->rtl_ops.autosuspend_en(tp, false);
8330 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8336 static int rtl8152_system_resume(struct r8152 *tp)
8338 struct net_device *netdev = tp->netdev;
8340 netif_device_attach(netdev);
8342 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8344 netif_carrier_off(netdev);
8345 set_bit(WORK_ENABLE, &tp->flags);
8346 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8352 static int rtl8152_runtime_suspend(struct r8152 *tp)
8354 struct net_device *netdev = tp->netdev;
8357 if (!tp->rtl_ops.autosuspend_en)
8360 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8361 smp_mb__after_atomic();
8363 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8366 if (netif_carrier_ok(netdev)) {
8369 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8370 ocp_data = rcr & ~RCR_ACPT_ALL;
8371 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8372 rxdy_gated_en(tp, true);
8373 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8375 if (!(ocp_data & RXFIFO_EMPTY)) {
8376 rxdy_gated_en(tp, false);
8377 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8378 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8379 smp_mb__after_atomic();
8385 clear_bit(WORK_ENABLE, &tp->flags);
8386 usb_kill_urb(tp->intr_urb);
8388 tp->rtl_ops.autosuspend_en(tp, true);
8390 if (netif_carrier_ok(netdev)) {
8391 struct napi_struct *napi = &tp->napi;
8395 rxdy_gated_en(tp, false);
8396 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8400 if (delay_autosuspend(tp)) {
8401 rtl8152_runtime_resume(tp);
8410 static int rtl8152_system_suspend(struct r8152 *tp)
8412 struct net_device *netdev = tp->netdev;
8414 netif_device_detach(netdev);
8416 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8417 struct napi_struct *napi = &tp->napi;
8419 clear_bit(WORK_ENABLE, &tp->flags);
8420 usb_kill_urb(tp->intr_urb);
8421 tasklet_disable(&tp->tx_tl);
8423 cancel_delayed_work_sync(&tp->schedule);
8424 tp->rtl_ops.down(tp);
8426 tasklet_enable(&tp->tx_tl);
8432 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8434 struct r8152 *tp = usb_get_intfdata(intf);
8437 mutex_lock(&tp->control);
8439 if (PMSG_IS_AUTO(message))
8440 ret = rtl8152_runtime_suspend(tp);
8442 ret = rtl8152_system_suspend(tp);
8444 mutex_unlock(&tp->control);
8449 static int rtl8152_resume(struct usb_interface *intf)
8451 struct r8152 *tp = usb_get_intfdata(intf);
8454 mutex_lock(&tp->control);
8456 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8457 ret = rtl8152_runtime_resume(tp);
8459 ret = rtl8152_system_resume(tp);
8461 mutex_unlock(&tp->control);
8466 static int rtl8152_reset_resume(struct usb_interface *intf)
8468 struct r8152 *tp = usb_get_intfdata(intf);
8470 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8471 tp->rtl_ops.init(tp);
8472 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8473 set_ethernet_addr(tp, true);
8474 return rtl8152_resume(intf);
8477 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8479 struct r8152 *tp = netdev_priv(dev);
8481 if (usb_autopm_get_interface(tp->intf) < 0)
8484 if (!rtl_can_wakeup(tp)) {
8488 mutex_lock(&tp->control);
8489 wol->supported = WAKE_ANY;
8490 wol->wolopts = __rtl_get_wol(tp);
8491 mutex_unlock(&tp->control);
8494 usb_autopm_put_interface(tp->intf);
8497 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8499 struct r8152 *tp = netdev_priv(dev);
8502 if (!rtl_can_wakeup(tp))
8505 if (wol->wolopts & ~WAKE_ANY)
8508 ret = usb_autopm_get_interface(tp->intf);
8512 mutex_lock(&tp->control);
8514 __rtl_set_wol(tp, wol->wolopts);
8515 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8517 mutex_unlock(&tp->control);
8519 usb_autopm_put_interface(tp->intf);
8525 static u32 rtl8152_get_msglevel(struct net_device *dev)
8527 struct r8152 *tp = netdev_priv(dev);
8529 return tp->msg_enable;
8532 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8534 struct r8152 *tp = netdev_priv(dev);
8536 tp->msg_enable = value;
8539 static void rtl8152_get_drvinfo(struct net_device *netdev,
8540 struct ethtool_drvinfo *info)
8542 struct r8152 *tp = netdev_priv(netdev);
8544 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
8545 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
8546 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8547 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8548 strlcpy(info->fw_version, tp->rtl_fw.version,
8549 sizeof(info->fw_version));
8553 int rtl8152_get_link_ksettings(struct net_device *netdev,
8554 struct ethtool_link_ksettings *cmd)
8556 struct r8152 *tp = netdev_priv(netdev);
8559 if (!tp->mii.mdio_read)
8562 ret = usb_autopm_get_interface(tp->intf);
8566 mutex_lock(&tp->control);
8568 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8570 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8571 cmd->link_modes.supported, tp->support_2500full);
8573 if (tp->support_2500full) {
8574 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8575 cmd->link_modes.advertising,
8576 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8578 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8579 cmd->link_modes.lp_advertising,
8580 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8582 if (is_speed_2500(rtl8152_get_speed(tp)))
8583 cmd->base.speed = SPEED_2500;
8586 mutex_unlock(&tp->control);
8588 usb_autopm_put_interface(tp->intf);
8594 static int rtl8152_set_link_ksettings(struct net_device *dev,
8595 const struct ethtool_link_ksettings *cmd)
8597 struct r8152 *tp = netdev_priv(dev);
8598 u32 advertising = 0;
8601 ret = usb_autopm_get_interface(tp->intf);
8605 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8606 cmd->link_modes.advertising))
8607 advertising |= RTL_ADVERTISED_10_HALF;
8609 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8610 cmd->link_modes.advertising))
8611 advertising |= RTL_ADVERTISED_10_FULL;
8613 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8614 cmd->link_modes.advertising))
8615 advertising |= RTL_ADVERTISED_100_HALF;
8617 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8618 cmd->link_modes.advertising))
8619 advertising |= RTL_ADVERTISED_100_FULL;
8621 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8622 cmd->link_modes.advertising))
8623 advertising |= RTL_ADVERTISED_1000_HALF;
8625 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8626 cmd->link_modes.advertising))
8627 advertising |= RTL_ADVERTISED_1000_FULL;
8629 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8630 cmd->link_modes.advertising))
8631 advertising |= RTL_ADVERTISED_2500_FULL;
8633 mutex_lock(&tp->control);
8635 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8636 cmd->base.duplex, advertising);
8638 tp->autoneg = cmd->base.autoneg;
8639 tp->speed = cmd->base.speed;
8640 tp->duplex = cmd->base.duplex;
8641 tp->advertising = advertising;
8644 mutex_unlock(&tp->control);
8646 usb_autopm_put_interface(tp->intf);
8652 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8659 "tx_single_collisions",
8660 "tx_multi_collisions",
8668 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8672 return ARRAY_SIZE(rtl8152_gstrings);
8678 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8679 struct ethtool_stats *stats, u64 *data)
8681 struct r8152 *tp = netdev_priv(dev);
8682 struct tally_counter tally;
8684 if (usb_autopm_get_interface(tp->intf) < 0)
8687 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8689 usb_autopm_put_interface(tp->intf);
8691 data[0] = le64_to_cpu(tally.tx_packets);
8692 data[1] = le64_to_cpu(tally.rx_packets);
8693 data[2] = le64_to_cpu(tally.tx_errors);
8694 data[3] = le32_to_cpu(tally.rx_errors);
8695 data[4] = le16_to_cpu(tally.rx_missed);
8696 data[5] = le16_to_cpu(tally.align_errors);
8697 data[6] = le32_to_cpu(tally.tx_one_collision);
8698 data[7] = le32_to_cpu(tally.tx_multi_collision);
8699 data[8] = le64_to_cpu(tally.rx_unicast);
8700 data[9] = le64_to_cpu(tally.rx_broadcast);
8701 data[10] = le32_to_cpu(tally.rx_multicast);
8702 data[11] = le16_to_cpu(tally.tx_aborted);
8703 data[12] = le16_to_cpu(tally.tx_underrun);
8706 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8708 switch (stringset) {
8710 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8715 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8717 u32 lp, adv, supported = 0;
8720 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8721 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8723 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8724 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8726 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8727 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8729 eee->eee_enabled = tp->eee_en;
8730 eee->eee_active = !!(supported & adv & lp);
8731 eee->supported = supported;
8732 eee->advertised = tp->eee_adv;
8733 eee->lp_advertised = lp;
8738 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8740 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8742 tp->eee_en = eee->eee_enabled;
8745 rtl_eee_enable(tp, tp->eee_en);
8750 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8752 u32 lp, adv, supported = 0;
8755 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8756 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8758 val = ocp_reg_read(tp, OCP_EEE_ADV);
8759 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8761 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8762 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8764 eee->eee_enabled = tp->eee_en;
8765 eee->eee_active = !!(supported & adv & lp);
8766 eee->supported = supported;
8767 eee->advertised = tp->eee_adv;
8768 eee->lp_advertised = lp;
8774 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8776 struct r8152 *tp = netdev_priv(net);
8779 if (!tp->rtl_ops.eee_get) {
8784 ret = usb_autopm_get_interface(tp->intf);
8788 mutex_lock(&tp->control);
8790 ret = tp->rtl_ops.eee_get(tp, edata);
8792 mutex_unlock(&tp->control);
8794 usb_autopm_put_interface(tp->intf);
8801 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8803 struct r8152 *tp = netdev_priv(net);
8806 if (!tp->rtl_ops.eee_set) {
8811 ret = usb_autopm_get_interface(tp->intf);
8815 mutex_lock(&tp->control);
8817 ret = tp->rtl_ops.eee_set(tp, edata);
8819 ret = mii_nway_restart(&tp->mii);
8821 mutex_unlock(&tp->control);
8823 usb_autopm_put_interface(tp->intf);
8829 static int rtl8152_nway_reset(struct net_device *dev)
8831 struct r8152 *tp = netdev_priv(dev);
8834 ret = usb_autopm_get_interface(tp->intf);
8838 mutex_lock(&tp->control);
8840 ret = mii_nway_restart(&tp->mii);
8842 mutex_unlock(&tp->control);
8844 usb_autopm_put_interface(tp->intf);
8850 static int rtl8152_get_coalesce(struct net_device *netdev,
8851 struct ethtool_coalesce *coalesce)
8853 struct r8152 *tp = netdev_priv(netdev);
8855 switch (tp->version) {
8864 coalesce->rx_coalesce_usecs = tp->coalesce;
8869 static int rtl8152_set_coalesce(struct net_device *netdev,
8870 struct ethtool_coalesce *coalesce)
8872 struct r8152 *tp = netdev_priv(netdev);
8875 switch (tp->version) {
8884 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8887 ret = usb_autopm_get_interface(tp->intf);
8891 mutex_lock(&tp->control);
8893 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8894 tp->coalesce = coalesce->rx_coalesce_usecs;
8896 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8897 netif_stop_queue(netdev);
8898 napi_disable(&tp->napi);
8899 tp->rtl_ops.disable(tp);
8900 tp->rtl_ops.enable(tp);
8902 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8903 _rtl8152_set_rx_mode(netdev);
8904 napi_enable(&tp->napi);
8905 netif_wake_queue(netdev);
8909 mutex_unlock(&tp->control);
8911 usb_autopm_put_interface(tp->intf);
8916 static int rtl8152_get_tunable(struct net_device *netdev,
8917 const struct ethtool_tunable *tunable, void *d)
8919 struct r8152 *tp = netdev_priv(netdev);
8921 switch (tunable->id) {
8922 case ETHTOOL_RX_COPYBREAK:
8923 *(u32 *)d = tp->rx_copybreak;
8932 static int rtl8152_set_tunable(struct net_device *netdev,
8933 const struct ethtool_tunable *tunable,
8936 struct r8152 *tp = netdev_priv(netdev);
8939 switch (tunable->id) {
8940 case ETHTOOL_RX_COPYBREAK:
8942 if (val < ETH_ZLEN) {
8943 netif_err(tp, rx_err, netdev,
8944 "Invalid rx copy break value\n");
8948 if (tp->rx_copybreak != val) {
8949 if (netdev->flags & IFF_UP) {
8950 mutex_lock(&tp->control);
8951 napi_disable(&tp->napi);
8952 tp->rx_copybreak = val;
8953 napi_enable(&tp->napi);
8954 mutex_unlock(&tp->control);
8956 tp->rx_copybreak = val;
8967 static void rtl8152_get_ringparam(struct net_device *netdev,
8968 struct ethtool_ringparam *ring)
8970 struct r8152 *tp = netdev_priv(netdev);
8972 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
8973 ring->rx_pending = tp->rx_pending;
8976 static int rtl8152_set_ringparam(struct net_device *netdev,
8977 struct ethtool_ringparam *ring)
8979 struct r8152 *tp = netdev_priv(netdev);
8981 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
8984 if (tp->rx_pending != ring->rx_pending) {
8985 if (netdev->flags & IFF_UP) {
8986 mutex_lock(&tp->control);
8987 napi_disable(&tp->napi);
8988 tp->rx_pending = ring->rx_pending;
8989 napi_enable(&tp->napi);
8990 mutex_unlock(&tp->control);
8992 tp->rx_pending = ring->rx_pending;
8999 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9001 struct r8152 *tp = netdev_priv(netdev);
9002 u16 bmcr, lcladv, rmtadv;
9005 if (usb_autopm_get_interface(tp->intf) < 0)
9008 mutex_lock(&tp->control);
9010 bmcr = r8152_mdio_read(tp, MII_BMCR);
9011 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9012 rmtadv = r8152_mdio_read(tp, MII_LPA);
9014 mutex_unlock(&tp->control);
9016 usb_autopm_put_interface(tp->intf);
9018 if (!(bmcr & BMCR_ANENABLE)) {
9020 pause->rx_pause = 0;
9021 pause->tx_pause = 0;
9027 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9029 if (cap & FLOW_CTRL_RX)
9030 pause->rx_pause = 1;
9032 if (cap & FLOW_CTRL_TX)
9033 pause->tx_pause = 1;
9036 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9038 struct r8152 *tp = netdev_priv(netdev);
9043 ret = usb_autopm_get_interface(tp->intf);
9047 mutex_lock(&tp->control);
9049 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9054 if (pause->rx_pause)
9055 cap |= FLOW_CTRL_RX;
9057 if (pause->tx_pause)
9058 cap |= FLOW_CTRL_TX;
9060 old = r8152_mdio_read(tp, MII_ADVERTISE);
9061 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9063 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9066 mutex_unlock(&tp->control);
9067 usb_autopm_put_interface(tp->intf);
9072 static const struct ethtool_ops ops = {
9073 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9074 .get_drvinfo = rtl8152_get_drvinfo,
9075 .get_link = ethtool_op_get_link,
9076 .nway_reset = rtl8152_nway_reset,
9077 .get_msglevel = rtl8152_get_msglevel,
9078 .set_msglevel = rtl8152_set_msglevel,
9079 .get_wol = rtl8152_get_wol,
9080 .set_wol = rtl8152_set_wol,
9081 .get_strings = rtl8152_get_strings,
9082 .get_sset_count = rtl8152_get_sset_count,
9083 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9084 .get_coalesce = rtl8152_get_coalesce,
9085 .set_coalesce = rtl8152_set_coalesce,
9086 .get_eee = rtl_ethtool_get_eee,
9087 .set_eee = rtl_ethtool_set_eee,
9088 .get_link_ksettings = rtl8152_get_link_ksettings,
9089 .set_link_ksettings = rtl8152_set_link_ksettings,
9090 .get_tunable = rtl8152_get_tunable,
9091 .set_tunable = rtl8152_set_tunable,
9092 .get_ringparam = rtl8152_get_ringparam,
9093 .set_ringparam = rtl8152_set_ringparam,
9094 .get_pauseparam = rtl8152_get_pauseparam,
9095 .set_pauseparam = rtl8152_set_pauseparam,
9098 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9100 struct r8152 *tp = netdev_priv(netdev);
9101 struct mii_ioctl_data *data = if_mii(rq);
9104 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9107 res = usb_autopm_get_interface(tp->intf);
9113 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9117 mutex_lock(&tp->control);
9118 data->val_out = r8152_mdio_read(tp, data->reg_num);
9119 mutex_unlock(&tp->control);
9123 if (!capable(CAP_NET_ADMIN)) {
9127 mutex_lock(&tp->control);
9128 r8152_mdio_write(tp, data->reg_num, data->val_in);
9129 mutex_unlock(&tp->control);
9136 usb_autopm_put_interface(tp->intf);
9142 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9144 struct r8152 *tp = netdev_priv(dev);
9147 switch (tp->version) {
9157 ret = usb_autopm_get_interface(tp->intf);
9161 mutex_lock(&tp->control);
9165 if (netif_running(dev)) {
9166 if (tp->rtl_ops.change_mtu)
9167 tp->rtl_ops.change_mtu(tp);
9169 if (netif_carrier_ok(dev)) {
9170 netif_stop_queue(dev);
9171 napi_disable(&tp->napi);
9172 tasklet_disable(&tp->tx_tl);
9173 tp->rtl_ops.disable(tp);
9174 tp->rtl_ops.enable(tp);
9176 tasklet_enable(&tp->tx_tl);
9177 napi_enable(&tp->napi);
9178 rtl8152_set_rx_mode(dev);
9179 netif_wake_queue(dev);
9183 mutex_unlock(&tp->control);
9185 usb_autopm_put_interface(tp->intf);
9190 static const struct net_device_ops rtl8152_netdev_ops = {
9191 .ndo_open = rtl8152_open,
9192 .ndo_stop = rtl8152_close,
9193 .ndo_do_ioctl = rtl8152_ioctl,
9194 .ndo_start_xmit = rtl8152_start_xmit,
9195 .ndo_tx_timeout = rtl8152_tx_timeout,
9196 .ndo_set_features = rtl8152_set_features,
9197 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9198 .ndo_set_mac_address = rtl8152_set_mac_address,
9199 .ndo_change_mtu = rtl8152_change_mtu,
9200 .ndo_validate_addr = eth_validate_addr,
9201 .ndo_features_check = rtl8152_features_check,
9204 static void rtl8152_unload(struct r8152 *tp)
9206 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9209 if (tp->version != RTL_VER_01)
9210 r8152_power_cut_en(tp, true);
9213 static void rtl8153_unload(struct r8152 *tp)
9215 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9218 r8153_power_cut_en(tp, false);
9221 static void rtl8153b_unload(struct r8152 *tp)
9223 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9226 r8153b_power_cut_en(tp, false);
9229 static int rtl_ops_init(struct r8152 *tp)
9231 struct rtl_ops *ops = &tp->rtl_ops;
9234 switch (tp->version) {
9238 ops->init = r8152b_init;
9239 ops->enable = rtl8152_enable;
9240 ops->disable = rtl8152_disable;
9241 ops->up = rtl8152_up;
9242 ops->down = rtl8152_down;
9243 ops->unload = rtl8152_unload;
9244 ops->eee_get = r8152_get_eee;
9245 ops->eee_set = r8152_set_eee;
9246 ops->in_nway = rtl8152_in_nway;
9247 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9248 ops->autosuspend_en = rtl_runtime_suspend_enable;
9249 tp->rx_buf_sz = 16 * 1024;
9251 tp->eee_adv = MDIO_EEE_100TX;
9258 ops->init = r8153_init;
9259 ops->enable = rtl8153_enable;
9260 ops->disable = rtl8153_disable;
9261 ops->up = rtl8153_up;
9262 ops->down = rtl8153_down;
9263 ops->unload = rtl8153_unload;
9264 ops->eee_get = r8153_get_eee;
9265 ops->eee_set = r8152_set_eee;
9266 ops->in_nway = rtl8153_in_nway;
9267 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9268 ops->autosuspend_en = rtl8153_runtime_enable;
9269 ops->change_mtu = rtl8153_change_mtu;
9270 if (tp->udev->speed < USB_SPEED_SUPER)
9271 tp->rx_buf_sz = 16 * 1024;
9273 tp->rx_buf_sz = 32 * 1024;
9275 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9280 ops->init = r8153b_init;
9281 ops->enable = rtl8153_enable;
9282 ops->disable = rtl8153_disable;
9283 ops->up = rtl8153b_up;
9284 ops->down = rtl8153b_down;
9285 ops->unload = rtl8153b_unload;
9286 ops->eee_get = r8153_get_eee;
9287 ops->eee_set = r8152_set_eee;
9288 ops->in_nway = rtl8153_in_nway;
9289 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9290 ops->autosuspend_en = rtl8153b_runtime_enable;
9291 ops->change_mtu = rtl8153_change_mtu;
9292 tp->rx_buf_sz = 32 * 1024;
9294 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9299 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9302 ops->init = r8156_init;
9303 ops->enable = rtl8156_enable;
9304 ops->disable = rtl8153_disable;
9305 ops->up = rtl8156_up;
9306 ops->down = rtl8156_down;
9307 ops->unload = rtl8153_unload;
9308 ops->eee_get = r8153_get_eee;
9309 ops->eee_set = r8152_set_eee;
9310 ops->in_nway = rtl8153_in_nway;
9311 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9312 ops->autosuspend_en = rtl8156_runtime_enable;
9313 ops->change_mtu = rtl8156_change_mtu;
9314 tp->rx_buf_sz = 48 * 1024;
9315 tp->support_2500full = 1;
9320 tp->support_2500full = 1;
9324 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9325 ops->init = r8156b_init;
9326 ops->enable = rtl8156b_enable;
9327 ops->disable = rtl8153_disable;
9328 ops->up = rtl8156_up;
9329 ops->down = rtl8156_down;
9330 ops->unload = rtl8153_unload;
9331 ops->eee_get = r8153_get_eee;
9332 ops->eee_set = r8152_set_eee;
9333 ops->in_nway = rtl8153_in_nway;
9334 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9335 ops->autosuspend_en = rtl8156_runtime_enable;
9336 ops->change_mtu = rtl8156_change_mtu;
9337 tp->rx_buf_sz = 48 * 1024;
9341 ops->init = r8153c_init;
9342 ops->enable = rtl8153_enable;
9343 ops->disable = rtl8153_disable;
9344 ops->up = rtl8153c_up;
9345 ops->down = rtl8153b_down;
9346 ops->unload = rtl8153_unload;
9347 ops->eee_get = r8153_get_eee;
9348 ops->eee_set = r8152_set_eee;
9349 ops->in_nway = rtl8153_in_nway;
9350 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9351 ops->autosuspend_en = rtl8153c_runtime_enable;
9352 ops->change_mtu = rtl8153c_change_mtu;
9353 tp->rx_buf_sz = 32 * 1024;
9355 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9360 dev_err(&tp->intf->dev, "Unknown Device\n");
9367 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9368 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9369 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9370 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9371 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9372 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9373 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9375 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9376 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9377 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9378 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9379 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9380 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9381 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9383 static int rtl_fw_init(struct r8152 *tp)
9385 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9387 switch (tp->version) {
9389 rtl_fw->fw_name = FIRMWARE_8153A_2;
9390 rtl_fw->pre_fw = r8153_pre_firmware_1;
9391 rtl_fw->post_fw = r8153_post_firmware_1;
9394 rtl_fw->fw_name = FIRMWARE_8153A_3;
9395 rtl_fw->pre_fw = r8153_pre_firmware_2;
9396 rtl_fw->post_fw = r8153_post_firmware_2;
9399 rtl_fw->fw_name = FIRMWARE_8153A_4;
9400 rtl_fw->post_fw = r8153_post_firmware_3;
9403 rtl_fw->fw_name = FIRMWARE_8153B_2;
9404 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9405 rtl_fw->post_fw = r8153b_post_firmware_1;
9408 rtl_fw->fw_name = FIRMWARE_8156A_2;
9409 rtl_fw->post_fw = r8156a_post_firmware_1;
9413 rtl_fw->fw_name = FIRMWARE_8156B_2;
9416 rtl_fw->fw_name = FIRMWARE_8153C_1;
9417 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9418 rtl_fw->post_fw = r8153c_post_firmware_1;
9427 u8 rtl8152_get_version(struct usb_interface *intf)
9429 struct usb_device *udev = interface_to_usbdev(intf);
9435 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9439 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9440 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9441 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9443 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9449 version = RTL_VER_01;
9452 version = RTL_VER_02;
9455 version = RTL_VER_03;
9458 version = RTL_VER_04;
9461 version = RTL_VER_05;
9464 version = RTL_VER_06;
9467 version = RTL_VER_07;
9470 version = RTL_VER_08;
9473 version = RTL_VER_09;
9476 version = RTL_TEST_01;
9479 version = RTL_VER_10;
9482 version = RTL_VER_11;
9485 version = RTL_VER_12;
9488 version = RTL_VER_13;
9491 version = RTL_VER_14;
9494 version = RTL_VER_15;
9497 version = RTL_VER_UNKNOWN;
9498 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
9502 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9506 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9508 static int rtl8152_probe(struct usb_interface *intf,
9509 const struct usb_device_id *id)
9511 struct usb_device *udev = interface_to_usbdev(intf);
9512 u8 version = rtl8152_get_version(intf);
9514 struct net_device *netdev;
9517 if (version == RTL_VER_UNKNOWN)
9520 if (!rtl_vendor_mode(intf))
9523 usb_reset_device(udev);
9524 netdev = alloc_etherdev(sizeof(struct r8152));
9526 dev_err(&intf->dev, "Out of memory\n");
9530 SET_NETDEV_DEV(netdev, &intf->dev);
9531 tp = netdev_priv(netdev);
9532 tp->msg_enable = 0x7FFF;
9535 tp->netdev = netdev;
9537 tp->version = version;
9539 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9540 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9541 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9542 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9543 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9549 tp->mii.supports_gmii = 0;
9552 tp->mii.supports_gmii = 1;
9556 ret = rtl_ops_init(tp);
9562 mutex_init(&tp->control);
9563 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9564 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9565 tasklet_setup(&tp->tx_tl, bottom_half);
9566 tasklet_disable(&tp->tx_tl);
9568 netdev->netdev_ops = &rtl8152_netdev_ops;
9569 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9571 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9572 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9573 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9574 NETIF_F_HW_VLAN_CTAG_TX;
9575 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9576 NETIF_F_TSO | NETIF_F_FRAGLIST |
9577 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9578 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9579 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9580 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9581 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9583 if (tp->version == RTL_VER_01) {
9584 netdev->features &= ~NETIF_F_RXCSUM;
9585 netdev->hw_features &= ~NETIF_F_RXCSUM;
9588 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
9589 switch (le16_to_cpu(udev->descriptor.idProduct)) {
9590 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9591 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9592 tp->lenovo_macpassthru = 1;
9596 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9597 (!strcmp(udev->serial, "000001000000") ||
9598 !strcmp(udev->serial, "000002000000"))) {
9599 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9600 tp->dell_tb_rx_agg_bug = 1;
9603 netdev->ethtool_ops = &ops;
9604 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9606 /* MTU range: 68 - 1500 or 9194 */
9607 netdev->min_mtu = ETH_MIN_MTU;
9608 switch (tp->version) {
9616 netdev->max_mtu = size_to_mtu(9 * 1024);
9620 netdev->max_mtu = size_to_mtu(15 * 1024);
9625 netdev->max_mtu = size_to_mtu(16 * 1024);
9631 netdev->max_mtu = ETH_DATA_LEN;
9635 tp->mii.dev = netdev;
9636 tp->mii.mdio_read = read_mii_word;
9637 tp->mii.mdio_write = write_mii_word;
9638 tp->mii.phy_id_mask = 0x3f;
9639 tp->mii.reg_num_mask = 0x1f;
9640 tp->mii.phy_id = R8152_PHY_ID;
9642 tp->autoneg = AUTONEG_ENABLE;
9643 tp->speed = SPEED_100;
9644 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9645 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9646 if (tp->mii.supports_gmii) {
9647 if (tp->support_2500full &&
9648 tp->udev->speed >= USB_SPEED_SUPER) {
9649 tp->speed = SPEED_2500;
9650 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9652 tp->speed = SPEED_1000;
9654 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9656 tp->duplex = DUPLEX_FULL;
9658 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9659 tp->rx_pending = 10 * RTL8152_MAX_RX;
9661 intf->needs_remote_wakeup = 1;
9663 if (!rtl_can_wakeup(tp))
9664 __rtl_set_wol(tp, 0);
9666 tp->saved_wolopts = __rtl_get_wol(tp);
9668 tp->rtl_ops.init(tp);
9669 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9670 /* Retry in case request_firmware() is not ready yet. */
9671 tp->rtl_fw.retry = true;
9673 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9674 set_ethernet_addr(tp, false);
9676 usb_set_intfdata(intf, tp);
9678 if (tp->support_2500full)
9679 netif_napi_add(netdev, &tp->napi, r8152_poll, 256);
9681 netif_napi_add(netdev, &tp->napi, r8152_poll, 64);
9683 ret = register_netdev(netdev);
9685 dev_err(&intf->dev, "couldn't register the device\n");
9689 if (tp->saved_wolopts)
9690 device_set_wakeup_enable(&udev->dev, true);
9692 device_set_wakeup_enable(&udev->dev, false);
9694 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9699 tasklet_kill(&tp->tx_tl);
9700 usb_set_intfdata(intf, NULL);
9702 free_netdev(netdev);
9706 static void rtl8152_disconnect(struct usb_interface *intf)
9708 struct r8152 *tp = usb_get_intfdata(intf);
9710 usb_set_intfdata(intf, NULL);
9714 unregister_netdev(tp->netdev);
9715 tasklet_kill(&tp->tx_tl);
9716 cancel_delayed_work_sync(&tp->hw_phy_work);
9717 if (tp->rtl_ops.unload)
9718 tp->rtl_ops.unload(tp);
9719 rtl8152_release_firmware(tp);
9720 free_netdev(tp->netdev);
9724 #define REALTEK_USB_DEVICE(vend, prod) { \
9725 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9728 USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9729 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9732 /* table of devices that work with this driver */
9733 static const struct usb_device_id rtl8152_table[] = {
9735 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9736 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9737 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9738 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9739 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9740 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9743 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9744 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9745 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9746 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9747 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
9748 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
9749 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
9750 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
9751 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
9752 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
9753 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
9754 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
9755 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
9756 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9757 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
9758 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),
9762 MODULE_DEVICE_TABLE(usb, rtl8152_table);
9764 static struct usb_driver rtl8152_driver = {
9766 .id_table = rtl8152_table,
9767 .probe = rtl8152_probe,
9768 .disconnect = rtl8152_disconnect,
9769 .suspend = rtl8152_suspend,
9770 .resume = rtl8152_resume,
9771 .reset_resume = rtl8152_reset_resume,
9772 .pre_reset = rtl8152_pre_reset,
9773 .post_reset = rtl8152_post_reset,
9774 .supports_autosuspend = 1,
9775 .disable_hub_initiated_lpm = 1,
9778 module_usb_driver(rtl8152_driver);
9780 MODULE_AUTHOR(DRIVER_AUTHOR);
9781 MODULE_DESCRIPTION(DRIVER_DESC);
9782 MODULE_LICENSE("GPL");
9783 MODULE_VERSION(DRIVER_VERSION);