Merge branch 'tegra/dt64' into arm/fixes
[linux-2.6-microblaze.git] / drivers / net / usb / r8152.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "11"
33
34 /* Information for net */
35 #define NET_VERSION             "11"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PLA_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_UPHY_TIMER          0xd388
61 #define PLA_SUSPEND_FLAG        0xd38a
62 #define PLA_INDICATE_FALG       0xd38c
63 #define PLA_MACDBG_PRE          0xd38c  /* RTL_VER_04 only */
64 #define PLA_MACDBG_POST         0xd38e  /* RTL_VER_04 only */
65 #define PLA_EXTRA_STATUS        0xd398
66 #define PLA_EFUSE_DATA          0xdd00
67 #define PLA_EFUSE_CMD           0xdd02
68 #define PLA_LEDSEL              0xdd90
69 #define PLA_LED_FEATURE         0xdd92
70 #define PLA_PHYAR               0xde00
71 #define PLA_BOOT_CTRL           0xe004
72 #define PLA_LWAKE_CTRL_REG      0xe007
73 #define PLA_GPHY_INTR_IMR       0xe022
74 #define PLA_EEE_CR              0xe040
75 #define PLA_EEEP_CR             0xe080
76 #define PLA_MAC_PWR_CTRL        0xe0c0
77 #define PLA_MAC_PWR_CTRL2       0xe0ca
78 #define PLA_MAC_PWR_CTRL3       0xe0cc
79 #define PLA_MAC_PWR_CTRL4       0xe0ce
80 #define PLA_WDT6_CTRL           0xe428
81 #define PLA_TCR0                0xe610
82 #define PLA_TCR1                0xe612
83 #define PLA_MTPS                0xe615
84 #define PLA_TXFIFO_CTRL         0xe618
85 #define PLA_RSTTALLY            0xe800
86 #define PLA_CR                  0xe813
87 #define PLA_CRWECR              0xe81c
88 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
89 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
90 #define PLA_CONFIG5             0xe822
91 #define PLA_PHY_PWR             0xe84c
92 #define PLA_OOB_CTRL            0xe84f
93 #define PLA_CPCR                0xe854
94 #define PLA_MISC_0              0xe858
95 #define PLA_MISC_1              0xe85a
96 #define PLA_OCP_GPHY_BASE       0xe86c
97 #define PLA_TALLYCNT            0xe890
98 #define PLA_SFF_STS_7           0xe8de
99 #define PLA_PHYSTATUS           0xe908
100 #define PLA_CONFIG6             0xe90a /* CONFIG6 */
101 #define PLA_BP_BA               0xfc26
102 #define PLA_BP_0                0xfc28
103 #define PLA_BP_1                0xfc2a
104 #define PLA_BP_2                0xfc2c
105 #define PLA_BP_3                0xfc2e
106 #define PLA_BP_4                0xfc30
107 #define PLA_BP_5                0xfc32
108 #define PLA_BP_6                0xfc34
109 #define PLA_BP_7                0xfc36
110 #define PLA_BP_EN               0xfc38
111
112 #define USB_USB2PHY             0xb41e
113 #define USB_SSPHYLINK1          0xb426
114 #define USB_SSPHYLINK2          0xb428
115 #define USB_U2P3_CTRL           0xb460
116 #define USB_CSR_DUMMY1          0xb464
117 #define USB_CSR_DUMMY2          0xb466
118 #define USB_DEV_STAT            0xb808
119 #define USB_CONNECT_TIMER       0xcbf8
120 #define USB_MSC_TIMER           0xcbfc
121 #define USB_BURST_SIZE          0xcfc0
122 #define USB_FW_FIX_EN0          0xcfca
123 #define USB_FW_FIX_EN1          0xcfcc
124 #define USB_LPM_CONFIG          0xcfd8
125 #define USB_CSTMR               0xcfef  /* RTL8153A */
126 #define USB_FW_CTRL             0xd334  /* RTL8153B */
127 #define USB_FC_TIMER            0xd340
128 #define USB_USB_CTRL            0xd406
129 #define USB_PHY_CTRL            0xd408
130 #define USB_TX_AGG              0xd40a
131 #define USB_RX_BUF_TH           0xd40c
132 #define USB_USB_TIMER           0xd428
133 #define USB_RX_EARLY_TIMEOUT    0xd42c
134 #define USB_RX_EARLY_SIZE       0xd42e
135 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
136 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
137 #define USB_TX_DMA              0xd434
138 #define USB_UPT_RXDMA_OWN       0xd437
139 #define USB_TOLERANCE           0xd490
140 #define USB_LPM_CTRL            0xd41a
141 #define USB_BMU_RESET           0xd4b0
142 #define USB_U1U2_TIMER          0xd4da
143 #define USB_FW_TASK             0xd4e8  /* RTL8153B */
144 #define USB_UPS_CTRL            0xd800
145 #define USB_POWER_CUT           0xd80a
146 #define USB_MISC_0              0xd81a
147 #define USB_MISC_1              0xd81f
148 #define USB_AFE_CTRL2           0xd824
149 #define USB_UPS_CFG             0xd842
150 #define USB_UPS_FLAGS           0xd848
151 #define USB_WDT1_CTRL           0xe404
152 #define USB_WDT11_CTRL          0xe43c
153 #define USB_BP_BA               PLA_BP_BA
154 #define USB_BP_0                PLA_BP_0
155 #define USB_BP_1                PLA_BP_1
156 #define USB_BP_2                PLA_BP_2
157 #define USB_BP_3                PLA_BP_3
158 #define USB_BP_4                PLA_BP_4
159 #define USB_BP_5                PLA_BP_5
160 #define USB_BP_6                PLA_BP_6
161 #define USB_BP_7                PLA_BP_7
162 #define USB_BP_EN               PLA_BP_EN       /* RTL8153A */
163 #define USB_BP_8                0xfc38          /* RTL8153B */
164 #define USB_BP_9                0xfc3a
165 #define USB_BP_10               0xfc3c
166 #define USB_BP_11               0xfc3e
167 #define USB_BP_12               0xfc40
168 #define USB_BP_13               0xfc42
169 #define USB_BP_14               0xfc44
170 #define USB_BP_15               0xfc46
171 #define USB_BP2_EN              0xfc48
172
173 /* OCP Registers */
174 #define OCP_ALDPS_CONFIG        0x2010
175 #define OCP_EEE_CONFIG1         0x2080
176 #define OCP_EEE_CONFIG2         0x2092
177 #define OCP_EEE_CONFIG3         0x2094
178 #define OCP_BASE_MII            0xa400
179 #define OCP_EEE_AR              0xa41a
180 #define OCP_EEE_DATA            0xa41c
181 #define OCP_PHY_STATUS          0xa420
182 #define OCP_NCTL_CFG            0xa42c
183 #define OCP_POWER_CFG           0xa430
184 #define OCP_EEE_CFG             0xa432
185 #define OCP_SRAM_ADDR           0xa436
186 #define OCP_SRAM_DATA           0xa438
187 #define OCP_DOWN_SPEED          0xa442
188 #define OCP_EEE_ABLE            0xa5c4
189 #define OCP_EEE_ADV             0xa5d0
190 #define OCP_EEE_LPABLE          0xa5d2
191 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
192 #define OCP_PHY_PATCH_STAT      0xb800
193 #define OCP_PHY_PATCH_CMD       0xb820
194 #define OCP_PHY_LOCK            0xb82e
195 #define OCP_ADC_IOFFSET         0xbcfc
196 #define OCP_ADC_CFG             0xbc06
197 #define OCP_SYSCLK_CFG          0xc416
198
199 /* SRAM Register */
200 #define SRAM_GREEN_CFG          0x8011
201 #define SRAM_LPF_CFG            0x8012
202 #define SRAM_10M_AMP1           0x8080
203 #define SRAM_10M_AMP2           0x8082
204 #define SRAM_IMPEDANCE          0x8084
205 #define SRAM_PHY_LOCK           0xb82e
206
207 /* PLA_RCR */
208 #define RCR_AAP                 0x00000001
209 #define RCR_APM                 0x00000002
210 #define RCR_AM                  0x00000004
211 #define RCR_AB                  0x00000008
212 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
213
214 /* PLA_RXFIFO_CTRL0 */
215 #define RXFIFO_THR1_NORMAL      0x00080002
216 #define RXFIFO_THR1_OOB         0x01800003
217
218 /* PLA_RXFIFO_CTRL1 */
219 #define RXFIFO_THR2_FULL        0x00000060
220 #define RXFIFO_THR2_HIGH        0x00000038
221 #define RXFIFO_THR2_OOB         0x0000004a
222 #define RXFIFO_THR2_NORMAL      0x00a0
223
224 /* PLA_RXFIFO_CTRL2 */
225 #define RXFIFO_THR3_FULL        0x00000078
226 #define RXFIFO_THR3_HIGH        0x00000048
227 #define RXFIFO_THR3_OOB         0x0000005a
228 #define RXFIFO_THR3_NORMAL      0x0110
229
230 /* PLA_TXFIFO_CTRL */
231 #define TXFIFO_THR_NORMAL       0x00400008
232 #define TXFIFO_THR_NORMAL2      0x01000008
233
234 /* PLA_DMY_REG0 */
235 #define ECM_ALDPS               0x0002
236
237 /* PLA_FMC */
238 #define FMC_FCR_MCU_EN          0x0001
239
240 /* PLA_EEEP_CR */
241 #define EEEP_CR_EEEP_TX         0x0002
242
243 /* PLA_WDT6_CTRL */
244 #define WDT6_SET_MODE           0x0010
245
246 /* PLA_TCR0 */
247 #define TCR0_TX_EMPTY           0x0800
248 #define TCR0_AUTO_FIFO          0x0080
249
250 /* PLA_TCR1 */
251 #define VERSION_MASK            0x7cf0
252
253 /* PLA_MTPS */
254 #define MTPS_JUMBO              (12 * 1024 / 64)
255 #define MTPS_DEFAULT            (6 * 1024 / 64)
256
257 /* PLA_RSTTALLY */
258 #define TALLY_RESET             0x0001
259
260 /* PLA_CR */
261 #define CR_RST                  0x10
262 #define CR_RE                   0x08
263 #define CR_TE                   0x04
264
265 /* PLA_CRWECR */
266 #define CRWECR_NORAML           0x00
267 #define CRWECR_CONFIG           0xc0
268
269 /* PLA_OOB_CTRL */
270 #define NOW_IS_OOB              0x80
271 #define TXFIFO_EMPTY            0x20
272 #define RXFIFO_EMPTY            0x10
273 #define LINK_LIST_READY         0x02
274 #define DIS_MCU_CLROOB          0x01
275 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
276
277 /* PLA_MISC_1 */
278 #define RXDY_GATED_EN           0x0008
279
280 /* PLA_SFF_STS_7 */
281 #define RE_INIT_LL              0x8000
282 #define MCU_BORW_EN             0x4000
283
284 /* PLA_CPCR */
285 #define CPCR_RX_VLAN            0x0040
286
287 /* PLA_CFG_WOL */
288 #define MAGIC_EN                0x0001
289
290 /* PLA_TEREDO_CFG */
291 #define TEREDO_SEL              0x8000
292 #define TEREDO_WAKE_MASK        0x7f00
293 #define TEREDO_RS_EVENT_MASK    0x00fe
294 #define OOB_TEREDO_EN           0x0001
295
296 /* PLA_BDC_CR */
297 #define ALDPS_PROXY_MODE        0x0001
298
299 /* PLA_EFUSE_CMD */
300 #define EFUSE_READ_CMD          BIT(15)
301 #define EFUSE_DATA_BIT16        BIT(7)
302
303 /* PLA_CONFIG34 */
304 #define LINK_ON_WAKE_EN         0x0010
305 #define LINK_OFF_WAKE_EN        0x0008
306
307 /* PLA_CONFIG6 */
308 #define LANWAKE_CLR_EN          BIT(0)
309
310 /* PLA_CONFIG5 */
311 #define BWF_EN                  0x0040
312 #define MWF_EN                  0x0020
313 #define UWF_EN                  0x0010
314 #define LAN_WAKE_EN             0x0002
315
316 /* PLA_LED_FEATURE */
317 #define LED_MODE_MASK           0x0700
318
319 /* PLA_PHY_PWR */
320 #define TX_10M_IDLE_EN          0x0080
321 #define PFM_PWM_SWITCH          0x0040
322 #define TEST_IO_OFF             BIT(4)
323
324 /* PLA_MAC_PWR_CTRL */
325 #define D3_CLK_GATED_EN         0x00004000
326 #define MCU_CLK_RATIO           0x07010f07
327 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
328 #define ALDPS_SPDWN_RATIO       0x0f87
329
330 /* PLA_MAC_PWR_CTRL2 */
331 #define EEE_SPDWN_RATIO         0x8007
332 #define MAC_CLK_SPDWN_EN        BIT(15)
333
334 /* PLA_MAC_PWR_CTRL3 */
335 #define PLA_MCU_SPDWN_EN        BIT(14)
336 #define PKT_AVAIL_SPDWN_EN      0x0100
337 #define SUSPEND_SPDWN_EN        0x0004
338 #define U1U2_SPDWN_EN           0x0002
339 #define L1_SPDWN_EN             0x0001
340
341 /* PLA_MAC_PWR_CTRL4 */
342 #define PWRSAVE_SPDWN_EN        0x1000
343 #define RXDV_SPDWN_EN           0x0800
344 #define TX10MIDLE_EN            0x0100
345 #define TP100_SPDWN_EN          0x0020
346 #define TP500_SPDWN_EN          0x0010
347 #define TP1000_SPDWN_EN         0x0008
348 #define EEE_SPDWN_EN            0x0001
349
350 /* PLA_GPHY_INTR_IMR */
351 #define GPHY_STS_MSK            0x0001
352 #define SPEED_DOWN_MSK          0x0002
353 #define SPDWN_RXDV_MSK          0x0004
354 #define SPDWN_LINKCHG_MSK       0x0008
355
356 /* PLA_PHYAR */
357 #define PHYAR_FLAG              0x80000000
358
359 /* PLA_EEE_CR */
360 #define EEE_RX_EN               0x0001
361 #define EEE_TX_EN               0x0002
362
363 /* PLA_BOOT_CTRL */
364 #define AUTOLOAD_DONE           0x0002
365
366 /* PLA_LWAKE_CTRL_REG */
367 #define LANWAKE_PIN             BIT(7)
368
369 /* PLA_SUSPEND_FLAG */
370 #define LINK_CHG_EVENT          BIT(0)
371
372 /* PLA_INDICATE_FALG */
373 #define UPCOMING_RUNTIME_D3     BIT(0)
374
375 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
376 #define DEBUG_OE                BIT(0)
377 #define DEBUG_LTSSM             0x0082
378
379 /* PLA_EXTRA_STATUS */
380 #define CUR_LINK_OK             BIT(15)
381 #define U3P3_CHECK_EN           BIT(7)  /* RTL_VER_05 only */
382 #define LINK_CHANGE_FLAG        BIT(8)
383 #define POLL_LINK_CHG           BIT(0)
384
385 /* USB_USB2PHY */
386 #define USB2PHY_SUSPEND         0x0001
387 #define USB2PHY_L1              0x0002
388
389 /* USB_SSPHYLINK1 */
390 #define DELAY_PHY_PWR_CHG       BIT(1)
391
392 /* USB_SSPHYLINK2 */
393 #define pwd_dn_scale_mask       0x3ffe
394 #define pwd_dn_scale(x)         ((x) << 1)
395
396 /* USB_CSR_DUMMY1 */
397 #define DYNAMIC_BURST           0x0001
398
399 /* USB_CSR_DUMMY2 */
400 #define EP4_FULL_FC             0x0001
401
402 /* USB_DEV_STAT */
403 #define STAT_SPEED_MASK         0x0006
404 #define STAT_SPEED_HIGH         0x0000
405 #define STAT_SPEED_FULL         0x0002
406
407 /* USB_FW_FIX_EN0 */
408 #define FW_FIX_SUSPEND          BIT(14)
409
410 /* USB_FW_FIX_EN1 */
411 #define FW_IP_RESET_EN          BIT(9)
412
413 /* USB_LPM_CONFIG */
414 #define LPM_U1U2_EN             BIT(0)
415
416 /* USB_TX_AGG */
417 #define TX_AGG_MAX_THRESHOLD    0x03
418
419 /* USB_RX_BUF_TH */
420 #define RX_THR_SUPPER           0x0c350180
421 #define RX_THR_HIGH             0x7a120180
422 #define RX_THR_SLOW             0xffff0180
423 #define RX_THR_B                0x00010001
424
425 /* USB_TX_DMA */
426 #define TEST_MODE_DISABLE       0x00000001
427 #define TX_SIZE_ADJUST1         0x00000100
428
429 /* USB_BMU_RESET */
430 #define BMU_RESET_EP_IN         0x01
431 #define BMU_RESET_EP_OUT        0x02
432
433 /* USB_UPT_RXDMA_OWN */
434 #define OWN_UPDATE              BIT(0)
435 #define OWN_CLEAR               BIT(1)
436
437 /* USB_FW_TASK */
438 #define FC_PATCH_TASK           BIT(1)
439
440 /* USB_UPS_CTRL */
441 #define POWER_CUT               0x0100
442
443 /* USB_PM_CTRL_STATUS */
444 #define RESUME_INDICATE         0x0001
445
446 /* USB_CSTMR */
447 #define FORCE_SUPER             BIT(0)
448
449 /* USB_FW_CTRL */
450 #define FLOW_CTRL_PATCH_OPT     BIT(1)
451
452 /* USB_FC_TIMER */
453 #define CTRL_TIMER_EN           BIT(15)
454
455 /* USB_USB_CTRL */
456 #define RX_AGG_DISABLE          0x0010
457 #define RX_ZERO_EN              0x0080
458
459 /* USB_U2P3_CTRL */
460 #define U2P3_ENABLE             0x0001
461
462 /* USB_POWER_CUT */
463 #define PWR_EN                  0x0001
464 #define PHASE2_EN               0x0008
465 #define UPS_EN                  BIT(4)
466 #define USP_PREWAKE             BIT(5)
467
468 /* USB_MISC_0 */
469 #define PCUT_STATUS             0x0001
470
471 /* USB_RX_EARLY_TIMEOUT */
472 #define COALESCE_SUPER           85000U
473 #define COALESCE_HIGH           250000U
474 #define COALESCE_SLOW           524280U
475
476 /* USB_WDT1_CTRL */
477 #define WTD1_EN                 BIT(0)
478
479 /* USB_WDT11_CTRL */
480 #define TIMER11_EN              0x0001
481
482 /* USB_LPM_CTRL */
483 /* bit 4 ~ 5: fifo empty boundary */
484 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
485 /* bit 2 ~ 3: LMP timer */
486 #define LPM_TIMER_MASK          0x0c
487 #define LPM_TIMER_500MS         0x04    /* 500 ms */
488 #define LPM_TIMER_500US         0x0c    /* 500 us */
489 #define ROK_EXIT_LPM            0x02
490
491 /* USB_AFE_CTRL2 */
492 #define SEN_VAL_MASK            0xf800
493 #define SEN_VAL_NORMAL          0xa000
494 #define SEL_RXIDLE              0x0100
495
496 /* USB_UPS_CFG */
497 #define SAW_CNT_1MS_MASK        0x0fff
498
499 /* USB_UPS_FLAGS */
500 #define UPS_FLAGS_R_TUNE                BIT(0)
501 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
502 #define UPS_FLAGS_250M_CKDIV            BIT(2)
503 #define UPS_FLAGS_EN_ALDPS              BIT(3)
504 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
505 #define ups_flags_speed(x)              ((x) << 16)
506 #define UPS_FLAGS_EN_EEE                BIT(20)
507 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
508 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
509 #define UPS_FLAGS_EEE_PLLOFF_100        BIT(23)
510 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
511 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
512 #define UPS_FLAGS_EN_GREEN              BIT(26)
513 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
514
515 enum spd_duplex {
516         NWAY_10M_HALF,
517         NWAY_10M_FULL,
518         NWAY_100M_HALF,
519         NWAY_100M_FULL,
520         NWAY_1000M_FULL,
521         FORCE_10M_HALF,
522         FORCE_10M_FULL,
523         FORCE_100M_HALF,
524         FORCE_100M_FULL,
525 };
526
527 /* OCP_ALDPS_CONFIG */
528 #define ENPWRSAVE               0x8000
529 #define ENPDNPS                 0x0200
530 #define LINKENA                 0x0100
531 #define DIS_SDSAVE              0x0010
532
533 /* OCP_PHY_STATUS */
534 #define PHY_STAT_MASK           0x0007
535 #define PHY_STAT_EXT_INIT       2
536 #define PHY_STAT_LAN_ON         3
537 #define PHY_STAT_PWRDN          5
538
539 /* OCP_NCTL_CFG */
540 #define PGA_RETURN_EN           BIT(1)
541
542 /* OCP_POWER_CFG */
543 #define EEE_CLKDIV_EN           0x8000
544 #define EN_ALDPS                0x0004
545 #define EN_10M_PLLOFF           0x0001
546
547 /* OCP_EEE_CONFIG1 */
548 #define RG_TXLPI_MSK_HFDUP      0x8000
549 #define RG_MATCLR_EN            0x4000
550 #define EEE_10_CAP              0x2000
551 #define EEE_NWAY_EN             0x1000
552 #define TX_QUIET_EN             0x0200
553 #define RX_QUIET_EN             0x0100
554 #define sd_rise_time_mask       0x0070
555 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
556 #define RG_RXLPI_MSK_HFDUP      0x0008
557 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
558
559 /* OCP_EEE_CONFIG2 */
560 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
561 #define RG_DACQUIET_EN          0x0400
562 #define RG_LDVQUIET_EN          0x0200
563 #define RG_CKRSEL               0x0020
564 #define RG_EEEPRG_EN            0x0010
565
566 /* OCP_EEE_CONFIG3 */
567 #define fast_snr_mask           0xff80
568 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
569 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
570 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
571
572 /* OCP_EEE_AR */
573 /* bit[15:14] function */
574 #define FUN_ADDR                0x0000
575 #define FUN_DATA                0x4000
576 /* bit[4:0] device addr */
577
578 /* OCP_EEE_CFG */
579 #define CTAP_SHORT_EN           0x0040
580 #define EEE10_EN                0x0010
581
582 /* OCP_DOWN_SPEED */
583 #define EN_EEE_CMODE            BIT(14)
584 #define EN_EEE_1000             BIT(13)
585 #define EN_EEE_100              BIT(12)
586 #define EN_10M_CLKDIV           BIT(11)
587 #define EN_10M_BGOFF            0x0080
588
589 /* OCP_PHY_STATE */
590 #define TXDIS_STATE             0x01
591 #define ABD_STATE               0x02
592
593 /* OCP_PHY_PATCH_STAT */
594 #define PATCH_READY             BIT(6)
595
596 /* OCP_PHY_PATCH_CMD */
597 #define PATCH_REQUEST           BIT(4)
598
599 /* OCP_PHY_LOCK */
600 #define PATCH_LOCK              BIT(0)
601
602 /* OCP_ADC_CFG */
603 #define CKADSEL_L               0x0100
604 #define ADC_EN                  0x0080
605 #define EN_EMI_L                0x0040
606
607 /* OCP_SYSCLK_CFG */
608 #define clk_div_expo(x)         (min(x, 5) << 8)
609
610 /* SRAM_GREEN_CFG */
611 #define GREEN_ETH_EN            BIT(15)
612 #define R_TUNE_EN               BIT(11)
613
614 /* SRAM_LPF_CFG */
615 #define LPF_AUTO_TUNE           0x8000
616
617 /* SRAM_10M_AMP1 */
618 #define GDAC_IB_UPALL           0x0008
619
620 /* SRAM_10M_AMP2 */
621 #define AMP_DN                  0x0200
622
623 /* SRAM_IMPEDANCE */
624 #define RX_DRIVING_MASK         0x6000
625
626 /* SRAM_PHY_LOCK */
627 #define PHY_PATCH_LOCK          0x0001
628
629 /* MAC PASSTHRU */
630 #define AD_MASK                 0xfee0
631 #define BND_MASK                0x0004
632 #define BD_MASK                 0x0001
633 #define EFUSE                   0xcfdb
634 #define PASS_THRU_MASK          0x1
635
636 #define BP4_SUPER_ONLY          0x1578  /* RTL_VER_04 only */
637
638 enum rtl_register_content {
639         _1000bps        = 0x10,
640         _100bps         = 0x08,
641         _10bps          = 0x04,
642         LINK_STATUS     = 0x02,
643         FULL_DUP        = 0x01,
644 };
645
646 #define RTL8152_MAX_TX          4
647 #define RTL8152_MAX_RX          10
648 #define INTBUFSIZE              2
649 #define TX_ALIGN                4
650 #define RX_ALIGN                8
651
652 #define RTL8152_RX_MAX_PENDING  4096
653 #define RTL8152_RXFG_HEADSZ     256
654
655 #define INTR_LINK               0x0004
656
657 #define RTL8153_MAX_PACKET      9216 /* 9K */
658 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
659                                  ETH_FCS_LEN)
660 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
661 #define RTL8153_RMS             RTL8153_MAX_PACKET
662 #define RTL8152_TX_TIMEOUT      (5 * HZ)
663 #define RTL8152_NAPI_WEIGHT     64
664 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
665                                  sizeof(struct rx_desc) + RX_ALIGN)
666
667 /* rtl8152 flags */
668 enum rtl8152_flags {
669         RTL8152_UNPLUG = 0,
670         RTL8152_SET_RX_MODE,
671         WORK_ENABLE,
672         RTL8152_LINK_CHG,
673         SELECTIVE_SUSPEND,
674         PHY_RESET,
675         SCHEDULE_TASKLET,
676         GREEN_ETHERNET,
677         DELL_TB_RX_AGG_BUG,
678         LENOVO_MACPASSTHRU,
679 };
680
681 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2       0x3082
682 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2              0xa387
683
684 struct tally_counter {
685         __le64  tx_packets;
686         __le64  rx_packets;
687         __le64  tx_errors;
688         __le32  rx_errors;
689         __le16  rx_missed;
690         __le16  align_errors;
691         __le32  tx_one_collision;
692         __le32  tx_multi_collision;
693         __le64  rx_unicast;
694         __le64  rx_broadcast;
695         __le32  rx_multicast;
696         __le16  tx_aborted;
697         __le16  tx_underrun;
698 };
699
700 struct rx_desc {
701         __le32 opts1;
702 #define RX_LEN_MASK                     0x7fff
703
704         __le32 opts2;
705 #define RD_UDP_CS                       BIT(23)
706 #define RD_TCP_CS                       BIT(22)
707 #define RD_IPV6_CS                      BIT(20)
708 #define RD_IPV4_CS                      BIT(19)
709
710         __le32 opts3;
711 #define IPF                             BIT(23) /* IP checksum fail */
712 #define UDPF                            BIT(22) /* UDP checksum fail */
713 #define TCPF                            BIT(21) /* TCP checksum fail */
714 #define RX_VLAN_TAG                     BIT(16)
715
716         __le32 opts4;
717         __le32 opts5;
718         __le32 opts6;
719 };
720
721 struct tx_desc {
722         __le32 opts1;
723 #define TX_FS                   BIT(31) /* First segment of a packet */
724 #define TX_LS                   BIT(30) /* Final segment of a packet */
725 #define GTSENDV4                BIT(28)
726 #define GTSENDV6                BIT(27)
727 #define GTTCPHO_SHIFT           18
728 #define GTTCPHO_MAX             0x7fU
729 #define TX_LEN_MAX              0x3ffffU
730
731         __le32 opts2;
732 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
733 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
734 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
735 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
736 #define MSS_SHIFT               17
737 #define MSS_MAX                 0x7ffU
738 #define TCPHO_SHIFT             17
739 #define TCPHO_MAX               0x7ffU
740 #define TX_VLAN_TAG             BIT(16)
741 };
742
743 struct r8152;
744
745 struct rx_agg {
746         struct list_head list, info_list;
747         struct urb *urb;
748         struct r8152 *context;
749         struct page *page;
750         void *buffer;
751 };
752
753 struct tx_agg {
754         struct list_head list;
755         struct urb *urb;
756         struct r8152 *context;
757         void *buffer;
758         void *head;
759         u32 skb_num;
760         u32 skb_len;
761 };
762
763 struct r8152 {
764         unsigned long flags;
765         struct usb_device *udev;
766         struct napi_struct napi;
767         struct usb_interface *intf;
768         struct net_device *netdev;
769         struct urb *intr_urb;
770         struct tx_agg tx_info[RTL8152_MAX_TX];
771         struct list_head rx_info, rx_used;
772         struct list_head rx_done, tx_free;
773         struct sk_buff_head tx_queue, rx_queue;
774         spinlock_t rx_lock, tx_lock;
775         struct delayed_work schedule, hw_phy_work;
776         struct mii_if_info mii;
777         struct mutex control;   /* use for hw setting */
778 #ifdef CONFIG_PM_SLEEP
779         struct notifier_block pm_notifier;
780 #endif
781         struct tasklet_struct tx_tl;
782
783         struct rtl_ops {
784                 void (*init)(struct r8152 *tp);
785                 int (*enable)(struct r8152 *tp);
786                 void (*disable)(struct r8152 *tp);
787                 void (*up)(struct r8152 *tp);
788                 void (*down)(struct r8152 *tp);
789                 void (*unload)(struct r8152 *tp);
790                 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
791                 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
792                 bool (*in_nway)(struct r8152 *tp);
793                 void (*hw_phy_cfg)(struct r8152 *tp);
794                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
795         } rtl_ops;
796
797         struct ups_info {
798                 u32 _10m_ckdiv:1;
799                 u32 _250m_ckdiv:1;
800                 u32 aldps:1;
801                 u32 lite_mode:2;
802                 u32 speed_duplex:4;
803                 u32 eee:1;
804                 u32 eee_lite:1;
805                 u32 eee_ckdiv:1;
806                 u32 eee_plloff_100:1;
807                 u32 eee_plloff_giga:1;
808                 u32 eee_cmod_lv:1;
809                 u32 green:1;
810                 u32 flow_control:1;
811                 u32 ctap_short_off:1;
812         } ups_info;
813
814 #define RTL_VER_SIZE            32
815
816         struct rtl_fw {
817                 const char *fw_name;
818                 const struct firmware *fw;
819
820                 char version[RTL_VER_SIZE];
821                 int (*pre_fw)(struct r8152 *tp);
822                 int (*post_fw)(struct r8152 *tp);
823
824                 bool retry;
825         } rtl_fw;
826
827         atomic_t rx_count;
828
829         bool eee_en;
830         int intr_interval;
831         u32 saved_wolopts;
832         u32 msg_enable;
833         u32 tx_qlen;
834         u32 coalesce;
835         u32 advertising;
836         u32 rx_buf_sz;
837         u32 rx_copybreak;
838         u32 rx_pending;
839
840         u16 ocp_base;
841         u16 speed;
842         u16 eee_adv;
843         u8 *intr_buff;
844         u8 version;
845         u8 duplex;
846         u8 autoneg;
847 };
848
849 /**
850  * struct fw_block - block type and total length
851  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
852  *      RTL_FW_USB and so on.
853  * @length: total length of the current block.
854  */
855 struct fw_block {
856         __le32 type;
857         __le32 length;
858 } __packed;
859
860 /**
861  * struct fw_header - header of the firmware file
862  * @checksum: checksum of sha256 which is calculated from the whole file
863  *      except the checksum field of the file. That is, calculate sha256
864  *      from the version field to the end of the file.
865  * @version: version of this firmware.
866  * @blocks: the first firmware block of the file
867  */
868 struct fw_header {
869         u8 checksum[32];
870         char version[RTL_VER_SIZE];
871         struct fw_block blocks[];
872 } __packed;
873
874 /**
875  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
876  *      The layout of the firmware block is:
877  *      <struct fw_mac> + <info> + <firmware data>.
878  * @blk_hdr: firmware descriptor (type, length)
879  * @fw_offset: offset of the firmware binary data. The start address of
880  *      the data would be the address of struct fw_mac + @fw_offset.
881  * @fw_reg: the register to load the firmware. Depends on chip.
882  * @bp_ba_addr: the register to write break point base address. Depends on
883  *      chip.
884  * @bp_ba_value: break point base address. Depends on chip.
885  * @bp_en_addr: the register to write break point enabled mask. Depends
886  *      on chip.
887  * @bp_en_value: break point enabled mask. Depends on the firmware.
888  * @bp_start: the start register of break points. Depends on chip.
889  * @bp_num: the break point number which needs to be set for this firmware.
890  *      Depends on the firmware.
891  * @bp: break points. Depends on firmware.
892  * @reserved: reserved space (unused)
893  * @fw_ver_reg: the register to store the fw version.
894  * @fw_ver_data: the firmware version of the current type.
895  * @info: additional information for debugging, and is followed by the
896  *      binary data of firmware.
897  */
898 struct fw_mac {
899         struct fw_block blk_hdr;
900         __le16 fw_offset;
901         __le16 fw_reg;
902         __le16 bp_ba_addr;
903         __le16 bp_ba_value;
904         __le16 bp_en_addr;
905         __le16 bp_en_value;
906         __le16 bp_start;
907         __le16 bp_num;
908         __le16 bp[16]; /* any value determined by firmware */
909         __le32 reserved;
910         __le16 fw_ver_reg;
911         u8 fw_ver_data;
912         char info[];
913 } __packed;
914
915 /**
916  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
917  *      This is used to set patch key when loading the firmware of PHY.
918  * @blk_hdr: firmware descriptor (type, length)
919  * @key_reg: the register to write the patch key.
920  * @key_data: patch key.
921  * @reserved: reserved space (unused)
922  */
923 struct fw_phy_patch_key {
924         struct fw_block blk_hdr;
925         __le16 key_reg;
926         __le16 key_data;
927         __le32 reserved;
928 } __packed;
929
930 /**
931  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
932  *      The layout of the firmware block is:
933  *      <struct fw_phy_nc> + <info> + <firmware data>.
934  * @blk_hdr: firmware descriptor (type, length)
935  * @fw_offset: offset of the firmware binary data. The start address of
936  *      the data would be the address of struct fw_phy_nc + @fw_offset.
937  * @fw_reg: the register to load the firmware. Depends on chip.
938  * @ba_reg: the register to write the base address. Depends on chip.
939  * @ba_data: base address. Depends on chip.
940  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
941  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
942  * @mode_reg: the regitster of switching the mode.
943  * @mode_pre: the mode needing to be set before loading the firmware.
944  * @mode_post: the mode to be set when finishing to load the firmware.
945  * @reserved: reserved space (unused)
946  * @bp_start: the start register of break points. Depends on chip.
947  * @bp_num: the break point number which needs to be set for this firmware.
948  *      Depends on the firmware.
949  * @bp: break points. Depends on firmware.
950  * @info: additional information for debugging, and is followed by the
951  *      binary data of firmware.
952  */
953 struct fw_phy_nc {
954         struct fw_block blk_hdr;
955         __le16 fw_offset;
956         __le16 fw_reg;
957         __le16 ba_reg;
958         __le16 ba_data;
959         __le16 patch_en_addr;
960         __le16 patch_en_value;
961         __le16 mode_reg;
962         __le16 mode_pre;
963         __le16 mode_post;
964         __le16 reserved;
965         __le16 bp_start;
966         __le16 bp_num;
967         __le16 bp[4];
968         char info[];
969 } __packed;
970
971 enum rtl_fw_type {
972         RTL_FW_END = 0,
973         RTL_FW_PLA,
974         RTL_FW_USB,
975         RTL_FW_PHY_START,
976         RTL_FW_PHY_STOP,
977         RTL_FW_PHY_NC,
978 };
979
980 enum rtl_version {
981         RTL_VER_UNKNOWN = 0,
982         RTL_VER_01,
983         RTL_VER_02,
984         RTL_VER_03,
985         RTL_VER_04,
986         RTL_VER_05,
987         RTL_VER_06,
988         RTL_VER_07,
989         RTL_VER_08,
990         RTL_VER_09,
991         RTL_VER_MAX
992 };
993
994 enum tx_csum_stat {
995         TX_CSUM_SUCCESS = 0,
996         TX_CSUM_TSO,
997         TX_CSUM_NONE
998 };
999
1000 #define RTL_ADVERTISED_10_HALF                  BIT(0)
1001 #define RTL_ADVERTISED_10_FULL                  BIT(1)
1002 #define RTL_ADVERTISED_100_HALF                 BIT(2)
1003 #define RTL_ADVERTISED_100_FULL                 BIT(3)
1004 #define RTL_ADVERTISED_1000_HALF                BIT(4)
1005 #define RTL_ADVERTISED_1000_FULL                BIT(5)
1006
1007 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1008  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1009  */
1010 static const int multicast_filter_limit = 32;
1011 static unsigned int agg_buf_sz = 16384;
1012
1013 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
1014                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
1015
1016 static
1017 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1018 {
1019         int ret;
1020         void *tmp;
1021
1022         tmp = kmalloc(size, GFP_KERNEL);
1023         if (!tmp)
1024                 return -ENOMEM;
1025
1026         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1027                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1028                               value, index, tmp, size, 500);
1029         if (ret < 0)
1030                 memset(data, 0xff, size);
1031         else
1032                 memcpy(data, tmp, size);
1033
1034         kfree(tmp);
1035
1036         return ret;
1037 }
1038
1039 static
1040 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1041 {
1042         int ret;
1043         void *tmp;
1044
1045         tmp = kmemdup(data, size, GFP_KERNEL);
1046         if (!tmp)
1047                 return -ENOMEM;
1048
1049         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1050                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1051                               value, index, tmp, size, 500);
1052
1053         kfree(tmp);
1054
1055         return ret;
1056 }
1057
1058 static void rtl_set_unplug(struct r8152 *tp)
1059 {
1060         if (tp->udev->state == USB_STATE_NOTATTACHED) {
1061                 set_bit(RTL8152_UNPLUG, &tp->flags);
1062                 smp_mb__after_atomic();
1063         }
1064 }
1065
1066 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1067                             void *data, u16 type)
1068 {
1069         u16 limit = 64;
1070         int ret = 0;
1071
1072         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1073                 return -ENODEV;
1074
1075         /* both size and indix must be 4 bytes align */
1076         if ((size & 3) || !size || (index & 3) || !data)
1077                 return -EPERM;
1078
1079         if ((u32)index + (u32)size > 0xffff)
1080                 return -EPERM;
1081
1082         while (size) {
1083                 if (size > limit) {
1084                         ret = get_registers(tp, index, type, limit, data);
1085                         if (ret < 0)
1086                                 break;
1087
1088                         index += limit;
1089                         data += limit;
1090                         size -= limit;
1091                 } else {
1092                         ret = get_registers(tp, index, type, size, data);
1093                         if (ret < 0)
1094                                 break;
1095
1096                         index += size;
1097                         data += size;
1098                         size = 0;
1099                         break;
1100                 }
1101         }
1102
1103         if (ret == -ENODEV)
1104                 rtl_set_unplug(tp);
1105
1106         return ret;
1107 }
1108
1109 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1110                              u16 size, void *data, u16 type)
1111 {
1112         int ret;
1113         u16 byteen_start, byteen_end, byen;
1114         u16 limit = 512;
1115
1116         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117                 return -ENODEV;
1118
1119         /* both size and indix must be 4 bytes align */
1120         if ((size & 3) || !size || (index & 3) || !data)
1121                 return -EPERM;
1122
1123         if ((u32)index + (u32)size > 0xffff)
1124                 return -EPERM;
1125
1126         byteen_start = byteen & BYTE_EN_START_MASK;
1127         byteen_end = byteen & BYTE_EN_END_MASK;
1128
1129         byen = byteen_start | (byteen_start << 4);
1130         ret = set_registers(tp, index, type | byen, 4, data);
1131         if (ret < 0)
1132                 goto error1;
1133
1134         index += 4;
1135         data += 4;
1136         size -= 4;
1137
1138         if (size) {
1139                 size -= 4;
1140
1141                 while (size) {
1142                         if (size > limit) {
1143                                 ret = set_registers(tp, index,
1144                                                     type | BYTE_EN_DWORD,
1145                                                     limit, data);
1146                                 if (ret < 0)
1147                                         goto error1;
1148
1149                                 index += limit;
1150                                 data += limit;
1151                                 size -= limit;
1152                         } else {
1153                                 ret = set_registers(tp, index,
1154                                                     type | BYTE_EN_DWORD,
1155                                                     size, data);
1156                                 if (ret < 0)
1157                                         goto error1;
1158
1159                                 index += size;
1160                                 data += size;
1161                                 size = 0;
1162                                 break;
1163                         }
1164                 }
1165
1166                 byen = byteen_end | (byteen_end >> 4);
1167                 ret = set_registers(tp, index, type | byen, 4, data);
1168                 if (ret < 0)
1169                         goto error1;
1170         }
1171
1172 error1:
1173         if (ret == -ENODEV)
1174                 rtl_set_unplug(tp);
1175
1176         return ret;
1177 }
1178
1179 static inline
1180 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1181 {
1182         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1183 }
1184
1185 static inline
1186 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1187 {
1188         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1189 }
1190
1191 static inline
1192 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1193 {
1194         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1195 }
1196
1197 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1198 {
1199         __le32 data;
1200
1201         generic_ocp_read(tp, index, sizeof(data), &data, type);
1202
1203         return __le32_to_cpu(data);
1204 }
1205
1206 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1207 {
1208         __le32 tmp = __cpu_to_le32(data);
1209
1210         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1211 }
1212
1213 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1214 {
1215         u32 data;
1216         __le32 tmp;
1217         u16 byen = BYTE_EN_WORD;
1218         u8 shift = index & 2;
1219
1220         index &= ~3;
1221         byen <<= shift;
1222
1223         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1224
1225         data = __le32_to_cpu(tmp);
1226         data >>= (shift * 8);
1227         data &= 0xffff;
1228
1229         return (u16)data;
1230 }
1231
1232 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1233 {
1234         u32 mask = 0xffff;
1235         __le32 tmp;
1236         u16 byen = BYTE_EN_WORD;
1237         u8 shift = index & 2;
1238
1239         data &= mask;
1240
1241         if (index & 2) {
1242                 byen <<= shift;
1243                 mask <<= (shift * 8);
1244                 data <<= (shift * 8);
1245                 index &= ~3;
1246         }
1247
1248         tmp = __cpu_to_le32(data);
1249
1250         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1251 }
1252
1253 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1254 {
1255         u32 data;
1256         __le32 tmp;
1257         u8 shift = index & 3;
1258
1259         index &= ~3;
1260
1261         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1262
1263         data = __le32_to_cpu(tmp);
1264         data >>= (shift * 8);
1265         data &= 0xff;
1266
1267         return (u8)data;
1268 }
1269
1270 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1271 {
1272         u32 mask = 0xff;
1273         __le32 tmp;
1274         u16 byen = BYTE_EN_BYTE;
1275         u8 shift = index & 3;
1276
1277         data &= mask;
1278
1279         if (index & 3) {
1280                 byen <<= shift;
1281                 mask <<= (shift * 8);
1282                 data <<= (shift * 8);
1283                 index &= ~3;
1284         }
1285
1286         tmp = __cpu_to_le32(data);
1287
1288         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1289 }
1290
1291 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1292 {
1293         u16 ocp_base, ocp_index;
1294
1295         ocp_base = addr & 0xf000;
1296         if (ocp_base != tp->ocp_base) {
1297                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1298                 tp->ocp_base = ocp_base;
1299         }
1300
1301         ocp_index = (addr & 0x0fff) | 0xb000;
1302         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1303 }
1304
1305 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1306 {
1307         u16 ocp_base, ocp_index;
1308
1309         ocp_base = addr & 0xf000;
1310         if (ocp_base != tp->ocp_base) {
1311                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1312                 tp->ocp_base = ocp_base;
1313         }
1314
1315         ocp_index = (addr & 0x0fff) | 0xb000;
1316         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1317 }
1318
1319 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1320 {
1321         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1322 }
1323
1324 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1325 {
1326         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1327 }
1328
1329 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1330 {
1331         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1332         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1333 }
1334
1335 static u16 sram_read(struct r8152 *tp, u16 addr)
1336 {
1337         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1338         return ocp_reg_read(tp, OCP_SRAM_DATA);
1339 }
1340
1341 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1342 {
1343         struct r8152 *tp = netdev_priv(netdev);
1344         int ret;
1345
1346         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1347                 return -ENODEV;
1348
1349         if (phy_id != R8152_PHY_ID)
1350                 return -EINVAL;
1351
1352         ret = r8152_mdio_read(tp, reg);
1353
1354         return ret;
1355 }
1356
1357 static
1358 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1359 {
1360         struct r8152 *tp = netdev_priv(netdev);
1361
1362         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1363                 return;
1364
1365         if (phy_id != R8152_PHY_ID)
1366                 return;
1367
1368         r8152_mdio_write(tp, reg, val);
1369 }
1370
1371 static int
1372 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1373
1374 static int
1375 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1376                   u32 advertising);
1377
1378 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1379 {
1380         struct r8152 *tp = netdev_priv(netdev);
1381         struct sockaddr *addr = p;
1382         int ret = -EADDRNOTAVAIL;
1383
1384         if (!is_valid_ether_addr(addr->sa_data))
1385                 goto out1;
1386
1387         ret = usb_autopm_get_interface(tp->intf);
1388         if (ret < 0)
1389                 goto out1;
1390
1391         mutex_lock(&tp->control);
1392
1393         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1394
1395         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1396         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1397         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1398
1399         mutex_unlock(&tp->control);
1400
1401         usb_autopm_put_interface(tp->intf);
1402 out1:
1403         return ret;
1404 }
1405
1406 /* Devices containing proper chips can support a persistent
1407  * host system provided MAC address.
1408  * Examples of this are Dell TB15 and Dell WD15 docks
1409  */
1410 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1411 {
1412         acpi_status status;
1413         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1414         union acpi_object *obj;
1415         int ret = -EINVAL;
1416         u32 ocp_data;
1417         unsigned char buf[6];
1418         char *mac_obj_name;
1419         acpi_object_type mac_obj_type;
1420         int mac_strlen;
1421
1422         if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1423                 mac_obj_name = "\\MACA";
1424                 mac_obj_type = ACPI_TYPE_STRING;
1425                 mac_strlen = 0x16;
1426         } else {
1427                 /* test for -AD variant of RTL8153 */
1428                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1429                 if ((ocp_data & AD_MASK) == 0x1000) {
1430                         /* test for MAC address pass-through bit */
1431                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1432                         if ((ocp_data & PASS_THRU_MASK) != 1) {
1433                                 netif_dbg(tp, probe, tp->netdev,
1434                                                 "No efuse for RTL8153-AD MAC pass through\n");
1435                                 return -ENODEV;
1436                         }
1437                 } else {
1438                         /* test for RTL8153-BND and RTL8153-BD */
1439                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1440                         if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1441                                 netif_dbg(tp, probe, tp->netdev,
1442                                                 "Invalid variant for MAC pass through\n");
1443                                 return -ENODEV;
1444                         }
1445                 }
1446
1447                 mac_obj_name = "\\_SB.AMAC";
1448                 mac_obj_type = ACPI_TYPE_BUFFER;
1449                 mac_strlen = 0x17;
1450         }
1451
1452         /* returns _AUXMAC_#AABBCCDDEEFF# */
1453         status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1454         obj = (union acpi_object *)buffer.pointer;
1455         if (!ACPI_SUCCESS(status))
1456                 return -ENODEV;
1457         if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1458                 netif_warn(tp, probe, tp->netdev,
1459                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1460                            obj->type, obj->string.length);
1461                 goto amacout;
1462         }
1463
1464         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1465             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1466                 netif_warn(tp, probe, tp->netdev,
1467                            "Invalid header when reading pass-thru MAC addr\n");
1468                 goto amacout;
1469         }
1470         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1471         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1472                 netif_warn(tp, probe, tp->netdev,
1473                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1474                            ret, buf);
1475                 ret = -EINVAL;
1476                 goto amacout;
1477         }
1478         memcpy(sa->sa_data, buf, 6);
1479         netif_info(tp, probe, tp->netdev,
1480                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1481
1482 amacout:
1483         kfree(obj);
1484         return ret;
1485 }
1486
1487 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1488 {
1489         struct net_device *dev = tp->netdev;
1490         int ret;
1491
1492         sa->sa_family = dev->type;
1493
1494         ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1495         if (ret < 0) {
1496                 if (tp->version == RTL_VER_01) {
1497                         ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1498                 } else {
1499                         /* if device doesn't support MAC pass through this will
1500                          * be expected to be non-zero
1501                          */
1502                         ret = vendor_mac_passthru_addr_read(tp, sa);
1503                         if (ret < 0)
1504                                 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1505                                                    sa->sa_data);
1506                 }
1507         }
1508
1509         if (ret < 0) {
1510                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1511         } else if (!is_valid_ether_addr(sa->sa_data)) {
1512                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1513                           sa->sa_data);
1514                 eth_hw_addr_random(dev);
1515                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1516                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1517                            sa->sa_data);
1518                 return 0;
1519         }
1520
1521         return ret;
1522 }
1523
1524 static int set_ethernet_addr(struct r8152 *tp)
1525 {
1526         struct net_device *dev = tp->netdev;
1527         struct sockaddr sa;
1528         int ret;
1529
1530         ret = determine_ethernet_addr(tp, &sa);
1531         if (ret < 0)
1532                 return ret;
1533
1534         if (tp->version == RTL_VER_01)
1535                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1536         else
1537                 ret = rtl8152_set_mac_address(dev, &sa);
1538
1539         return ret;
1540 }
1541
1542 static void read_bulk_callback(struct urb *urb)
1543 {
1544         struct net_device *netdev;
1545         int status = urb->status;
1546         struct rx_agg *agg;
1547         struct r8152 *tp;
1548         unsigned long flags;
1549
1550         agg = urb->context;
1551         if (!agg)
1552                 return;
1553
1554         tp = agg->context;
1555         if (!tp)
1556                 return;
1557
1558         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1559                 return;
1560
1561         if (!test_bit(WORK_ENABLE, &tp->flags))
1562                 return;
1563
1564         netdev = tp->netdev;
1565
1566         /* When link down, the driver would cancel all bulks. */
1567         /* This avoid the re-submitting bulk */
1568         if (!netif_carrier_ok(netdev))
1569                 return;
1570
1571         usb_mark_last_busy(tp->udev);
1572
1573         switch (status) {
1574         case 0:
1575                 if (urb->actual_length < ETH_ZLEN)
1576                         break;
1577
1578                 spin_lock_irqsave(&tp->rx_lock, flags);
1579                 list_add_tail(&agg->list, &tp->rx_done);
1580                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1581                 napi_schedule(&tp->napi);
1582                 return;
1583         case -ESHUTDOWN:
1584                 rtl_set_unplug(tp);
1585                 netif_device_detach(tp->netdev);
1586                 return;
1587         case -ENOENT:
1588                 return; /* the urb is in unlink state */
1589         case -ETIME:
1590                 if (net_ratelimit())
1591                         netdev_warn(netdev, "maybe reset is needed?\n");
1592                 break;
1593         default:
1594                 if (net_ratelimit())
1595                         netdev_warn(netdev, "Rx status %d\n", status);
1596                 break;
1597         }
1598
1599         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1600 }
1601
1602 static void write_bulk_callback(struct urb *urb)
1603 {
1604         struct net_device_stats *stats;
1605         struct net_device *netdev;
1606         struct tx_agg *agg;
1607         struct r8152 *tp;
1608         unsigned long flags;
1609         int status = urb->status;
1610
1611         agg = urb->context;
1612         if (!agg)
1613                 return;
1614
1615         tp = agg->context;
1616         if (!tp)
1617                 return;
1618
1619         netdev = tp->netdev;
1620         stats = &netdev->stats;
1621         if (status) {
1622                 if (net_ratelimit())
1623                         netdev_warn(netdev, "Tx status %d\n", status);
1624                 stats->tx_errors += agg->skb_num;
1625         } else {
1626                 stats->tx_packets += agg->skb_num;
1627                 stats->tx_bytes += agg->skb_len;
1628         }
1629
1630         spin_lock_irqsave(&tp->tx_lock, flags);
1631         list_add_tail(&agg->list, &tp->tx_free);
1632         spin_unlock_irqrestore(&tp->tx_lock, flags);
1633
1634         usb_autopm_put_interface_async(tp->intf);
1635
1636         if (!netif_carrier_ok(netdev))
1637                 return;
1638
1639         if (!test_bit(WORK_ENABLE, &tp->flags))
1640                 return;
1641
1642         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1643                 return;
1644
1645         if (!skb_queue_empty(&tp->tx_queue))
1646                 tasklet_schedule(&tp->tx_tl);
1647 }
1648
1649 static void intr_callback(struct urb *urb)
1650 {
1651         struct r8152 *tp;
1652         __le16 *d;
1653         int status = urb->status;
1654         int res;
1655
1656         tp = urb->context;
1657         if (!tp)
1658                 return;
1659
1660         if (!test_bit(WORK_ENABLE, &tp->flags))
1661                 return;
1662
1663         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1664                 return;
1665
1666         switch (status) {
1667         case 0:                 /* success */
1668                 break;
1669         case -ECONNRESET:       /* unlink */
1670         case -ESHUTDOWN:
1671                 netif_device_detach(tp->netdev);
1672                 fallthrough;
1673         case -ENOENT:
1674         case -EPROTO:
1675                 netif_info(tp, intr, tp->netdev,
1676                            "Stop submitting intr, status %d\n", status);
1677                 return;
1678         case -EOVERFLOW:
1679                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1680                 goto resubmit;
1681         /* -EPIPE:  should clear the halt */
1682         default:
1683                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1684                 goto resubmit;
1685         }
1686
1687         d = urb->transfer_buffer;
1688         if (INTR_LINK & __le16_to_cpu(d[0])) {
1689                 if (!netif_carrier_ok(tp->netdev)) {
1690                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1691                         schedule_delayed_work(&tp->schedule, 0);
1692                 }
1693         } else {
1694                 if (netif_carrier_ok(tp->netdev)) {
1695                         netif_stop_queue(tp->netdev);
1696                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1697                         schedule_delayed_work(&tp->schedule, 0);
1698                 }
1699         }
1700
1701 resubmit:
1702         res = usb_submit_urb(urb, GFP_ATOMIC);
1703         if (res == -ENODEV) {
1704                 rtl_set_unplug(tp);
1705                 netif_device_detach(tp->netdev);
1706         } else if (res) {
1707                 netif_err(tp, intr, tp->netdev,
1708                           "can't resubmit intr, status %d\n", res);
1709         }
1710 }
1711
1712 static inline void *rx_agg_align(void *data)
1713 {
1714         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1715 }
1716
1717 static inline void *tx_agg_align(void *data)
1718 {
1719         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1720 }
1721
1722 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1723 {
1724         list_del(&agg->info_list);
1725
1726         usb_free_urb(agg->urb);
1727         put_page(agg->page);
1728         kfree(agg);
1729
1730         atomic_dec(&tp->rx_count);
1731 }
1732
1733 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1734 {
1735         struct net_device *netdev = tp->netdev;
1736         int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1737         unsigned int order = get_order(tp->rx_buf_sz);
1738         struct rx_agg *rx_agg;
1739         unsigned long flags;
1740
1741         rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1742         if (!rx_agg)
1743                 return NULL;
1744
1745         rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1746         if (!rx_agg->page)
1747                 goto free_rx;
1748
1749         rx_agg->buffer = page_address(rx_agg->page);
1750
1751         rx_agg->urb = usb_alloc_urb(0, mflags);
1752         if (!rx_agg->urb)
1753                 goto free_buf;
1754
1755         rx_agg->context = tp;
1756
1757         INIT_LIST_HEAD(&rx_agg->list);
1758         INIT_LIST_HEAD(&rx_agg->info_list);
1759         spin_lock_irqsave(&tp->rx_lock, flags);
1760         list_add_tail(&rx_agg->info_list, &tp->rx_info);
1761         spin_unlock_irqrestore(&tp->rx_lock, flags);
1762
1763         atomic_inc(&tp->rx_count);
1764
1765         return rx_agg;
1766
1767 free_buf:
1768         __free_pages(rx_agg->page, order);
1769 free_rx:
1770         kfree(rx_agg);
1771         return NULL;
1772 }
1773
1774 static void free_all_mem(struct r8152 *tp)
1775 {
1776         struct rx_agg *agg, *agg_next;
1777         unsigned long flags;
1778         int i;
1779
1780         spin_lock_irqsave(&tp->rx_lock, flags);
1781
1782         list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1783                 free_rx_agg(tp, agg);
1784
1785         spin_unlock_irqrestore(&tp->rx_lock, flags);
1786
1787         WARN_ON(atomic_read(&tp->rx_count));
1788
1789         for (i = 0; i < RTL8152_MAX_TX; i++) {
1790                 usb_free_urb(tp->tx_info[i].urb);
1791                 tp->tx_info[i].urb = NULL;
1792
1793                 kfree(tp->tx_info[i].buffer);
1794                 tp->tx_info[i].buffer = NULL;
1795                 tp->tx_info[i].head = NULL;
1796         }
1797
1798         usb_free_urb(tp->intr_urb);
1799         tp->intr_urb = NULL;
1800
1801         kfree(tp->intr_buff);
1802         tp->intr_buff = NULL;
1803 }
1804
1805 static int alloc_all_mem(struct r8152 *tp)
1806 {
1807         struct net_device *netdev = tp->netdev;
1808         struct usb_interface *intf = tp->intf;
1809         struct usb_host_interface *alt = intf->cur_altsetting;
1810         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1811         int node, i;
1812
1813         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1814
1815         spin_lock_init(&tp->rx_lock);
1816         spin_lock_init(&tp->tx_lock);
1817         INIT_LIST_HEAD(&tp->rx_info);
1818         INIT_LIST_HEAD(&tp->tx_free);
1819         INIT_LIST_HEAD(&tp->rx_done);
1820         skb_queue_head_init(&tp->tx_queue);
1821         skb_queue_head_init(&tp->rx_queue);
1822         atomic_set(&tp->rx_count, 0);
1823
1824         for (i = 0; i < RTL8152_MAX_RX; i++) {
1825                 if (!alloc_rx_agg(tp, GFP_KERNEL))
1826                         goto err1;
1827         }
1828
1829         for (i = 0; i < RTL8152_MAX_TX; i++) {
1830                 struct urb *urb;
1831                 u8 *buf;
1832
1833                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1834                 if (!buf)
1835                         goto err1;
1836
1837                 if (buf != tx_agg_align(buf)) {
1838                         kfree(buf);
1839                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1840                                            node);
1841                         if (!buf)
1842                                 goto err1;
1843                 }
1844
1845                 urb = usb_alloc_urb(0, GFP_KERNEL);
1846                 if (!urb) {
1847                         kfree(buf);
1848                         goto err1;
1849                 }
1850
1851                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1852                 tp->tx_info[i].context = tp;
1853                 tp->tx_info[i].urb = urb;
1854                 tp->tx_info[i].buffer = buf;
1855                 tp->tx_info[i].head = tx_agg_align(buf);
1856
1857                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1858         }
1859
1860         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1861         if (!tp->intr_urb)
1862                 goto err1;
1863
1864         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1865         if (!tp->intr_buff)
1866                 goto err1;
1867
1868         tp->intr_interval = (int)ep_intr->desc.bInterval;
1869         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1870                          tp->intr_buff, INTBUFSIZE, intr_callback,
1871                          tp, tp->intr_interval);
1872
1873         return 0;
1874
1875 err1:
1876         free_all_mem(tp);
1877         return -ENOMEM;
1878 }
1879
1880 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1881 {
1882         struct tx_agg *agg = NULL;
1883         unsigned long flags;
1884
1885         if (list_empty(&tp->tx_free))
1886                 return NULL;
1887
1888         spin_lock_irqsave(&tp->tx_lock, flags);
1889         if (!list_empty(&tp->tx_free)) {
1890                 struct list_head *cursor;
1891
1892                 cursor = tp->tx_free.next;
1893                 list_del_init(cursor);
1894                 agg = list_entry(cursor, struct tx_agg, list);
1895         }
1896         spin_unlock_irqrestore(&tp->tx_lock, flags);
1897
1898         return agg;
1899 }
1900
1901 /* r8152_csum_workaround()
1902  * The hw limits the value of the transport offset. When the offset is out of
1903  * range, calculate the checksum by sw.
1904  */
1905 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1906                                   struct sk_buff_head *list)
1907 {
1908         if (skb_shinfo(skb)->gso_size) {
1909                 netdev_features_t features = tp->netdev->features;
1910                 struct sk_buff *segs, *seg, *next;
1911                 struct sk_buff_head seg_list;
1912
1913                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1914                 segs = skb_gso_segment(skb, features);
1915                 if (IS_ERR(segs) || !segs)
1916                         goto drop;
1917
1918                 __skb_queue_head_init(&seg_list);
1919
1920                 skb_list_walk_safe(segs, seg, next) {
1921                         skb_mark_not_on_list(seg);
1922                         __skb_queue_tail(&seg_list, seg);
1923                 }
1924
1925                 skb_queue_splice(&seg_list, list);
1926                 dev_kfree_skb(skb);
1927         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1928                 if (skb_checksum_help(skb) < 0)
1929                         goto drop;
1930
1931                 __skb_queue_head(list, skb);
1932         } else {
1933                 struct net_device_stats *stats;
1934
1935 drop:
1936                 stats = &tp->netdev->stats;
1937                 stats->tx_dropped++;
1938                 dev_kfree_skb(skb);
1939         }
1940 }
1941
1942 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1943 {
1944         if (skb_vlan_tag_present(skb)) {
1945                 u32 opts2;
1946
1947                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1948                 desc->opts2 |= cpu_to_le32(opts2);
1949         }
1950 }
1951
1952 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1953 {
1954         u32 opts2 = le32_to_cpu(desc->opts2);
1955
1956         if (opts2 & RX_VLAN_TAG)
1957                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1958                                        swab16(opts2 & 0xffff));
1959 }
1960
1961 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1962                          struct sk_buff *skb, u32 len, u32 transport_offset)
1963 {
1964         u32 mss = skb_shinfo(skb)->gso_size;
1965         u32 opts1, opts2 = 0;
1966         int ret = TX_CSUM_SUCCESS;
1967
1968         WARN_ON_ONCE(len > TX_LEN_MAX);
1969
1970         opts1 = len | TX_FS | TX_LS;
1971
1972         if (mss) {
1973                 if (transport_offset > GTTCPHO_MAX) {
1974                         netif_warn(tp, tx_err, tp->netdev,
1975                                    "Invalid transport offset 0x%x for TSO\n",
1976                                    transport_offset);
1977                         ret = TX_CSUM_TSO;
1978                         goto unavailable;
1979                 }
1980
1981                 switch (vlan_get_protocol(skb)) {
1982                 case htons(ETH_P_IP):
1983                         opts1 |= GTSENDV4;
1984                         break;
1985
1986                 case htons(ETH_P_IPV6):
1987                         if (skb_cow_head(skb, 0)) {
1988                                 ret = TX_CSUM_TSO;
1989                                 goto unavailable;
1990                         }
1991                         tcp_v6_gso_csum_prep(skb);
1992                         opts1 |= GTSENDV6;
1993                         break;
1994
1995                 default:
1996                         WARN_ON_ONCE(1);
1997                         break;
1998                 }
1999
2000                 opts1 |= transport_offset << GTTCPHO_SHIFT;
2001                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2002         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2003                 u8 ip_protocol;
2004
2005                 if (transport_offset > TCPHO_MAX) {
2006                         netif_warn(tp, tx_err, tp->netdev,
2007                                    "Invalid transport offset 0x%x\n",
2008                                    transport_offset);
2009                         ret = TX_CSUM_NONE;
2010                         goto unavailable;
2011                 }
2012
2013                 switch (vlan_get_protocol(skb)) {
2014                 case htons(ETH_P_IP):
2015                         opts2 |= IPV4_CS;
2016                         ip_protocol = ip_hdr(skb)->protocol;
2017                         break;
2018
2019                 case htons(ETH_P_IPV6):
2020                         opts2 |= IPV6_CS;
2021                         ip_protocol = ipv6_hdr(skb)->nexthdr;
2022                         break;
2023
2024                 default:
2025                         ip_protocol = IPPROTO_RAW;
2026                         break;
2027                 }
2028
2029                 if (ip_protocol == IPPROTO_TCP)
2030                         opts2 |= TCP_CS;
2031                 else if (ip_protocol == IPPROTO_UDP)
2032                         opts2 |= UDP_CS;
2033                 else
2034                         WARN_ON_ONCE(1);
2035
2036                 opts2 |= transport_offset << TCPHO_SHIFT;
2037         }
2038
2039         desc->opts2 = cpu_to_le32(opts2);
2040         desc->opts1 = cpu_to_le32(opts1);
2041
2042 unavailable:
2043         return ret;
2044 }
2045
2046 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2047 {
2048         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2049         int remain, ret;
2050         u8 *tx_data;
2051
2052         __skb_queue_head_init(&skb_head);
2053         spin_lock(&tx_queue->lock);
2054         skb_queue_splice_init(tx_queue, &skb_head);
2055         spin_unlock(&tx_queue->lock);
2056
2057         tx_data = agg->head;
2058         agg->skb_num = 0;
2059         agg->skb_len = 0;
2060         remain = agg_buf_sz;
2061
2062         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2063                 struct tx_desc *tx_desc;
2064                 struct sk_buff *skb;
2065                 unsigned int len;
2066                 u32 offset;
2067
2068                 skb = __skb_dequeue(&skb_head);
2069                 if (!skb)
2070                         break;
2071
2072                 len = skb->len + sizeof(*tx_desc);
2073
2074                 if (len > remain) {
2075                         __skb_queue_head(&skb_head, skb);
2076                         break;
2077                 }
2078
2079                 tx_data = tx_agg_align(tx_data);
2080                 tx_desc = (struct tx_desc *)tx_data;
2081
2082                 offset = (u32)skb_transport_offset(skb);
2083
2084                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2085                         r8152_csum_workaround(tp, skb, &skb_head);
2086                         continue;
2087                 }
2088
2089                 rtl_tx_vlan_tag(tx_desc, skb);
2090
2091                 tx_data += sizeof(*tx_desc);
2092
2093                 len = skb->len;
2094                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2095                         struct net_device_stats *stats = &tp->netdev->stats;
2096
2097                         stats->tx_dropped++;
2098                         dev_kfree_skb_any(skb);
2099                         tx_data -= sizeof(*tx_desc);
2100                         continue;
2101                 }
2102
2103                 tx_data += len;
2104                 agg->skb_len += len;
2105                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2106
2107                 dev_kfree_skb_any(skb);
2108
2109                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2110
2111                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2112                         break;
2113         }
2114
2115         if (!skb_queue_empty(&skb_head)) {
2116                 spin_lock(&tx_queue->lock);
2117                 skb_queue_splice(&skb_head, tx_queue);
2118                 spin_unlock(&tx_queue->lock);
2119         }
2120
2121         netif_tx_lock(tp->netdev);
2122
2123         if (netif_queue_stopped(tp->netdev) &&
2124             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2125                 netif_wake_queue(tp->netdev);
2126
2127         netif_tx_unlock(tp->netdev);
2128
2129         ret = usb_autopm_get_interface_async(tp->intf);
2130         if (ret < 0)
2131                 goto out_tx_fill;
2132
2133         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2134                           agg->head, (int)(tx_data - (u8 *)agg->head),
2135                           (usb_complete_t)write_bulk_callback, agg);
2136
2137         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2138         if (ret < 0)
2139                 usb_autopm_put_interface_async(tp->intf);
2140
2141 out_tx_fill:
2142         return ret;
2143 }
2144
2145 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2146 {
2147         u8 checksum = CHECKSUM_NONE;
2148         u32 opts2, opts3;
2149
2150         if (!(tp->netdev->features & NETIF_F_RXCSUM))
2151                 goto return_result;
2152
2153         opts2 = le32_to_cpu(rx_desc->opts2);
2154         opts3 = le32_to_cpu(rx_desc->opts3);
2155
2156         if (opts2 & RD_IPV4_CS) {
2157                 if (opts3 & IPF)
2158                         checksum = CHECKSUM_NONE;
2159                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2160                         checksum = CHECKSUM_UNNECESSARY;
2161                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2162                         checksum = CHECKSUM_UNNECESSARY;
2163         } else if (opts2 & RD_IPV6_CS) {
2164                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2165                         checksum = CHECKSUM_UNNECESSARY;
2166                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2167                         checksum = CHECKSUM_UNNECESSARY;
2168         }
2169
2170 return_result:
2171         return checksum;
2172 }
2173
2174 static inline bool rx_count_exceed(struct r8152 *tp)
2175 {
2176         return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2177 }
2178
2179 static inline int agg_offset(struct rx_agg *agg, void *addr)
2180 {
2181         return (int)(addr - agg->buffer);
2182 }
2183
2184 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2185 {
2186         struct rx_agg *agg, *agg_next, *agg_free = NULL;
2187         unsigned long flags;
2188
2189         spin_lock_irqsave(&tp->rx_lock, flags);
2190
2191         list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2192                 if (page_count(agg->page) == 1) {
2193                         if (!agg_free) {
2194                                 list_del_init(&agg->list);
2195                                 agg_free = agg;
2196                                 continue;
2197                         }
2198                         if (rx_count_exceed(tp)) {
2199                                 list_del_init(&agg->list);
2200                                 free_rx_agg(tp, agg);
2201                         }
2202                         break;
2203                 }
2204         }
2205
2206         spin_unlock_irqrestore(&tp->rx_lock, flags);
2207
2208         if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2209                 agg_free = alloc_rx_agg(tp, mflags);
2210
2211         return agg_free;
2212 }
2213
2214 static int rx_bottom(struct r8152 *tp, int budget)
2215 {
2216         unsigned long flags;
2217         struct list_head *cursor, *next, rx_queue;
2218         int ret = 0, work_done = 0;
2219         struct napi_struct *napi = &tp->napi;
2220
2221         if (!skb_queue_empty(&tp->rx_queue)) {
2222                 while (work_done < budget) {
2223                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2224                         struct net_device *netdev = tp->netdev;
2225                         struct net_device_stats *stats = &netdev->stats;
2226                         unsigned int pkt_len;
2227
2228                         if (!skb)
2229                                 break;
2230
2231                         pkt_len = skb->len;
2232                         napi_gro_receive(napi, skb);
2233                         work_done++;
2234                         stats->rx_packets++;
2235                         stats->rx_bytes += pkt_len;
2236                 }
2237         }
2238
2239         if (list_empty(&tp->rx_done))
2240                 goto out1;
2241
2242         INIT_LIST_HEAD(&rx_queue);
2243         spin_lock_irqsave(&tp->rx_lock, flags);
2244         list_splice_init(&tp->rx_done, &rx_queue);
2245         spin_unlock_irqrestore(&tp->rx_lock, flags);
2246
2247         list_for_each_safe(cursor, next, &rx_queue) {
2248                 struct rx_desc *rx_desc;
2249                 struct rx_agg *agg, *agg_free;
2250                 int len_used = 0;
2251                 struct urb *urb;
2252                 u8 *rx_data;
2253
2254                 list_del_init(cursor);
2255
2256                 agg = list_entry(cursor, struct rx_agg, list);
2257                 urb = agg->urb;
2258                 if (urb->actual_length < ETH_ZLEN)
2259                         goto submit;
2260
2261                 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2262
2263                 rx_desc = agg->buffer;
2264                 rx_data = agg->buffer;
2265                 len_used += sizeof(struct rx_desc);
2266
2267                 while (urb->actual_length > len_used) {
2268                         struct net_device *netdev = tp->netdev;
2269                         struct net_device_stats *stats = &netdev->stats;
2270                         unsigned int pkt_len, rx_frag_head_sz;
2271                         struct sk_buff *skb;
2272
2273                         /* limite the skb numbers for rx_queue */
2274                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2275                                 break;
2276
2277                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2278                         if (pkt_len < ETH_ZLEN)
2279                                 break;
2280
2281                         len_used += pkt_len;
2282                         if (urb->actual_length < len_used)
2283                                 break;
2284
2285                         pkt_len -= ETH_FCS_LEN;
2286                         rx_data += sizeof(struct rx_desc);
2287
2288                         if (!agg_free || tp->rx_copybreak > pkt_len)
2289                                 rx_frag_head_sz = pkt_len;
2290                         else
2291                                 rx_frag_head_sz = tp->rx_copybreak;
2292
2293                         skb = napi_alloc_skb(napi, rx_frag_head_sz);
2294                         if (!skb) {
2295                                 stats->rx_dropped++;
2296                                 goto find_next_rx;
2297                         }
2298
2299                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2300                         memcpy(skb->data, rx_data, rx_frag_head_sz);
2301                         skb_put(skb, rx_frag_head_sz);
2302                         pkt_len -= rx_frag_head_sz;
2303                         rx_data += rx_frag_head_sz;
2304                         if (pkt_len) {
2305                                 skb_add_rx_frag(skb, 0, agg->page,
2306                                                 agg_offset(agg, rx_data),
2307                                                 pkt_len,
2308                                                 SKB_DATA_ALIGN(pkt_len));
2309                                 get_page(agg->page);
2310                         }
2311
2312                         skb->protocol = eth_type_trans(skb, netdev);
2313                         rtl_rx_vlan_tag(rx_desc, skb);
2314                         if (work_done < budget) {
2315                                 work_done++;
2316                                 stats->rx_packets++;
2317                                 stats->rx_bytes += skb->len;
2318                                 napi_gro_receive(napi, skb);
2319                         } else {
2320                                 __skb_queue_tail(&tp->rx_queue, skb);
2321                         }
2322
2323 find_next_rx:
2324                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2325                         rx_desc = (struct rx_desc *)rx_data;
2326                         len_used = agg_offset(agg, rx_data);
2327                         len_used += sizeof(struct rx_desc);
2328                 }
2329
2330                 WARN_ON(!agg_free && page_count(agg->page) > 1);
2331
2332                 if (agg_free) {
2333                         spin_lock_irqsave(&tp->rx_lock, flags);
2334                         if (page_count(agg->page) == 1) {
2335                                 list_add(&agg_free->list, &tp->rx_used);
2336                         } else {
2337                                 list_add_tail(&agg->list, &tp->rx_used);
2338                                 agg = agg_free;
2339                                 urb = agg->urb;
2340                         }
2341                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2342                 }
2343
2344 submit:
2345                 if (!ret) {
2346                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2347                 } else {
2348                         urb->actual_length = 0;
2349                         list_add_tail(&agg->list, next);
2350                 }
2351         }
2352
2353         if (!list_empty(&rx_queue)) {
2354                 spin_lock_irqsave(&tp->rx_lock, flags);
2355                 list_splice_tail(&rx_queue, &tp->rx_done);
2356                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2357         }
2358
2359 out1:
2360         return work_done;
2361 }
2362
2363 static void tx_bottom(struct r8152 *tp)
2364 {
2365         int res;
2366
2367         do {
2368                 struct net_device *netdev = tp->netdev;
2369                 struct tx_agg *agg;
2370
2371                 if (skb_queue_empty(&tp->tx_queue))
2372                         break;
2373
2374                 agg = r8152_get_tx_agg(tp);
2375                 if (!agg)
2376                         break;
2377
2378                 res = r8152_tx_agg_fill(tp, agg);
2379                 if (!res)
2380                         continue;
2381
2382                 if (res == -ENODEV) {
2383                         rtl_set_unplug(tp);
2384                         netif_device_detach(netdev);
2385                 } else {
2386                         struct net_device_stats *stats = &netdev->stats;
2387                         unsigned long flags;
2388
2389                         netif_warn(tp, tx_err, netdev,
2390                                    "failed tx_urb %d\n", res);
2391                         stats->tx_dropped += agg->skb_num;
2392
2393                         spin_lock_irqsave(&tp->tx_lock, flags);
2394                         list_add_tail(&agg->list, &tp->tx_free);
2395                         spin_unlock_irqrestore(&tp->tx_lock, flags);
2396                 }
2397         } while (res == 0);
2398 }
2399
2400 static void bottom_half(struct tasklet_struct *t)
2401 {
2402         struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2403
2404         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2405                 return;
2406
2407         if (!test_bit(WORK_ENABLE, &tp->flags))
2408                 return;
2409
2410         /* When link down, the driver would cancel all bulks. */
2411         /* This avoid the re-submitting bulk */
2412         if (!netif_carrier_ok(tp->netdev))
2413                 return;
2414
2415         clear_bit(SCHEDULE_TASKLET, &tp->flags);
2416
2417         tx_bottom(tp);
2418 }
2419
2420 static int r8152_poll(struct napi_struct *napi, int budget)
2421 {
2422         struct r8152 *tp = container_of(napi, struct r8152, napi);
2423         int work_done;
2424
2425         work_done = rx_bottom(tp, budget);
2426
2427         if (work_done < budget) {
2428                 if (!napi_complete_done(napi, work_done))
2429                         goto out;
2430                 if (!list_empty(&tp->rx_done))
2431                         napi_schedule(napi);
2432         }
2433
2434 out:
2435         return work_done;
2436 }
2437
2438 static
2439 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2440 {
2441         int ret;
2442
2443         /* The rx would be stopped, so skip submitting */
2444         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2445             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2446                 return 0;
2447
2448         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2449                           agg->buffer, tp->rx_buf_sz,
2450                           (usb_complete_t)read_bulk_callback, agg);
2451
2452         ret = usb_submit_urb(agg->urb, mem_flags);
2453         if (ret == -ENODEV) {
2454                 rtl_set_unplug(tp);
2455                 netif_device_detach(tp->netdev);
2456         } else if (ret) {
2457                 struct urb *urb = agg->urb;
2458                 unsigned long flags;
2459
2460                 urb->actual_length = 0;
2461                 spin_lock_irqsave(&tp->rx_lock, flags);
2462                 list_add_tail(&agg->list, &tp->rx_done);
2463                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2464
2465                 netif_err(tp, rx_err, tp->netdev,
2466                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2467
2468                 napi_schedule(&tp->napi);
2469         }
2470
2471         return ret;
2472 }
2473
2474 static void rtl_drop_queued_tx(struct r8152 *tp)
2475 {
2476         struct net_device_stats *stats = &tp->netdev->stats;
2477         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2478         struct sk_buff *skb;
2479
2480         if (skb_queue_empty(tx_queue))
2481                 return;
2482
2483         __skb_queue_head_init(&skb_head);
2484         spin_lock_bh(&tx_queue->lock);
2485         skb_queue_splice_init(tx_queue, &skb_head);
2486         spin_unlock_bh(&tx_queue->lock);
2487
2488         while ((skb = __skb_dequeue(&skb_head))) {
2489                 dev_kfree_skb(skb);
2490                 stats->tx_dropped++;
2491         }
2492 }
2493
2494 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2495 {
2496         struct r8152 *tp = netdev_priv(netdev);
2497
2498         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2499
2500         usb_queue_reset_device(tp->intf);
2501 }
2502
2503 static void rtl8152_set_rx_mode(struct net_device *netdev)
2504 {
2505         struct r8152 *tp = netdev_priv(netdev);
2506
2507         if (netif_carrier_ok(netdev)) {
2508                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2509                 schedule_delayed_work(&tp->schedule, 0);
2510         }
2511 }
2512
2513 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2514 {
2515         struct r8152 *tp = netdev_priv(netdev);
2516         u32 mc_filter[2];       /* Multicast hash filter */
2517         __le32 tmp[2];
2518         u32 ocp_data;
2519
2520         netif_stop_queue(netdev);
2521         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2522         ocp_data &= ~RCR_ACPT_ALL;
2523         ocp_data |= RCR_AB | RCR_APM;
2524
2525         if (netdev->flags & IFF_PROMISC) {
2526                 /* Unconditionally log net taps. */
2527                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2528                 ocp_data |= RCR_AM | RCR_AAP;
2529                 mc_filter[1] = 0xffffffff;
2530                 mc_filter[0] = 0xffffffff;
2531         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2532                    (netdev->flags & IFF_ALLMULTI)) {
2533                 /* Too many to filter perfectly -- accept all multicasts. */
2534                 ocp_data |= RCR_AM;
2535                 mc_filter[1] = 0xffffffff;
2536                 mc_filter[0] = 0xffffffff;
2537         } else {
2538                 struct netdev_hw_addr *ha;
2539
2540                 mc_filter[1] = 0;
2541                 mc_filter[0] = 0;
2542                 netdev_for_each_mc_addr(ha, netdev) {
2543                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2544
2545                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2546                         ocp_data |= RCR_AM;
2547                 }
2548         }
2549
2550         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2551         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2552
2553         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2554         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2555         netif_wake_queue(netdev);
2556 }
2557
2558 static netdev_features_t
2559 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2560                        netdev_features_t features)
2561 {
2562         u32 mss = skb_shinfo(skb)->gso_size;
2563         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2564         int offset = skb_transport_offset(skb);
2565
2566         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2567                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2568         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2569                 features &= ~NETIF_F_GSO_MASK;
2570
2571         return features;
2572 }
2573
2574 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2575                                       struct net_device *netdev)
2576 {
2577         struct r8152 *tp = netdev_priv(netdev);
2578
2579         skb_tx_timestamp(skb);
2580
2581         skb_queue_tail(&tp->tx_queue, skb);
2582
2583         if (!list_empty(&tp->tx_free)) {
2584                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2585                         set_bit(SCHEDULE_TASKLET, &tp->flags);
2586                         schedule_delayed_work(&tp->schedule, 0);
2587                 } else {
2588                         usb_mark_last_busy(tp->udev);
2589                         tasklet_schedule(&tp->tx_tl);
2590                 }
2591         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2592                 netif_stop_queue(netdev);
2593         }
2594
2595         return NETDEV_TX_OK;
2596 }
2597
2598 static void r8152b_reset_packet_filter(struct r8152 *tp)
2599 {
2600         u32     ocp_data;
2601
2602         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2603         ocp_data &= ~FMC_FCR_MCU_EN;
2604         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2605         ocp_data |= FMC_FCR_MCU_EN;
2606         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2607 }
2608
2609 static void rtl8152_nic_reset(struct r8152 *tp)
2610 {
2611         int     i;
2612
2613         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2614
2615         for (i = 0; i < 1000; i++) {
2616                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2617                         break;
2618                 usleep_range(100, 400);
2619         }
2620 }
2621
2622 static void set_tx_qlen(struct r8152 *tp)
2623 {
2624         struct net_device *netdev = tp->netdev;
2625
2626         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2627                                     sizeof(struct tx_desc));
2628 }
2629
2630 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2631 {
2632         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2633 }
2634
2635 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2636 {
2637         u32 ocp_data;
2638
2639         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2640         if (enable)
2641                 ocp_data |= EEEP_CR_EEEP_TX;
2642         else
2643                 ocp_data &= ~EEEP_CR_EEEP_TX;
2644         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2645 }
2646
2647 static void rtl_set_eee_plus(struct r8152 *tp)
2648 {
2649         if (rtl8152_get_speed(tp) & _10bps)
2650                 rtl_eee_plus_en(tp, true);
2651         else
2652                 rtl_eee_plus_en(tp, false);
2653 }
2654
2655 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2656 {
2657         u32 ocp_data;
2658
2659         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2660         if (enable)
2661                 ocp_data |= RXDY_GATED_EN;
2662         else
2663                 ocp_data &= ~RXDY_GATED_EN;
2664         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2665 }
2666
2667 static int rtl_start_rx(struct r8152 *tp)
2668 {
2669         struct rx_agg *agg, *agg_next;
2670         struct list_head tmp_list;
2671         unsigned long flags;
2672         int ret = 0, i = 0;
2673
2674         INIT_LIST_HEAD(&tmp_list);
2675
2676         spin_lock_irqsave(&tp->rx_lock, flags);
2677
2678         INIT_LIST_HEAD(&tp->rx_done);
2679         INIT_LIST_HEAD(&tp->rx_used);
2680
2681         list_splice_init(&tp->rx_info, &tmp_list);
2682
2683         spin_unlock_irqrestore(&tp->rx_lock, flags);
2684
2685         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2686                 INIT_LIST_HEAD(&agg->list);
2687
2688                 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2689                 if (++i > RTL8152_MAX_RX) {
2690                         spin_lock_irqsave(&tp->rx_lock, flags);
2691                         list_add_tail(&agg->list, &tp->rx_used);
2692                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2693                 } else if (unlikely(ret < 0)) {
2694                         spin_lock_irqsave(&tp->rx_lock, flags);
2695                         list_add_tail(&agg->list, &tp->rx_done);
2696                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2697                 } else {
2698                         ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2699                 }
2700         }
2701
2702         spin_lock_irqsave(&tp->rx_lock, flags);
2703         WARN_ON(!list_empty(&tp->rx_info));
2704         list_splice(&tmp_list, &tp->rx_info);
2705         spin_unlock_irqrestore(&tp->rx_lock, flags);
2706
2707         return ret;
2708 }
2709
2710 static int rtl_stop_rx(struct r8152 *tp)
2711 {
2712         struct rx_agg *agg, *agg_next;
2713         struct list_head tmp_list;
2714         unsigned long flags;
2715
2716         INIT_LIST_HEAD(&tmp_list);
2717
2718         /* The usb_kill_urb() couldn't be used in atomic.
2719          * Therefore, move the list of rx_info to a tmp one.
2720          * Then, list_for_each_entry_safe could be used without
2721          * spin lock.
2722          */
2723
2724         spin_lock_irqsave(&tp->rx_lock, flags);
2725         list_splice_init(&tp->rx_info, &tmp_list);
2726         spin_unlock_irqrestore(&tp->rx_lock, flags);
2727
2728         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2729                 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2730                  * equal to 1, so the other ones could be freed safely.
2731                  */
2732                 if (page_count(agg->page) > 1)
2733                         free_rx_agg(tp, agg);
2734                 else
2735                         usb_kill_urb(agg->urb);
2736         }
2737
2738         /* Move back the list of temp to the rx_info */
2739         spin_lock_irqsave(&tp->rx_lock, flags);
2740         WARN_ON(!list_empty(&tp->rx_info));
2741         list_splice(&tmp_list, &tp->rx_info);
2742         spin_unlock_irqrestore(&tp->rx_lock, flags);
2743
2744         while (!skb_queue_empty(&tp->rx_queue))
2745                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2746
2747         return 0;
2748 }
2749
2750 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2751 {
2752         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2753                        OWN_UPDATE | OWN_CLEAR);
2754 }
2755
2756 static int rtl_enable(struct r8152 *tp)
2757 {
2758         u32 ocp_data;
2759
2760         r8152b_reset_packet_filter(tp);
2761
2762         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2763         ocp_data |= CR_RE | CR_TE;
2764         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2765
2766         switch (tp->version) {
2767         case RTL_VER_08:
2768         case RTL_VER_09:
2769                 r8153b_rx_agg_chg_indicate(tp);
2770                 break;
2771         default:
2772                 break;
2773         }
2774
2775         rxdy_gated_en(tp, false);
2776
2777         return 0;
2778 }
2779
2780 static int rtl8152_enable(struct r8152 *tp)
2781 {
2782         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2783                 return -ENODEV;
2784
2785         set_tx_qlen(tp);
2786         rtl_set_eee_plus(tp);
2787
2788         return rtl_enable(tp);
2789 }
2790
2791 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2792 {
2793         u32 ocp_data = tp->coalesce / 8;
2794
2795         switch (tp->version) {
2796         case RTL_VER_03:
2797         case RTL_VER_04:
2798         case RTL_VER_05:
2799         case RTL_VER_06:
2800                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2801                                ocp_data);
2802                 break;
2803
2804         case RTL_VER_08:
2805         case RTL_VER_09:
2806                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2807                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2808                  */
2809                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2810                                128 / 8);
2811                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2812                                ocp_data);
2813                 break;
2814
2815         default:
2816                 break;
2817         }
2818 }
2819
2820 static void r8153_set_rx_early_size(struct r8152 *tp)
2821 {
2822         u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2823
2824         switch (tp->version) {
2825         case RTL_VER_03:
2826         case RTL_VER_04:
2827         case RTL_VER_05:
2828         case RTL_VER_06:
2829                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2830                                ocp_data / 4);
2831                 break;
2832         case RTL_VER_08:
2833         case RTL_VER_09:
2834                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2835                                ocp_data / 8);
2836                 break;
2837         default:
2838                 WARN_ON_ONCE(1);
2839                 break;
2840         }
2841 }
2842
2843 static int rtl8153_enable(struct r8152 *tp)
2844 {
2845         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2846                 return -ENODEV;
2847
2848         set_tx_qlen(tp);
2849         rtl_set_eee_plus(tp);
2850         r8153_set_rx_early_timeout(tp);
2851         r8153_set_rx_early_size(tp);
2852
2853         if (tp->version == RTL_VER_09) {
2854                 u32 ocp_data;
2855
2856                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2857                 ocp_data &= ~FC_PATCH_TASK;
2858                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2859                 usleep_range(1000, 2000);
2860                 ocp_data |= FC_PATCH_TASK;
2861                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2862         }
2863
2864         return rtl_enable(tp);
2865 }
2866
2867 static void rtl_disable(struct r8152 *tp)
2868 {
2869         u32 ocp_data;
2870         int i;
2871
2872         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2873                 rtl_drop_queued_tx(tp);
2874                 return;
2875         }
2876
2877         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2878         ocp_data &= ~RCR_ACPT_ALL;
2879         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2880
2881         rtl_drop_queued_tx(tp);
2882
2883         for (i = 0; i < RTL8152_MAX_TX; i++)
2884                 usb_kill_urb(tp->tx_info[i].urb);
2885
2886         rxdy_gated_en(tp, true);
2887
2888         for (i = 0; i < 1000; i++) {
2889                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2890                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2891                         break;
2892                 usleep_range(1000, 2000);
2893         }
2894
2895         for (i = 0; i < 1000; i++) {
2896                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2897                         break;
2898                 usleep_range(1000, 2000);
2899         }
2900
2901         rtl_stop_rx(tp);
2902
2903         rtl8152_nic_reset(tp);
2904 }
2905
2906 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2907 {
2908         u32 ocp_data;
2909
2910         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2911         if (enable)
2912                 ocp_data |= POWER_CUT;
2913         else
2914                 ocp_data &= ~POWER_CUT;
2915         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2916
2917         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2918         ocp_data &= ~RESUME_INDICATE;
2919         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2920 }
2921
2922 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2923 {
2924         u32 ocp_data;
2925
2926         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2927         if (enable)
2928                 ocp_data |= CPCR_RX_VLAN;
2929         else
2930                 ocp_data &= ~CPCR_RX_VLAN;
2931         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2932 }
2933
2934 static int rtl8152_set_features(struct net_device *dev,
2935                                 netdev_features_t features)
2936 {
2937         netdev_features_t changed = features ^ dev->features;
2938         struct r8152 *tp = netdev_priv(dev);
2939         int ret;
2940
2941         ret = usb_autopm_get_interface(tp->intf);
2942         if (ret < 0)
2943                 goto out;
2944
2945         mutex_lock(&tp->control);
2946
2947         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2948                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2949                         rtl_rx_vlan_en(tp, true);
2950                 else
2951                         rtl_rx_vlan_en(tp, false);
2952         }
2953
2954         mutex_unlock(&tp->control);
2955
2956         usb_autopm_put_interface(tp->intf);
2957
2958 out:
2959         return ret;
2960 }
2961
2962 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2963
2964 static u32 __rtl_get_wol(struct r8152 *tp)
2965 {
2966         u32 ocp_data;
2967         u32 wolopts = 0;
2968
2969         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2970         if (ocp_data & LINK_ON_WAKE_EN)
2971                 wolopts |= WAKE_PHY;
2972
2973         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2974         if (ocp_data & UWF_EN)
2975                 wolopts |= WAKE_UCAST;
2976         if (ocp_data & BWF_EN)
2977                 wolopts |= WAKE_BCAST;
2978         if (ocp_data & MWF_EN)
2979                 wolopts |= WAKE_MCAST;
2980
2981         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2982         if (ocp_data & MAGIC_EN)
2983                 wolopts |= WAKE_MAGIC;
2984
2985         return wolopts;
2986 }
2987
2988 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2989 {
2990         u32 ocp_data;
2991
2992         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2993
2994         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2995         ocp_data &= ~LINK_ON_WAKE_EN;
2996         if (wolopts & WAKE_PHY)
2997                 ocp_data |= LINK_ON_WAKE_EN;
2998         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2999
3000         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3001         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3002         if (wolopts & WAKE_UCAST)
3003                 ocp_data |= UWF_EN;
3004         if (wolopts & WAKE_BCAST)
3005                 ocp_data |= BWF_EN;
3006         if (wolopts & WAKE_MCAST)
3007                 ocp_data |= MWF_EN;
3008         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3009
3010         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3011
3012         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3013         ocp_data &= ~MAGIC_EN;
3014         if (wolopts & WAKE_MAGIC)
3015                 ocp_data |= MAGIC_EN;
3016         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3017
3018         if (wolopts & WAKE_ANY)
3019                 device_set_wakeup_enable(&tp->udev->dev, true);
3020         else
3021                 device_set_wakeup_enable(&tp->udev->dev, false);
3022 }
3023
3024 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3025 {
3026         u8 u1u2[8];
3027
3028         if (enable)
3029                 memset(u1u2, 0xff, sizeof(u1u2));
3030         else
3031                 memset(u1u2, 0x00, sizeof(u1u2));
3032
3033         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3034 }
3035
3036 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3037 {
3038         u32 ocp_data;
3039
3040         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3041         if (enable)
3042                 ocp_data |= LPM_U1U2_EN;
3043         else
3044                 ocp_data &= ~LPM_U1U2_EN;
3045
3046         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3047 }
3048
3049 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3050 {
3051         u32 ocp_data;
3052
3053         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3054         if (enable)
3055                 ocp_data |= U2P3_ENABLE;
3056         else
3057                 ocp_data &= ~U2P3_ENABLE;
3058         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3059 }
3060
3061 static void r8153b_ups_flags(struct r8152 *tp)
3062 {
3063         u32 ups_flags = 0;
3064
3065         if (tp->ups_info.green)
3066                 ups_flags |= UPS_FLAGS_EN_GREEN;
3067
3068         if (tp->ups_info.aldps)
3069                 ups_flags |= UPS_FLAGS_EN_ALDPS;
3070
3071         if (tp->ups_info.eee)
3072                 ups_flags |= UPS_FLAGS_EN_EEE;
3073
3074         if (tp->ups_info.flow_control)
3075                 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3076
3077         if (tp->ups_info.eee_ckdiv)
3078                 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3079
3080         if (tp->ups_info.eee_cmod_lv)
3081                 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3082
3083         if (tp->ups_info._10m_ckdiv)
3084                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3085
3086         if (tp->ups_info.eee_plloff_100)
3087                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3088
3089         if (tp->ups_info.eee_plloff_giga)
3090                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3091
3092         if (tp->ups_info._250m_ckdiv)
3093                 ups_flags |= UPS_FLAGS_250M_CKDIV;
3094
3095         if (tp->ups_info.ctap_short_off)
3096                 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3097
3098         switch (tp->ups_info.speed_duplex) {
3099         case NWAY_10M_HALF:
3100                 ups_flags |= ups_flags_speed(1);
3101                 break;
3102         case NWAY_10M_FULL:
3103                 ups_flags |= ups_flags_speed(2);
3104                 break;
3105         case NWAY_100M_HALF:
3106                 ups_flags |= ups_flags_speed(3);
3107                 break;
3108         case NWAY_100M_FULL:
3109                 ups_flags |= ups_flags_speed(4);
3110                 break;
3111         case NWAY_1000M_FULL:
3112                 ups_flags |= ups_flags_speed(5);
3113                 break;
3114         case FORCE_10M_HALF:
3115                 ups_flags |= ups_flags_speed(6);
3116                 break;
3117         case FORCE_10M_FULL:
3118                 ups_flags |= ups_flags_speed(7);
3119                 break;
3120         case FORCE_100M_HALF:
3121                 ups_flags |= ups_flags_speed(8);
3122                 break;
3123         case FORCE_100M_FULL:
3124                 ups_flags |= ups_flags_speed(9);
3125                 break;
3126         default:
3127                 break;
3128         }
3129
3130         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3131 }
3132
3133 static void rtl_green_en(struct r8152 *tp, bool enable)
3134 {
3135         u16 data;
3136
3137         data = sram_read(tp, SRAM_GREEN_CFG);
3138         if (enable)
3139                 data |= GREEN_ETH_EN;
3140         else
3141                 data &= ~GREEN_ETH_EN;
3142         sram_write(tp, SRAM_GREEN_CFG, data);
3143
3144         tp->ups_info.green = enable;
3145 }
3146
3147 static void r8153b_green_en(struct r8152 *tp, bool enable)
3148 {
3149         if (enable) {
3150                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
3151                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3152                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3153         } else {
3154                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3155                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3156                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3157         }
3158
3159         rtl_green_en(tp, true);
3160 }
3161
3162 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3163 {
3164         u16 data;
3165         int i;
3166
3167         for (i = 0; i < 500; i++) {
3168                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3169                 data &= PHY_STAT_MASK;
3170                 if (desired) {
3171                         if (data == desired)
3172                                 break;
3173                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3174                            data == PHY_STAT_EXT_INIT) {
3175                         break;
3176                 }
3177
3178                 msleep(20);
3179                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3180                         break;
3181         }
3182
3183         return data;
3184 }
3185
3186 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3187 {
3188         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3189
3190         if (enable) {
3191                 r8153b_ups_flags(tp);
3192
3193                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3194                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3195
3196                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3197                 ocp_data |= BIT(0);
3198                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3199         } else {
3200                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3201                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3202
3203                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3204                 ocp_data &= ~BIT(0);
3205                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3206
3207                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3208                         int i;
3209
3210                         for (i = 0; i < 500; i++) {
3211                                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3212                                     AUTOLOAD_DONE)
3213                                         break;
3214                                 msleep(20);
3215                         }
3216
3217                         tp->rtl_ops.hw_phy_cfg(tp);
3218
3219                         rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3220                                           tp->duplex, tp->advertising);
3221                 }
3222         }
3223 }
3224
3225 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3226 {
3227         u32 ocp_data;
3228
3229         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3230         if (enable)
3231                 ocp_data |= PWR_EN | PHASE2_EN;
3232         else
3233                 ocp_data &= ~(PWR_EN | PHASE2_EN);
3234         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3235
3236         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3237         ocp_data &= ~PCUT_STATUS;
3238         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3239 }
3240
3241 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3242 {
3243         u32 ocp_data;
3244
3245         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3246         if (enable)
3247                 ocp_data |= PWR_EN | PHASE2_EN;
3248         else
3249                 ocp_data &= ~PWR_EN;
3250         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3251
3252         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3253         ocp_data &= ~PCUT_STATUS;
3254         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3255 }
3256
3257 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3258 {
3259         u32 ocp_data;
3260
3261         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3262         if (enable)
3263                 ocp_data |= UPCOMING_RUNTIME_D3;
3264         else
3265                 ocp_data &= ~UPCOMING_RUNTIME_D3;
3266         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3267
3268         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3269         ocp_data &= ~LINK_CHG_EVENT;
3270         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3271
3272         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3273         ocp_data &= ~LINK_CHANGE_FLAG;
3274         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3275 }
3276
3277 static bool rtl_can_wakeup(struct r8152 *tp)
3278 {
3279         struct usb_device *udev = tp->udev;
3280
3281         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3282 }
3283
3284 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3285 {
3286         if (enable) {
3287                 u32 ocp_data;
3288
3289                 __rtl_set_wol(tp, WAKE_ANY);
3290
3291                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3292
3293                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3294                 ocp_data |= LINK_OFF_WAKE_EN;
3295                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3296
3297                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3298         } else {
3299                 u32 ocp_data;
3300
3301                 __rtl_set_wol(tp, tp->saved_wolopts);
3302
3303                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3304
3305                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3306                 ocp_data &= ~LINK_OFF_WAKE_EN;
3307                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3308
3309                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3310         }
3311 }
3312
3313 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3314 {
3315         if (enable) {
3316                 r8153_u1u2en(tp, false);
3317                 r8153_u2p3en(tp, false);
3318                 rtl_runtime_suspend_enable(tp, true);
3319         } else {
3320                 rtl_runtime_suspend_enable(tp, false);
3321
3322                 switch (tp->version) {
3323                 case RTL_VER_03:
3324                 case RTL_VER_04:
3325                         break;
3326                 case RTL_VER_05:
3327                 case RTL_VER_06:
3328                 default:
3329                         r8153_u2p3en(tp, true);
3330                         break;
3331                 }
3332
3333                 r8153_u1u2en(tp, true);
3334         }
3335 }
3336
3337 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3338 {
3339         if (enable) {
3340                 r8153_queue_wake(tp, true);
3341                 r8153b_u1u2en(tp, false);
3342                 r8153_u2p3en(tp, false);
3343                 rtl_runtime_suspend_enable(tp, true);
3344                 r8153b_ups_en(tp, true);
3345         } else {
3346                 r8153b_ups_en(tp, false);
3347                 r8153_queue_wake(tp, false);
3348                 rtl_runtime_suspend_enable(tp, false);
3349                 if (tp->udev->speed >= USB_SPEED_SUPER)
3350                         r8153b_u1u2en(tp, true);
3351         }
3352 }
3353
3354 static void r8153_teredo_off(struct r8152 *tp)
3355 {
3356         u32 ocp_data;
3357
3358         switch (tp->version) {
3359         case RTL_VER_01:
3360         case RTL_VER_02:
3361         case RTL_VER_03:
3362         case RTL_VER_04:
3363         case RTL_VER_05:
3364         case RTL_VER_06:
3365         case RTL_VER_07:
3366                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3367                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3368                               OOB_TEREDO_EN);
3369                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3370                 break;
3371
3372         case RTL_VER_08:
3373         case RTL_VER_09:
3374                 /* The bit 0 ~ 7 are relative with teredo settings. They are
3375                  * W1C (write 1 to clear), so set all 1 to disable it.
3376                  */
3377                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3378                 break;
3379
3380         default:
3381                 break;
3382         }
3383
3384         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3385         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3386         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3387 }
3388
3389 static void rtl_reset_bmu(struct r8152 *tp)
3390 {
3391         u32 ocp_data;
3392
3393         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3394         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3395         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3396         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3397         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3398 }
3399
3400 /* Clear the bp to stop the firmware before loading a new one */
3401 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3402 {
3403         switch (tp->version) {
3404         case RTL_VER_01:
3405         case RTL_VER_02:
3406         case RTL_VER_07:
3407                 break;
3408         case RTL_VER_03:
3409         case RTL_VER_04:
3410         case RTL_VER_05:
3411         case RTL_VER_06:
3412                 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3413                 break;
3414         case RTL_VER_08:
3415         case RTL_VER_09:
3416         default:
3417                 if (type == MCU_TYPE_USB) {
3418                         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3419
3420                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3421                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3422                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3423                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3424                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3425                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3426                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3427                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3428                 } else {
3429                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3430                 }
3431                 break;
3432         }
3433
3434         ocp_write_word(tp, type, PLA_BP_0, 0);
3435         ocp_write_word(tp, type, PLA_BP_1, 0);
3436         ocp_write_word(tp, type, PLA_BP_2, 0);
3437         ocp_write_word(tp, type, PLA_BP_3, 0);
3438         ocp_write_word(tp, type, PLA_BP_4, 0);
3439         ocp_write_word(tp, type, PLA_BP_5, 0);
3440         ocp_write_word(tp, type, PLA_BP_6, 0);
3441         ocp_write_word(tp, type, PLA_BP_7, 0);
3442
3443         /* wait 3 ms to make sure the firmware is stopped */
3444         usleep_range(3000, 6000);
3445         ocp_write_word(tp, type, PLA_BP_BA, 0);
3446 }
3447
3448 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
3449 {
3450         u16 data, check;
3451         int i;
3452
3453         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3454         if (request) {
3455                 data |= PATCH_REQUEST;
3456                 check = 0;
3457         } else {
3458                 data &= ~PATCH_REQUEST;
3459                 check = PATCH_READY;
3460         }
3461         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3462
3463         for (i = 0; wait && i < 5000; i++) {
3464                 u32 ocp_data;
3465
3466                 usleep_range(1000, 2000);
3467                 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
3468                 if ((ocp_data & PATCH_READY) ^ check)
3469                         break;
3470         }
3471
3472         if (request && wait &&
3473             !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3474                 dev_err(&tp->intf->dev, "PHY patch request fail\n");
3475                 rtl_phy_patch_request(tp, false, false);
3476                 return -ETIME;
3477         } else {
3478                 return 0;
3479         }
3480 }
3481
3482 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
3483 {
3484         if (patch_key && key_addr) {
3485                 sram_write(tp, key_addr, patch_key);
3486                 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3487         } else if (key_addr) {
3488                 u16 data;
3489
3490                 sram_write(tp, 0x0000, 0x0000);
3491
3492                 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3493                 data &= ~PATCH_LOCK;
3494                 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3495
3496                 sram_write(tp, key_addr, 0x0000);
3497         } else {
3498                 WARN_ON_ONCE(1);
3499         }
3500 }
3501
3502 static int
3503 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
3504 {
3505         if (rtl_phy_patch_request(tp, true, wait))
3506                 return -ETIME;
3507
3508         rtl_patch_key_set(tp, key_addr, patch_key);
3509
3510         return 0;
3511 }
3512
3513 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
3514 {
3515         rtl_patch_key_set(tp, key_addr, 0);
3516
3517         rtl_phy_patch_request(tp, false, wait);
3518
3519         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3520
3521         return 0;
3522 }
3523
3524 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3525 {
3526         u32 length;
3527         u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3528         bool rc = false;
3529
3530         switch (tp->version) {
3531         case RTL_VER_04:
3532         case RTL_VER_05:
3533         case RTL_VER_06:
3534                 fw_reg = 0xa014;
3535                 ba_reg = 0xa012;
3536                 patch_en_addr = 0xa01a;
3537                 mode_reg = 0xb820;
3538                 bp_start = 0xa000;
3539                 break;
3540         default:
3541                 goto out;
3542         }
3543
3544         fw_offset = __le16_to_cpu(phy->fw_offset);
3545         if (fw_offset < sizeof(*phy)) {
3546                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3547                 goto out;
3548         }
3549
3550         length = __le32_to_cpu(phy->blk_hdr.length);
3551         if (length < fw_offset) {
3552                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3553                 goto out;
3554         }
3555
3556         length -= __le16_to_cpu(phy->fw_offset);
3557         if (!length || (length & 1)) {
3558                 dev_err(&tp->intf->dev, "invalid block length\n");
3559                 goto out;
3560         }
3561
3562         if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3563                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3564                 goto out;
3565         }
3566
3567         if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3568                 dev_err(&tp->intf->dev, "invalid base address register\n");
3569                 goto out;
3570         }
3571
3572         if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3573                 dev_err(&tp->intf->dev,
3574                         "invalid patch mode enabled register\n");
3575                 goto out;
3576         }
3577
3578         if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3579                 dev_err(&tp->intf->dev,
3580                         "invalid register to switch the mode\n");
3581                 goto out;
3582         }
3583
3584         if (__le16_to_cpu(phy->bp_start) != bp_start) {
3585                 dev_err(&tp->intf->dev,
3586                         "invalid start register of break point\n");
3587                 goto out;
3588         }
3589
3590         if (__le16_to_cpu(phy->bp_num) > 4) {
3591                 dev_err(&tp->intf->dev, "invalid break point number\n");
3592                 goto out;
3593         }
3594
3595         rc = true;
3596 out:
3597         return rc;
3598 }
3599
3600 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3601 {
3602         u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3603         bool rc = false;
3604         u32 length, type;
3605         int i, max_bp;
3606
3607         type = __le32_to_cpu(mac->blk_hdr.type);
3608         if (type == RTL_FW_PLA) {
3609                 switch (tp->version) {
3610                 case RTL_VER_01:
3611                 case RTL_VER_02:
3612                 case RTL_VER_07:
3613                         fw_reg = 0xf800;
3614                         bp_ba_addr = PLA_BP_BA;
3615                         bp_en_addr = 0;
3616                         bp_start = PLA_BP_0;
3617                         max_bp = 8;
3618                         break;
3619                 case RTL_VER_03:
3620                 case RTL_VER_04:
3621                 case RTL_VER_05:
3622                 case RTL_VER_06:
3623                 case RTL_VER_08:
3624                 case RTL_VER_09:
3625                         fw_reg = 0xf800;
3626                         bp_ba_addr = PLA_BP_BA;
3627                         bp_en_addr = PLA_BP_EN;
3628                         bp_start = PLA_BP_0;
3629                         max_bp = 8;
3630                         break;
3631                 default:
3632                         goto out;
3633                 }
3634         } else if (type == RTL_FW_USB) {
3635                 switch (tp->version) {
3636                 case RTL_VER_03:
3637                 case RTL_VER_04:
3638                 case RTL_VER_05:
3639                 case RTL_VER_06:
3640                         fw_reg = 0xf800;
3641                         bp_ba_addr = USB_BP_BA;
3642                         bp_en_addr = USB_BP_EN;
3643                         bp_start = USB_BP_0;
3644                         max_bp = 8;
3645                         break;
3646                 case RTL_VER_08:
3647                 case RTL_VER_09:
3648                         fw_reg = 0xe600;
3649                         bp_ba_addr = USB_BP_BA;
3650                         bp_en_addr = USB_BP2_EN;
3651                         bp_start = USB_BP_0;
3652                         max_bp = 16;
3653                         break;
3654                 case RTL_VER_01:
3655                 case RTL_VER_02:
3656                 case RTL_VER_07:
3657                 default:
3658                         goto out;
3659                 }
3660         } else {
3661                 goto out;
3662         }
3663
3664         fw_offset = __le16_to_cpu(mac->fw_offset);
3665         if (fw_offset < sizeof(*mac)) {
3666                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3667                 goto out;
3668         }
3669
3670         length = __le32_to_cpu(mac->blk_hdr.length);
3671         if (length < fw_offset) {
3672                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3673                 goto out;
3674         }
3675
3676         length -= fw_offset;
3677         if (length < 4 || (length & 3)) {
3678                 dev_err(&tp->intf->dev, "invalid block length\n");
3679                 goto out;
3680         }
3681
3682         if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3683                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3684                 goto out;
3685         }
3686
3687         if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3688                 dev_err(&tp->intf->dev, "invalid base address register\n");
3689                 goto out;
3690         }
3691
3692         if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3693                 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3694                 goto out;
3695         }
3696
3697         if (__le16_to_cpu(mac->bp_start) != bp_start) {
3698                 dev_err(&tp->intf->dev,
3699                         "invalid start register of break point\n");
3700                 goto out;
3701         }
3702
3703         if (__le16_to_cpu(mac->bp_num) > max_bp) {
3704                 dev_err(&tp->intf->dev, "invalid break point number\n");
3705                 goto out;
3706         }
3707
3708         for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3709                 if (mac->bp[i]) {
3710                         dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3711                         goto out;
3712                 }
3713         }
3714
3715         rc = true;
3716 out:
3717         return rc;
3718 }
3719
3720 /* Verify the checksum for the firmware file. It is calculated from the version
3721  * field to the end of the file. Compare the result with the checksum field to
3722  * make sure the file is correct.
3723  */
3724 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3725                                        struct fw_header *fw_hdr, size_t size)
3726 {
3727         unsigned char checksum[sizeof(fw_hdr->checksum)];
3728         struct crypto_shash *alg;
3729         struct shash_desc *sdesc;
3730         size_t len;
3731         long rc;
3732
3733         alg = crypto_alloc_shash("sha256", 0, 0);
3734         if (IS_ERR(alg)) {
3735                 rc = PTR_ERR(alg);
3736                 goto out;
3737         }
3738
3739         if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3740                 rc = -EFAULT;
3741                 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3742                         crypto_shash_digestsize(alg));
3743                 goto free_shash;
3744         }
3745
3746         len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3747         sdesc = kmalloc(len, GFP_KERNEL);
3748         if (!sdesc) {
3749                 rc = -ENOMEM;
3750                 goto free_shash;
3751         }
3752         sdesc->tfm = alg;
3753
3754         len = size - sizeof(fw_hdr->checksum);
3755         rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3756         kfree(sdesc);
3757         if (rc)
3758                 goto free_shash;
3759
3760         if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3761                 dev_err(&tp->intf->dev, "checksum fail\n");
3762                 rc = -EFAULT;
3763         }
3764
3765 free_shash:
3766         crypto_free_shash(alg);
3767 out:
3768         return rc;
3769 }
3770
3771 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3772 {
3773         const struct firmware *fw = rtl_fw->fw;
3774         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3775         struct fw_mac *pla = NULL, *usb = NULL;
3776         struct fw_phy_patch_key *start = NULL;
3777         struct fw_phy_nc *phy_nc = NULL;
3778         struct fw_block *stop = NULL;
3779         long ret = -EFAULT;
3780         int i;
3781
3782         if (fw->size < sizeof(*fw_hdr)) {
3783                 dev_err(&tp->intf->dev, "file too small\n");
3784                 goto fail;
3785         }
3786
3787         ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3788         if (ret)
3789                 goto fail;
3790
3791         ret = -EFAULT;
3792
3793         for (i = sizeof(*fw_hdr); i < fw->size;) {
3794                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3795                 u32 type;
3796
3797                 if ((i + sizeof(*block)) > fw->size)
3798                         goto fail;
3799
3800                 type = __le32_to_cpu(block->type);
3801                 switch (type) {
3802                 case RTL_FW_END:
3803                         if (__le32_to_cpu(block->length) != sizeof(*block))
3804                                 goto fail;
3805                         goto fw_end;
3806                 case RTL_FW_PLA:
3807                         if (pla) {
3808                                 dev_err(&tp->intf->dev,
3809                                         "multiple PLA firmware encountered");
3810                                 goto fail;
3811                         }
3812
3813                         pla = (struct fw_mac *)block;
3814                         if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3815                                 dev_err(&tp->intf->dev,
3816                                         "check PLA firmware failed\n");
3817                                 goto fail;
3818                         }
3819                         break;
3820                 case RTL_FW_USB:
3821                         if (usb) {
3822                                 dev_err(&tp->intf->dev,
3823                                         "multiple USB firmware encountered");
3824                                 goto fail;
3825                         }
3826
3827                         usb = (struct fw_mac *)block;
3828                         if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3829                                 dev_err(&tp->intf->dev,
3830                                         "check USB firmware failed\n");
3831                                 goto fail;
3832                         }
3833                         break;
3834                 case RTL_FW_PHY_START:
3835                         if (start || phy_nc || stop) {
3836                                 dev_err(&tp->intf->dev,
3837                                         "check PHY_START fail\n");
3838                                 goto fail;
3839                         }
3840
3841                         if (__le32_to_cpu(block->length) != sizeof(*start)) {
3842                                 dev_err(&tp->intf->dev,
3843                                         "Invalid length for PHY_START\n");
3844                                 goto fail;
3845                         }
3846
3847                         start = (struct fw_phy_patch_key *)block;
3848                         break;
3849                 case RTL_FW_PHY_STOP:
3850                         if (stop || !start) {
3851                                 dev_err(&tp->intf->dev,
3852                                         "Check PHY_STOP fail\n");
3853                                 goto fail;
3854                         }
3855
3856                         if (__le32_to_cpu(block->length) != sizeof(*block)) {
3857                                 dev_err(&tp->intf->dev,
3858                                         "Invalid length for PHY_STOP\n");
3859                                 goto fail;
3860                         }
3861
3862                         stop = block;
3863                         break;
3864                 case RTL_FW_PHY_NC:
3865                         if (!start || stop) {
3866                                 dev_err(&tp->intf->dev,
3867                                         "check PHY_NC fail\n");
3868                                 goto fail;
3869                         }
3870
3871                         if (phy_nc) {
3872                                 dev_err(&tp->intf->dev,
3873                                         "multiple PHY NC encountered\n");
3874                                 goto fail;
3875                         }
3876
3877                         phy_nc = (struct fw_phy_nc *)block;
3878                         if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3879                                 dev_err(&tp->intf->dev,
3880                                         "check PHY NC firmware failed\n");
3881                                 goto fail;
3882                         }
3883
3884                         break;
3885                 default:
3886                         dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3887                                  type);
3888                         break;
3889                 }
3890
3891                 /* next block */
3892                 i += ALIGN(__le32_to_cpu(block->length), 8);
3893         }
3894
3895 fw_end:
3896         if ((phy_nc || start) && !stop) {
3897                 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3898                 goto fail;
3899         }
3900
3901         return 0;
3902 fail:
3903         return ret;
3904 }
3905
3906 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3907 {
3908         u16 mode_reg, bp_index;
3909         u32 length, i, num;
3910         __le16 *data;
3911
3912         mode_reg = __le16_to_cpu(phy->mode_reg);
3913         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3914         sram_write(tp, __le16_to_cpu(phy->ba_reg),
3915                    __le16_to_cpu(phy->ba_data));
3916
3917         length = __le32_to_cpu(phy->blk_hdr.length);
3918         length -= __le16_to_cpu(phy->fw_offset);
3919         num = length / 2;
3920         data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3921
3922         ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3923         for (i = 0; i < num; i++)
3924                 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3925
3926         sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3927                    __le16_to_cpu(phy->patch_en_value));
3928
3929         bp_index = __le16_to_cpu(phy->bp_start);
3930         num = __le16_to_cpu(phy->bp_num);
3931         for (i = 0; i < num; i++) {
3932                 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3933                 bp_index += 2;
3934         }
3935
3936         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3937
3938         dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3939 }
3940
3941 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3942 {
3943         u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3944         u32 length;
3945         u8 *data;
3946         int i;
3947
3948         switch (__le32_to_cpu(mac->blk_hdr.type)) {
3949         case RTL_FW_PLA:
3950                 type = MCU_TYPE_PLA;
3951                 break;
3952         case RTL_FW_USB:
3953                 type = MCU_TYPE_USB;
3954                 break;
3955         default:
3956                 return;
3957         }
3958
3959         rtl_clear_bp(tp, type);
3960
3961         /* Enable backup/restore of MACDBG. This is required after clearing PLA
3962          * break points and before applying the PLA firmware.
3963          */
3964         if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3965             !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3966                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3967                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3968         }
3969
3970         length = __le32_to_cpu(mac->blk_hdr.length);
3971         length -= __le16_to_cpu(mac->fw_offset);
3972
3973         data = (u8 *)mac;
3974         data += __le16_to_cpu(mac->fw_offset);
3975
3976         generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3977                           type);
3978
3979         ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3980                        __le16_to_cpu(mac->bp_ba_value));
3981
3982         bp_index = __le16_to_cpu(mac->bp_start);
3983         bp_num = __le16_to_cpu(mac->bp_num);
3984         for (i = 0; i < bp_num; i++) {
3985                 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3986                 bp_index += 2;
3987         }
3988
3989         bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3990         if (bp_en_addr)
3991                 ocp_write_word(tp, type, bp_en_addr,
3992                                __le16_to_cpu(mac->bp_en_value));
3993
3994         fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
3995         if (fw_ver_reg)
3996                 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
3997                                mac->fw_ver_data);
3998
3999         dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4000 }
4001
4002 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
4003 {
4004         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4005         const struct firmware *fw;
4006         struct fw_header *fw_hdr;
4007         struct fw_phy_patch_key *key;
4008         u16 key_addr = 0;
4009         int i;
4010
4011         if (IS_ERR_OR_NULL(rtl_fw->fw))
4012                 return;
4013
4014         fw = rtl_fw->fw;
4015         fw_hdr = (struct fw_header *)fw->data;
4016
4017         if (rtl_fw->pre_fw)
4018                 rtl_fw->pre_fw(tp);
4019
4020         for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4021                 struct fw_block *block = (struct fw_block *)&fw->data[i];
4022
4023                 switch (__le32_to_cpu(block->type)) {
4024                 case RTL_FW_END:
4025                         goto post_fw;
4026                 case RTL_FW_PLA:
4027                 case RTL_FW_USB:
4028                         rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4029                         break;
4030                 case RTL_FW_PHY_START:
4031                         key = (struct fw_phy_patch_key *)block;
4032                         key_addr = __le16_to_cpu(key->key_reg);
4033                         rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
4034                         break;
4035                 case RTL_FW_PHY_STOP:
4036                         WARN_ON(!key_addr);
4037                         rtl_post_ram_code(tp, key_addr, !power_cut);
4038                         break;
4039                 case RTL_FW_PHY_NC:
4040                         rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4041                         break;
4042                 default:
4043                         break;
4044                 }
4045
4046                 i += ALIGN(__le32_to_cpu(block->length), 8);
4047         }
4048
4049 post_fw:
4050         if (rtl_fw->post_fw)
4051                 rtl_fw->post_fw(tp);
4052
4053         strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4054         dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4055 }
4056
4057 static void rtl8152_release_firmware(struct r8152 *tp)
4058 {
4059         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4060
4061         if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4062                 release_firmware(rtl_fw->fw);
4063                 rtl_fw->fw = NULL;
4064         }
4065 }
4066
4067 static int rtl8152_request_firmware(struct r8152 *tp)
4068 {
4069         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4070         long rc;
4071
4072         if (rtl_fw->fw || !rtl_fw->fw_name) {
4073                 dev_info(&tp->intf->dev, "skip request firmware\n");
4074                 rc = 0;
4075                 goto result;
4076         }
4077
4078         rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4079         if (rc < 0)
4080                 goto result;
4081
4082         rc = rtl8152_check_firmware(tp, rtl_fw);
4083         if (rc < 0)
4084                 release_firmware(rtl_fw->fw);
4085
4086 result:
4087         if (rc) {
4088                 rtl_fw->fw = ERR_PTR(rc);
4089
4090                 dev_warn(&tp->intf->dev,
4091                          "unable to load firmware patch %s (%ld)\n",
4092                          rtl_fw->fw_name, rc);
4093         }
4094
4095         return rc;
4096 }
4097
4098 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4099 {
4100         if (enable) {
4101                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4102                                                     LINKENA | DIS_SDSAVE);
4103         } else {
4104                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4105                                                     DIS_SDSAVE);
4106                 msleep(20);
4107         }
4108 }
4109
4110 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4111 {
4112         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4113         ocp_reg_write(tp, OCP_EEE_DATA, reg);
4114         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4115 }
4116
4117 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4118 {
4119         u16 data;
4120
4121         r8152_mmd_indirect(tp, dev, reg);
4122         data = ocp_reg_read(tp, OCP_EEE_DATA);
4123         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4124
4125         return data;
4126 }
4127
4128 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4129 {
4130         r8152_mmd_indirect(tp, dev, reg);
4131         ocp_reg_write(tp, OCP_EEE_DATA, data);
4132         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4133 }
4134
4135 static void r8152_eee_en(struct r8152 *tp, bool enable)
4136 {
4137         u16 config1, config2, config3;
4138         u32 ocp_data;
4139
4140         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4141         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4142         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4143         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4144
4145         if (enable) {
4146                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4147                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4148                 config1 |= sd_rise_time(1);
4149                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4150                 config3 |= fast_snr(42);
4151         } else {
4152                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4153                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4154                              RX_QUIET_EN);
4155                 config1 |= sd_rise_time(7);
4156                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4157                 config3 |= fast_snr(511);
4158         }
4159
4160         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4161         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4162         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4163         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4164 }
4165
4166 static void r8153_eee_en(struct r8152 *tp, bool enable)
4167 {
4168         u32 ocp_data;
4169         u16 config;
4170
4171         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4172         config = ocp_reg_read(tp, OCP_EEE_CFG);
4173
4174         if (enable) {
4175                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4176                 config |= EEE10_EN;
4177         } else {
4178                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4179                 config &= ~EEE10_EN;
4180         }
4181
4182         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4183         ocp_reg_write(tp, OCP_EEE_CFG, config);
4184
4185         tp->ups_info.eee = enable;
4186 }
4187
4188 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4189 {
4190         switch (tp->version) {
4191         case RTL_VER_01:
4192         case RTL_VER_02:
4193         case RTL_VER_07:
4194                 if (enable) {
4195                         r8152_eee_en(tp, true);
4196                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4197                                         tp->eee_adv);
4198                 } else {
4199                         r8152_eee_en(tp, false);
4200                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4201                 }
4202                 break;
4203         case RTL_VER_03:
4204         case RTL_VER_04:
4205         case RTL_VER_05:
4206         case RTL_VER_06:
4207         case RTL_VER_08:
4208         case RTL_VER_09:
4209                 if (enable) {
4210                         r8153_eee_en(tp, true);
4211                         ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4212                 } else {
4213                         r8153_eee_en(tp, false);
4214                         ocp_reg_write(tp, OCP_EEE_ADV, 0);
4215                 }
4216                 break;
4217         default:
4218                 break;
4219         }
4220 }
4221
4222 static void r8152b_enable_fc(struct r8152 *tp)
4223 {
4224         u16 anar;
4225
4226         anar = r8152_mdio_read(tp, MII_ADVERTISE);
4227         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4228         r8152_mdio_write(tp, MII_ADVERTISE, anar);
4229
4230         tp->ups_info.flow_control = true;
4231 }
4232
4233 static void rtl8152_disable(struct r8152 *tp)
4234 {
4235         r8152_aldps_en(tp, false);
4236         rtl_disable(tp);
4237         r8152_aldps_en(tp, true);
4238 }
4239
4240 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4241 {
4242         rtl8152_apply_firmware(tp, false);
4243         rtl_eee_enable(tp, tp->eee_en);
4244         r8152_aldps_en(tp, true);
4245         r8152b_enable_fc(tp);
4246
4247         set_bit(PHY_RESET, &tp->flags);
4248 }
4249
4250 static void wait_oob_link_list_ready(struct r8152 *tp)
4251 {
4252         u32 ocp_data;
4253         int i;
4254
4255         for (i = 0; i < 1000; i++) {
4256                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4257                 if (ocp_data & LINK_LIST_READY)
4258                         break;
4259                 usleep_range(1000, 2000);
4260         }
4261 }
4262
4263 static void r8152b_exit_oob(struct r8152 *tp)
4264 {
4265         u32 ocp_data;
4266
4267         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4268         ocp_data &= ~RCR_ACPT_ALL;
4269         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4270
4271         rxdy_gated_en(tp, true);
4272         r8153_teredo_off(tp);
4273         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4274         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4275
4276         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4277         ocp_data &= ~NOW_IS_OOB;
4278         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4279
4280         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4281         ocp_data &= ~MCU_BORW_EN;
4282         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4283
4284         wait_oob_link_list_ready(tp);
4285
4286         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4287         ocp_data |= RE_INIT_LL;
4288         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4289
4290         wait_oob_link_list_ready(tp);
4291
4292         rtl8152_nic_reset(tp);
4293
4294         /* rx share fifo credit full threshold */
4295         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4296
4297         if (tp->udev->speed == USB_SPEED_FULL ||
4298             tp->udev->speed == USB_SPEED_LOW) {
4299                 /* rx share fifo credit near full threshold */
4300                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4301                                 RXFIFO_THR2_FULL);
4302                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4303                                 RXFIFO_THR3_FULL);
4304         } else {
4305                 /* rx share fifo credit near full threshold */
4306                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4307                                 RXFIFO_THR2_HIGH);
4308                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4309                                 RXFIFO_THR3_HIGH);
4310         }
4311
4312         /* TX share fifo free credit full threshold */
4313         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4314
4315         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4316         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4317         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4318                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4319
4320         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4321
4322         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4323
4324         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4325         ocp_data |= TCR0_AUTO_FIFO;
4326         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4327 }
4328
4329 static void r8152b_enter_oob(struct r8152 *tp)
4330 {
4331         u32 ocp_data;
4332
4333         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4334         ocp_data &= ~NOW_IS_OOB;
4335         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4336
4337         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4338         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4339         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4340
4341         rtl_disable(tp);
4342
4343         wait_oob_link_list_ready(tp);
4344
4345         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4346         ocp_data |= RE_INIT_LL;
4347         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4348
4349         wait_oob_link_list_ready(tp);
4350
4351         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4352
4353         rtl_rx_vlan_en(tp, true);
4354
4355         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4356         ocp_data |= ALDPS_PROXY_MODE;
4357         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4358
4359         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4360         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4361         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4362
4363         rxdy_gated_en(tp, false);
4364
4365         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4366         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4367         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4368 }
4369
4370 static int r8153_pre_firmware_1(struct r8152 *tp)
4371 {
4372         int i;
4373
4374         /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4375         for (i = 0; i < 104; i++) {
4376                 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4377
4378                 if (!(ocp_data & WTD1_EN))
4379                         break;
4380                 usleep_range(1000, 2000);
4381         }
4382
4383         return 0;
4384 }
4385
4386 static int r8153_post_firmware_1(struct r8152 *tp)
4387 {
4388         /* set USB_BP_4 to support USB_SPEED_SUPER only */
4389         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4390                 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4391
4392         /* reset UPHY timer to 36 ms */
4393         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4394
4395         return 0;
4396 }
4397
4398 static int r8153_pre_firmware_2(struct r8152 *tp)
4399 {
4400         u32 ocp_data;
4401
4402         r8153_pre_firmware_1(tp);
4403
4404         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4405         ocp_data &= ~FW_FIX_SUSPEND;
4406         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4407
4408         return 0;
4409 }
4410
4411 static int r8153_post_firmware_2(struct r8152 *tp)
4412 {
4413         u32 ocp_data;
4414
4415         /* enable bp0 if support USB_SPEED_SUPER only */
4416         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4417                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4418                 ocp_data |= BIT(0);
4419                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4420         }
4421
4422         /* reset UPHY timer to 36 ms */
4423         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4424
4425         /* enable U3P3 check, set the counter to 4 */
4426         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4427
4428         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4429         ocp_data |= FW_FIX_SUSPEND;
4430         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4431
4432         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4433         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4434         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4435
4436         return 0;
4437 }
4438
4439 static int r8153_post_firmware_3(struct r8152 *tp)
4440 {
4441         u32 ocp_data;
4442
4443         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4444         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4445         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4446
4447         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4448         ocp_data |= FW_IP_RESET_EN;
4449         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4450
4451         return 0;
4452 }
4453
4454 static int r8153b_pre_firmware_1(struct r8152 *tp)
4455 {
4456         /* enable fc timer and set timer to 1 second. */
4457         ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4458                        CTRL_TIMER_EN | (1000 / 8));
4459
4460         return 0;
4461 }
4462
4463 static int r8153b_post_firmware_1(struct r8152 *tp)
4464 {
4465         u32 ocp_data;
4466
4467         /* enable bp0 for RTL8153-BND */
4468         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4469         if (ocp_data & BND_MASK) {
4470                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4471                 ocp_data |= BIT(0);
4472                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4473         }
4474
4475         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4476         ocp_data |= FLOW_CTRL_PATCH_OPT;
4477         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4478
4479         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4480         ocp_data |= FC_PATCH_TASK;
4481         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4482
4483         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4484         ocp_data |= FW_IP_RESET_EN;
4485         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4486
4487         return 0;
4488 }
4489
4490 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4491 {
4492         u16 data;
4493
4494         data = ocp_reg_read(tp, OCP_POWER_CFG);
4495         if (enable) {
4496                 data |= EN_ALDPS;
4497                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4498         } else {
4499                 int i;
4500
4501                 data &= ~EN_ALDPS;
4502                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4503                 for (i = 0; i < 20; i++) {
4504                         usleep_range(1000, 2000);
4505                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4506                                 break;
4507                 }
4508         }
4509
4510         tp->ups_info.aldps = enable;
4511 }
4512
4513 static void r8153_hw_phy_cfg(struct r8152 *tp)
4514 {
4515         u32 ocp_data;
4516         u16 data;
4517
4518         /* disable ALDPS before updating the PHY parameters */
4519         r8153_aldps_en(tp, false);
4520
4521         /* disable EEE before updating the PHY parameters */
4522         rtl_eee_enable(tp, false);
4523
4524         rtl8152_apply_firmware(tp, false);
4525
4526         if (tp->version == RTL_VER_03) {
4527                 data = ocp_reg_read(tp, OCP_EEE_CFG);
4528                 data &= ~CTAP_SHORT_EN;
4529                 ocp_reg_write(tp, OCP_EEE_CFG, data);
4530         }
4531
4532         data = ocp_reg_read(tp, OCP_POWER_CFG);
4533         data |= EEE_CLKDIV_EN;
4534         ocp_reg_write(tp, OCP_POWER_CFG, data);
4535
4536         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4537         data |= EN_10M_BGOFF;
4538         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4539         data = ocp_reg_read(tp, OCP_POWER_CFG);
4540         data |= EN_10M_PLLOFF;
4541         ocp_reg_write(tp, OCP_POWER_CFG, data);
4542         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4543
4544         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4545         ocp_data |= PFM_PWM_SWITCH;
4546         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4547
4548         /* Enable LPF corner auto tune */
4549         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4550
4551         /* Adjust 10M Amplitude */
4552         sram_write(tp, SRAM_10M_AMP1, 0x00af);
4553         sram_write(tp, SRAM_10M_AMP2, 0x0208);
4554
4555         if (tp->eee_en)
4556                 rtl_eee_enable(tp, true);
4557
4558         r8153_aldps_en(tp, true);
4559         r8152b_enable_fc(tp);
4560
4561         switch (tp->version) {
4562         case RTL_VER_03:
4563         case RTL_VER_04:
4564                 break;
4565         case RTL_VER_05:
4566         case RTL_VER_06:
4567         default:
4568                 r8153_u2p3en(tp, true);
4569                 break;
4570         }
4571
4572         set_bit(PHY_RESET, &tp->flags);
4573 }
4574
4575 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4576 {
4577         u32 ocp_data;
4578
4579         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4580         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4581         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
4582         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4583
4584         return ocp_data;
4585 }
4586
4587 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4588 {
4589         u32 ocp_data;
4590         u16 data;
4591
4592         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
4593         if (ocp_data & PCUT_STATUS) {
4594                 ocp_data &= ~PCUT_STATUS;
4595                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
4596         }
4597
4598         /* disable ALDPS before updating the PHY parameters */
4599         r8153_aldps_en(tp, false);
4600
4601         /* disable EEE before updating the PHY parameters */
4602         rtl_eee_enable(tp, false);
4603
4604         /* U1/U2/L1 idle timer. 500 us */
4605         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4606
4607         data = r8153_phy_status(tp, 0);
4608
4609         switch (data) {
4610         case PHY_STAT_PWRDN:
4611         case PHY_STAT_EXT_INIT:
4612                 rtl8152_apply_firmware(tp, true);
4613
4614                 data = r8152_mdio_read(tp, MII_BMCR);
4615                 data &= ~BMCR_PDOWN;
4616                 r8152_mdio_write(tp, MII_BMCR, data);
4617                 break;
4618         case PHY_STAT_LAN_ON:
4619         default:
4620                 rtl8152_apply_firmware(tp, false);
4621                 break;
4622         }
4623
4624         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4625
4626         data = sram_read(tp, SRAM_GREEN_CFG);
4627         data |= R_TUNE_EN;
4628         sram_write(tp, SRAM_GREEN_CFG, data);
4629         data = ocp_reg_read(tp, OCP_NCTL_CFG);
4630         data |= PGA_RETURN_EN;
4631         ocp_reg_write(tp, OCP_NCTL_CFG, data);
4632
4633         /* ADC Bias Calibration:
4634          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4635          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4636          * ADC ioffset.
4637          */
4638         ocp_data = r8152_efuse_read(tp, 0x7d);
4639         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4640         if (data != 0xffff)
4641                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4642
4643         /* ups mode tx-link-pulse timing adjustment:
4644          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4645          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4646          */
4647         ocp_data = ocp_reg_read(tp, 0xc426);
4648         ocp_data &= 0x3fff;
4649         if (ocp_data) {
4650                 u32 swr_cnt_1ms_ini;
4651
4652                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4653                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4654                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4655                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4656         }
4657
4658         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4659         ocp_data |= PFM_PWM_SWITCH;
4660         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4661
4662         /* Advnace EEE */
4663         if (!rtl_phy_patch_request(tp, true, true)) {
4664                 data = ocp_reg_read(tp, OCP_POWER_CFG);
4665                 data |= EEE_CLKDIV_EN;
4666                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4667                 tp->ups_info.eee_ckdiv = true;
4668
4669                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4670                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4671                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4672                 tp->ups_info.eee_cmod_lv = true;
4673                 tp->ups_info._10m_ckdiv = true;
4674                 tp->ups_info.eee_plloff_giga = true;
4675
4676                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4677                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4678                 tp->ups_info._250m_ckdiv = true;
4679
4680                 rtl_phy_patch_request(tp, false, true);
4681         }
4682
4683         if (tp->eee_en)
4684                 rtl_eee_enable(tp, true);
4685
4686         r8153_aldps_en(tp, true);
4687         r8152b_enable_fc(tp);
4688
4689         set_bit(PHY_RESET, &tp->flags);
4690 }
4691
4692 static void r8153_first_init(struct r8152 *tp)
4693 {
4694         u32 ocp_data;
4695
4696         rxdy_gated_en(tp, true);
4697         r8153_teredo_off(tp);
4698
4699         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4700         ocp_data &= ~RCR_ACPT_ALL;
4701         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4702
4703         rtl8152_nic_reset(tp);
4704         rtl_reset_bmu(tp);
4705
4706         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4707         ocp_data &= ~NOW_IS_OOB;
4708         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4709
4710         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4711         ocp_data &= ~MCU_BORW_EN;
4712         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4713
4714         wait_oob_link_list_ready(tp);
4715
4716         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4717         ocp_data |= RE_INIT_LL;
4718         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4719
4720         wait_oob_link_list_ready(tp);
4721
4722         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4723
4724         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4725         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4726         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4727
4728         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4729         ocp_data |= TCR0_AUTO_FIFO;
4730         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4731
4732         rtl8152_nic_reset(tp);
4733
4734         /* rx share fifo credit full threshold */
4735         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4736         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4737         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4738         /* TX share fifo free credit full threshold */
4739         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4740 }
4741
4742 static void r8153_enter_oob(struct r8152 *tp)
4743 {
4744         u32 ocp_data;
4745
4746         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4747         ocp_data &= ~NOW_IS_OOB;
4748         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4749
4750         rtl_disable(tp);
4751         rtl_reset_bmu(tp);
4752
4753         wait_oob_link_list_ready(tp);
4754
4755         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4756         ocp_data |= RE_INIT_LL;
4757         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4758
4759         wait_oob_link_list_ready(tp);
4760
4761         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4762         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4763
4764         switch (tp->version) {
4765         case RTL_VER_03:
4766         case RTL_VER_04:
4767         case RTL_VER_05:
4768         case RTL_VER_06:
4769                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4770                 ocp_data &= ~TEREDO_WAKE_MASK;
4771                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4772                 break;
4773
4774         case RTL_VER_08:
4775         case RTL_VER_09:
4776                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4777                  * type. Set it to zero. bits[7:0] are the W1C bits about
4778                  * the events. Set them to all 1 to clear them.
4779                  */
4780                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4781                 break;
4782
4783         default:
4784                 break;
4785         }
4786
4787         rtl_rx_vlan_en(tp, true);
4788
4789         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4790         ocp_data |= ALDPS_PROXY_MODE;
4791         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4792
4793         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4794         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4795         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4796
4797         rxdy_gated_en(tp, false);
4798
4799         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4800         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4801         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4802 }
4803
4804 static void rtl8153_disable(struct r8152 *tp)
4805 {
4806         r8153_aldps_en(tp, false);
4807         rtl_disable(tp);
4808         rtl_reset_bmu(tp);
4809         r8153_aldps_en(tp, true);
4810 }
4811
4812 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4813                              u32 advertising)
4814 {
4815         u16 bmcr;
4816         int ret = 0;
4817
4818         if (autoneg == AUTONEG_DISABLE) {
4819                 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4820                         return -EINVAL;
4821
4822                 switch (speed) {
4823                 case SPEED_10:
4824                         bmcr = BMCR_SPEED10;
4825                         if (duplex == DUPLEX_FULL) {
4826                                 bmcr |= BMCR_FULLDPLX;
4827                                 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4828                         } else {
4829                                 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4830                         }
4831                         break;
4832                 case SPEED_100:
4833                         bmcr = BMCR_SPEED100;
4834                         if (duplex == DUPLEX_FULL) {
4835                                 bmcr |= BMCR_FULLDPLX;
4836                                 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4837                         } else {
4838                                 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4839                         }
4840                         break;
4841                 case SPEED_1000:
4842                         if (tp->mii.supports_gmii) {
4843                                 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4844                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4845                                 break;
4846                         }
4847                         fallthrough;
4848                 default:
4849                         ret = -EINVAL;
4850                         goto out;
4851                 }
4852
4853                 if (duplex == DUPLEX_FULL)
4854                         tp->mii.full_duplex = 1;
4855                 else
4856                         tp->mii.full_duplex = 0;
4857
4858                 tp->mii.force_media = 1;
4859         } else {
4860                 u16 anar, tmp1;
4861                 u32 support;
4862
4863                 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4864                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4865
4866                 if (tp->mii.supports_gmii)
4867                         support |= RTL_ADVERTISED_1000_FULL;
4868
4869                 if (!(advertising & support))
4870                         return -EINVAL;
4871
4872                 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4873                 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4874                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
4875                 if (advertising & RTL_ADVERTISED_10_HALF) {
4876                         tmp1 |= ADVERTISE_10HALF;
4877                         tp->ups_info.speed_duplex = NWAY_10M_HALF;
4878                 }
4879                 if (advertising & RTL_ADVERTISED_10_FULL) {
4880                         tmp1 |= ADVERTISE_10FULL;
4881                         tp->ups_info.speed_duplex = NWAY_10M_FULL;
4882                 }
4883
4884                 if (advertising & RTL_ADVERTISED_100_HALF) {
4885                         tmp1 |= ADVERTISE_100HALF;
4886                         tp->ups_info.speed_duplex = NWAY_100M_HALF;
4887                 }
4888                 if (advertising & RTL_ADVERTISED_100_FULL) {
4889                         tmp1 |= ADVERTISE_100FULL;
4890                         tp->ups_info.speed_duplex = NWAY_100M_FULL;
4891                 }
4892
4893                 if (anar != tmp1) {
4894                         r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4895                         tp->mii.advertising = tmp1;
4896                 }
4897
4898                 if (tp->mii.supports_gmii) {
4899                         u16 gbcr;
4900
4901                         gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4902                         tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4903                                         ADVERTISE_1000HALF);
4904
4905                         if (advertising & RTL_ADVERTISED_1000_FULL) {
4906                                 tmp1 |= ADVERTISE_1000FULL;
4907                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4908                         }
4909
4910                         if (gbcr != tmp1)
4911                                 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4912                 }
4913
4914                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4915
4916                 tp->mii.force_media = 0;
4917         }
4918
4919         if (test_and_clear_bit(PHY_RESET, &tp->flags))
4920                 bmcr |= BMCR_RESET;
4921
4922         r8152_mdio_write(tp, MII_BMCR, bmcr);
4923
4924         if (bmcr & BMCR_RESET) {
4925                 int i;
4926
4927                 for (i = 0; i < 50; i++) {
4928                         msleep(20);
4929                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4930                                 break;
4931                 }
4932         }
4933
4934 out:
4935         return ret;
4936 }
4937
4938 static void rtl8152_up(struct r8152 *tp)
4939 {
4940         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4941                 return;
4942
4943         r8152_aldps_en(tp, false);
4944         r8152b_exit_oob(tp);
4945         r8152_aldps_en(tp, true);
4946 }
4947
4948 static void rtl8152_down(struct r8152 *tp)
4949 {
4950         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4951                 rtl_drop_queued_tx(tp);
4952                 return;
4953         }
4954
4955         r8152_power_cut_en(tp, false);
4956         r8152_aldps_en(tp, false);
4957         r8152b_enter_oob(tp);
4958         r8152_aldps_en(tp, true);
4959 }
4960
4961 static void rtl8153_up(struct r8152 *tp)
4962 {
4963         u32 ocp_data;
4964
4965         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4966                 return;
4967
4968         r8153_u1u2en(tp, false);
4969         r8153_u2p3en(tp, false);
4970         r8153_aldps_en(tp, false);
4971         r8153_first_init(tp);
4972
4973         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4974         ocp_data |= LANWAKE_CLR_EN;
4975         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4976
4977         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4978         ocp_data &= ~LANWAKE_PIN;
4979         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4980
4981         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4982         ocp_data &= ~DELAY_PHY_PWR_CHG;
4983         ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4984
4985         r8153_aldps_en(tp, true);
4986
4987         switch (tp->version) {
4988         case RTL_VER_03:
4989         case RTL_VER_04:
4990                 break;
4991         case RTL_VER_05:
4992         case RTL_VER_06:
4993         default:
4994                 r8153_u2p3en(tp, true);
4995                 break;
4996         }
4997
4998         r8153_u1u2en(tp, true);
4999 }
5000
5001 static void rtl8153_down(struct r8152 *tp)
5002 {
5003         u32 ocp_data;
5004
5005         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5006                 rtl_drop_queued_tx(tp);
5007                 return;
5008         }
5009
5010         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5011         ocp_data &= ~LANWAKE_CLR_EN;
5012         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5013
5014         r8153_u1u2en(tp, false);
5015         r8153_u2p3en(tp, false);
5016         r8153_power_cut_en(tp, false);
5017         r8153_aldps_en(tp, false);
5018         r8153_enter_oob(tp);
5019         r8153_aldps_en(tp, true);
5020 }
5021
5022 static void rtl8153b_up(struct r8152 *tp)
5023 {
5024         u32 ocp_data;
5025
5026         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5027                 return;
5028
5029         r8153b_u1u2en(tp, false);
5030         r8153_u2p3en(tp, false);
5031         r8153_aldps_en(tp, false);
5032
5033         r8153_first_init(tp);
5034         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5035
5036         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5037         ocp_data &= ~PLA_MCU_SPDWN_EN;
5038         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5039
5040         r8153_aldps_en(tp, true);
5041
5042         if (tp->udev->speed >= USB_SPEED_SUPER)
5043                 r8153b_u1u2en(tp, true);
5044 }
5045
5046 static void rtl8153b_down(struct r8152 *tp)
5047 {
5048         u32 ocp_data;
5049
5050         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5051                 rtl_drop_queued_tx(tp);
5052                 return;
5053         }
5054
5055         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5056         ocp_data |= PLA_MCU_SPDWN_EN;
5057         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5058
5059         r8153b_u1u2en(tp, false);
5060         r8153_u2p3en(tp, false);
5061         r8153b_power_cut_en(tp, false);
5062         r8153_aldps_en(tp, false);
5063         r8153_enter_oob(tp);
5064         r8153_aldps_en(tp, true);
5065 }
5066
5067 static bool rtl8152_in_nway(struct r8152 *tp)
5068 {
5069         u16 nway_state;
5070
5071         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5072         tp->ocp_base = 0x2000;
5073         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
5074         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5075
5076         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5077         if (nway_state & 0xc000)
5078                 return false;
5079         else
5080                 return true;
5081 }
5082
5083 static bool rtl8153_in_nway(struct r8152 *tp)
5084 {
5085         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5086
5087         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5088                 return false;
5089         else
5090                 return true;
5091 }
5092
5093 static void set_carrier(struct r8152 *tp)
5094 {
5095         struct net_device *netdev = tp->netdev;
5096         struct napi_struct *napi = &tp->napi;
5097         u8 speed;
5098
5099         speed = rtl8152_get_speed(tp);
5100
5101         if (speed & LINK_STATUS) {
5102                 if (!netif_carrier_ok(netdev)) {
5103                         tp->rtl_ops.enable(tp);
5104                         netif_stop_queue(netdev);
5105                         napi_disable(napi);
5106                         netif_carrier_on(netdev);
5107                         rtl_start_rx(tp);
5108                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5109                         _rtl8152_set_rx_mode(netdev);
5110                         napi_enable(&tp->napi);
5111                         netif_wake_queue(netdev);
5112                         netif_info(tp, link, netdev, "carrier on\n");
5113                 } else if (netif_queue_stopped(netdev) &&
5114                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5115                         netif_wake_queue(netdev);
5116                 }
5117         } else {
5118                 if (netif_carrier_ok(netdev)) {
5119                         netif_carrier_off(netdev);
5120                         tasklet_disable(&tp->tx_tl);
5121                         napi_disable(napi);
5122                         tp->rtl_ops.disable(tp);
5123                         napi_enable(napi);
5124                         tasklet_enable(&tp->tx_tl);
5125                         netif_info(tp, link, netdev, "carrier off\n");
5126                 }
5127         }
5128 }
5129
5130 static void rtl_work_func_t(struct work_struct *work)
5131 {
5132         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5133
5134         /* If the device is unplugged or !netif_running(), the workqueue
5135          * doesn't need to wake the device, and could return directly.
5136          */
5137         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5138                 return;
5139
5140         if (usb_autopm_get_interface(tp->intf) < 0)
5141                 return;
5142
5143         if (!test_bit(WORK_ENABLE, &tp->flags))
5144                 goto out1;
5145
5146         if (!mutex_trylock(&tp->control)) {
5147                 schedule_delayed_work(&tp->schedule, 0);
5148                 goto out1;
5149         }
5150
5151         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5152                 set_carrier(tp);
5153
5154         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5155                 _rtl8152_set_rx_mode(tp->netdev);
5156
5157         /* don't schedule tasket before linking */
5158         if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5159             netif_carrier_ok(tp->netdev))
5160                 tasklet_schedule(&tp->tx_tl);
5161
5162         mutex_unlock(&tp->control);
5163
5164 out1:
5165         usb_autopm_put_interface(tp->intf);
5166 }
5167
5168 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5169 {
5170         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5171
5172         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5173                 return;
5174
5175         if (usb_autopm_get_interface(tp->intf) < 0)
5176                 return;
5177
5178         mutex_lock(&tp->control);
5179
5180         if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5181                 tp->rtl_fw.retry = false;
5182                 tp->rtl_fw.fw = NULL;
5183
5184                 /* Delay execution in case request_firmware() is not ready yet.
5185                  */
5186                 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5187                 goto ignore_once;
5188         }
5189
5190         tp->rtl_ops.hw_phy_cfg(tp);
5191
5192         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5193                           tp->advertising);
5194
5195 ignore_once:
5196         mutex_unlock(&tp->control);
5197
5198         usb_autopm_put_interface(tp->intf);
5199 }
5200
5201 #ifdef CONFIG_PM_SLEEP
5202 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5203                         void *data)
5204 {
5205         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5206
5207         switch (action) {
5208         case PM_HIBERNATION_PREPARE:
5209         case PM_SUSPEND_PREPARE:
5210                 usb_autopm_get_interface(tp->intf);
5211                 break;
5212
5213         case PM_POST_HIBERNATION:
5214         case PM_POST_SUSPEND:
5215                 usb_autopm_put_interface(tp->intf);
5216                 break;
5217
5218         case PM_POST_RESTORE:
5219         case PM_RESTORE_PREPARE:
5220         default:
5221                 break;
5222         }
5223
5224         return NOTIFY_DONE;
5225 }
5226 #endif
5227
5228 static int rtl8152_open(struct net_device *netdev)
5229 {
5230         struct r8152 *tp = netdev_priv(netdev);
5231         int res = 0;
5232
5233         if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5234                 cancel_delayed_work_sync(&tp->hw_phy_work);
5235                 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5236         }
5237
5238         res = alloc_all_mem(tp);
5239         if (res)
5240                 goto out;
5241
5242         res = usb_autopm_get_interface(tp->intf);
5243         if (res < 0)
5244                 goto out_free;
5245
5246         mutex_lock(&tp->control);
5247
5248         tp->rtl_ops.up(tp);
5249
5250         netif_carrier_off(netdev);
5251         netif_start_queue(netdev);
5252         set_bit(WORK_ENABLE, &tp->flags);
5253
5254         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5255         if (res) {
5256                 if (res == -ENODEV)
5257                         netif_device_detach(tp->netdev);
5258                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5259                            res);
5260                 goto out_unlock;
5261         }
5262         napi_enable(&tp->napi);
5263         tasklet_enable(&tp->tx_tl);
5264
5265         mutex_unlock(&tp->control);
5266
5267         usb_autopm_put_interface(tp->intf);
5268 #ifdef CONFIG_PM_SLEEP
5269         tp->pm_notifier.notifier_call = rtl_notifier;
5270         register_pm_notifier(&tp->pm_notifier);
5271 #endif
5272         return 0;
5273
5274 out_unlock:
5275         mutex_unlock(&tp->control);
5276         usb_autopm_put_interface(tp->intf);
5277 out_free:
5278         free_all_mem(tp);
5279 out:
5280         return res;
5281 }
5282
5283 static int rtl8152_close(struct net_device *netdev)
5284 {
5285         struct r8152 *tp = netdev_priv(netdev);
5286         int res = 0;
5287
5288 #ifdef CONFIG_PM_SLEEP
5289         unregister_pm_notifier(&tp->pm_notifier);
5290 #endif
5291         tasklet_disable(&tp->tx_tl);
5292         clear_bit(WORK_ENABLE, &tp->flags);
5293         usb_kill_urb(tp->intr_urb);
5294         cancel_delayed_work_sync(&tp->schedule);
5295         napi_disable(&tp->napi);
5296         netif_stop_queue(netdev);
5297
5298         res = usb_autopm_get_interface(tp->intf);
5299         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5300                 rtl_drop_queued_tx(tp);
5301                 rtl_stop_rx(tp);
5302         } else {
5303                 mutex_lock(&tp->control);
5304
5305                 tp->rtl_ops.down(tp);
5306
5307                 mutex_unlock(&tp->control);
5308
5309                 usb_autopm_put_interface(tp->intf);
5310         }
5311
5312         free_all_mem(tp);
5313
5314         return res;
5315 }
5316
5317 static void rtl_tally_reset(struct r8152 *tp)
5318 {
5319         u32 ocp_data;
5320
5321         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5322         ocp_data |= TALLY_RESET;
5323         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5324 }
5325
5326 static void r8152b_init(struct r8152 *tp)
5327 {
5328         u32 ocp_data;
5329         u16 data;
5330
5331         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5332                 return;
5333
5334         data = r8152_mdio_read(tp, MII_BMCR);
5335         if (data & BMCR_PDOWN) {
5336                 data &= ~BMCR_PDOWN;
5337                 r8152_mdio_write(tp, MII_BMCR, data);
5338         }
5339
5340         r8152_aldps_en(tp, false);
5341
5342         if (tp->version == RTL_VER_01) {
5343                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5344                 ocp_data &= ~LED_MODE_MASK;
5345                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5346         }
5347
5348         r8152_power_cut_en(tp, false);
5349
5350         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5351         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5352         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5353         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5354         ocp_data &= ~MCU_CLK_RATIO_MASK;
5355         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5356         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5357         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5358                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5359         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5360
5361         rtl_tally_reset(tp);
5362
5363         /* enable rx aggregation */
5364         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5365         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5366         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5367 }
5368
5369 static void r8153_init(struct r8152 *tp)
5370 {
5371         u32 ocp_data;
5372         u16 data;
5373         int i;
5374
5375         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5376                 return;
5377
5378         r8153_u1u2en(tp, false);
5379
5380         for (i = 0; i < 500; i++) {
5381                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5382                     AUTOLOAD_DONE)
5383                         break;
5384
5385                 msleep(20);
5386                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5387                         break;
5388         }
5389
5390         data = r8153_phy_status(tp, 0);
5391
5392         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5393             tp->version == RTL_VER_05)
5394                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5395
5396         data = r8152_mdio_read(tp, MII_BMCR);
5397         if (data & BMCR_PDOWN) {
5398                 data &= ~BMCR_PDOWN;
5399                 r8152_mdio_write(tp, MII_BMCR, data);
5400         }
5401
5402         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5403
5404         r8153_u2p3en(tp, false);
5405
5406         if (tp->version == RTL_VER_04) {
5407                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5408                 ocp_data &= ~pwd_dn_scale_mask;
5409                 ocp_data |= pwd_dn_scale(96);
5410                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5411
5412                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5413                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5414                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5415         } else if (tp->version == RTL_VER_05) {
5416                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5417                 ocp_data &= ~ECM_ALDPS;
5418                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5419
5420                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5421                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5422                         ocp_data &= ~DYNAMIC_BURST;
5423                 else
5424                         ocp_data |= DYNAMIC_BURST;
5425                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5426         } else if (tp->version == RTL_VER_06) {
5427                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5428                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5429                         ocp_data &= ~DYNAMIC_BURST;
5430                 else
5431                         ocp_data |= DYNAMIC_BURST;
5432                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5433
5434                 r8153_queue_wake(tp, false);
5435
5436                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5437                 if (rtl8152_get_speed(tp) & LINK_STATUS)
5438                         ocp_data |= CUR_LINK_OK;
5439                 else
5440                         ocp_data &= ~CUR_LINK_OK;
5441                 ocp_data |= POLL_LINK_CHG;
5442                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5443         }
5444
5445         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5446         ocp_data |= EP4_FULL_FC;
5447         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5448
5449         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5450         ocp_data &= ~TIMER11_EN;
5451         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5452
5453         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5454         ocp_data &= ~LED_MODE_MASK;
5455         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5456
5457         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5458         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5459                 ocp_data |= LPM_TIMER_500MS;
5460         else
5461                 ocp_data |= LPM_TIMER_500US;
5462         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5463
5464         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5465         ocp_data &= ~SEN_VAL_MASK;
5466         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5467         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5468
5469         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5470
5471         /* MAC clock speed down */
5472         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
5473         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
5474         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
5475         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
5476
5477         r8153_power_cut_en(tp, false);
5478         rtl_runtime_suspend_enable(tp, false);
5479         r8153_u1u2en(tp, true);
5480         usb_enable_lpm(tp->udev);
5481
5482         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5483         ocp_data |= LANWAKE_CLR_EN;
5484         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5485
5486         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5487         ocp_data &= ~LANWAKE_PIN;
5488         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5489
5490         /* rx aggregation */
5491         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5492         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5493         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5494                 ocp_data |= RX_AGG_DISABLE;
5495
5496         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5497
5498         rtl_tally_reset(tp);
5499
5500         switch (tp->udev->speed) {
5501         case USB_SPEED_SUPER:
5502         case USB_SPEED_SUPER_PLUS:
5503                 tp->coalesce = COALESCE_SUPER;
5504                 break;
5505         case USB_SPEED_HIGH:
5506                 tp->coalesce = COALESCE_HIGH;
5507                 break;
5508         default:
5509                 tp->coalesce = COALESCE_SLOW;
5510                 break;
5511         }
5512 }
5513
5514 static void r8153b_init(struct r8152 *tp)
5515 {
5516         u32 ocp_data;
5517         u16 data;
5518         int i;
5519
5520         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5521                 return;
5522
5523         r8153b_u1u2en(tp, false);
5524
5525         for (i = 0; i < 500; i++) {
5526                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5527                     AUTOLOAD_DONE)
5528                         break;
5529
5530                 msleep(20);
5531                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5532                         break;
5533         }
5534
5535         data = r8153_phy_status(tp, 0);
5536
5537         data = r8152_mdio_read(tp, MII_BMCR);
5538         if (data & BMCR_PDOWN) {
5539                 data &= ~BMCR_PDOWN;
5540                 r8152_mdio_write(tp, MII_BMCR, data);
5541         }
5542
5543         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5544
5545         r8153_u2p3en(tp, false);
5546
5547         /* MSC timer = 0xfff * 8ms = 32760 ms */
5548         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5549
5550         r8153b_power_cut_en(tp, false);
5551         r8153b_ups_en(tp, false);
5552         r8153_queue_wake(tp, false);
5553         rtl_runtime_suspend_enable(tp, false);
5554
5555         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5556         if (rtl8152_get_speed(tp) & LINK_STATUS)
5557                 ocp_data |= CUR_LINK_OK;
5558         else
5559                 ocp_data &= ~CUR_LINK_OK;
5560         ocp_data |= POLL_LINK_CHG;
5561         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5562
5563         if (tp->udev->speed >= USB_SPEED_SUPER)
5564                 r8153b_u1u2en(tp, true);
5565
5566         usb_enable_lpm(tp->udev);
5567
5568         /* MAC clock speed down */
5569         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5570         ocp_data |= MAC_CLK_SPDWN_EN;
5571         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5572
5573         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5574         ocp_data &= ~PLA_MCU_SPDWN_EN;
5575         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5576
5577         if (tp->version == RTL_VER_09) {
5578                 /* Disable Test IO for 32QFN */
5579                 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5580                         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5581                         ocp_data |= TEST_IO_OFF;
5582                         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5583                 }
5584         }
5585
5586         set_bit(GREEN_ETHERNET, &tp->flags);
5587
5588         /* rx aggregation */
5589         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5590         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5591         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5592
5593         rtl_tally_reset(tp);
5594
5595         tp->coalesce = 15000;   /* 15 us */
5596 }
5597
5598 static int rtl8152_pre_reset(struct usb_interface *intf)
5599 {
5600         struct r8152 *tp = usb_get_intfdata(intf);
5601         struct net_device *netdev;
5602
5603         if (!tp)
5604                 return 0;
5605
5606         netdev = tp->netdev;
5607         if (!netif_running(netdev))
5608                 return 0;
5609
5610         netif_stop_queue(netdev);
5611         tasklet_disable(&tp->tx_tl);
5612         clear_bit(WORK_ENABLE, &tp->flags);
5613         usb_kill_urb(tp->intr_urb);
5614         cancel_delayed_work_sync(&tp->schedule);
5615         napi_disable(&tp->napi);
5616         if (netif_carrier_ok(netdev)) {
5617                 mutex_lock(&tp->control);
5618                 tp->rtl_ops.disable(tp);
5619                 mutex_unlock(&tp->control);
5620         }
5621
5622         return 0;
5623 }
5624
5625 static int rtl8152_post_reset(struct usb_interface *intf)
5626 {
5627         struct r8152 *tp = usb_get_intfdata(intf);
5628         struct net_device *netdev;
5629         struct sockaddr sa;
5630
5631         if (!tp)
5632                 return 0;
5633
5634         /* reset the MAC adddress in case of policy change */
5635         if (determine_ethernet_addr(tp, &sa) >= 0) {
5636                 rtnl_lock();
5637                 dev_set_mac_address (tp->netdev, &sa, NULL);
5638                 rtnl_unlock();
5639         }
5640
5641         netdev = tp->netdev;
5642         if (!netif_running(netdev))
5643                 return 0;
5644
5645         set_bit(WORK_ENABLE, &tp->flags);
5646         if (netif_carrier_ok(netdev)) {
5647                 mutex_lock(&tp->control);
5648                 tp->rtl_ops.enable(tp);
5649                 rtl_start_rx(tp);
5650                 _rtl8152_set_rx_mode(netdev);
5651                 mutex_unlock(&tp->control);
5652         }
5653
5654         napi_enable(&tp->napi);
5655         tasklet_enable(&tp->tx_tl);
5656         netif_wake_queue(netdev);
5657         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5658
5659         if (!list_empty(&tp->rx_done))
5660                 napi_schedule(&tp->napi);
5661
5662         return 0;
5663 }
5664
5665 static bool delay_autosuspend(struct r8152 *tp)
5666 {
5667         bool sw_linking = !!netif_carrier_ok(tp->netdev);
5668         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5669
5670         /* This means a linking change occurs and the driver doesn't detect it,
5671          * yet. If the driver has disabled tx/rx and hw is linking on, the
5672          * device wouldn't wake up by receiving any packet.
5673          */
5674         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5675                 return true;
5676
5677         /* If the linking down is occurred by nway, the device may miss the
5678          * linking change event. And it wouldn't wake when linking on.
5679          */
5680         if (!sw_linking && tp->rtl_ops.in_nway(tp))
5681                 return true;
5682         else if (!skb_queue_empty(&tp->tx_queue))
5683                 return true;
5684         else
5685                 return false;
5686 }
5687
5688 static int rtl8152_runtime_resume(struct r8152 *tp)
5689 {
5690         struct net_device *netdev = tp->netdev;
5691
5692         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5693                 struct napi_struct *napi = &tp->napi;
5694
5695                 tp->rtl_ops.autosuspend_en(tp, false);
5696                 napi_disable(napi);
5697                 set_bit(WORK_ENABLE, &tp->flags);
5698
5699                 if (netif_carrier_ok(netdev)) {
5700                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
5701                                 rtl_start_rx(tp);
5702                         } else {
5703                                 netif_carrier_off(netdev);
5704                                 tp->rtl_ops.disable(tp);
5705                                 netif_info(tp, link, netdev, "linking down\n");
5706                         }
5707                 }
5708
5709                 napi_enable(napi);
5710                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5711                 smp_mb__after_atomic();
5712
5713                 if (!list_empty(&tp->rx_done))
5714                         napi_schedule(&tp->napi);
5715
5716                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5717         } else {
5718                 if (netdev->flags & IFF_UP)
5719                         tp->rtl_ops.autosuspend_en(tp, false);
5720
5721                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5722         }
5723
5724         return 0;
5725 }
5726
5727 static int rtl8152_system_resume(struct r8152 *tp)
5728 {
5729         struct net_device *netdev = tp->netdev;
5730
5731         netif_device_attach(netdev);
5732
5733         if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5734                 tp->rtl_ops.up(tp);
5735                 netif_carrier_off(netdev);
5736                 set_bit(WORK_ENABLE, &tp->flags);
5737                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5738         }
5739
5740         return 0;
5741 }
5742
5743 static int rtl8152_runtime_suspend(struct r8152 *tp)
5744 {
5745         struct net_device *netdev = tp->netdev;
5746         int ret = 0;
5747
5748         if (!tp->rtl_ops.autosuspend_en)
5749                 return -EBUSY;
5750
5751         set_bit(SELECTIVE_SUSPEND, &tp->flags);
5752         smp_mb__after_atomic();
5753
5754         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5755                 u32 rcr = 0;
5756
5757                 if (netif_carrier_ok(netdev)) {
5758                         u32 ocp_data;
5759
5760                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5761                         ocp_data = rcr & ~RCR_ACPT_ALL;
5762                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5763                         rxdy_gated_en(tp, true);
5764                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5765                                                  PLA_OOB_CTRL);
5766                         if (!(ocp_data & RXFIFO_EMPTY)) {
5767                                 rxdy_gated_en(tp, false);
5768                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5769                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5770                                 smp_mb__after_atomic();
5771                                 ret = -EBUSY;
5772                                 goto out1;
5773                         }
5774                 }
5775
5776                 clear_bit(WORK_ENABLE, &tp->flags);
5777                 usb_kill_urb(tp->intr_urb);
5778
5779                 tp->rtl_ops.autosuspend_en(tp, true);
5780
5781                 if (netif_carrier_ok(netdev)) {
5782                         struct napi_struct *napi = &tp->napi;
5783
5784                         napi_disable(napi);
5785                         rtl_stop_rx(tp);
5786                         rxdy_gated_en(tp, false);
5787                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5788                         napi_enable(napi);
5789                 }
5790
5791                 if (delay_autosuspend(tp)) {
5792                         rtl8152_runtime_resume(tp);
5793                         ret = -EBUSY;
5794                 }
5795         }
5796
5797 out1:
5798         return ret;
5799 }
5800
5801 static int rtl8152_system_suspend(struct r8152 *tp)
5802 {
5803         struct net_device *netdev = tp->netdev;
5804
5805         netif_device_detach(netdev);
5806
5807         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5808                 struct napi_struct *napi = &tp->napi;
5809
5810                 clear_bit(WORK_ENABLE, &tp->flags);
5811                 usb_kill_urb(tp->intr_urb);
5812                 tasklet_disable(&tp->tx_tl);
5813                 napi_disable(napi);
5814                 cancel_delayed_work_sync(&tp->schedule);
5815                 tp->rtl_ops.down(tp);
5816                 napi_enable(napi);
5817                 tasklet_enable(&tp->tx_tl);
5818         }
5819
5820         return 0;
5821 }
5822
5823 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5824 {
5825         struct r8152 *tp = usb_get_intfdata(intf);
5826         int ret;
5827
5828         mutex_lock(&tp->control);
5829
5830         if (PMSG_IS_AUTO(message))
5831                 ret = rtl8152_runtime_suspend(tp);
5832         else
5833                 ret = rtl8152_system_suspend(tp);
5834
5835         mutex_unlock(&tp->control);
5836
5837         return ret;
5838 }
5839
5840 static int rtl8152_resume(struct usb_interface *intf)
5841 {
5842         struct r8152 *tp = usb_get_intfdata(intf);
5843         int ret;
5844
5845         mutex_lock(&tp->control);
5846
5847         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5848                 ret = rtl8152_runtime_resume(tp);
5849         else
5850                 ret = rtl8152_system_resume(tp);
5851
5852         mutex_unlock(&tp->control);
5853
5854         return ret;
5855 }
5856
5857 static int rtl8152_reset_resume(struct usb_interface *intf)
5858 {
5859         struct r8152 *tp = usb_get_intfdata(intf);
5860
5861         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5862         tp->rtl_ops.init(tp);
5863         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5864         set_ethernet_addr(tp);
5865         return rtl8152_resume(intf);
5866 }
5867
5868 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5869 {
5870         struct r8152 *tp = netdev_priv(dev);
5871
5872         if (usb_autopm_get_interface(tp->intf) < 0)
5873                 return;
5874
5875         if (!rtl_can_wakeup(tp)) {
5876                 wol->supported = 0;
5877                 wol->wolopts = 0;
5878         } else {
5879                 mutex_lock(&tp->control);
5880                 wol->supported = WAKE_ANY;
5881                 wol->wolopts = __rtl_get_wol(tp);
5882                 mutex_unlock(&tp->control);
5883         }
5884
5885         usb_autopm_put_interface(tp->intf);
5886 }
5887
5888 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5889 {
5890         struct r8152 *tp = netdev_priv(dev);
5891         int ret;
5892
5893         if (!rtl_can_wakeup(tp))
5894                 return -EOPNOTSUPP;
5895
5896         if (wol->wolopts & ~WAKE_ANY)
5897                 return -EINVAL;
5898
5899         ret = usb_autopm_get_interface(tp->intf);
5900         if (ret < 0)
5901                 goto out_set_wol;
5902
5903         mutex_lock(&tp->control);
5904
5905         __rtl_set_wol(tp, wol->wolopts);
5906         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5907
5908         mutex_unlock(&tp->control);
5909
5910         usb_autopm_put_interface(tp->intf);
5911
5912 out_set_wol:
5913         return ret;
5914 }
5915
5916 static u32 rtl8152_get_msglevel(struct net_device *dev)
5917 {
5918         struct r8152 *tp = netdev_priv(dev);
5919
5920         return tp->msg_enable;
5921 }
5922
5923 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5924 {
5925         struct r8152 *tp = netdev_priv(dev);
5926
5927         tp->msg_enable = value;
5928 }
5929
5930 static void rtl8152_get_drvinfo(struct net_device *netdev,
5931                                 struct ethtool_drvinfo *info)
5932 {
5933         struct r8152 *tp = netdev_priv(netdev);
5934
5935         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5936         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5937         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5938         if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5939                 strlcpy(info->fw_version, tp->rtl_fw.version,
5940                         sizeof(info->fw_version));
5941 }
5942
5943 static
5944 int rtl8152_get_link_ksettings(struct net_device *netdev,
5945                                struct ethtool_link_ksettings *cmd)
5946 {
5947         struct r8152 *tp = netdev_priv(netdev);
5948         int ret;
5949
5950         if (!tp->mii.mdio_read)
5951                 return -EOPNOTSUPP;
5952
5953         ret = usb_autopm_get_interface(tp->intf);
5954         if (ret < 0)
5955                 goto out;
5956
5957         mutex_lock(&tp->control);
5958
5959         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5960
5961         mutex_unlock(&tp->control);
5962
5963         usb_autopm_put_interface(tp->intf);
5964
5965 out:
5966         return ret;
5967 }
5968
5969 static int rtl8152_set_link_ksettings(struct net_device *dev,
5970                                       const struct ethtool_link_ksettings *cmd)
5971 {
5972         struct r8152 *tp = netdev_priv(dev);
5973         u32 advertising = 0;
5974         int ret;
5975
5976         ret = usb_autopm_get_interface(tp->intf);
5977         if (ret < 0)
5978                 goto out;
5979
5980         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5981                      cmd->link_modes.advertising))
5982                 advertising |= RTL_ADVERTISED_10_HALF;
5983
5984         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5985                      cmd->link_modes.advertising))
5986                 advertising |= RTL_ADVERTISED_10_FULL;
5987
5988         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5989                      cmd->link_modes.advertising))
5990                 advertising |= RTL_ADVERTISED_100_HALF;
5991
5992         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5993                      cmd->link_modes.advertising))
5994                 advertising |= RTL_ADVERTISED_100_FULL;
5995
5996         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5997                      cmd->link_modes.advertising))
5998                 advertising |= RTL_ADVERTISED_1000_HALF;
5999
6000         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
6001                      cmd->link_modes.advertising))
6002                 advertising |= RTL_ADVERTISED_1000_FULL;
6003
6004         mutex_lock(&tp->control);
6005
6006         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
6007                                 cmd->base.duplex, advertising);
6008         if (!ret) {
6009                 tp->autoneg = cmd->base.autoneg;
6010                 tp->speed = cmd->base.speed;
6011                 tp->duplex = cmd->base.duplex;
6012                 tp->advertising = advertising;
6013         }
6014
6015         mutex_unlock(&tp->control);
6016
6017         usb_autopm_put_interface(tp->intf);
6018
6019 out:
6020         return ret;
6021 }
6022
6023 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6024         "tx_packets",
6025         "rx_packets",
6026         "tx_errors",
6027         "rx_errors",
6028         "rx_missed",
6029         "align_errors",
6030         "tx_single_collisions",
6031         "tx_multi_collisions",
6032         "rx_unicast",
6033         "rx_broadcast",
6034         "rx_multicast",
6035         "tx_aborted",
6036         "tx_underrun",
6037 };
6038
6039 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6040 {
6041         switch (sset) {
6042         case ETH_SS_STATS:
6043                 return ARRAY_SIZE(rtl8152_gstrings);
6044         default:
6045                 return -EOPNOTSUPP;
6046         }
6047 }
6048
6049 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6050                                       struct ethtool_stats *stats, u64 *data)
6051 {
6052         struct r8152 *tp = netdev_priv(dev);
6053         struct tally_counter tally;
6054
6055         if (usb_autopm_get_interface(tp->intf) < 0)
6056                 return;
6057
6058         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6059
6060         usb_autopm_put_interface(tp->intf);
6061
6062         data[0] = le64_to_cpu(tally.tx_packets);
6063         data[1] = le64_to_cpu(tally.rx_packets);
6064         data[2] = le64_to_cpu(tally.tx_errors);
6065         data[3] = le32_to_cpu(tally.rx_errors);
6066         data[4] = le16_to_cpu(tally.rx_missed);
6067         data[5] = le16_to_cpu(tally.align_errors);
6068         data[6] = le32_to_cpu(tally.tx_one_collision);
6069         data[7] = le32_to_cpu(tally.tx_multi_collision);
6070         data[8] = le64_to_cpu(tally.rx_unicast);
6071         data[9] = le64_to_cpu(tally.rx_broadcast);
6072         data[10] = le32_to_cpu(tally.rx_multicast);
6073         data[11] = le16_to_cpu(tally.tx_aborted);
6074         data[12] = le16_to_cpu(tally.tx_underrun);
6075 }
6076
6077 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6078 {
6079         switch (stringset) {
6080         case ETH_SS_STATS:
6081                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6082                 break;
6083         }
6084 }
6085
6086 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6087 {
6088         u32 lp, adv, supported = 0;
6089         u16 val;
6090
6091         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6092         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6093
6094         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6095         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6096
6097         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6098         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6099
6100         eee->eee_enabled = tp->eee_en;
6101         eee->eee_active = !!(supported & adv & lp);
6102         eee->supported = supported;
6103         eee->advertised = tp->eee_adv;
6104         eee->lp_advertised = lp;
6105
6106         return 0;
6107 }
6108
6109 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6110 {
6111         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6112
6113         tp->eee_en = eee->eee_enabled;
6114         tp->eee_adv = val;
6115
6116         rtl_eee_enable(tp, tp->eee_en);
6117
6118         return 0;
6119 }
6120
6121 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6122 {
6123         u32 lp, adv, supported = 0;
6124         u16 val;
6125
6126         val = ocp_reg_read(tp, OCP_EEE_ABLE);
6127         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6128
6129         val = ocp_reg_read(tp, OCP_EEE_ADV);
6130         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6131
6132         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6133         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6134
6135         eee->eee_enabled = tp->eee_en;
6136         eee->eee_active = !!(supported & adv & lp);
6137         eee->supported = supported;
6138         eee->advertised = tp->eee_adv;
6139         eee->lp_advertised = lp;
6140
6141         return 0;
6142 }
6143
6144 static int
6145 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6146 {
6147         struct r8152 *tp = netdev_priv(net);
6148         int ret;
6149
6150         if (!tp->rtl_ops.eee_get) {
6151                 ret = -EOPNOTSUPP;
6152                 goto out;
6153         }
6154
6155         ret = usb_autopm_get_interface(tp->intf);
6156         if (ret < 0)
6157                 goto out;
6158
6159         mutex_lock(&tp->control);
6160
6161         ret = tp->rtl_ops.eee_get(tp, edata);
6162
6163         mutex_unlock(&tp->control);
6164
6165         usb_autopm_put_interface(tp->intf);
6166
6167 out:
6168         return ret;
6169 }
6170
6171 static int
6172 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6173 {
6174         struct r8152 *tp = netdev_priv(net);
6175         int ret;
6176
6177         if (!tp->rtl_ops.eee_set) {
6178                 ret = -EOPNOTSUPP;
6179                 goto out;
6180         }
6181
6182         ret = usb_autopm_get_interface(tp->intf);
6183         if (ret < 0)
6184                 goto out;
6185
6186         mutex_lock(&tp->control);
6187
6188         ret = tp->rtl_ops.eee_set(tp, edata);
6189         if (!ret)
6190                 ret = mii_nway_restart(&tp->mii);
6191
6192         mutex_unlock(&tp->control);
6193
6194         usb_autopm_put_interface(tp->intf);
6195
6196 out:
6197         return ret;
6198 }
6199
6200 static int rtl8152_nway_reset(struct net_device *dev)
6201 {
6202         struct r8152 *tp = netdev_priv(dev);
6203         int ret;
6204
6205         ret = usb_autopm_get_interface(tp->intf);
6206         if (ret < 0)
6207                 goto out;
6208
6209         mutex_lock(&tp->control);
6210
6211         ret = mii_nway_restart(&tp->mii);
6212
6213         mutex_unlock(&tp->control);
6214
6215         usb_autopm_put_interface(tp->intf);
6216
6217 out:
6218         return ret;
6219 }
6220
6221 static int rtl8152_get_coalesce(struct net_device *netdev,
6222                                 struct ethtool_coalesce *coalesce)
6223 {
6224         struct r8152 *tp = netdev_priv(netdev);
6225
6226         switch (tp->version) {
6227         case RTL_VER_01:
6228         case RTL_VER_02:
6229         case RTL_VER_07:
6230                 return -EOPNOTSUPP;
6231         default:
6232                 break;
6233         }
6234
6235         coalesce->rx_coalesce_usecs = tp->coalesce;
6236
6237         return 0;
6238 }
6239
6240 static int rtl8152_set_coalesce(struct net_device *netdev,
6241                                 struct ethtool_coalesce *coalesce)
6242 {
6243         struct r8152 *tp = netdev_priv(netdev);
6244         int ret;
6245
6246         switch (tp->version) {
6247         case RTL_VER_01:
6248         case RTL_VER_02:
6249         case RTL_VER_07:
6250                 return -EOPNOTSUPP;
6251         default:
6252                 break;
6253         }
6254
6255         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6256                 return -EINVAL;
6257
6258         ret = usb_autopm_get_interface(tp->intf);
6259         if (ret < 0)
6260                 return ret;
6261
6262         mutex_lock(&tp->control);
6263
6264         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6265                 tp->coalesce = coalesce->rx_coalesce_usecs;
6266
6267                 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6268                         netif_stop_queue(netdev);
6269                         napi_disable(&tp->napi);
6270                         tp->rtl_ops.disable(tp);
6271                         tp->rtl_ops.enable(tp);
6272                         rtl_start_rx(tp);
6273                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6274                         _rtl8152_set_rx_mode(netdev);
6275                         napi_enable(&tp->napi);
6276                         netif_wake_queue(netdev);
6277                 }
6278         }
6279
6280         mutex_unlock(&tp->control);
6281
6282         usb_autopm_put_interface(tp->intf);
6283
6284         return ret;
6285 }
6286
6287 static int rtl8152_get_tunable(struct net_device *netdev,
6288                                const struct ethtool_tunable *tunable, void *d)
6289 {
6290         struct r8152 *tp = netdev_priv(netdev);
6291
6292         switch (tunable->id) {
6293         case ETHTOOL_RX_COPYBREAK:
6294                 *(u32 *)d = tp->rx_copybreak;
6295                 break;
6296         default:
6297                 return -EOPNOTSUPP;
6298         }
6299
6300         return 0;
6301 }
6302
6303 static int rtl8152_set_tunable(struct net_device *netdev,
6304                                const struct ethtool_tunable *tunable,
6305                                const void *d)
6306 {
6307         struct r8152 *tp = netdev_priv(netdev);
6308         u32 val;
6309
6310         switch (tunable->id) {
6311         case ETHTOOL_RX_COPYBREAK:
6312                 val = *(u32 *)d;
6313                 if (val < ETH_ZLEN) {
6314                         netif_err(tp, rx_err, netdev,
6315                                   "Invalid rx copy break value\n");
6316                         return -EINVAL;
6317                 }
6318
6319                 if (tp->rx_copybreak != val) {
6320                         if (netdev->flags & IFF_UP) {
6321                                 mutex_lock(&tp->control);
6322                                 napi_disable(&tp->napi);
6323                                 tp->rx_copybreak = val;
6324                                 napi_enable(&tp->napi);
6325                                 mutex_unlock(&tp->control);
6326                         } else {
6327                                 tp->rx_copybreak = val;
6328                         }
6329                 }
6330                 break;
6331         default:
6332                 return -EOPNOTSUPP;
6333         }
6334
6335         return 0;
6336 }
6337
6338 static void rtl8152_get_ringparam(struct net_device *netdev,
6339                                   struct ethtool_ringparam *ring)
6340 {
6341         struct r8152 *tp = netdev_priv(netdev);
6342
6343         ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6344         ring->rx_pending = tp->rx_pending;
6345 }
6346
6347 static int rtl8152_set_ringparam(struct net_device *netdev,
6348                                  struct ethtool_ringparam *ring)
6349 {
6350         struct r8152 *tp = netdev_priv(netdev);
6351
6352         if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6353                 return -EINVAL;
6354
6355         if (tp->rx_pending != ring->rx_pending) {
6356                 if (netdev->flags & IFF_UP) {
6357                         mutex_lock(&tp->control);
6358                         napi_disable(&tp->napi);
6359                         tp->rx_pending = ring->rx_pending;
6360                         napi_enable(&tp->napi);
6361                         mutex_unlock(&tp->control);
6362                 } else {
6363                         tp->rx_pending = ring->rx_pending;
6364                 }
6365         }
6366
6367         return 0;
6368 }
6369
6370 static const struct ethtool_ops ops = {
6371         .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6372         .get_drvinfo = rtl8152_get_drvinfo,
6373         .get_link = ethtool_op_get_link,
6374         .nway_reset = rtl8152_nway_reset,
6375         .get_msglevel = rtl8152_get_msglevel,
6376         .set_msglevel = rtl8152_set_msglevel,
6377         .get_wol = rtl8152_get_wol,
6378         .set_wol = rtl8152_set_wol,
6379         .get_strings = rtl8152_get_strings,
6380         .get_sset_count = rtl8152_get_sset_count,
6381         .get_ethtool_stats = rtl8152_get_ethtool_stats,
6382         .get_coalesce = rtl8152_get_coalesce,
6383         .set_coalesce = rtl8152_set_coalesce,
6384         .get_eee = rtl_ethtool_get_eee,
6385         .set_eee = rtl_ethtool_set_eee,
6386         .get_link_ksettings = rtl8152_get_link_ksettings,
6387         .set_link_ksettings = rtl8152_set_link_ksettings,
6388         .get_tunable = rtl8152_get_tunable,
6389         .set_tunable = rtl8152_set_tunable,
6390         .get_ringparam = rtl8152_get_ringparam,
6391         .set_ringparam = rtl8152_set_ringparam,
6392 };
6393
6394 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6395 {
6396         struct r8152 *tp = netdev_priv(netdev);
6397         struct mii_ioctl_data *data = if_mii(rq);
6398         int res;
6399
6400         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6401                 return -ENODEV;
6402
6403         res = usb_autopm_get_interface(tp->intf);
6404         if (res < 0)
6405                 goto out;
6406
6407         switch (cmd) {
6408         case SIOCGMIIPHY:
6409                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6410                 break;
6411
6412         case SIOCGMIIREG:
6413                 mutex_lock(&tp->control);
6414                 data->val_out = r8152_mdio_read(tp, data->reg_num);
6415                 mutex_unlock(&tp->control);
6416                 break;
6417
6418         case SIOCSMIIREG:
6419                 if (!capable(CAP_NET_ADMIN)) {
6420                         res = -EPERM;
6421                         break;
6422                 }
6423                 mutex_lock(&tp->control);
6424                 r8152_mdio_write(tp, data->reg_num, data->val_in);
6425                 mutex_unlock(&tp->control);
6426                 break;
6427
6428         default:
6429                 res = -EOPNOTSUPP;
6430         }
6431
6432         usb_autopm_put_interface(tp->intf);
6433
6434 out:
6435         return res;
6436 }
6437
6438 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6439 {
6440         struct r8152 *tp = netdev_priv(dev);
6441         int ret;
6442
6443         switch (tp->version) {
6444         case RTL_VER_01:
6445         case RTL_VER_02:
6446         case RTL_VER_07:
6447                 dev->mtu = new_mtu;
6448                 return 0;
6449         default:
6450                 break;
6451         }
6452
6453         ret = usb_autopm_get_interface(tp->intf);
6454         if (ret < 0)
6455                 return ret;
6456
6457         mutex_lock(&tp->control);
6458
6459         dev->mtu = new_mtu;
6460
6461         if (netif_running(dev)) {
6462                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6463
6464                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6465
6466                 if (netif_carrier_ok(dev))
6467                         r8153_set_rx_early_size(tp);
6468         }
6469
6470         mutex_unlock(&tp->control);
6471
6472         usb_autopm_put_interface(tp->intf);
6473
6474         return ret;
6475 }
6476
6477 static const struct net_device_ops rtl8152_netdev_ops = {
6478         .ndo_open               = rtl8152_open,
6479         .ndo_stop               = rtl8152_close,
6480         .ndo_do_ioctl           = rtl8152_ioctl,
6481         .ndo_start_xmit         = rtl8152_start_xmit,
6482         .ndo_tx_timeout         = rtl8152_tx_timeout,
6483         .ndo_set_features       = rtl8152_set_features,
6484         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
6485         .ndo_set_mac_address    = rtl8152_set_mac_address,
6486         .ndo_change_mtu         = rtl8152_change_mtu,
6487         .ndo_validate_addr      = eth_validate_addr,
6488         .ndo_features_check     = rtl8152_features_check,
6489 };
6490
6491 static void rtl8152_unload(struct r8152 *tp)
6492 {
6493         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6494                 return;
6495
6496         if (tp->version != RTL_VER_01)
6497                 r8152_power_cut_en(tp, true);
6498 }
6499
6500 static void rtl8153_unload(struct r8152 *tp)
6501 {
6502         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6503                 return;
6504
6505         r8153_power_cut_en(tp, false);
6506 }
6507
6508 static void rtl8153b_unload(struct r8152 *tp)
6509 {
6510         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6511                 return;
6512
6513         r8153b_power_cut_en(tp, false);
6514 }
6515
6516 static int rtl_ops_init(struct r8152 *tp)
6517 {
6518         struct rtl_ops *ops = &tp->rtl_ops;
6519         int ret = 0;
6520
6521         switch (tp->version) {
6522         case RTL_VER_01:
6523         case RTL_VER_02:
6524         case RTL_VER_07:
6525                 ops->init               = r8152b_init;
6526                 ops->enable             = rtl8152_enable;
6527                 ops->disable            = rtl8152_disable;
6528                 ops->up                 = rtl8152_up;
6529                 ops->down               = rtl8152_down;
6530                 ops->unload             = rtl8152_unload;
6531                 ops->eee_get            = r8152_get_eee;
6532                 ops->eee_set            = r8152_set_eee;
6533                 ops->in_nway            = rtl8152_in_nway;
6534                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
6535                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
6536                 tp->rx_buf_sz           = 16 * 1024;
6537                 tp->eee_en              = true;
6538                 tp->eee_adv             = MDIO_EEE_100TX;
6539                 break;
6540
6541         case RTL_VER_03:
6542         case RTL_VER_04:
6543         case RTL_VER_05:
6544         case RTL_VER_06:
6545                 ops->init               = r8153_init;
6546                 ops->enable             = rtl8153_enable;
6547                 ops->disable            = rtl8153_disable;
6548                 ops->up                 = rtl8153_up;
6549                 ops->down               = rtl8153_down;
6550                 ops->unload             = rtl8153_unload;
6551                 ops->eee_get            = r8153_get_eee;
6552                 ops->eee_set            = r8152_set_eee;
6553                 ops->in_nway            = rtl8153_in_nway;
6554                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
6555                 ops->autosuspend_en     = rtl8153_runtime_enable;
6556                 if (tp->udev->speed < USB_SPEED_SUPER)
6557                         tp->rx_buf_sz   = 16 * 1024;
6558                 else
6559                         tp->rx_buf_sz   = 32 * 1024;
6560                 tp->eee_en              = true;
6561                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6562                 break;
6563
6564         case RTL_VER_08:
6565         case RTL_VER_09:
6566                 ops->init               = r8153b_init;
6567                 ops->enable             = rtl8153_enable;
6568                 ops->disable            = rtl8153_disable;
6569                 ops->up                 = rtl8153b_up;
6570                 ops->down               = rtl8153b_down;
6571                 ops->unload             = rtl8153b_unload;
6572                 ops->eee_get            = r8153_get_eee;
6573                 ops->eee_set            = r8152_set_eee;
6574                 ops->in_nway            = rtl8153_in_nway;
6575                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
6576                 ops->autosuspend_en     = rtl8153b_runtime_enable;
6577                 tp->rx_buf_sz           = 32 * 1024;
6578                 tp->eee_en              = true;
6579                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6580                 break;
6581
6582         default:
6583                 ret = -ENODEV;
6584                 dev_err(&tp->intf->dev, "Unknown Device\n");
6585                 break;
6586         }
6587
6588         return ret;
6589 }
6590
6591 #define FIRMWARE_8153A_2        "rtl_nic/rtl8153a-2.fw"
6592 #define FIRMWARE_8153A_3        "rtl_nic/rtl8153a-3.fw"
6593 #define FIRMWARE_8153A_4        "rtl_nic/rtl8153a-4.fw"
6594 #define FIRMWARE_8153B_2        "rtl_nic/rtl8153b-2.fw"
6595
6596 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6597 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6598 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6599 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6600
6601 static int rtl_fw_init(struct r8152 *tp)
6602 {
6603         struct rtl_fw *rtl_fw = &tp->rtl_fw;
6604
6605         switch (tp->version) {
6606         case RTL_VER_04:
6607                 rtl_fw->fw_name         = FIRMWARE_8153A_2;
6608                 rtl_fw->pre_fw          = r8153_pre_firmware_1;
6609                 rtl_fw->post_fw         = r8153_post_firmware_1;
6610                 break;
6611         case RTL_VER_05:
6612                 rtl_fw->fw_name         = FIRMWARE_8153A_3;
6613                 rtl_fw->pre_fw          = r8153_pre_firmware_2;
6614                 rtl_fw->post_fw         = r8153_post_firmware_2;
6615                 break;
6616         case RTL_VER_06:
6617                 rtl_fw->fw_name         = FIRMWARE_8153A_4;
6618                 rtl_fw->post_fw         = r8153_post_firmware_3;
6619                 break;
6620         case RTL_VER_09:
6621                 rtl_fw->fw_name         = FIRMWARE_8153B_2;
6622                 rtl_fw->pre_fw          = r8153b_pre_firmware_1;
6623                 rtl_fw->post_fw         = r8153b_post_firmware_1;
6624                 break;
6625         default:
6626                 break;
6627         }
6628
6629         return 0;
6630 }
6631
6632 u8 rtl8152_get_version(struct usb_interface *intf)
6633 {
6634         struct usb_device *udev = interface_to_usbdev(intf);
6635         u32 ocp_data = 0;
6636         __le32 *tmp;
6637         u8 version;
6638         int ret;
6639
6640         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6641         if (!tmp)
6642                 return 0;
6643
6644         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6645                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6646                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6647         if (ret > 0)
6648                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6649
6650         kfree(tmp);
6651
6652         switch (ocp_data) {
6653         case 0x4c00:
6654                 version = RTL_VER_01;
6655                 break;
6656         case 0x4c10:
6657                 version = RTL_VER_02;
6658                 break;
6659         case 0x5c00:
6660                 version = RTL_VER_03;
6661                 break;
6662         case 0x5c10:
6663                 version = RTL_VER_04;
6664                 break;
6665         case 0x5c20:
6666                 version = RTL_VER_05;
6667                 break;
6668         case 0x5c30:
6669                 version = RTL_VER_06;
6670                 break;
6671         case 0x4800:
6672                 version = RTL_VER_07;
6673                 break;
6674         case 0x6000:
6675                 version = RTL_VER_08;
6676                 break;
6677         case 0x6010:
6678                 version = RTL_VER_09;
6679                 break;
6680         default:
6681                 version = RTL_VER_UNKNOWN;
6682                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6683                 break;
6684         }
6685
6686         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6687
6688         return version;
6689 }
6690 EXPORT_SYMBOL_GPL(rtl8152_get_version);
6691
6692 static int rtl8152_probe(struct usb_interface *intf,
6693                          const struct usb_device_id *id)
6694 {
6695         struct usb_device *udev = interface_to_usbdev(intf);
6696         u8 version = rtl8152_get_version(intf);
6697         struct r8152 *tp;
6698         struct net_device *netdev;
6699         int ret;
6700
6701         if (version == RTL_VER_UNKNOWN)
6702                 return -ENODEV;
6703
6704         if (udev->actconfig->desc.bConfigurationValue != 1) {
6705                 usb_driver_set_configuration(udev, 1);
6706                 return -ENODEV;
6707         }
6708
6709         if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6710                 return -ENODEV;
6711
6712         usb_reset_device(udev);
6713         netdev = alloc_etherdev(sizeof(struct r8152));
6714         if (!netdev) {
6715                 dev_err(&intf->dev, "Out of memory\n");
6716                 return -ENOMEM;
6717         }
6718
6719         SET_NETDEV_DEV(netdev, &intf->dev);
6720         tp = netdev_priv(netdev);
6721         tp->msg_enable = 0x7FFF;
6722
6723         tp->udev = udev;
6724         tp->netdev = netdev;
6725         tp->intf = intf;
6726         tp->version = version;
6727
6728         switch (version) {
6729         case RTL_VER_01:
6730         case RTL_VER_02:
6731         case RTL_VER_07:
6732                 tp->mii.supports_gmii = 0;
6733                 break;
6734         default:
6735                 tp->mii.supports_gmii = 1;
6736                 break;
6737         }
6738
6739         ret = rtl_ops_init(tp);
6740         if (ret)
6741                 goto out;
6742
6743         rtl_fw_init(tp);
6744
6745         mutex_init(&tp->control);
6746         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6747         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6748         tasklet_setup(&tp->tx_tl, bottom_half);
6749         tasklet_disable(&tp->tx_tl);
6750
6751         netdev->netdev_ops = &rtl8152_netdev_ops;
6752         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6753
6754         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6755                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6756                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6757                             NETIF_F_HW_VLAN_CTAG_TX;
6758         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6759                               NETIF_F_TSO | NETIF_F_FRAGLIST |
6760                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6761                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6762         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6763                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6764                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6765
6766         if (tp->version == RTL_VER_01) {
6767                 netdev->features &= ~NETIF_F_RXCSUM;
6768                 netdev->hw_features &= ~NETIF_F_RXCSUM;
6769         }
6770
6771         if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6772                 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6773                 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6774                 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6775                         set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6776                 }
6777         }
6778
6779         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6780             (!strcmp(udev->serial, "000001000000") ||
6781              !strcmp(udev->serial, "000002000000"))) {
6782                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6783                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6784         }
6785
6786         netdev->ethtool_ops = &ops;
6787         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6788
6789         /* MTU range: 68 - 1500 or 9194 */
6790         netdev->min_mtu = ETH_MIN_MTU;
6791         switch (tp->version) {
6792         case RTL_VER_01:
6793         case RTL_VER_02:
6794                 netdev->max_mtu = ETH_DATA_LEN;
6795                 break;
6796         default:
6797                 netdev->max_mtu = RTL8153_MAX_MTU;
6798                 break;
6799         }
6800
6801         tp->mii.dev = netdev;
6802         tp->mii.mdio_read = read_mii_word;
6803         tp->mii.mdio_write = write_mii_word;
6804         tp->mii.phy_id_mask = 0x3f;
6805         tp->mii.reg_num_mask = 0x1f;
6806         tp->mii.phy_id = R8152_PHY_ID;
6807
6808         tp->autoneg = AUTONEG_ENABLE;
6809         tp->speed = SPEED_100;
6810         tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6811                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6812         if (tp->mii.supports_gmii) {
6813                 tp->speed = SPEED_1000;
6814                 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6815         }
6816         tp->duplex = DUPLEX_FULL;
6817
6818         tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6819         tp->rx_pending = 10 * RTL8152_MAX_RX;
6820
6821         intf->needs_remote_wakeup = 1;
6822
6823         if (!rtl_can_wakeup(tp))
6824                 __rtl_set_wol(tp, 0);
6825         else
6826                 tp->saved_wolopts = __rtl_get_wol(tp);
6827
6828         tp->rtl_ops.init(tp);
6829 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6830         /* Retry in case request_firmware() is not ready yet. */
6831         tp->rtl_fw.retry = true;
6832 #endif
6833         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6834         set_ethernet_addr(tp);
6835
6836         usb_set_intfdata(intf, tp);
6837         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6838
6839         ret = register_netdev(netdev);
6840         if (ret != 0) {
6841                 dev_err(&intf->dev, "couldn't register the device\n");
6842                 goto out1;
6843         }
6844
6845         if (tp->saved_wolopts)
6846                 device_set_wakeup_enable(&udev->dev, true);
6847         else
6848                 device_set_wakeup_enable(&udev->dev, false);
6849
6850         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6851
6852         return 0;
6853
6854 out1:
6855         tasklet_kill(&tp->tx_tl);
6856         usb_set_intfdata(intf, NULL);
6857 out:
6858         free_netdev(netdev);
6859         return ret;
6860 }
6861
6862 static void rtl8152_disconnect(struct usb_interface *intf)
6863 {
6864         struct r8152 *tp = usb_get_intfdata(intf);
6865
6866         usb_set_intfdata(intf, NULL);
6867         if (tp) {
6868                 rtl_set_unplug(tp);
6869
6870                 unregister_netdev(tp->netdev);
6871                 tasklet_kill(&tp->tx_tl);
6872                 cancel_delayed_work_sync(&tp->hw_phy_work);
6873                 tp->rtl_ops.unload(tp);
6874                 rtl8152_release_firmware(tp);
6875                 free_netdev(tp->netdev);
6876         }
6877 }
6878
6879 #define REALTEK_USB_DEVICE(vend, prod)  \
6880         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6881                        USB_DEVICE_ID_MATCH_INT_CLASS, \
6882         .idVendor = (vend), \
6883         .idProduct = (prod), \
6884         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6885 }, \
6886 { \
6887         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6888                        USB_DEVICE_ID_MATCH_DEVICE, \
6889         .idVendor = (vend), \
6890         .idProduct = (prod), \
6891         .bInterfaceClass = USB_CLASS_COMM, \
6892         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6893         .bInterfaceProtocol = USB_CDC_PROTO_NONE
6894
6895 /* table of devices that work with this driver */
6896 static const struct usb_device_id rtl8152_table[] = {
6897         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6898         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6899         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6900         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6901         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6902         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6903         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6904         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6905         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6906         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6907         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6908         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6909         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6910         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6911         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e)},
6912         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6913         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6914         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6915         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6916         {}
6917 };
6918
6919 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6920
6921 static struct usb_driver rtl8152_driver = {
6922         .name =         MODULENAME,
6923         .id_table =     rtl8152_table,
6924         .probe =        rtl8152_probe,
6925         .disconnect =   rtl8152_disconnect,
6926         .suspend =      rtl8152_suspend,
6927         .resume =       rtl8152_resume,
6928         .reset_resume = rtl8152_reset_resume,
6929         .pre_reset =    rtl8152_pre_reset,
6930         .post_reset =   rtl8152_post_reset,
6931         .supports_autosuspend = 1,
6932         .disable_hub_initiated_lpm = 1,
6933 };
6934
6935 module_usb_driver(rtl8152_driver);
6936
6937 MODULE_AUTHOR(DRIVER_AUTHOR);
6938 MODULE_DESCRIPTION(DRIVER_DESC);
6939 MODULE_LICENSE("GPL");
6940 MODULE_VERSION(DRIVER_VERSION);