1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "11"
34 /* Information for net */
35 #define NET_VERSION "11"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PLA_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_UPHY_TIMER 0xd388
61 #define PLA_SUSPEND_FLAG 0xd38a
62 #define PLA_INDICATE_FALG 0xd38c
63 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
64 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
65 #define PLA_EXTRA_STATUS 0xd398
66 #define PLA_EFUSE_DATA 0xdd00
67 #define PLA_EFUSE_CMD 0xdd02
68 #define PLA_LEDSEL 0xdd90
69 #define PLA_LED_FEATURE 0xdd92
70 #define PLA_PHYAR 0xde00
71 #define PLA_BOOT_CTRL 0xe004
72 #define PLA_LWAKE_CTRL_REG 0xe007
73 #define PLA_GPHY_INTR_IMR 0xe022
74 #define PLA_EEE_CR 0xe040
75 #define PLA_EEEP_CR 0xe080
76 #define PLA_MAC_PWR_CTRL 0xe0c0
77 #define PLA_MAC_PWR_CTRL2 0xe0ca
78 #define PLA_MAC_PWR_CTRL3 0xe0cc
79 #define PLA_MAC_PWR_CTRL4 0xe0ce
80 #define PLA_WDT6_CTRL 0xe428
81 #define PLA_TCR0 0xe610
82 #define PLA_TCR1 0xe612
83 #define PLA_MTPS 0xe615
84 #define PLA_TXFIFO_CTRL 0xe618
85 #define PLA_RSTTALLY 0xe800
87 #define PLA_CRWECR 0xe81c
88 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
89 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
90 #define PLA_CONFIG5 0xe822
91 #define PLA_PHY_PWR 0xe84c
92 #define PLA_OOB_CTRL 0xe84f
93 #define PLA_CPCR 0xe854
94 #define PLA_MISC_0 0xe858
95 #define PLA_MISC_1 0xe85a
96 #define PLA_OCP_GPHY_BASE 0xe86c
97 #define PLA_TALLYCNT 0xe890
98 #define PLA_SFF_STS_7 0xe8de
99 #define PLA_PHYSTATUS 0xe908
100 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
101 #define PLA_BP_BA 0xfc26
102 #define PLA_BP_0 0xfc28
103 #define PLA_BP_1 0xfc2a
104 #define PLA_BP_2 0xfc2c
105 #define PLA_BP_3 0xfc2e
106 #define PLA_BP_4 0xfc30
107 #define PLA_BP_5 0xfc32
108 #define PLA_BP_6 0xfc34
109 #define PLA_BP_7 0xfc36
110 #define PLA_BP_EN 0xfc38
112 #define USB_USB2PHY 0xb41e
113 #define USB_SSPHYLINK1 0xb426
114 #define USB_SSPHYLINK2 0xb428
115 #define USB_U2P3_CTRL 0xb460
116 #define USB_CSR_DUMMY1 0xb464
117 #define USB_CSR_DUMMY2 0xb466
118 #define USB_DEV_STAT 0xb808
119 #define USB_CONNECT_TIMER 0xcbf8
120 #define USB_MSC_TIMER 0xcbfc
121 #define USB_BURST_SIZE 0xcfc0
122 #define USB_FW_FIX_EN0 0xcfca
123 #define USB_FW_FIX_EN1 0xcfcc
124 #define USB_LPM_CONFIG 0xcfd8
125 #define USB_CSTMR 0xcfef /* RTL8153A */
126 #define USB_FW_CTRL 0xd334 /* RTL8153B */
127 #define USB_FC_TIMER 0xd340
128 #define USB_USB_CTRL 0xd406
129 #define USB_PHY_CTRL 0xd408
130 #define USB_TX_AGG 0xd40a
131 #define USB_RX_BUF_TH 0xd40c
132 #define USB_USB_TIMER 0xd428
133 #define USB_RX_EARLY_TIMEOUT 0xd42c
134 #define USB_RX_EARLY_SIZE 0xd42e
135 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
136 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
137 #define USB_TX_DMA 0xd434
138 #define USB_UPT_RXDMA_OWN 0xd437
139 #define USB_TOLERANCE 0xd490
140 #define USB_LPM_CTRL 0xd41a
141 #define USB_BMU_RESET 0xd4b0
142 #define USB_U1U2_TIMER 0xd4da
143 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
144 #define USB_UPS_CTRL 0xd800
145 #define USB_POWER_CUT 0xd80a
146 #define USB_MISC_0 0xd81a
147 #define USB_MISC_1 0xd81f
148 #define USB_AFE_CTRL2 0xd824
149 #define USB_UPS_CFG 0xd842
150 #define USB_UPS_FLAGS 0xd848
151 #define USB_WDT1_CTRL 0xe404
152 #define USB_WDT11_CTRL 0xe43c
153 #define USB_BP_BA PLA_BP_BA
154 #define USB_BP_0 PLA_BP_0
155 #define USB_BP_1 PLA_BP_1
156 #define USB_BP_2 PLA_BP_2
157 #define USB_BP_3 PLA_BP_3
158 #define USB_BP_4 PLA_BP_4
159 #define USB_BP_5 PLA_BP_5
160 #define USB_BP_6 PLA_BP_6
161 #define USB_BP_7 PLA_BP_7
162 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
163 #define USB_BP_8 0xfc38 /* RTL8153B */
164 #define USB_BP_9 0xfc3a
165 #define USB_BP_10 0xfc3c
166 #define USB_BP_11 0xfc3e
167 #define USB_BP_12 0xfc40
168 #define USB_BP_13 0xfc42
169 #define USB_BP_14 0xfc44
170 #define USB_BP_15 0xfc46
171 #define USB_BP2_EN 0xfc48
174 #define OCP_ALDPS_CONFIG 0x2010
175 #define OCP_EEE_CONFIG1 0x2080
176 #define OCP_EEE_CONFIG2 0x2092
177 #define OCP_EEE_CONFIG3 0x2094
178 #define OCP_BASE_MII 0xa400
179 #define OCP_EEE_AR 0xa41a
180 #define OCP_EEE_DATA 0xa41c
181 #define OCP_PHY_STATUS 0xa420
182 #define OCP_NCTL_CFG 0xa42c
183 #define OCP_POWER_CFG 0xa430
184 #define OCP_EEE_CFG 0xa432
185 #define OCP_SRAM_ADDR 0xa436
186 #define OCP_SRAM_DATA 0xa438
187 #define OCP_DOWN_SPEED 0xa442
188 #define OCP_EEE_ABLE 0xa5c4
189 #define OCP_EEE_ADV 0xa5d0
190 #define OCP_EEE_LPABLE 0xa5d2
191 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
192 #define OCP_PHY_PATCH_STAT 0xb800
193 #define OCP_PHY_PATCH_CMD 0xb820
194 #define OCP_PHY_LOCK 0xb82e
195 #define OCP_ADC_IOFFSET 0xbcfc
196 #define OCP_ADC_CFG 0xbc06
197 #define OCP_SYSCLK_CFG 0xc416
200 #define SRAM_GREEN_CFG 0x8011
201 #define SRAM_LPF_CFG 0x8012
202 #define SRAM_10M_AMP1 0x8080
203 #define SRAM_10M_AMP2 0x8082
204 #define SRAM_IMPEDANCE 0x8084
205 #define SRAM_PHY_LOCK 0xb82e
208 #define RCR_AAP 0x00000001
209 #define RCR_APM 0x00000002
210 #define RCR_AM 0x00000004
211 #define RCR_AB 0x00000008
212 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
214 /* PLA_RXFIFO_CTRL0 */
215 #define RXFIFO_THR1_NORMAL 0x00080002
216 #define RXFIFO_THR1_OOB 0x01800003
218 /* PLA_RXFIFO_CTRL1 */
219 #define RXFIFO_THR2_FULL 0x00000060
220 #define RXFIFO_THR2_HIGH 0x00000038
221 #define RXFIFO_THR2_OOB 0x0000004a
222 #define RXFIFO_THR2_NORMAL 0x00a0
224 /* PLA_RXFIFO_CTRL2 */
225 #define RXFIFO_THR3_FULL 0x00000078
226 #define RXFIFO_THR3_HIGH 0x00000048
227 #define RXFIFO_THR3_OOB 0x0000005a
228 #define RXFIFO_THR3_NORMAL 0x0110
230 /* PLA_TXFIFO_CTRL */
231 #define TXFIFO_THR_NORMAL 0x00400008
232 #define TXFIFO_THR_NORMAL2 0x01000008
235 #define ECM_ALDPS 0x0002
238 #define FMC_FCR_MCU_EN 0x0001
241 #define EEEP_CR_EEEP_TX 0x0002
244 #define WDT6_SET_MODE 0x0010
247 #define TCR0_TX_EMPTY 0x0800
248 #define TCR0_AUTO_FIFO 0x0080
251 #define VERSION_MASK 0x7cf0
254 #define MTPS_JUMBO (12 * 1024 / 64)
255 #define MTPS_DEFAULT (6 * 1024 / 64)
258 #define TALLY_RESET 0x0001
266 #define CRWECR_NORAML 0x00
267 #define CRWECR_CONFIG 0xc0
270 #define NOW_IS_OOB 0x80
271 #define TXFIFO_EMPTY 0x20
272 #define RXFIFO_EMPTY 0x10
273 #define LINK_LIST_READY 0x02
274 #define DIS_MCU_CLROOB 0x01
275 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
278 #define RXDY_GATED_EN 0x0008
281 #define RE_INIT_LL 0x8000
282 #define MCU_BORW_EN 0x4000
285 #define CPCR_RX_VLAN 0x0040
288 #define MAGIC_EN 0x0001
291 #define TEREDO_SEL 0x8000
292 #define TEREDO_WAKE_MASK 0x7f00
293 #define TEREDO_RS_EVENT_MASK 0x00fe
294 #define OOB_TEREDO_EN 0x0001
297 #define ALDPS_PROXY_MODE 0x0001
300 #define EFUSE_READ_CMD BIT(15)
301 #define EFUSE_DATA_BIT16 BIT(7)
304 #define LINK_ON_WAKE_EN 0x0010
305 #define LINK_OFF_WAKE_EN 0x0008
308 #define LANWAKE_CLR_EN BIT(0)
311 #define BWF_EN 0x0040
312 #define MWF_EN 0x0020
313 #define UWF_EN 0x0010
314 #define LAN_WAKE_EN 0x0002
316 /* PLA_LED_FEATURE */
317 #define LED_MODE_MASK 0x0700
320 #define TX_10M_IDLE_EN 0x0080
321 #define PFM_PWM_SWITCH 0x0040
322 #define TEST_IO_OFF BIT(4)
324 /* PLA_MAC_PWR_CTRL */
325 #define D3_CLK_GATED_EN 0x00004000
326 #define MCU_CLK_RATIO 0x07010f07
327 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
328 #define ALDPS_SPDWN_RATIO 0x0f87
330 /* PLA_MAC_PWR_CTRL2 */
331 #define EEE_SPDWN_RATIO 0x8007
332 #define MAC_CLK_SPDWN_EN BIT(15)
334 /* PLA_MAC_PWR_CTRL3 */
335 #define PLA_MCU_SPDWN_EN BIT(14)
336 #define PKT_AVAIL_SPDWN_EN 0x0100
337 #define SUSPEND_SPDWN_EN 0x0004
338 #define U1U2_SPDWN_EN 0x0002
339 #define L1_SPDWN_EN 0x0001
341 /* PLA_MAC_PWR_CTRL4 */
342 #define PWRSAVE_SPDWN_EN 0x1000
343 #define RXDV_SPDWN_EN 0x0800
344 #define TX10MIDLE_EN 0x0100
345 #define TP100_SPDWN_EN 0x0020
346 #define TP500_SPDWN_EN 0x0010
347 #define TP1000_SPDWN_EN 0x0008
348 #define EEE_SPDWN_EN 0x0001
350 /* PLA_GPHY_INTR_IMR */
351 #define GPHY_STS_MSK 0x0001
352 #define SPEED_DOWN_MSK 0x0002
353 #define SPDWN_RXDV_MSK 0x0004
354 #define SPDWN_LINKCHG_MSK 0x0008
357 #define PHYAR_FLAG 0x80000000
360 #define EEE_RX_EN 0x0001
361 #define EEE_TX_EN 0x0002
364 #define AUTOLOAD_DONE 0x0002
366 /* PLA_LWAKE_CTRL_REG */
367 #define LANWAKE_PIN BIT(7)
369 /* PLA_SUSPEND_FLAG */
370 #define LINK_CHG_EVENT BIT(0)
372 /* PLA_INDICATE_FALG */
373 #define UPCOMING_RUNTIME_D3 BIT(0)
375 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
376 #define DEBUG_OE BIT(0)
377 #define DEBUG_LTSSM 0x0082
379 /* PLA_EXTRA_STATUS */
380 #define CUR_LINK_OK BIT(15)
381 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
382 #define LINK_CHANGE_FLAG BIT(8)
383 #define POLL_LINK_CHG BIT(0)
386 #define USB2PHY_SUSPEND 0x0001
387 #define USB2PHY_L1 0x0002
390 #define DELAY_PHY_PWR_CHG BIT(1)
393 #define pwd_dn_scale_mask 0x3ffe
394 #define pwd_dn_scale(x) ((x) << 1)
397 #define DYNAMIC_BURST 0x0001
400 #define EP4_FULL_FC 0x0001
403 #define STAT_SPEED_MASK 0x0006
404 #define STAT_SPEED_HIGH 0x0000
405 #define STAT_SPEED_FULL 0x0002
408 #define FW_FIX_SUSPEND BIT(14)
411 #define FW_IP_RESET_EN BIT(9)
414 #define LPM_U1U2_EN BIT(0)
417 #define TX_AGG_MAX_THRESHOLD 0x03
420 #define RX_THR_SUPPER 0x0c350180
421 #define RX_THR_HIGH 0x7a120180
422 #define RX_THR_SLOW 0xffff0180
423 #define RX_THR_B 0x00010001
426 #define TEST_MODE_DISABLE 0x00000001
427 #define TX_SIZE_ADJUST1 0x00000100
430 #define BMU_RESET_EP_IN 0x01
431 #define BMU_RESET_EP_OUT 0x02
433 /* USB_UPT_RXDMA_OWN */
434 #define OWN_UPDATE BIT(0)
435 #define OWN_CLEAR BIT(1)
438 #define FC_PATCH_TASK BIT(1)
441 #define POWER_CUT 0x0100
443 /* USB_PM_CTRL_STATUS */
444 #define RESUME_INDICATE 0x0001
447 #define FORCE_SUPER BIT(0)
450 #define FLOW_CTRL_PATCH_OPT BIT(1)
453 #define CTRL_TIMER_EN BIT(15)
456 #define RX_AGG_DISABLE 0x0010
457 #define RX_ZERO_EN 0x0080
460 #define U2P3_ENABLE 0x0001
463 #define PWR_EN 0x0001
464 #define PHASE2_EN 0x0008
465 #define UPS_EN BIT(4)
466 #define USP_PREWAKE BIT(5)
469 #define PCUT_STATUS 0x0001
471 /* USB_RX_EARLY_TIMEOUT */
472 #define COALESCE_SUPER 85000U
473 #define COALESCE_HIGH 250000U
474 #define COALESCE_SLOW 524280U
477 #define WTD1_EN BIT(0)
480 #define TIMER11_EN 0x0001
483 /* bit 4 ~ 5: fifo empty boundary */
484 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
485 /* bit 2 ~ 3: LMP timer */
486 #define LPM_TIMER_MASK 0x0c
487 #define LPM_TIMER_500MS 0x04 /* 500 ms */
488 #define LPM_TIMER_500US 0x0c /* 500 us */
489 #define ROK_EXIT_LPM 0x02
492 #define SEN_VAL_MASK 0xf800
493 #define SEN_VAL_NORMAL 0xa000
494 #define SEL_RXIDLE 0x0100
497 #define SAW_CNT_1MS_MASK 0x0fff
500 #define UPS_FLAGS_R_TUNE BIT(0)
501 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
502 #define UPS_FLAGS_250M_CKDIV BIT(2)
503 #define UPS_FLAGS_EN_ALDPS BIT(3)
504 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
505 #define ups_flags_speed(x) ((x) << 16)
506 #define UPS_FLAGS_EN_EEE BIT(20)
507 #define UPS_FLAGS_EN_500M_EEE BIT(21)
508 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
509 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
510 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
511 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
512 #define UPS_FLAGS_EN_GREEN BIT(26)
513 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
527 /* OCP_ALDPS_CONFIG */
528 #define ENPWRSAVE 0x8000
529 #define ENPDNPS 0x0200
530 #define LINKENA 0x0100
531 #define DIS_SDSAVE 0x0010
534 #define PHY_STAT_MASK 0x0007
535 #define PHY_STAT_EXT_INIT 2
536 #define PHY_STAT_LAN_ON 3
537 #define PHY_STAT_PWRDN 5
540 #define PGA_RETURN_EN BIT(1)
543 #define EEE_CLKDIV_EN 0x8000
544 #define EN_ALDPS 0x0004
545 #define EN_10M_PLLOFF 0x0001
547 /* OCP_EEE_CONFIG1 */
548 #define RG_TXLPI_MSK_HFDUP 0x8000
549 #define RG_MATCLR_EN 0x4000
550 #define EEE_10_CAP 0x2000
551 #define EEE_NWAY_EN 0x1000
552 #define TX_QUIET_EN 0x0200
553 #define RX_QUIET_EN 0x0100
554 #define sd_rise_time_mask 0x0070
555 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
556 #define RG_RXLPI_MSK_HFDUP 0x0008
557 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
559 /* OCP_EEE_CONFIG2 */
560 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
561 #define RG_DACQUIET_EN 0x0400
562 #define RG_LDVQUIET_EN 0x0200
563 #define RG_CKRSEL 0x0020
564 #define RG_EEEPRG_EN 0x0010
566 /* OCP_EEE_CONFIG3 */
567 #define fast_snr_mask 0xff80
568 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
569 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
570 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
573 /* bit[15:14] function */
574 #define FUN_ADDR 0x0000
575 #define FUN_DATA 0x4000
576 /* bit[4:0] device addr */
579 #define CTAP_SHORT_EN 0x0040
580 #define EEE10_EN 0x0010
583 #define EN_EEE_CMODE BIT(14)
584 #define EN_EEE_1000 BIT(13)
585 #define EN_EEE_100 BIT(12)
586 #define EN_10M_CLKDIV BIT(11)
587 #define EN_10M_BGOFF 0x0080
590 #define TXDIS_STATE 0x01
591 #define ABD_STATE 0x02
593 /* OCP_PHY_PATCH_STAT */
594 #define PATCH_READY BIT(6)
596 /* OCP_PHY_PATCH_CMD */
597 #define PATCH_REQUEST BIT(4)
600 #define PATCH_LOCK BIT(0)
603 #define CKADSEL_L 0x0100
604 #define ADC_EN 0x0080
605 #define EN_EMI_L 0x0040
608 #define clk_div_expo(x) (min(x, 5) << 8)
611 #define GREEN_ETH_EN BIT(15)
612 #define R_TUNE_EN BIT(11)
615 #define LPF_AUTO_TUNE 0x8000
618 #define GDAC_IB_UPALL 0x0008
621 #define AMP_DN 0x0200
624 #define RX_DRIVING_MASK 0x6000
627 #define PHY_PATCH_LOCK 0x0001
630 #define AD_MASK 0xfee0
631 #define BND_MASK 0x0004
632 #define BD_MASK 0x0001
634 #define PASS_THRU_MASK 0x1
636 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
638 enum rtl_register_content {
646 #define RTL8152_MAX_TX 4
647 #define RTL8152_MAX_RX 10
652 #define RTL8152_RX_MAX_PENDING 4096
653 #define RTL8152_RXFG_HEADSZ 256
655 #define INTR_LINK 0x0004
657 #define RTL8153_MAX_PACKET 9216 /* 9K */
658 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
660 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
661 #define RTL8153_RMS RTL8153_MAX_PACKET
662 #define RTL8152_TX_TIMEOUT (5 * HZ)
663 #define RTL8152_NAPI_WEIGHT 64
664 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
665 sizeof(struct rx_desc) + RX_ALIGN)
681 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
682 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
684 struct tally_counter {
691 __le32 tx_one_collision;
692 __le32 tx_multi_collision;
702 #define RX_LEN_MASK 0x7fff
705 #define RD_UDP_CS BIT(23)
706 #define RD_TCP_CS BIT(22)
707 #define RD_IPV6_CS BIT(20)
708 #define RD_IPV4_CS BIT(19)
711 #define IPF BIT(23) /* IP checksum fail */
712 #define UDPF BIT(22) /* UDP checksum fail */
713 #define TCPF BIT(21) /* TCP checksum fail */
714 #define RX_VLAN_TAG BIT(16)
723 #define TX_FS BIT(31) /* First segment of a packet */
724 #define TX_LS BIT(30) /* Final segment of a packet */
725 #define GTSENDV4 BIT(28)
726 #define GTSENDV6 BIT(27)
727 #define GTTCPHO_SHIFT 18
728 #define GTTCPHO_MAX 0x7fU
729 #define TX_LEN_MAX 0x3ffffU
732 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
733 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
734 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
735 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
737 #define MSS_MAX 0x7ffU
738 #define TCPHO_SHIFT 17
739 #define TCPHO_MAX 0x7ffU
740 #define TX_VLAN_TAG BIT(16)
746 struct list_head list, info_list;
748 struct r8152 *context;
754 struct list_head list;
756 struct r8152 *context;
765 struct usb_device *udev;
766 struct napi_struct napi;
767 struct usb_interface *intf;
768 struct net_device *netdev;
769 struct urb *intr_urb;
770 struct tx_agg tx_info[RTL8152_MAX_TX];
771 struct list_head rx_info, rx_used;
772 struct list_head rx_done, tx_free;
773 struct sk_buff_head tx_queue, rx_queue;
774 spinlock_t rx_lock, tx_lock;
775 struct delayed_work schedule, hw_phy_work;
776 struct mii_if_info mii;
777 struct mutex control; /* use for hw setting */
778 #ifdef CONFIG_PM_SLEEP
779 struct notifier_block pm_notifier;
781 struct tasklet_struct tx_tl;
784 void (*init)(struct r8152 *tp);
785 int (*enable)(struct r8152 *tp);
786 void (*disable)(struct r8152 *tp);
787 void (*up)(struct r8152 *tp);
788 void (*down)(struct r8152 *tp);
789 void (*unload)(struct r8152 *tp);
790 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
791 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
792 bool (*in_nway)(struct r8152 *tp);
793 void (*hw_phy_cfg)(struct r8152 *tp);
794 void (*autosuspend_en)(struct r8152 *tp, bool enable);
806 u32 eee_plloff_100:1;
807 u32 eee_plloff_giga:1;
811 u32 ctap_short_off:1;
814 #define RTL_VER_SIZE 32
818 const struct firmware *fw;
820 char version[RTL_VER_SIZE];
821 int (*pre_fw)(struct r8152 *tp);
822 int (*post_fw)(struct r8152 *tp);
850 * struct fw_block - block type and total length
851 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
852 * RTL_FW_USB and so on.
853 * @length: total length of the current block.
861 * struct fw_header - header of the firmware file
862 * @checksum: checksum of sha256 which is calculated from the whole file
863 * except the checksum field of the file. That is, calculate sha256
864 * from the version field to the end of the file.
865 * @version: version of this firmware.
866 * @blocks: the first firmware block of the file
870 char version[RTL_VER_SIZE];
871 struct fw_block blocks[];
875 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
876 * The layout of the firmware block is:
877 * <struct fw_mac> + <info> + <firmware data>.
878 * @blk_hdr: firmware descriptor (type, length)
879 * @fw_offset: offset of the firmware binary data. The start address of
880 * the data would be the address of struct fw_mac + @fw_offset.
881 * @fw_reg: the register to load the firmware. Depends on chip.
882 * @bp_ba_addr: the register to write break point base address. Depends on
884 * @bp_ba_value: break point base address. Depends on chip.
885 * @bp_en_addr: the register to write break point enabled mask. Depends
887 * @bp_en_value: break point enabled mask. Depends on the firmware.
888 * @bp_start: the start register of break points. Depends on chip.
889 * @bp_num: the break point number which needs to be set for this firmware.
890 * Depends on the firmware.
891 * @bp: break points. Depends on firmware.
892 * @reserved: reserved space (unused)
893 * @fw_ver_reg: the register to store the fw version.
894 * @fw_ver_data: the firmware version of the current type.
895 * @info: additional information for debugging, and is followed by the
896 * binary data of firmware.
899 struct fw_block blk_hdr;
908 __le16 bp[16]; /* any value determined by firmware */
916 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
917 * This is used to set patch key when loading the firmware of PHY.
918 * @blk_hdr: firmware descriptor (type, length)
919 * @key_reg: the register to write the patch key.
920 * @key_data: patch key.
921 * @reserved: reserved space (unused)
923 struct fw_phy_patch_key {
924 struct fw_block blk_hdr;
931 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
932 * The layout of the firmware block is:
933 * <struct fw_phy_nc> + <info> + <firmware data>.
934 * @blk_hdr: firmware descriptor (type, length)
935 * @fw_offset: offset of the firmware binary data. The start address of
936 * the data would be the address of struct fw_phy_nc + @fw_offset.
937 * @fw_reg: the register to load the firmware. Depends on chip.
938 * @ba_reg: the register to write the base address. Depends on chip.
939 * @ba_data: base address. Depends on chip.
940 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
941 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
942 * @mode_reg: the regitster of switching the mode.
943 * @mode_pre: the mode needing to be set before loading the firmware.
944 * @mode_post: the mode to be set when finishing to load the firmware.
945 * @reserved: reserved space (unused)
946 * @bp_start: the start register of break points. Depends on chip.
947 * @bp_num: the break point number which needs to be set for this firmware.
948 * Depends on the firmware.
949 * @bp: break points. Depends on firmware.
950 * @info: additional information for debugging, and is followed by the
951 * binary data of firmware.
954 struct fw_block blk_hdr;
959 __le16 patch_en_addr;
960 __le16 patch_en_value;
1000 #define RTL_ADVERTISED_10_HALF BIT(0)
1001 #define RTL_ADVERTISED_10_FULL BIT(1)
1002 #define RTL_ADVERTISED_100_HALF BIT(2)
1003 #define RTL_ADVERTISED_100_FULL BIT(3)
1004 #define RTL_ADVERTISED_1000_HALF BIT(4)
1005 #define RTL_ADVERTISED_1000_FULL BIT(5)
1007 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1008 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1010 static const int multicast_filter_limit = 32;
1011 static unsigned int agg_buf_sz = 16384;
1013 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
1014 VLAN_ETH_HLEN - ETH_FCS_LEN)
1017 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1022 tmp = kmalloc(size, GFP_KERNEL);
1026 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1027 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1028 value, index, tmp, size, 500);
1030 memset(data, 0xff, size);
1032 memcpy(data, tmp, size);
1040 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1045 tmp = kmemdup(data, size, GFP_KERNEL);
1049 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1050 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1051 value, index, tmp, size, 500);
1058 static void rtl_set_unplug(struct r8152 *tp)
1060 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1061 set_bit(RTL8152_UNPLUG, &tp->flags);
1062 smp_mb__after_atomic();
1066 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1067 void *data, u16 type)
1072 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1075 /* both size and indix must be 4 bytes align */
1076 if ((size & 3) || !size || (index & 3) || !data)
1079 if ((u32)index + (u32)size > 0xffff)
1084 ret = get_registers(tp, index, type, limit, data);
1092 ret = get_registers(tp, index, type, size, data);
1109 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1110 u16 size, void *data, u16 type)
1113 u16 byteen_start, byteen_end, byen;
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1119 /* both size and indix must be 4 bytes align */
1120 if ((size & 3) || !size || (index & 3) || !data)
1123 if ((u32)index + (u32)size > 0xffff)
1126 byteen_start = byteen & BYTE_EN_START_MASK;
1127 byteen_end = byteen & BYTE_EN_END_MASK;
1129 byen = byteen_start | (byteen_start << 4);
1130 ret = set_registers(tp, index, type | byen, 4, data);
1143 ret = set_registers(tp, index,
1144 type | BYTE_EN_DWORD,
1153 ret = set_registers(tp, index,
1154 type | BYTE_EN_DWORD,
1166 byen = byteen_end | (byteen_end >> 4);
1167 ret = set_registers(tp, index, type | byen, 4, data);
1180 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1182 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1186 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1188 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1192 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1194 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1197 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1201 generic_ocp_read(tp, index, sizeof(data), &data, type);
1203 return __le32_to_cpu(data);
1206 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1208 __le32 tmp = __cpu_to_le32(data);
1210 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1213 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1217 u16 byen = BYTE_EN_WORD;
1218 u8 shift = index & 2;
1223 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1225 data = __le32_to_cpu(tmp);
1226 data >>= (shift * 8);
1232 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1236 u16 byen = BYTE_EN_WORD;
1237 u8 shift = index & 2;
1243 mask <<= (shift * 8);
1244 data <<= (shift * 8);
1248 tmp = __cpu_to_le32(data);
1250 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1253 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1257 u8 shift = index & 3;
1261 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1263 data = __le32_to_cpu(tmp);
1264 data >>= (shift * 8);
1270 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1274 u16 byen = BYTE_EN_BYTE;
1275 u8 shift = index & 3;
1281 mask <<= (shift * 8);
1282 data <<= (shift * 8);
1286 tmp = __cpu_to_le32(data);
1288 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1291 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1293 u16 ocp_base, ocp_index;
1295 ocp_base = addr & 0xf000;
1296 if (ocp_base != tp->ocp_base) {
1297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1298 tp->ocp_base = ocp_base;
1301 ocp_index = (addr & 0x0fff) | 0xb000;
1302 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1305 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1307 u16 ocp_base, ocp_index;
1309 ocp_base = addr & 0xf000;
1310 if (ocp_base != tp->ocp_base) {
1311 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1312 tp->ocp_base = ocp_base;
1315 ocp_index = (addr & 0x0fff) | 0xb000;
1316 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1319 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1321 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1324 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1326 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1329 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1331 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1332 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1335 static u16 sram_read(struct r8152 *tp, u16 addr)
1337 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1338 return ocp_reg_read(tp, OCP_SRAM_DATA);
1341 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1343 struct r8152 *tp = netdev_priv(netdev);
1346 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1349 if (phy_id != R8152_PHY_ID)
1352 ret = r8152_mdio_read(tp, reg);
1358 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1360 struct r8152 *tp = netdev_priv(netdev);
1362 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1365 if (phy_id != R8152_PHY_ID)
1368 r8152_mdio_write(tp, reg, val);
1372 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1375 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1378 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1380 struct r8152 *tp = netdev_priv(netdev);
1381 struct sockaddr *addr = p;
1382 int ret = -EADDRNOTAVAIL;
1384 if (!is_valid_ether_addr(addr->sa_data))
1387 ret = usb_autopm_get_interface(tp->intf);
1391 mutex_lock(&tp->control);
1393 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1395 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1396 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1397 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1399 mutex_unlock(&tp->control);
1401 usb_autopm_put_interface(tp->intf);
1406 /* Devices containing proper chips can support a persistent
1407 * host system provided MAC address.
1408 * Examples of this are Dell TB15 and Dell WD15 docks
1410 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1413 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1414 union acpi_object *obj;
1417 unsigned char buf[6];
1419 acpi_object_type mac_obj_type;
1422 if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1423 mac_obj_name = "\\MACA";
1424 mac_obj_type = ACPI_TYPE_STRING;
1427 /* test for -AD variant of RTL8153 */
1428 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1429 if ((ocp_data & AD_MASK) == 0x1000) {
1430 /* test for MAC address pass-through bit */
1431 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1432 if ((ocp_data & PASS_THRU_MASK) != 1) {
1433 netif_dbg(tp, probe, tp->netdev,
1434 "No efuse for RTL8153-AD MAC pass through\n");
1438 /* test for RTL8153-BND and RTL8153-BD */
1439 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1440 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1441 netif_dbg(tp, probe, tp->netdev,
1442 "Invalid variant for MAC pass through\n");
1447 mac_obj_name = "\\_SB.AMAC";
1448 mac_obj_type = ACPI_TYPE_BUFFER;
1452 /* returns _AUXMAC_#AABBCCDDEEFF# */
1453 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1454 obj = (union acpi_object *)buffer.pointer;
1455 if (!ACPI_SUCCESS(status))
1457 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1458 netif_warn(tp, probe, tp->netdev,
1459 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1460 obj->type, obj->string.length);
1464 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1465 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1466 netif_warn(tp, probe, tp->netdev,
1467 "Invalid header when reading pass-thru MAC addr\n");
1470 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1471 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1472 netif_warn(tp, probe, tp->netdev,
1473 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1478 memcpy(sa->sa_data, buf, 6);
1479 netif_info(tp, probe, tp->netdev,
1480 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1487 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1489 struct net_device *dev = tp->netdev;
1492 sa->sa_family = dev->type;
1494 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1496 if (tp->version == RTL_VER_01) {
1497 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1499 /* if device doesn't support MAC pass through this will
1500 * be expected to be non-zero
1502 ret = vendor_mac_passthru_addr_read(tp, sa);
1504 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1510 netif_err(tp, probe, dev, "Get ether addr fail\n");
1511 } else if (!is_valid_ether_addr(sa->sa_data)) {
1512 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1514 eth_hw_addr_random(dev);
1515 ether_addr_copy(sa->sa_data, dev->dev_addr);
1516 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1524 static int set_ethernet_addr(struct r8152 *tp)
1526 struct net_device *dev = tp->netdev;
1530 ret = determine_ethernet_addr(tp, &sa);
1534 if (tp->version == RTL_VER_01)
1535 ether_addr_copy(dev->dev_addr, sa.sa_data);
1537 ret = rtl8152_set_mac_address(dev, &sa);
1542 static void read_bulk_callback(struct urb *urb)
1544 struct net_device *netdev;
1545 int status = urb->status;
1548 unsigned long flags;
1558 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1561 if (!test_bit(WORK_ENABLE, &tp->flags))
1564 netdev = tp->netdev;
1566 /* When link down, the driver would cancel all bulks. */
1567 /* This avoid the re-submitting bulk */
1568 if (!netif_carrier_ok(netdev))
1571 usb_mark_last_busy(tp->udev);
1575 if (urb->actual_length < ETH_ZLEN)
1578 spin_lock_irqsave(&tp->rx_lock, flags);
1579 list_add_tail(&agg->list, &tp->rx_done);
1580 spin_unlock_irqrestore(&tp->rx_lock, flags);
1581 napi_schedule(&tp->napi);
1585 netif_device_detach(tp->netdev);
1588 return; /* the urb is in unlink state */
1590 if (net_ratelimit())
1591 netdev_warn(netdev, "maybe reset is needed?\n");
1594 if (net_ratelimit())
1595 netdev_warn(netdev, "Rx status %d\n", status);
1599 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1602 static void write_bulk_callback(struct urb *urb)
1604 struct net_device_stats *stats;
1605 struct net_device *netdev;
1608 unsigned long flags;
1609 int status = urb->status;
1619 netdev = tp->netdev;
1620 stats = &netdev->stats;
1622 if (net_ratelimit())
1623 netdev_warn(netdev, "Tx status %d\n", status);
1624 stats->tx_errors += agg->skb_num;
1626 stats->tx_packets += agg->skb_num;
1627 stats->tx_bytes += agg->skb_len;
1630 spin_lock_irqsave(&tp->tx_lock, flags);
1631 list_add_tail(&agg->list, &tp->tx_free);
1632 spin_unlock_irqrestore(&tp->tx_lock, flags);
1634 usb_autopm_put_interface_async(tp->intf);
1636 if (!netif_carrier_ok(netdev))
1639 if (!test_bit(WORK_ENABLE, &tp->flags))
1642 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1645 if (!skb_queue_empty(&tp->tx_queue))
1646 tasklet_schedule(&tp->tx_tl);
1649 static void intr_callback(struct urb *urb)
1653 int status = urb->status;
1660 if (!test_bit(WORK_ENABLE, &tp->flags))
1663 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1667 case 0: /* success */
1669 case -ECONNRESET: /* unlink */
1671 netif_device_detach(tp->netdev);
1675 netif_info(tp, intr, tp->netdev,
1676 "Stop submitting intr, status %d\n", status);
1679 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1681 /* -EPIPE: should clear the halt */
1683 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1687 d = urb->transfer_buffer;
1688 if (INTR_LINK & __le16_to_cpu(d[0])) {
1689 if (!netif_carrier_ok(tp->netdev)) {
1690 set_bit(RTL8152_LINK_CHG, &tp->flags);
1691 schedule_delayed_work(&tp->schedule, 0);
1694 if (netif_carrier_ok(tp->netdev)) {
1695 netif_stop_queue(tp->netdev);
1696 set_bit(RTL8152_LINK_CHG, &tp->flags);
1697 schedule_delayed_work(&tp->schedule, 0);
1702 res = usb_submit_urb(urb, GFP_ATOMIC);
1703 if (res == -ENODEV) {
1705 netif_device_detach(tp->netdev);
1707 netif_err(tp, intr, tp->netdev,
1708 "can't resubmit intr, status %d\n", res);
1712 static inline void *rx_agg_align(void *data)
1714 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1717 static inline void *tx_agg_align(void *data)
1719 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1722 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1724 list_del(&agg->info_list);
1726 usb_free_urb(agg->urb);
1727 put_page(agg->page);
1730 atomic_dec(&tp->rx_count);
1733 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1735 struct net_device *netdev = tp->netdev;
1736 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1737 unsigned int order = get_order(tp->rx_buf_sz);
1738 struct rx_agg *rx_agg;
1739 unsigned long flags;
1741 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1745 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1749 rx_agg->buffer = page_address(rx_agg->page);
1751 rx_agg->urb = usb_alloc_urb(0, mflags);
1755 rx_agg->context = tp;
1757 INIT_LIST_HEAD(&rx_agg->list);
1758 INIT_LIST_HEAD(&rx_agg->info_list);
1759 spin_lock_irqsave(&tp->rx_lock, flags);
1760 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1761 spin_unlock_irqrestore(&tp->rx_lock, flags);
1763 atomic_inc(&tp->rx_count);
1768 __free_pages(rx_agg->page, order);
1774 static void free_all_mem(struct r8152 *tp)
1776 struct rx_agg *agg, *agg_next;
1777 unsigned long flags;
1780 spin_lock_irqsave(&tp->rx_lock, flags);
1782 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1783 free_rx_agg(tp, agg);
1785 spin_unlock_irqrestore(&tp->rx_lock, flags);
1787 WARN_ON(atomic_read(&tp->rx_count));
1789 for (i = 0; i < RTL8152_MAX_TX; i++) {
1790 usb_free_urb(tp->tx_info[i].urb);
1791 tp->tx_info[i].urb = NULL;
1793 kfree(tp->tx_info[i].buffer);
1794 tp->tx_info[i].buffer = NULL;
1795 tp->tx_info[i].head = NULL;
1798 usb_free_urb(tp->intr_urb);
1799 tp->intr_urb = NULL;
1801 kfree(tp->intr_buff);
1802 tp->intr_buff = NULL;
1805 static int alloc_all_mem(struct r8152 *tp)
1807 struct net_device *netdev = tp->netdev;
1808 struct usb_interface *intf = tp->intf;
1809 struct usb_host_interface *alt = intf->cur_altsetting;
1810 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1813 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1815 spin_lock_init(&tp->rx_lock);
1816 spin_lock_init(&tp->tx_lock);
1817 INIT_LIST_HEAD(&tp->rx_info);
1818 INIT_LIST_HEAD(&tp->tx_free);
1819 INIT_LIST_HEAD(&tp->rx_done);
1820 skb_queue_head_init(&tp->tx_queue);
1821 skb_queue_head_init(&tp->rx_queue);
1822 atomic_set(&tp->rx_count, 0);
1824 for (i = 0; i < RTL8152_MAX_RX; i++) {
1825 if (!alloc_rx_agg(tp, GFP_KERNEL))
1829 for (i = 0; i < RTL8152_MAX_TX; i++) {
1833 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1837 if (buf != tx_agg_align(buf)) {
1839 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1845 urb = usb_alloc_urb(0, GFP_KERNEL);
1851 INIT_LIST_HEAD(&tp->tx_info[i].list);
1852 tp->tx_info[i].context = tp;
1853 tp->tx_info[i].urb = urb;
1854 tp->tx_info[i].buffer = buf;
1855 tp->tx_info[i].head = tx_agg_align(buf);
1857 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1860 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1864 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1868 tp->intr_interval = (int)ep_intr->desc.bInterval;
1869 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1870 tp->intr_buff, INTBUFSIZE, intr_callback,
1871 tp, tp->intr_interval);
1880 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1882 struct tx_agg *agg = NULL;
1883 unsigned long flags;
1885 if (list_empty(&tp->tx_free))
1888 spin_lock_irqsave(&tp->tx_lock, flags);
1889 if (!list_empty(&tp->tx_free)) {
1890 struct list_head *cursor;
1892 cursor = tp->tx_free.next;
1893 list_del_init(cursor);
1894 agg = list_entry(cursor, struct tx_agg, list);
1896 spin_unlock_irqrestore(&tp->tx_lock, flags);
1901 /* r8152_csum_workaround()
1902 * The hw limits the value of the transport offset. When the offset is out of
1903 * range, calculate the checksum by sw.
1905 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1906 struct sk_buff_head *list)
1908 if (skb_shinfo(skb)->gso_size) {
1909 netdev_features_t features = tp->netdev->features;
1910 struct sk_buff *segs, *seg, *next;
1911 struct sk_buff_head seg_list;
1913 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1914 segs = skb_gso_segment(skb, features);
1915 if (IS_ERR(segs) || !segs)
1918 __skb_queue_head_init(&seg_list);
1920 skb_list_walk_safe(segs, seg, next) {
1921 skb_mark_not_on_list(seg);
1922 __skb_queue_tail(&seg_list, seg);
1925 skb_queue_splice(&seg_list, list);
1927 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1928 if (skb_checksum_help(skb) < 0)
1931 __skb_queue_head(list, skb);
1933 struct net_device_stats *stats;
1936 stats = &tp->netdev->stats;
1937 stats->tx_dropped++;
1942 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1944 if (skb_vlan_tag_present(skb)) {
1947 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1948 desc->opts2 |= cpu_to_le32(opts2);
1952 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1954 u32 opts2 = le32_to_cpu(desc->opts2);
1956 if (opts2 & RX_VLAN_TAG)
1957 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1958 swab16(opts2 & 0xffff));
1961 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1962 struct sk_buff *skb, u32 len, u32 transport_offset)
1964 u32 mss = skb_shinfo(skb)->gso_size;
1965 u32 opts1, opts2 = 0;
1966 int ret = TX_CSUM_SUCCESS;
1968 WARN_ON_ONCE(len > TX_LEN_MAX);
1970 opts1 = len | TX_FS | TX_LS;
1973 if (transport_offset > GTTCPHO_MAX) {
1974 netif_warn(tp, tx_err, tp->netdev,
1975 "Invalid transport offset 0x%x for TSO\n",
1981 switch (vlan_get_protocol(skb)) {
1982 case htons(ETH_P_IP):
1986 case htons(ETH_P_IPV6):
1987 if (skb_cow_head(skb, 0)) {
1991 tcp_v6_gso_csum_prep(skb);
2000 opts1 |= transport_offset << GTTCPHO_SHIFT;
2001 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2002 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2005 if (transport_offset > TCPHO_MAX) {
2006 netif_warn(tp, tx_err, tp->netdev,
2007 "Invalid transport offset 0x%x\n",
2013 switch (vlan_get_protocol(skb)) {
2014 case htons(ETH_P_IP):
2016 ip_protocol = ip_hdr(skb)->protocol;
2019 case htons(ETH_P_IPV6):
2021 ip_protocol = ipv6_hdr(skb)->nexthdr;
2025 ip_protocol = IPPROTO_RAW;
2029 if (ip_protocol == IPPROTO_TCP)
2031 else if (ip_protocol == IPPROTO_UDP)
2036 opts2 |= transport_offset << TCPHO_SHIFT;
2039 desc->opts2 = cpu_to_le32(opts2);
2040 desc->opts1 = cpu_to_le32(opts1);
2046 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2048 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2052 __skb_queue_head_init(&skb_head);
2053 spin_lock(&tx_queue->lock);
2054 skb_queue_splice_init(tx_queue, &skb_head);
2055 spin_unlock(&tx_queue->lock);
2057 tx_data = agg->head;
2060 remain = agg_buf_sz;
2062 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2063 struct tx_desc *tx_desc;
2064 struct sk_buff *skb;
2068 skb = __skb_dequeue(&skb_head);
2072 len = skb->len + sizeof(*tx_desc);
2075 __skb_queue_head(&skb_head, skb);
2079 tx_data = tx_agg_align(tx_data);
2080 tx_desc = (struct tx_desc *)tx_data;
2082 offset = (u32)skb_transport_offset(skb);
2084 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2085 r8152_csum_workaround(tp, skb, &skb_head);
2089 rtl_tx_vlan_tag(tx_desc, skb);
2091 tx_data += sizeof(*tx_desc);
2094 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2095 struct net_device_stats *stats = &tp->netdev->stats;
2097 stats->tx_dropped++;
2098 dev_kfree_skb_any(skb);
2099 tx_data -= sizeof(*tx_desc);
2104 agg->skb_len += len;
2105 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2107 dev_kfree_skb_any(skb);
2109 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2111 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2115 if (!skb_queue_empty(&skb_head)) {
2116 spin_lock(&tx_queue->lock);
2117 skb_queue_splice(&skb_head, tx_queue);
2118 spin_unlock(&tx_queue->lock);
2121 netif_tx_lock(tp->netdev);
2123 if (netif_queue_stopped(tp->netdev) &&
2124 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2125 netif_wake_queue(tp->netdev);
2127 netif_tx_unlock(tp->netdev);
2129 ret = usb_autopm_get_interface_async(tp->intf);
2133 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2134 agg->head, (int)(tx_data - (u8 *)agg->head),
2135 (usb_complete_t)write_bulk_callback, agg);
2137 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2139 usb_autopm_put_interface_async(tp->intf);
2145 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2147 u8 checksum = CHECKSUM_NONE;
2150 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2153 opts2 = le32_to_cpu(rx_desc->opts2);
2154 opts3 = le32_to_cpu(rx_desc->opts3);
2156 if (opts2 & RD_IPV4_CS) {
2158 checksum = CHECKSUM_NONE;
2159 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2160 checksum = CHECKSUM_UNNECESSARY;
2161 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2162 checksum = CHECKSUM_UNNECESSARY;
2163 } else if (opts2 & RD_IPV6_CS) {
2164 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2165 checksum = CHECKSUM_UNNECESSARY;
2166 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2167 checksum = CHECKSUM_UNNECESSARY;
2174 static inline bool rx_count_exceed(struct r8152 *tp)
2176 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2179 static inline int agg_offset(struct rx_agg *agg, void *addr)
2181 return (int)(addr - agg->buffer);
2184 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2186 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2187 unsigned long flags;
2189 spin_lock_irqsave(&tp->rx_lock, flags);
2191 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2192 if (page_count(agg->page) == 1) {
2194 list_del_init(&agg->list);
2198 if (rx_count_exceed(tp)) {
2199 list_del_init(&agg->list);
2200 free_rx_agg(tp, agg);
2206 spin_unlock_irqrestore(&tp->rx_lock, flags);
2208 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2209 agg_free = alloc_rx_agg(tp, mflags);
2214 static int rx_bottom(struct r8152 *tp, int budget)
2216 unsigned long flags;
2217 struct list_head *cursor, *next, rx_queue;
2218 int ret = 0, work_done = 0;
2219 struct napi_struct *napi = &tp->napi;
2221 if (!skb_queue_empty(&tp->rx_queue)) {
2222 while (work_done < budget) {
2223 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2224 struct net_device *netdev = tp->netdev;
2225 struct net_device_stats *stats = &netdev->stats;
2226 unsigned int pkt_len;
2232 napi_gro_receive(napi, skb);
2234 stats->rx_packets++;
2235 stats->rx_bytes += pkt_len;
2239 if (list_empty(&tp->rx_done))
2242 INIT_LIST_HEAD(&rx_queue);
2243 spin_lock_irqsave(&tp->rx_lock, flags);
2244 list_splice_init(&tp->rx_done, &rx_queue);
2245 spin_unlock_irqrestore(&tp->rx_lock, flags);
2247 list_for_each_safe(cursor, next, &rx_queue) {
2248 struct rx_desc *rx_desc;
2249 struct rx_agg *agg, *agg_free;
2254 list_del_init(cursor);
2256 agg = list_entry(cursor, struct rx_agg, list);
2258 if (urb->actual_length < ETH_ZLEN)
2261 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2263 rx_desc = agg->buffer;
2264 rx_data = agg->buffer;
2265 len_used += sizeof(struct rx_desc);
2267 while (urb->actual_length > len_used) {
2268 struct net_device *netdev = tp->netdev;
2269 struct net_device_stats *stats = &netdev->stats;
2270 unsigned int pkt_len, rx_frag_head_sz;
2271 struct sk_buff *skb;
2273 /* limite the skb numbers for rx_queue */
2274 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2277 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2278 if (pkt_len < ETH_ZLEN)
2281 len_used += pkt_len;
2282 if (urb->actual_length < len_used)
2285 pkt_len -= ETH_FCS_LEN;
2286 rx_data += sizeof(struct rx_desc);
2288 if (!agg_free || tp->rx_copybreak > pkt_len)
2289 rx_frag_head_sz = pkt_len;
2291 rx_frag_head_sz = tp->rx_copybreak;
2293 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2295 stats->rx_dropped++;
2299 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2300 memcpy(skb->data, rx_data, rx_frag_head_sz);
2301 skb_put(skb, rx_frag_head_sz);
2302 pkt_len -= rx_frag_head_sz;
2303 rx_data += rx_frag_head_sz;
2305 skb_add_rx_frag(skb, 0, agg->page,
2306 agg_offset(agg, rx_data),
2308 SKB_DATA_ALIGN(pkt_len));
2309 get_page(agg->page);
2312 skb->protocol = eth_type_trans(skb, netdev);
2313 rtl_rx_vlan_tag(rx_desc, skb);
2314 if (work_done < budget) {
2316 stats->rx_packets++;
2317 stats->rx_bytes += skb->len;
2318 napi_gro_receive(napi, skb);
2320 __skb_queue_tail(&tp->rx_queue, skb);
2324 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2325 rx_desc = (struct rx_desc *)rx_data;
2326 len_used = agg_offset(agg, rx_data);
2327 len_used += sizeof(struct rx_desc);
2330 WARN_ON(!agg_free && page_count(agg->page) > 1);
2333 spin_lock_irqsave(&tp->rx_lock, flags);
2334 if (page_count(agg->page) == 1) {
2335 list_add(&agg_free->list, &tp->rx_used);
2337 list_add_tail(&agg->list, &tp->rx_used);
2341 spin_unlock_irqrestore(&tp->rx_lock, flags);
2346 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2348 urb->actual_length = 0;
2349 list_add_tail(&agg->list, next);
2353 if (!list_empty(&rx_queue)) {
2354 spin_lock_irqsave(&tp->rx_lock, flags);
2355 list_splice_tail(&rx_queue, &tp->rx_done);
2356 spin_unlock_irqrestore(&tp->rx_lock, flags);
2363 static void tx_bottom(struct r8152 *tp)
2368 struct net_device *netdev = tp->netdev;
2371 if (skb_queue_empty(&tp->tx_queue))
2374 agg = r8152_get_tx_agg(tp);
2378 res = r8152_tx_agg_fill(tp, agg);
2382 if (res == -ENODEV) {
2384 netif_device_detach(netdev);
2386 struct net_device_stats *stats = &netdev->stats;
2387 unsigned long flags;
2389 netif_warn(tp, tx_err, netdev,
2390 "failed tx_urb %d\n", res);
2391 stats->tx_dropped += agg->skb_num;
2393 spin_lock_irqsave(&tp->tx_lock, flags);
2394 list_add_tail(&agg->list, &tp->tx_free);
2395 spin_unlock_irqrestore(&tp->tx_lock, flags);
2400 static void bottom_half(struct tasklet_struct *t)
2402 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2404 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2407 if (!test_bit(WORK_ENABLE, &tp->flags))
2410 /* When link down, the driver would cancel all bulks. */
2411 /* This avoid the re-submitting bulk */
2412 if (!netif_carrier_ok(tp->netdev))
2415 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2420 static int r8152_poll(struct napi_struct *napi, int budget)
2422 struct r8152 *tp = container_of(napi, struct r8152, napi);
2425 work_done = rx_bottom(tp, budget);
2427 if (work_done < budget) {
2428 if (!napi_complete_done(napi, work_done))
2430 if (!list_empty(&tp->rx_done))
2431 napi_schedule(napi);
2439 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2443 /* The rx would be stopped, so skip submitting */
2444 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2445 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2448 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2449 agg->buffer, tp->rx_buf_sz,
2450 (usb_complete_t)read_bulk_callback, agg);
2452 ret = usb_submit_urb(agg->urb, mem_flags);
2453 if (ret == -ENODEV) {
2455 netif_device_detach(tp->netdev);
2457 struct urb *urb = agg->urb;
2458 unsigned long flags;
2460 urb->actual_length = 0;
2461 spin_lock_irqsave(&tp->rx_lock, flags);
2462 list_add_tail(&agg->list, &tp->rx_done);
2463 spin_unlock_irqrestore(&tp->rx_lock, flags);
2465 netif_err(tp, rx_err, tp->netdev,
2466 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2468 napi_schedule(&tp->napi);
2474 static void rtl_drop_queued_tx(struct r8152 *tp)
2476 struct net_device_stats *stats = &tp->netdev->stats;
2477 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2478 struct sk_buff *skb;
2480 if (skb_queue_empty(tx_queue))
2483 __skb_queue_head_init(&skb_head);
2484 spin_lock_bh(&tx_queue->lock);
2485 skb_queue_splice_init(tx_queue, &skb_head);
2486 spin_unlock_bh(&tx_queue->lock);
2488 while ((skb = __skb_dequeue(&skb_head))) {
2490 stats->tx_dropped++;
2494 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2496 struct r8152 *tp = netdev_priv(netdev);
2498 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2500 usb_queue_reset_device(tp->intf);
2503 static void rtl8152_set_rx_mode(struct net_device *netdev)
2505 struct r8152 *tp = netdev_priv(netdev);
2507 if (netif_carrier_ok(netdev)) {
2508 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2509 schedule_delayed_work(&tp->schedule, 0);
2513 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2515 struct r8152 *tp = netdev_priv(netdev);
2516 u32 mc_filter[2]; /* Multicast hash filter */
2520 netif_stop_queue(netdev);
2521 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2522 ocp_data &= ~RCR_ACPT_ALL;
2523 ocp_data |= RCR_AB | RCR_APM;
2525 if (netdev->flags & IFF_PROMISC) {
2526 /* Unconditionally log net taps. */
2527 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2528 ocp_data |= RCR_AM | RCR_AAP;
2529 mc_filter[1] = 0xffffffff;
2530 mc_filter[0] = 0xffffffff;
2531 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2532 (netdev->flags & IFF_ALLMULTI)) {
2533 /* Too many to filter perfectly -- accept all multicasts. */
2535 mc_filter[1] = 0xffffffff;
2536 mc_filter[0] = 0xffffffff;
2538 struct netdev_hw_addr *ha;
2542 netdev_for_each_mc_addr(ha, netdev) {
2543 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2545 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2550 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2551 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2553 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2554 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2555 netif_wake_queue(netdev);
2558 static netdev_features_t
2559 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2560 netdev_features_t features)
2562 u32 mss = skb_shinfo(skb)->gso_size;
2563 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2564 int offset = skb_transport_offset(skb);
2566 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2567 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2568 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2569 features &= ~NETIF_F_GSO_MASK;
2574 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2575 struct net_device *netdev)
2577 struct r8152 *tp = netdev_priv(netdev);
2579 skb_tx_timestamp(skb);
2581 skb_queue_tail(&tp->tx_queue, skb);
2583 if (!list_empty(&tp->tx_free)) {
2584 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2585 set_bit(SCHEDULE_TASKLET, &tp->flags);
2586 schedule_delayed_work(&tp->schedule, 0);
2588 usb_mark_last_busy(tp->udev);
2589 tasklet_schedule(&tp->tx_tl);
2591 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2592 netif_stop_queue(netdev);
2595 return NETDEV_TX_OK;
2598 static void r8152b_reset_packet_filter(struct r8152 *tp)
2602 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2603 ocp_data &= ~FMC_FCR_MCU_EN;
2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2605 ocp_data |= FMC_FCR_MCU_EN;
2606 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2609 static void rtl8152_nic_reset(struct r8152 *tp)
2613 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2615 for (i = 0; i < 1000; i++) {
2616 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2618 usleep_range(100, 400);
2622 static void set_tx_qlen(struct r8152 *tp)
2624 struct net_device *netdev = tp->netdev;
2626 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2627 sizeof(struct tx_desc));
2630 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2632 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2635 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2639 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2641 ocp_data |= EEEP_CR_EEEP_TX;
2643 ocp_data &= ~EEEP_CR_EEEP_TX;
2644 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2647 static void rtl_set_eee_plus(struct r8152 *tp)
2649 if (rtl8152_get_speed(tp) & _10bps)
2650 rtl_eee_plus_en(tp, true);
2652 rtl_eee_plus_en(tp, false);
2655 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2659 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2661 ocp_data |= RXDY_GATED_EN;
2663 ocp_data &= ~RXDY_GATED_EN;
2664 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2667 static int rtl_start_rx(struct r8152 *tp)
2669 struct rx_agg *agg, *agg_next;
2670 struct list_head tmp_list;
2671 unsigned long flags;
2674 INIT_LIST_HEAD(&tmp_list);
2676 spin_lock_irqsave(&tp->rx_lock, flags);
2678 INIT_LIST_HEAD(&tp->rx_done);
2679 INIT_LIST_HEAD(&tp->rx_used);
2681 list_splice_init(&tp->rx_info, &tmp_list);
2683 spin_unlock_irqrestore(&tp->rx_lock, flags);
2685 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2686 INIT_LIST_HEAD(&agg->list);
2688 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2689 if (++i > RTL8152_MAX_RX) {
2690 spin_lock_irqsave(&tp->rx_lock, flags);
2691 list_add_tail(&agg->list, &tp->rx_used);
2692 spin_unlock_irqrestore(&tp->rx_lock, flags);
2693 } else if (unlikely(ret < 0)) {
2694 spin_lock_irqsave(&tp->rx_lock, flags);
2695 list_add_tail(&agg->list, &tp->rx_done);
2696 spin_unlock_irqrestore(&tp->rx_lock, flags);
2698 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2702 spin_lock_irqsave(&tp->rx_lock, flags);
2703 WARN_ON(!list_empty(&tp->rx_info));
2704 list_splice(&tmp_list, &tp->rx_info);
2705 spin_unlock_irqrestore(&tp->rx_lock, flags);
2710 static int rtl_stop_rx(struct r8152 *tp)
2712 struct rx_agg *agg, *agg_next;
2713 struct list_head tmp_list;
2714 unsigned long flags;
2716 INIT_LIST_HEAD(&tmp_list);
2718 /* The usb_kill_urb() couldn't be used in atomic.
2719 * Therefore, move the list of rx_info to a tmp one.
2720 * Then, list_for_each_entry_safe could be used without
2724 spin_lock_irqsave(&tp->rx_lock, flags);
2725 list_splice_init(&tp->rx_info, &tmp_list);
2726 spin_unlock_irqrestore(&tp->rx_lock, flags);
2728 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2729 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2730 * equal to 1, so the other ones could be freed safely.
2732 if (page_count(agg->page) > 1)
2733 free_rx_agg(tp, agg);
2735 usb_kill_urb(agg->urb);
2738 /* Move back the list of temp to the rx_info */
2739 spin_lock_irqsave(&tp->rx_lock, flags);
2740 WARN_ON(!list_empty(&tp->rx_info));
2741 list_splice(&tmp_list, &tp->rx_info);
2742 spin_unlock_irqrestore(&tp->rx_lock, flags);
2744 while (!skb_queue_empty(&tp->rx_queue))
2745 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2750 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2752 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2753 OWN_UPDATE | OWN_CLEAR);
2756 static int rtl_enable(struct r8152 *tp)
2760 r8152b_reset_packet_filter(tp);
2762 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2763 ocp_data |= CR_RE | CR_TE;
2764 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2766 switch (tp->version) {
2769 r8153b_rx_agg_chg_indicate(tp);
2775 rxdy_gated_en(tp, false);
2780 static int rtl8152_enable(struct r8152 *tp)
2782 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2786 rtl_set_eee_plus(tp);
2788 return rtl_enable(tp);
2791 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2793 u32 ocp_data = tp->coalesce / 8;
2795 switch (tp->version) {
2800 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2806 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2807 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2809 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2811 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2820 static void r8153_set_rx_early_size(struct r8152 *tp)
2822 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2824 switch (tp->version) {
2829 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2834 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2843 static int rtl8153_enable(struct r8152 *tp)
2845 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2849 rtl_set_eee_plus(tp);
2850 r8153_set_rx_early_timeout(tp);
2851 r8153_set_rx_early_size(tp);
2853 if (tp->version == RTL_VER_09) {
2856 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2857 ocp_data &= ~FC_PATCH_TASK;
2858 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2859 usleep_range(1000, 2000);
2860 ocp_data |= FC_PATCH_TASK;
2861 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2864 return rtl_enable(tp);
2867 static void rtl_disable(struct r8152 *tp)
2872 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2873 rtl_drop_queued_tx(tp);
2877 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2878 ocp_data &= ~RCR_ACPT_ALL;
2879 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2881 rtl_drop_queued_tx(tp);
2883 for (i = 0; i < RTL8152_MAX_TX; i++)
2884 usb_kill_urb(tp->tx_info[i].urb);
2886 rxdy_gated_en(tp, true);
2888 for (i = 0; i < 1000; i++) {
2889 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2890 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2892 usleep_range(1000, 2000);
2895 for (i = 0; i < 1000; i++) {
2896 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2898 usleep_range(1000, 2000);
2903 rtl8152_nic_reset(tp);
2906 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2910 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2912 ocp_data |= POWER_CUT;
2914 ocp_data &= ~POWER_CUT;
2915 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2917 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2918 ocp_data &= ~RESUME_INDICATE;
2919 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2922 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2926 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2928 ocp_data |= CPCR_RX_VLAN;
2930 ocp_data &= ~CPCR_RX_VLAN;
2931 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2934 static int rtl8152_set_features(struct net_device *dev,
2935 netdev_features_t features)
2937 netdev_features_t changed = features ^ dev->features;
2938 struct r8152 *tp = netdev_priv(dev);
2941 ret = usb_autopm_get_interface(tp->intf);
2945 mutex_lock(&tp->control);
2947 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2948 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2949 rtl_rx_vlan_en(tp, true);
2951 rtl_rx_vlan_en(tp, false);
2954 mutex_unlock(&tp->control);
2956 usb_autopm_put_interface(tp->intf);
2962 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2964 static u32 __rtl_get_wol(struct r8152 *tp)
2969 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2970 if (ocp_data & LINK_ON_WAKE_EN)
2971 wolopts |= WAKE_PHY;
2973 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2974 if (ocp_data & UWF_EN)
2975 wolopts |= WAKE_UCAST;
2976 if (ocp_data & BWF_EN)
2977 wolopts |= WAKE_BCAST;
2978 if (ocp_data & MWF_EN)
2979 wolopts |= WAKE_MCAST;
2981 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2982 if (ocp_data & MAGIC_EN)
2983 wolopts |= WAKE_MAGIC;
2988 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2992 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2994 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2995 ocp_data &= ~LINK_ON_WAKE_EN;
2996 if (wolopts & WAKE_PHY)
2997 ocp_data |= LINK_ON_WAKE_EN;
2998 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3000 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3001 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3002 if (wolopts & WAKE_UCAST)
3004 if (wolopts & WAKE_BCAST)
3006 if (wolopts & WAKE_MCAST)
3008 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3012 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3013 ocp_data &= ~MAGIC_EN;
3014 if (wolopts & WAKE_MAGIC)
3015 ocp_data |= MAGIC_EN;
3016 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3018 if (wolopts & WAKE_ANY)
3019 device_set_wakeup_enable(&tp->udev->dev, true);
3021 device_set_wakeup_enable(&tp->udev->dev, false);
3024 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3029 memset(u1u2, 0xff, sizeof(u1u2));
3031 memset(u1u2, 0x00, sizeof(u1u2));
3033 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3036 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3040 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3042 ocp_data |= LPM_U1U2_EN;
3044 ocp_data &= ~LPM_U1U2_EN;
3046 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3049 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3053 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3055 ocp_data |= U2P3_ENABLE;
3057 ocp_data &= ~U2P3_ENABLE;
3058 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3061 static void r8153b_ups_flags(struct r8152 *tp)
3065 if (tp->ups_info.green)
3066 ups_flags |= UPS_FLAGS_EN_GREEN;
3068 if (tp->ups_info.aldps)
3069 ups_flags |= UPS_FLAGS_EN_ALDPS;
3071 if (tp->ups_info.eee)
3072 ups_flags |= UPS_FLAGS_EN_EEE;
3074 if (tp->ups_info.flow_control)
3075 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3077 if (tp->ups_info.eee_ckdiv)
3078 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3080 if (tp->ups_info.eee_cmod_lv)
3081 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3083 if (tp->ups_info._10m_ckdiv)
3084 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3086 if (tp->ups_info.eee_plloff_100)
3087 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3089 if (tp->ups_info.eee_plloff_giga)
3090 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3092 if (tp->ups_info._250m_ckdiv)
3093 ups_flags |= UPS_FLAGS_250M_CKDIV;
3095 if (tp->ups_info.ctap_short_off)
3096 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3098 switch (tp->ups_info.speed_duplex) {
3100 ups_flags |= ups_flags_speed(1);
3103 ups_flags |= ups_flags_speed(2);
3105 case NWAY_100M_HALF:
3106 ups_flags |= ups_flags_speed(3);
3108 case NWAY_100M_FULL:
3109 ups_flags |= ups_flags_speed(4);
3111 case NWAY_1000M_FULL:
3112 ups_flags |= ups_flags_speed(5);
3114 case FORCE_10M_HALF:
3115 ups_flags |= ups_flags_speed(6);
3117 case FORCE_10M_FULL:
3118 ups_flags |= ups_flags_speed(7);
3120 case FORCE_100M_HALF:
3121 ups_flags |= ups_flags_speed(8);
3123 case FORCE_100M_FULL:
3124 ups_flags |= ups_flags_speed(9);
3130 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3133 static void rtl_green_en(struct r8152 *tp, bool enable)
3137 data = sram_read(tp, SRAM_GREEN_CFG);
3139 data |= GREEN_ETH_EN;
3141 data &= ~GREEN_ETH_EN;
3142 sram_write(tp, SRAM_GREEN_CFG, data);
3144 tp->ups_info.green = enable;
3147 static void r8153b_green_en(struct r8152 *tp, bool enable)
3150 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3151 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3152 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3154 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3155 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3156 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3159 rtl_green_en(tp, true);
3162 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3167 for (i = 0; i < 500; i++) {
3168 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3169 data &= PHY_STAT_MASK;
3171 if (data == desired)
3173 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3174 data == PHY_STAT_EXT_INIT) {
3179 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3186 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3188 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3191 r8153b_ups_flags(tp);
3193 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3194 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3196 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3198 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3200 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3201 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3203 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3204 ocp_data &= ~BIT(0);
3205 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3207 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3210 for (i = 0; i < 500; i++) {
3211 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3217 tp->rtl_ops.hw_phy_cfg(tp);
3219 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3220 tp->duplex, tp->advertising);
3225 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3229 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3231 ocp_data |= PWR_EN | PHASE2_EN;
3233 ocp_data &= ~(PWR_EN | PHASE2_EN);
3234 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3236 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3237 ocp_data &= ~PCUT_STATUS;
3238 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3241 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3245 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3247 ocp_data |= PWR_EN | PHASE2_EN;
3249 ocp_data &= ~PWR_EN;
3250 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3252 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3253 ocp_data &= ~PCUT_STATUS;
3254 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3257 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3261 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3263 ocp_data |= UPCOMING_RUNTIME_D3;
3265 ocp_data &= ~UPCOMING_RUNTIME_D3;
3266 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3268 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3269 ocp_data &= ~LINK_CHG_EVENT;
3270 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3273 ocp_data &= ~LINK_CHANGE_FLAG;
3274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3277 static bool rtl_can_wakeup(struct r8152 *tp)
3279 struct usb_device *udev = tp->udev;
3281 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3284 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3289 __rtl_set_wol(tp, WAKE_ANY);
3291 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3294 ocp_data |= LINK_OFF_WAKE_EN;
3295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3297 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3301 __rtl_set_wol(tp, tp->saved_wolopts);
3303 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3306 ocp_data &= ~LINK_OFF_WAKE_EN;
3307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3309 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3313 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3316 r8153_u1u2en(tp, false);
3317 r8153_u2p3en(tp, false);
3318 rtl_runtime_suspend_enable(tp, true);
3320 rtl_runtime_suspend_enable(tp, false);
3322 switch (tp->version) {
3329 r8153_u2p3en(tp, true);
3333 r8153_u1u2en(tp, true);
3337 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3340 r8153_queue_wake(tp, true);
3341 r8153b_u1u2en(tp, false);
3342 r8153_u2p3en(tp, false);
3343 rtl_runtime_suspend_enable(tp, true);
3344 r8153b_ups_en(tp, true);
3346 r8153b_ups_en(tp, false);
3347 r8153_queue_wake(tp, false);
3348 rtl_runtime_suspend_enable(tp, false);
3349 if (tp->udev->speed >= USB_SPEED_SUPER)
3350 r8153b_u1u2en(tp, true);
3354 static void r8153_teredo_off(struct r8152 *tp)
3358 switch (tp->version) {
3366 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3367 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3374 /* The bit 0 ~ 7 are relative with teredo settings. They are
3375 * W1C (write 1 to clear), so set all 1 to disable it.
3377 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3385 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3386 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3389 static void rtl_reset_bmu(struct r8152 *tp)
3393 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3394 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3395 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3396 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3397 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3400 /* Clear the bp to stop the firmware before loading a new one */
3401 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3403 switch (tp->version) {
3412 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3417 if (type == MCU_TYPE_USB) {
3418 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3420 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3421 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3422 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3423 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3424 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3425 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3426 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3427 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3429 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3434 ocp_write_word(tp, type, PLA_BP_0, 0);
3435 ocp_write_word(tp, type, PLA_BP_1, 0);
3436 ocp_write_word(tp, type, PLA_BP_2, 0);
3437 ocp_write_word(tp, type, PLA_BP_3, 0);
3438 ocp_write_word(tp, type, PLA_BP_4, 0);
3439 ocp_write_word(tp, type, PLA_BP_5, 0);
3440 ocp_write_word(tp, type, PLA_BP_6, 0);
3441 ocp_write_word(tp, type, PLA_BP_7, 0);
3443 /* wait 3 ms to make sure the firmware is stopped */
3444 usleep_range(3000, 6000);
3445 ocp_write_word(tp, type, PLA_BP_BA, 0);
3448 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
3453 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3455 data |= PATCH_REQUEST;
3458 data &= ~PATCH_REQUEST;
3459 check = PATCH_READY;
3461 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3463 for (i = 0; wait && i < 5000; i++) {
3466 usleep_range(1000, 2000);
3467 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
3468 if ((ocp_data & PATCH_READY) ^ check)
3472 if (request && wait &&
3473 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3474 dev_err(&tp->intf->dev, "PHY patch request fail\n");
3475 rtl_phy_patch_request(tp, false, false);
3482 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
3484 if (patch_key && key_addr) {
3485 sram_write(tp, key_addr, patch_key);
3486 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3487 } else if (key_addr) {
3490 sram_write(tp, 0x0000, 0x0000);
3492 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3493 data &= ~PATCH_LOCK;
3494 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3496 sram_write(tp, key_addr, 0x0000);
3503 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
3505 if (rtl_phy_patch_request(tp, true, wait))
3508 rtl_patch_key_set(tp, key_addr, patch_key);
3513 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
3515 rtl_patch_key_set(tp, key_addr, 0);
3517 rtl_phy_patch_request(tp, false, wait);
3519 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3524 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3527 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3530 switch (tp->version) {
3536 patch_en_addr = 0xa01a;
3544 fw_offset = __le16_to_cpu(phy->fw_offset);
3545 if (fw_offset < sizeof(*phy)) {
3546 dev_err(&tp->intf->dev, "fw_offset too small\n");
3550 length = __le32_to_cpu(phy->blk_hdr.length);
3551 if (length < fw_offset) {
3552 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3556 length -= __le16_to_cpu(phy->fw_offset);
3557 if (!length || (length & 1)) {
3558 dev_err(&tp->intf->dev, "invalid block length\n");
3562 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3563 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3567 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3568 dev_err(&tp->intf->dev, "invalid base address register\n");
3572 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3573 dev_err(&tp->intf->dev,
3574 "invalid patch mode enabled register\n");
3578 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3579 dev_err(&tp->intf->dev,
3580 "invalid register to switch the mode\n");
3584 if (__le16_to_cpu(phy->bp_start) != bp_start) {
3585 dev_err(&tp->intf->dev,
3586 "invalid start register of break point\n");
3590 if (__le16_to_cpu(phy->bp_num) > 4) {
3591 dev_err(&tp->intf->dev, "invalid break point number\n");
3600 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3602 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3607 type = __le32_to_cpu(mac->blk_hdr.type);
3608 if (type == RTL_FW_PLA) {
3609 switch (tp->version) {
3614 bp_ba_addr = PLA_BP_BA;
3616 bp_start = PLA_BP_0;
3626 bp_ba_addr = PLA_BP_BA;
3627 bp_en_addr = PLA_BP_EN;
3628 bp_start = PLA_BP_0;
3634 } else if (type == RTL_FW_USB) {
3635 switch (tp->version) {
3641 bp_ba_addr = USB_BP_BA;
3642 bp_en_addr = USB_BP_EN;
3643 bp_start = USB_BP_0;
3649 bp_ba_addr = USB_BP_BA;
3650 bp_en_addr = USB_BP2_EN;
3651 bp_start = USB_BP_0;
3664 fw_offset = __le16_to_cpu(mac->fw_offset);
3665 if (fw_offset < sizeof(*mac)) {
3666 dev_err(&tp->intf->dev, "fw_offset too small\n");
3670 length = __le32_to_cpu(mac->blk_hdr.length);
3671 if (length < fw_offset) {
3672 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3676 length -= fw_offset;
3677 if (length < 4 || (length & 3)) {
3678 dev_err(&tp->intf->dev, "invalid block length\n");
3682 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3683 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3687 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3688 dev_err(&tp->intf->dev, "invalid base address register\n");
3692 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3693 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3697 if (__le16_to_cpu(mac->bp_start) != bp_start) {
3698 dev_err(&tp->intf->dev,
3699 "invalid start register of break point\n");
3703 if (__le16_to_cpu(mac->bp_num) > max_bp) {
3704 dev_err(&tp->intf->dev, "invalid break point number\n");
3708 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3710 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3720 /* Verify the checksum for the firmware file. It is calculated from the version
3721 * field to the end of the file. Compare the result with the checksum field to
3722 * make sure the file is correct.
3724 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3725 struct fw_header *fw_hdr, size_t size)
3727 unsigned char checksum[sizeof(fw_hdr->checksum)];
3728 struct crypto_shash *alg;
3729 struct shash_desc *sdesc;
3733 alg = crypto_alloc_shash("sha256", 0, 0);
3739 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3741 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3742 crypto_shash_digestsize(alg));
3746 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3747 sdesc = kmalloc(len, GFP_KERNEL);
3754 len = size - sizeof(fw_hdr->checksum);
3755 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3760 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3761 dev_err(&tp->intf->dev, "checksum fail\n");
3766 crypto_free_shash(alg);
3771 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3773 const struct firmware *fw = rtl_fw->fw;
3774 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3775 struct fw_mac *pla = NULL, *usb = NULL;
3776 struct fw_phy_patch_key *start = NULL;
3777 struct fw_phy_nc *phy_nc = NULL;
3778 struct fw_block *stop = NULL;
3782 if (fw->size < sizeof(*fw_hdr)) {
3783 dev_err(&tp->intf->dev, "file too small\n");
3787 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3793 for (i = sizeof(*fw_hdr); i < fw->size;) {
3794 struct fw_block *block = (struct fw_block *)&fw->data[i];
3797 if ((i + sizeof(*block)) > fw->size)
3800 type = __le32_to_cpu(block->type);
3803 if (__le32_to_cpu(block->length) != sizeof(*block))
3808 dev_err(&tp->intf->dev,
3809 "multiple PLA firmware encountered");
3813 pla = (struct fw_mac *)block;
3814 if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3815 dev_err(&tp->intf->dev,
3816 "check PLA firmware failed\n");
3822 dev_err(&tp->intf->dev,
3823 "multiple USB firmware encountered");
3827 usb = (struct fw_mac *)block;
3828 if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3829 dev_err(&tp->intf->dev,
3830 "check USB firmware failed\n");
3834 case RTL_FW_PHY_START:
3835 if (start || phy_nc || stop) {
3836 dev_err(&tp->intf->dev,
3837 "check PHY_START fail\n");
3841 if (__le32_to_cpu(block->length) != sizeof(*start)) {
3842 dev_err(&tp->intf->dev,
3843 "Invalid length for PHY_START\n");
3847 start = (struct fw_phy_patch_key *)block;
3849 case RTL_FW_PHY_STOP:
3850 if (stop || !start) {
3851 dev_err(&tp->intf->dev,
3852 "Check PHY_STOP fail\n");
3856 if (__le32_to_cpu(block->length) != sizeof(*block)) {
3857 dev_err(&tp->intf->dev,
3858 "Invalid length for PHY_STOP\n");
3865 if (!start || stop) {
3866 dev_err(&tp->intf->dev,
3867 "check PHY_NC fail\n");
3872 dev_err(&tp->intf->dev,
3873 "multiple PHY NC encountered\n");
3877 phy_nc = (struct fw_phy_nc *)block;
3878 if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3879 dev_err(&tp->intf->dev,
3880 "check PHY NC firmware failed\n");
3886 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3892 i += ALIGN(__le32_to_cpu(block->length), 8);
3896 if ((phy_nc || start) && !stop) {
3897 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3906 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3908 u16 mode_reg, bp_index;
3912 mode_reg = __le16_to_cpu(phy->mode_reg);
3913 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3914 sram_write(tp, __le16_to_cpu(phy->ba_reg),
3915 __le16_to_cpu(phy->ba_data));
3917 length = __le32_to_cpu(phy->blk_hdr.length);
3918 length -= __le16_to_cpu(phy->fw_offset);
3920 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3922 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3923 for (i = 0; i < num; i++)
3924 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3926 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3927 __le16_to_cpu(phy->patch_en_value));
3929 bp_index = __le16_to_cpu(phy->bp_start);
3930 num = __le16_to_cpu(phy->bp_num);
3931 for (i = 0; i < num; i++) {
3932 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3936 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3938 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3941 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3943 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3948 switch (__le32_to_cpu(mac->blk_hdr.type)) {
3950 type = MCU_TYPE_PLA;
3953 type = MCU_TYPE_USB;
3959 rtl_clear_bp(tp, type);
3961 /* Enable backup/restore of MACDBG. This is required after clearing PLA
3962 * break points and before applying the PLA firmware.
3964 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3965 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3966 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3967 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3970 length = __le32_to_cpu(mac->blk_hdr.length);
3971 length -= __le16_to_cpu(mac->fw_offset);
3974 data += __le16_to_cpu(mac->fw_offset);
3976 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3979 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3980 __le16_to_cpu(mac->bp_ba_value));
3982 bp_index = __le16_to_cpu(mac->bp_start);
3983 bp_num = __le16_to_cpu(mac->bp_num);
3984 for (i = 0; i < bp_num; i++) {
3985 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3989 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3991 ocp_write_word(tp, type, bp_en_addr,
3992 __le16_to_cpu(mac->bp_en_value));
3994 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
3996 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
3999 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4002 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
4004 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4005 const struct firmware *fw;
4006 struct fw_header *fw_hdr;
4007 struct fw_phy_patch_key *key;
4011 if (IS_ERR_OR_NULL(rtl_fw->fw))
4015 fw_hdr = (struct fw_header *)fw->data;
4020 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4021 struct fw_block *block = (struct fw_block *)&fw->data[i];
4023 switch (__le32_to_cpu(block->type)) {
4028 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4030 case RTL_FW_PHY_START:
4031 key = (struct fw_phy_patch_key *)block;
4032 key_addr = __le16_to_cpu(key->key_reg);
4033 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
4035 case RTL_FW_PHY_STOP:
4037 rtl_post_ram_code(tp, key_addr, !power_cut);
4040 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4046 i += ALIGN(__le32_to_cpu(block->length), 8);
4050 if (rtl_fw->post_fw)
4051 rtl_fw->post_fw(tp);
4053 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4054 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4057 static void rtl8152_release_firmware(struct r8152 *tp)
4059 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4061 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4062 release_firmware(rtl_fw->fw);
4067 static int rtl8152_request_firmware(struct r8152 *tp)
4069 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4072 if (rtl_fw->fw || !rtl_fw->fw_name) {
4073 dev_info(&tp->intf->dev, "skip request firmware\n");
4078 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4082 rc = rtl8152_check_firmware(tp, rtl_fw);
4084 release_firmware(rtl_fw->fw);
4088 rtl_fw->fw = ERR_PTR(rc);
4090 dev_warn(&tp->intf->dev,
4091 "unable to load firmware patch %s (%ld)\n",
4092 rtl_fw->fw_name, rc);
4098 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4101 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4102 LINKENA | DIS_SDSAVE);
4104 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4110 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4112 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4113 ocp_reg_write(tp, OCP_EEE_DATA, reg);
4114 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4117 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4121 r8152_mmd_indirect(tp, dev, reg);
4122 data = ocp_reg_read(tp, OCP_EEE_DATA);
4123 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4128 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4130 r8152_mmd_indirect(tp, dev, reg);
4131 ocp_reg_write(tp, OCP_EEE_DATA, data);
4132 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4135 static void r8152_eee_en(struct r8152 *tp, bool enable)
4137 u16 config1, config2, config3;
4140 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4141 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4142 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4143 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4146 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4147 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4148 config1 |= sd_rise_time(1);
4149 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4150 config3 |= fast_snr(42);
4152 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4153 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4155 config1 |= sd_rise_time(7);
4156 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4157 config3 |= fast_snr(511);
4160 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4161 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4162 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4163 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4166 static void r8153_eee_en(struct r8152 *tp, bool enable)
4171 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4172 config = ocp_reg_read(tp, OCP_EEE_CFG);
4175 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4178 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4179 config &= ~EEE10_EN;
4182 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4183 ocp_reg_write(tp, OCP_EEE_CFG, config);
4185 tp->ups_info.eee = enable;
4188 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4190 switch (tp->version) {
4195 r8152_eee_en(tp, true);
4196 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4199 r8152_eee_en(tp, false);
4200 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4210 r8153_eee_en(tp, true);
4211 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4213 r8153_eee_en(tp, false);
4214 ocp_reg_write(tp, OCP_EEE_ADV, 0);
4222 static void r8152b_enable_fc(struct r8152 *tp)
4226 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4227 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4228 r8152_mdio_write(tp, MII_ADVERTISE, anar);
4230 tp->ups_info.flow_control = true;
4233 static void rtl8152_disable(struct r8152 *tp)
4235 r8152_aldps_en(tp, false);
4237 r8152_aldps_en(tp, true);
4240 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4242 rtl8152_apply_firmware(tp, false);
4243 rtl_eee_enable(tp, tp->eee_en);
4244 r8152_aldps_en(tp, true);
4245 r8152b_enable_fc(tp);
4247 set_bit(PHY_RESET, &tp->flags);
4250 static void wait_oob_link_list_ready(struct r8152 *tp)
4255 for (i = 0; i < 1000; i++) {
4256 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4257 if (ocp_data & LINK_LIST_READY)
4259 usleep_range(1000, 2000);
4263 static void r8152b_exit_oob(struct r8152 *tp)
4267 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4268 ocp_data &= ~RCR_ACPT_ALL;
4269 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4271 rxdy_gated_en(tp, true);
4272 r8153_teredo_off(tp);
4273 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4274 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4276 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4277 ocp_data &= ~NOW_IS_OOB;
4278 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4280 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4281 ocp_data &= ~MCU_BORW_EN;
4282 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4284 wait_oob_link_list_ready(tp);
4286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4287 ocp_data |= RE_INIT_LL;
4288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4290 wait_oob_link_list_ready(tp);
4292 rtl8152_nic_reset(tp);
4294 /* rx share fifo credit full threshold */
4295 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4297 if (tp->udev->speed == USB_SPEED_FULL ||
4298 tp->udev->speed == USB_SPEED_LOW) {
4299 /* rx share fifo credit near full threshold */
4300 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4302 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4305 /* rx share fifo credit near full threshold */
4306 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4308 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4312 /* TX share fifo free credit full threshold */
4313 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4315 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4316 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4317 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4318 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4320 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4322 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4324 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4325 ocp_data |= TCR0_AUTO_FIFO;
4326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4329 static void r8152b_enter_oob(struct r8152 *tp)
4333 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4334 ocp_data &= ~NOW_IS_OOB;
4335 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4337 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4338 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4339 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4343 wait_oob_link_list_ready(tp);
4345 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4346 ocp_data |= RE_INIT_LL;
4347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4349 wait_oob_link_list_ready(tp);
4351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4353 rtl_rx_vlan_en(tp, true);
4355 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4356 ocp_data |= ALDPS_PROXY_MODE;
4357 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4359 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4360 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4361 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4363 rxdy_gated_en(tp, false);
4365 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4366 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4367 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4370 static int r8153_pre_firmware_1(struct r8152 *tp)
4374 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4375 for (i = 0; i < 104; i++) {
4376 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4378 if (!(ocp_data & WTD1_EN))
4380 usleep_range(1000, 2000);
4386 static int r8153_post_firmware_1(struct r8152 *tp)
4388 /* set USB_BP_4 to support USB_SPEED_SUPER only */
4389 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4390 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4392 /* reset UPHY timer to 36 ms */
4393 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4398 static int r8153_pre_firmware_2(struct r8152 *tp)
4402 r8153_pre_firmware_1(tp);
4404 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4405 ocp_data &= ~FW_FIX_SUSPEND;
4406 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4411 static int r8153_post_firmware_2(struct r8152 *tp)
4415 /* enable bp0 if support USB_SPEED_SUPER only */
4416 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4417 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4419 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4422 /* reset UPHY timer to 36 ms */
4423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4425 /* enable U3P3 check, set the counter to 4 */
4426 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4428 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4429 ocp_data |= FW_FIX_SUSPEND;
4430 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4432 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4433 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4434 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4439 static int r8153_post_firmware_3(struct r8152 *tp)
4443 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4444 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4445 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4447 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4448 ocp_data |= FW_IP_RESET_EN;
4449 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4454 static int r8153b_pre_firmware_1(struct r8152 *tp)
4456 /* enable fc timer and set timer to 1 second. */
4457 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4458 CTRL_TIMER_EN | (1000 / 8));
4463 static int r8153b_post_firmware_1(struct r8152 *tp)
4467 /* enable bp0 for RTL8153-BND */
4468 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4469 if (ocp_data & BND_MASK) {
4470 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4475 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4476 ocp_data |= FLOW_CTRL_PATCH_OPT;
4477 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4480 ocp_data |= FC_PATCH_TASK;
4481 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4483 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4484 ocp_data |= FW_IP_RESET_EN;
4485 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4490 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4494 data = ocp_reg_read(tp, OCP_POWER_CFG);
4497 ocp_reg_write(tp, OCP_POWER_CFG, data);
4502 ocp_reg_write(tp, OCP_POWER_CFG, data);
4503 for (i = 0; i < 20; i++) {
4504 usleep_range(1000, 2000);
4505 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4510 tp->ups_info.aldps = enable;
4513 static void r8153_hw_phy_cfg(struct r8152 *tp)
4518 /* disable ALDPS before updating the PHY parameters */
4519 r8153_aldps_en(tp, false);
4521 /* disable EEE before updating the PHY parameters */
4522 rtl_eee_enable(tp, false);
4524 rtl8152_apply_firmware(tp, false);
4526 if (tp->version == RTL_VER_03) {
4527 data = ocp_reg_read(tp, OCP_EEE_CFG);
4528 data &= ~CTAP_SHORT_EN;
4529 ocp_reg_write(tp, OCP_EEE_CFG, data);
4532 data = ocp_reg_read(tp, OCP_POWER_CFG);
4533 data |= EEE_CLKDIV_EN;
4534 ocp_reg_write(tp, OCP_POWER_CFG, data);
4536 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4537 data |= EN_10M_BGOFF;
4538 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4539 data = ocp_reg_read(tp, OCP_POWER_CFG);
4540 data |= EN_10M_PLLOFF;
4541 ocp_reg_write(tp, OCP_POWER_CFG, data);
4542 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4544 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4545 ocp_data |= PFM_PWM_SWITCH;
4546 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4548 /* Enable LPF corner auto tune */
4549 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4551 /* Adjust 10M Amplitude */
4552 sram_write(tp, SRAM_10M_AMP1, 0x00af);
4553 sram_write(tp, SRAM_10M_AMP2, 0x0208);
4556 rtl_eee_enable(tp, true);
4558 r8153_aldps_en(tp, true);
4559 r8152b_enable_fc(tp);
4561 switch (tp->version) {
4568 r8153_u2p3en(tp, true);
4572 set_bit(PHY_RESET, &tp->flags);
4575 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4581 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
4582 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4587 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4592 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
4593 if (ocp_data & PCUT_STATUS) {
4594 ocp_data &= ~PCUT_STATUS;
4595 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
4598 /* disable ALDPS before updating the PHY parameters */
4599 r8153_aldps_en(tp, false);
4601 /* disable EEE before updating the PHY parameters */
4602 rtl_eee_enable(tp, false);
4604 /* U1/U2/L1 idle timer. 500 us */
4605 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4607 data = r8153_phy_status(tp, 0);
4610 case PHY_STAT_PWRDN:
4611 case PHY_STAT_EXT_INIT:
4612 rtl8152_apply_firmware(tp, true);
4614 data = r8152_mdio_read(tp, MII_BMCR);
4615 data &= ~BMCR_PDOWN;
4616 r8152_mdio_write(tp, MII_BMCR, data);
4618 case PHY_STAT_LAN_ON:
4620 rtl8152_apply_firmware(tp, false);
4624 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4626 data = sram_read(tp, SRAM_GREEN_CFG);
4628 sram_write(tp, SRAM_GREEN_CFG, data);
4629 data = ocp_reg_read(tp, OCP_NCTL_CFG);
4630 data |= PGA_RETURN_EN;
4631 ocp_reg_write(tp, OCP_NCTL_CFG, data);
4633 /* ADC Bias Calibration:
4634 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4635 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4638 ocp_data = r8152_efuse_read(tp, 0x7d);
4639 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4641 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4643 /* ups mode tx-link-pulse timing adjustment:
4644 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4645 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4647 ocp_data = ocp_reg_read(tp, 0xc426);
4650 u32 swr_cnt_1ms_ini;
4652 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4653 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4654 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4655 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4658 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4659 ocp_data |= PFM_PWM_SWITCH;
4660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4663 if (!rtl_phy_patch_request(tp, true, true)) {
4664 data = ocp_reg_read(tp, OCP_POWER_CFG);
4665 data |= EEE_CLKDIV_EN;
4666 ocp_reg_write(tp, OCP_POWER_CFG, data);
4667 tp->ups_info.eee_ckdiv = true;
4669 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4670 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4671 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4672 tp->ups_info.eee_cmod_lv = true;
4673 tp->ups_info._10m_ckdiv = true;
4674 tp->ups_info.eee_plloff_giga = true;
4676 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4677 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4678 tp->ups_info._250m_ckdiv = true;
4680 rtl_phy_patch_request(tp, false, true);
4684 rtl_eee_enable(tp, true);
4686 r8153_aldps_en(tp, true);
4687 r8152b_enable_fc(tp);
4689 set_bit(PHY_RESET, &tp->flags);
4692 static void r8153_first_init(struct r8152 *tp)
4696 rxdy_gated_en(tp, true);
4697 r8153_teredo_off(tp);
4699 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4700 ocp_data &= ~RCR_ACPT_ALL;
4701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4703 rtl8152_nic_reset(tp);
4706 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4707 ocp_data &= ~NOW_IS_OOB;
4708 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4710 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4711 ocp_data &= ~MCU_BORW_EN;
4712 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4714 wait_oob_link_list_ready(tp);
4716 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4717 ocp_data |= RE_INIT_LL;
4718 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4720 wait_oob_link_list_ready(tp);
4722 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4724 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4725 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4726 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4728 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4729 ocp_data |= TCR0_AUTO_FIFO;
4730 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4732 rtl8152_nic_reset(tp);
4734 /* rx share fifo credit full threshold */
4735 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4736 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4737 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4738 /* TX share fifo free credit full threshold */
4739 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4742 static void r8153_enter_oob(struct r8152 *tp)
4746 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4747 ocp_data &= ~NOW_IS_OOB;
4748 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4753 wait_oob_link_list_ready(tp);
4755 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4756 ocp_data |= RE_INIT_LL;
4757 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4759 wait_oob_link_list_ready(tp);
4761 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4762 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4764 switch (tp->version) {
4769 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4770 ocp_data &= ~TEREDO_WAKE_MASK;
4771 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4776 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4777 * type. Set it to zero. bits[7:0] are the W1C bits about
4778 * the events. Set them to all 1 to clear them.
4780 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4787 rtl_rx_vlan_en(tp, true);
4789 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4790 ocp_data |= ALDPS_PROXY_MODE;
4791 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4793 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4794 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4795 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4797 rxdy_gated_en(tp, false);
4799 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4800 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4801 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4804 static void rtl8153_disable(struct r8152 *tp)
4806 r8153_aldps_en(tp, false);
4809 r8153_aldps_en(tp, true);
4812 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4818 if (autoneg == AUTONEG_DISABLE) {
4819 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4824 bmcr = BMCR_SPEED10;
4825 if (duplex == DUPLEX_FULL) {
4826 bmcr |= BMCR_FULLDPLX;
4827 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4829 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4833 bmcr = BMCR_SPEED100;
4834 if (duplex == DUPLEX_FULL) {
4835 bmcr |= BMCR_FULLDPLX;
4836 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4838 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4842 if (tp->mii.supports_gmii) {
4843 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4844 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4853 if (duplex == DUPLEX_FULL)
4854 tp->mii.full_duplex = 1;
4856 tp->mii.full_duplex = 0;
4858 tp->mii.force_media = 1;
4863 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4864 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4866 if (tp->mii.supports_gmii)
4867 support |= RTL_ADVERTISED_1000_FULL;
4869 if (!(advertising & support))
4872 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4873 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4874 ADVERTISE_100HALF | ADVERTISE_100FULL);
4875 if (advertising & RTL_ADVERTISED_10_HALF) {
4876 tmp1 |= ADVERTISE_10HALF;
4877 tp->ups_info.speed_duplex = NWAY_10M_HALF;
4879 if (advertising & RTL_ADVERTISED_10_FULL) {
4880 tmp1 |= ADVERTISE_10FULL;
4881 tp->ups_info.speed_duplex = NWAY_10M_FULL;
4884 if (advertising & RTL_ADVERTISED_100_HALF) {
4885 tmp1 |= ADVERTISE_100HALF;
4886 tp->ups_info.speed_duplex = NWAY_100M_HALF;
4888 if (advertising & RTL_ADVERTISED_100_FULL) {
4889 tmp1 |= ADVERTISE_100FULL;
4890 tp->ups_info.speed_duplex = NWAY_100M_FULL;
4894 r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4895 tp->mii.advertising = tmp1;
4898 if (tp->mii.supports_gmii) {
4901 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4902 tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4903 ADVERTISE_1000HALF);
4905 if (advertising & RTL_ADVERTISED_1000_FULL) {
4906 tmp1 |= ADVERTISE_1000FULL;
4907 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4911 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4914 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4916 tp->mii.force_media = 0;
4919 if (test_and_clear_bit(PHY_RESET, &tp->flags))
4922 r8152_mdio_write(tp, MII_BMCR, bmcr);
4924 if (bmcr & BMCR_RESET) {
4927 for (i = 0; i < 50; i++) {
4929 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4938 static void rtl8152_up(struct r8152 *tp)
4940 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4943 r8152_aldps_en(tp, false);
4944 r8152b_exit_oob(tp);
4945 r8152_aldps_en(tp, true);
4948 static void rtl8152_down(struct r8152 *tp)
4950 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4951 rtl_drop_queued_tx(tp);
4955 r8152_power_cut_en(tp, false);
4956 r8152_aldps_en(tp, false);
4957 r8152b_enter_oob(tp);
4958 r8152_aldps_en(tp, true);
4961 static void rtl8153_up(struct r8152 *tp)
4965 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4968 r8153_u1u2en(tp, false);
4969 r8153_u2p3en(tp, false);
4970 r8153_aldps_en(tp, false);
4971 r8153_first_init(tp);
4973 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4974 ocp_data |= LANWAKE_CLR_EN;
4975 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4977 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4978 ocp_data &= ~LANWAKE_PIN;
4979 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4981 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4982 ocp_data &= ~DELAY_PHY_PWR_CHG;
4983 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4985 r8153_aldps_en(tp, true);
4987 switch (tp->version) {
4994 r8153_u2p3en(tp, true);
4998 r8153_u1u2en(tp, true);
5001 static void rtl8153_down(struct r8152 *tp)
5005 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5006 rtl_drop_queued_tx(tp);
5010 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5011 ocp_data &= ~LANWAKE_CLR_EN;
5012 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5014 r8153_u1u2en(tp, false);
5015 r8153_u2p3en(tp, false);
5016 r8153_power_cut_en(tp, false);
5017 r8153_aldps_en(tp, false);
5018 r8153_enter_oob(tp);
5019 r8153_aldps_en(tp, true);
5022 static void rtl8153b_up(struct r8152 *tp)
5026 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5029 r8153b_u1u2en(tp, false);
5030 r8153_u2p3en(tp, false);
5031 r8153_aldps_en(tp, false);
5033 r8153_first_init(tp);
5034 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5036 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5037 ocp_data &= ~PLA_MCU_SPDWN_EN;
5038 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5040 r8153_aldps_en(tp, true);
5042 if (tp->udev->speed >= USB_SPEED_SUPER)
5043 r8153b_u1u2en(tp, true);
5046 static void rtl8153b_down(struct r8152 *tp)
5050 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5051 rtl_drop_queued_tx(tp);
5055 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5056 ocp_data |= PLA_MCU_SPDWN_EN;
5057 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5059 r8153b_u1u2en(tp, false);
5060 r8153_u2p3en(tp, false);
5061 r8153b_power_cut_en(tp, false);
5062 r8153_aldps_en(tp, false);
5063 r8153_enter_oob(tp);
5064 r8153_aldps_en(tp, true);
5067 static bool rtl8152_in_nway(struct r8152 *tp)
5071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5072 tp->ocp_base = 0x2000;
5073 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
5074 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5076 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5077 if (nway_state & 0xc000)
5083 static bool rtl8153_in_nway(struct r8152 *tp)
5085 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5087 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5093 static void set_carrier(struct r8152 *tp)
5095 struct net_device *netdev = tp->netdev;
5096 struct napi_struct *napi = &tp->napi;
5099 speed = rtl8152_get_speed(tp);
5101 if (speed & LINK_STATUS) {
5102 if (!netif_carrier_ok(netdev)) {
5103 tp->rtl_ops.enable(tp);
5104 netif_stop_queue(netdev);
5106 netif_carrier_on(netdev);
5108 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5109 _rtl8152_set_rx_mode(netdev);
5110 napi_enable(&tp->napi);
5111 netif_wake_queue(netdev);
5112 netif_info(tp, link, netdev, "carrier on\n");
5113 } else if (netif_queue_stopped(netdev) &&
5114 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5115 netif_wake_queue(netdev);
5118 if (netif_carrier_ok(netdev)) {
5119 netif_carrier_off(netdev);
5120 tasklet_disable(&tp->tx_tl);
5122 tp->rtl_ops.disable(tp);
5124 tasklet_enable(&tp->tx_tl);
5125 netif_info(tp, link, netdev, "carrier off\n");
5130 static void rtl_work_func_t(struct work_struct *work)
5132 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5134 /* If the device is unplugged or !netif_running(), the workqueue
5135 * doesn't need to wake the device, and could return directly.
5137 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5140 if (usb_autopm_get_interface(tp->intf) < 0)
5143 if (!test_bit(WORK_ENABLE, &tp->flags))
5146 if (!mutex_trylock(&tp->control)) {
5147 schedule_delayed_work(&tp->schedule, 0);
5151 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5154 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5155 _rtl8152_set_rx_mode(tp->netdev);
5157 /* don't schedule tasket before linking */
5158 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5159 netif_carrier_ok(tp->netdev))
5160 tasklet_schedule(&tp->tx_tl);
5162 mutex_unlock(&tp->control);
5165 usb_autopm_put_interface(tp->intf);
5168 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5170 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5172 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5175 if (usb_autopm_get_interface(tp->intf) < 0)
5178 mutex_lock(&tp->control);
5180 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5181 tp->rtl_fw.retry = false;
5182 tp->rtl_fw.fw = NULL;
5184 /* Delay execution in case request_firmware() is not ready yet.
5186 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5190 tp->rtl_ops.hw_phy_cfg(tp);
5192 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5196 mutex_unlock(&tp->control);
5198 usb_autopm_put_interface(tp->intf);
5201 #ifdef CONFIG_PM_SLEEP
5202 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5205 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5208 case PM_HIBERNATION_PREPARE:
5209 case PM_SUSPEND_PREPARE:
5210 usb_autopm_get_interface(tp->intf);
5213 case PM_POST_HIBERNATION:
5214 case PM_POST_SUSPEND:
5215 usb_autopm_put_interface(tp->intf);
5218 case PM_POST_RESTORE:
5219 case PM_RESTORE_PREPARE:
5228 static int rtl8152_open(struct net_device *netdev)
5230 struct r8152 *tp = netdev_priv(netdev);
5233 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5234 cancel_delayed_work_sync(&tp->hw_phy_work);
5235 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5238 res = alloc_all_mem(tp);
5242 res = usb_autopm_get_interface(tp->intf);
5246 mutex_lock(&tp->control);
5250 netif_carrier_off(netdev);
5251 netif_start_queue(netdev);
5252 set_bit(WORK_ENABLE, &tp->flags);
5254 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5257 netif_device_detach(tp->netdev);
5258 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5262 napi_enable(&tp->napi);
5263 tasklet_enable(&tp->tx_tl);
5265 mutex_unlock(&tp->control);
5267 usb_autopm_put_interface(tp->intf);
5268 #ifdef CONFIG_PM_SLEEP
5269 tp->pm_notifier.notifier_call = rtl_notifier;
5270 register_pm_notifier(&tp->pm_notifier);
5275 mutex_unlock(&tp->control);
5276 usb_autopm_put_interface(tp->intf);
5283 static int rtl8152_close(struct net_device *netdev)
5285 struct r8152 *tp = netdev_priv(netdev);
5288 #ifdef CONFIG_PM_SLEEP
5289 unregister_pm_notifier(&tp->pm_notifier);
5291 tasklet_disable(&tp->tx_tl);
5292 clear_bit(WORK_ENABLE, &tp->flags);
5293 usb_kill_urb(tp->intr_urb);
5294 cancel_delayed_work_sync(&tp->schedule);
5295 napi_disable(&tp->napi);
5296 netif_stop_queue(netdev);
5298 res = usb_autopm_get_interface(tp->intf);
5299 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5300 rtl_drop_queued_tx(tp);
5303 mutex_lock(&tp->control);
5305 tp->rtl_ops.down(tp);
5307 mutex_unlock(&tp->control);
5309 usb_autopm_put_interface(tp->intf);
5317 static void rtl_tally_reset(struct r8152 *tp)
5321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5322 ocp_data |= TALLY_RESET;
5323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5326 static void r8152b_init(struct r8152 *tp)
5331 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5334 data = r8152_mdio_read(tp, MII_BMCR);
5335 if (data & BMCR_PDOWN) {
5336 data &= ~BMCR_PDOWN;
5337 r8152_mdio_write(tp, MII_BMCR, data);
5340 r8152_aldps_en(tp, false);
5342 if (tp->version == RTL_VER_01) {
5343 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5344 ocp_data &= ~LED_MODE_MASK;
5345 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5348 r8152_power_cut_en(tp, false);
5350 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5351 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5352 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5353 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5354 ocp_data &= ~MCU_CLK_RATIO_MASK;
5355 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5356 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5357 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5358 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5359 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5361 rtl_tally_reset(tp);
5363 /* enable rx aggregation */
5364 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5365 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5366 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5369 static void r8153_init(struct r8152 *tp)
5375 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5378 r8153_u1u2en(tp, false);
5380 for (i = 0; i < 500; i++) {
5381 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5386 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5390 data = r8153_phy_status(tp, 0);
5392 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5393 tp->version == RTL_VER_05)
5394 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5396 data = r8152_mdio_read(tp, MII_BMCR);
5397 if (data & BMCR_PDOWN) {
5398 data &= ~BMCR_PDOWN;
5399 r8152_mdio_write(tp, MII_BMCR, data);
5402 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5404 r8153_u2p3en(tp, false);
5406 if (tp->version == RTL_VER_04) {
5407 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5408 ocp_data &= ~pwd_dn_scale_mask;
5409 ocp_data |= pwd_dn_scale(96);
5410 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5412 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5413 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5414 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5415 } else if (tp->version == RTL_VER_05) {
5416 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5417 ocp_data &= ~ECM_ALDPS;
5418 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5420 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5421 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5422 ocp_data &= ~DYNAMIC_BURST;
5424 ocp_data |= DYNAMIC_BURST;
5425 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5426 } else if (tp->version == RTL_VER_06) {
5427 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5428 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5429 ocp_data &= ~DYNAMIC_BURST;
5431 ocp_data |= DYNAMIC_BURST;
5432 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5434 r8153_queue_wake(tp, false);
5436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5437 if (rtl8152_get_speed(tp) & LINK_STATUS)
5438 ocp_data |= CUR_LINK_OK;
5440 ocp_data &= ~CUR_LINK_OK;
5441 ocp_data |= POLL_LINK_CHG;
5442 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5445 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5446 ocp_data |= EP4_FULL_FC;
5447 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5449 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5450 ocp_data &= ~TIMER11_EN;
5451 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5453 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5454 ocp_data &= ~LED_MODE_MASK;
5455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5457 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5458 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5459 ocp_data |= LPM_TIMER_500MS;
5461 ocp_data |= LPM_TIMER_500US;
5462 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5464 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5465 ocp_data &= ~SEN_VAL_MASK;
5466 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5467 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5469 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5471 /* MAC clock speed down */
5472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
5473 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
5474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
5475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
5477 r8153_power_cut_en(tp, false);
5478 rtl_runtime_suspend_enable(tp, false);
5479 r8153_u1u2en(tp, true);
5480 usb_enable_lpm(tp->udev);
5482 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5483 ocp_data |= LANWAKE_CLR_EN;
5484 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5487 ocp_data &= ~LANWAKE_PIN;
5488 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5490 /* rx aggregation */
5491 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5492 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5493 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5494 ocp_data |= RX_AGG_DISABLE;
5496 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5498 rtl_tally_reset(tp);
5500 switch (tp->udev->speed) {
5501 case USB_SPEED_SUPER:
5502 case USB_SPEED_SUPER_PLUS:
5503 tp->coalesce = COALESCE_SUPER;
5505 case USB_SPEED_HIGH:
5506 tp->coalesce = COALESCE_HIGH;
5509 tp->coalesce = COALESCE_SLOW;
5514 static void r8153b_init(struct r8152 *tp)
5520 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5523 r8153b_u1u2en(tp, false);
5525 for (i = 0; i < 500; i++) {
5526 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5531 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5535 data = r8153_phy_status(tp, 0);
5537 data = r8152_mdio_read(tp, MII_BMCR);
5538 if (data & BMCR_PDOWN) {
5539 data &= ~BMCR_PDOWN;
5540 r8152_mdio_write(tp, MII_BMCR, data);
5543 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5545 r8153_u2p3en(tp, false);
5547 /* MSC timer = 0xfff * 8ms = 32760 ms */
5548 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5550 r8153b_power_cut_en(tp, false);
5551 r8153b_ups_en(tp, false);
5552 r8153_queue_wake(tp, false);
5553 rtl_runtime_suspend_enable(tp, false);
5555 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5556 if (rtl8152_get_speed(tp) & LINK_STATUS)
5557 ocp_data |= CUR_LINK_OK;
5559 ocp_data &= ~CUR_LINK_OK;
5560 ocp_data |= POLL_LINK_CHG;
5561 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5563 if (tp->udev->speed >= USB_SPEED_SUPER)
5564 r8153b_u1u2en(tp, true);
5566 usb_enable_lpm(tp->udev);
5568 /* MAC clock speed down */
5569 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5570 ocp_data |= MAC_CLK_SPDWN_EN;
5571 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5573 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5574 ocp_data &= ~PLA_MCU_SPDWN_EN;
5575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5577 if (tp->version == RTL_VER_09) {
5578 /* Disable Test IO for 32QFN */
5579 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5581 ocp_data |= TEST_IO_OFF;
5582 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5586 set_bit(GREEN_ETHERNET, &tp->flags);
5588 /* rx aggregation */
5589 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5590 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5591 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5593 rtl_tally_reset(tp);
5595 tp->coalesce = 15000; /* 15 us */
5598 static int rtl8152_pre_reset(struct usb_interface *intf)
5600 struct r8152 *tp = usb_get_intfdata(intf);
5601 struct net_device *netdev;
5606 netdev = tp->netdev;
5607 if (!netif_running(netdev))
5610 netif_stop_queue(netdev);
5611 tasklet_disable(&tp->tx_tl);
5612 clear_bit(WORK_ENABLE, &tp->flags);
5613 usb_kill_urb(tp->intr_urb);
5614 cancel_delayed_work_sync(&tp->schedule);
5615 napi_disable(&tp->napi);
5616 if (netif_carrier_ok(netdev)) {
5617 mutex_lock(&tp->control);
5618 tp->rtl_ops.disable(tp);
5619 mutex_unlock(&tp->control);
5625 static int rtl8152_post_reset(struct usb_interface *intf)
5627 struct r8152 *tp = usb_get_intfdata(intf);
5628 struct net_device *netdev;
5634 /* reset the MAC adddress in case of policy change */
5635 if (determine_ethernet_addr(tp, &sa) >= 0) {
5637 dev_set_mac_address (tp->netdev, &sa, NULL);
5641 netdev = tp->netdev;
5642 if (!netif_running(netdev))
5645 set_bit(WORK_ENABLE, &tp->flags);
5646 if (netif_carrier_ok(netdev)) {
5647 mutex_lock(&tp->control);
5648 tp->rtl_ops.enable(tp);
5650 _rtl8152_set_rx_mode(netdev);
5651 mutex_unlock(&tp->control);
5654 napi_enable(&tp->napi);
5655 tasklet_enable(&tp->tx_tl);
5656 netif_wake_queue(netdev);
5657 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5659 if (!list_empty(&tp->rx_done))
5660 napi_schedule(&tp->napi);
5665 static bool delay_autosuspend(struct r8152 *tp)
5667 bool sw_linking = !!netif_carrier_ok(tp->netdev);
5668 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5670 /* This means a linking change occurs and the driver doesn't detect it,
5671 * yet. If the driver has disabled tx/rx and hw is linking on, the
5672 * device wouldn't wake up by receiving any packet.
5674 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5677 /* If the linking down is occurred by nway, the device may miss the
5678 * linking change event. And it wouldn't wake when linking on.
5680 if (!sw_linking && tp->rtl_ops.in_nway(tp))
5682 else if (!skb_queue_empty(&tp->tx_queue))
5688 static int rtl8152_runtime_resume(struct r8152 *tp)
5690 struct net_device *netdev = tp->netdev;
5692 if (netif_running(netdev) && netdev->flags & IFF_UP) {
5693 struct napi_struct *napi = &tp->napi;
5695 tp->rtl_ops.autosuspend_en(tp, false);
5697 set_bit(WORK_ENABLE, &tp->flags);
5699 if (netif_carrier_ok(netdev)) {
5700 if (rtl8152_get_speed(tp) & LINK_STATUS) {
5703 netif_carrier_off(netdev);
5704 tp->rtl_ops.disable(tp);
5705 netif_info(tp, link, netdev, "linking down\n");
5710 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5711 smp_mb__after_atomic();
5713 if (!list_empty(&tp->rx_done))
5714 napi_schedule(&tp->napi);
5716 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5718 if (netdev->flags & IFF_UP)
5719 tp->rtl_ops.autosuspend_en(tp, false);
5721 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5727 static int rtl8152_system_resume(struct r8152 *tp)
5729 struct net_device *netdev = tp->netdev;
5731 netif_device_attach(netdev);
5733 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5735 netif_carrier_off(netdev);
5736 set_bit(WORK_ENABLE, &tp->flags);
5737 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5743 static int rtl8152_runtime_suspend(struct r8152 *tp)
5745 struct net_device *netdev = tp->netdev;
5748 if (!tp->rtl_ops.autosuspend_en)
5751 set_bit(SELECTIVE_SUSPEND, &tp->flags);
5752 smp_mb__after_atomic();
5754 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5757 if (netif_carrier_ok(netdev)) {
5760 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5761 ocp_data = rcr & ~RCR_ACPT_ALL;
5762 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5763 rxdy_gated_en(tp, true);
5764 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5766 if (!(ocp_data & RXFIFO_EMPTY)) {
5767 rxdy_gated_en(tp, false);
5768 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5769 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5770 smp_mb__after_atomic();
5776 clear_bit(WORK_ENABLE, &tp->flags);
5777 usb_kill_urb(tp->intr_urb);
5779 tp->rtl_ops.autosuspend_en(tp, true);
5781 if (netif_carrier_ok(netdev)) {
5782 struct napi_struct *napi = &tp->napi;
5786 rxdy_gated_en(tp, false);
5787 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5791 if (delay_autosuspend(tp)) {
5792 rtl8152_runtime_resume(tp);
5801 static int rtl8152_system_suspend(struct r8152 *tp)
5803 struct net_device *netdev = tp->netdev;
5805 netif_device_detach(netdev);
5807 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5808 struct napi_struct *napi = &tp->napi;
5810 clear_bit(WORK_ENABLE, &tp->flags);
5811 usb_kill_urb(tp->intr_urb);
5812 tasklet_disable(&tp->tx_tl);
5814 cancel_delayed_work_sync(&tp->schedule);
5815 tp->rtl_ops.down(tp);
5817 tasklet_enable(&tp->tx_tl);
5823 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5825 struct r8152 *tp = usb_get_intfdata(intf);
5828 mutex_lock(&tp->control);
5830 if (PMSG_IS_AUTO(message))
5831 ret = rtl8152_runtime_suspend(tp);
5833 ret = rtl8152_system_suspend(tp);
5835 mutex_unlock(&tp->control);
5840 static int rtl8152_resume(struct usb_interface *intf)
5842 struct r8152 *tp = usb_get_intfdata(intf);
5845 mutex_lock(&tp->control);
5847 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5848 ret = rtl8152_runtime_resume(tp);
5850 ret = rtl8152_system_resume(tp);
5852 mutex_unlock(&tp->control);
5857 static int rtl8152_reset_resume(struct usb_interface *intf)
5859 struct r8152 *tp = usb_get_intfdata(intf);
5861 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5862 tp->rtl_ops.init(tp);
5863 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5864 set_ethernet_addr(tp);
5865 return rtl8152_resume(intf);
5868 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5870 struct r8152 *tp = netdev_priv(dev);
5872 if (usb_autopm_get_interface(tp->intf) < 0)
5875 if (!rtl_can_wakeup(tp)) {
5879 mutex_lock(&tp->control);
5880 wol->supported = WAKE_ANY;
5881 wol->wolopts = __rtl_get_wol(tp);
5882 mutex_unlock(&tp->control);
5885 usb_autopm_put_interface(tp->intf);
5888 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5890 struct r8152 *tp = netdev_priv(dev);
5893 if (!rtl_can_wakeup(tp))
5896 if (wol->wolopts & ~WAKE_ANY)
5899 ret = usb_autopm_get_interface(tp->intf);
5903 mutex_lock(&tp->control);
5905 __rtl_set_wol(tp, wol->wolopts);
5906 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5908 mutex_unlock(&tp->control);
5910 usb_autopm_put_interface(tp->intf);
5916 static u32 rtl8152_get_msglevel(struct net_device *dev)
5918 struct r8152 *tp = netdev_priv(dev);
5920 return tp->msg_enable;
5923 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5925 struct r8152 *tp = netdev_priv(dev);
5927 tp->msg_enable = value;
5930 static void rtl8152_get_drvinfo(struct net_device *netdev,
5931 struct ethtool_drvinfo *info)
5933 struct r8152 *tp = netdev_priv(netdev);
5935 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5936 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5937 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5938 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5939 strlcpy(info->fw_version, tp->rtl_fw.version,
5940 sizeof(info->fw_version));
5944 int rtl8152_get_link_ksettings(struct net_device *netdev,
5945 struct ethtool_link_ksettings *cmd)
5947 struct r8152 *tp = netdev_priv(netdev);
5950 if (!tp->mii.mdio_read)
5953 ret = usb_autopm_get_interface(tp->intf);
5957 mutex_lock(&tp->control);
5959 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5961 mutex_unlock(&tp->control);
5963 usb_autopm_put_interface(tp->intf);
5969 static int rtl8152_set_link_ksettings(struct net_device *dev,
5970 const struct ethtool_link_ksettings *cmd)
5972 struct r8152 *tp = netdev_priv(dev);
5973 u32 advertising = 0;
5976 ret = usb_autopm_get_interface(tp->intf);
5980 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5981 cmd->link_modes.advertising))
5982 advertising |= RTL_ADVERTISED_10_HALF;
5984 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5985 cmd->link_modes.advertising))
5986 advertising |= RTL_ADVERTISED_10_FULL;
5988 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5989 cmd->link_modes.advertising))
5990 advertising |= RTL_ADVERTISED_100_HALF;
5992 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5993 cmd->link_modes.advertising))
5994 advertising |= RTL_ADVERTISED_100_FULL;
5996 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5997 cmd->link_modes.advertising))
5998 advertising |= RTL_ADVERTISED_1000_HALF;
6000 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
6001 cmd->link_modes.advertising))
6002 advertising |= RTL_ADVERTISED_1000_FULL;
6004 mutex_lock(&tp->control);
6006 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
6007 cmd->base.duplex, advertising);
6009 tp->autoneg = cmd->base.autoneg;
6010 tp->speed = cmd->base.speed;
6011 tp->duplex = cmd->base.duplex;
6012 tp->advertising = advertising;
6015 mutex_unlock(&tp->control);
6017 usb_autopm_put_interface(tp->intf);
6023 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6030 "tx_single_collisions",
6031 "tx_multi_collisions",
6039 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6043 return ARRAY_SIZE(rtl8152_gstrings);
6049 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6050 struct ethtool_stats *stats, u64 *data)
6052 struct r8152 *tp = netdev_priv(dev);
6053 struct tally_counter tally;
6055 if (usb_autopm_get_interface(tp->intf) < 0)
6058 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6060 usb_autopm_put_interface(tp->intf);
6062 data[0] = le64_to_cpu(tally.tx_packets);
6063 data[1] = le64_to_cpu(tally.rx_packets);
6064 data[2] = le64_to_cpu(tally.tx_errors);
6065 data[3] = le32_to_cpu(tally.rx_errors);
6066 data[4] = le16_to_cpu(tally.rx_missed);
6067 data[5] = le16_to_cpu(tally.align_errors);
6068 data[6] = le32_to_cpu(tally.tx_one_collision);
6069 data[7] = le32_to_cpu(tally.tx_multi_collision);
6070 data[8] = le64_to_cpu(tally.rx_unicast);
6071 data[9] = le64_to_cpu(tally.rx_broadcast);
6072 data[10] = le32_to_cpu(tally.rx_multicast);
6073 data[11] = le16_to_cpu(tally.tx_aborted);
6074 data[12] = le16_to_cpu(tally.tx_underrun);
6077 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6079 switch (stringset) {
6081 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6086 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6088 u32 lp, adv, supported = 0;
6091 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6092 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6094 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6095 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6097 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6098 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6100 eee->eee_enabled = tp->eee_en;
6101 eee->eee_active = !!(supported & adv & lp);
6102 eee->supported = supported;
6103 eee->advertised = tp->eee_adv;
6104 eee->lp_advertised = lp;
6109 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6111 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6113 tp->eee_en = eee->eee_enabled;
6116 rtl_eee_enable(tp, tp->eee_en);
6121 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6123 u32 lp, adv, supported = 0;
6126 val = ocp_reg_read(tp, OCP_EEE_ABLE);
6127 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6129 val = ocp_reg_read(tp, OCP_EEE_ADV);
6130 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6132 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6133 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6135 eee->eee_enabled = tp->eee_en;
6136 eee->eee_active = !!(supported & adv & lp);
6137 eee->supported = supported;
6138 eee->advertised = tp->eee_adv;
6139 eee->lp_advertised = lp;
6145 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6147 struct r8152 *tp = netdev_priv(net);
6150 if (!tp->rtl_ops.eee_get) {
6155 ret = usb_autopm_get_interface(tp->intf);
6159 mutex_lock(&tp->control);
6161 ret = tp->rtl_ops.eee_get(tp, edata);
6163 mutex_unlock(&tp->control);
6165 usb_autopm_put_interface(tp->intf);
6172 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6174 struct r8152 *tp = netdev_priv(net);
6177 if (!tp->rtl_ops.eee_set) {
6182 ret = usb_autopm_get_interface(tp->intf);
6186 mutex_lock(&tp->control);
6188 ret = tp->rtl_ops.eee_set(tp, edata);
6190 ret = mii_nway_restart(&tp->mii);
6192 mutex_unlock(&tp->control);
6194 usb_autopm_put_interface(tp->intf);
6200 static int rtl8152_nway_reset(struct net_device *dev)
6202 struct r8152 *tp = netdev_priv(dev);
6205 ret = usb_autopm_get_interface(tp->intf);
6209 mutex_lock(&tp->control);
6211 ret = mii_nway_restart(&tp->mii);
6213 mutex_unlock(&tp->control);
6215 usb_autopm_put_interface(tp->intf);
6221 static int rtl8152_get_coalesce(struct net_device *netdev,
6222 struct ethtool_coalesce *coalesce)
6224 struct r8152 *tp = netdev_priv(netdev);
6226 switch (tp->version) {
6235 coalesce->rx_coalesce_usecs = tp->coalesce;
6240 static int rtl8152_set_coalesce(struct net_device *netdev,
6241 struct ethtool_coalesce *coalesce)
6243 struct r8152 *tp = netdev_priv(netdev);
6246 switch (tp->version) {
6255 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6258 ret = usb_autopm_get_interface(tp->intf);
6262 mutex_lock(&tp->control);
6264 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6265 tp->coalesce = coalesce->rx_coalesce_usecs;
6267 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6268 netif_stop_queue(netdev);
6269 napi_disable(&tp->napi);
6270 tp->rtl_ops.disable(tp);
6271 tp->rtl_ops.enable(tp);
6273 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6274 _rtl8152_set_rx_mode(netdev);
6275 napi_enable(&tp->napi);
6276 netif_wake_queue(netdev);
6280 mutex_unlock(&tp->control);
6282 usb_autopm_put_interface(tp->intf);
6287 static int rtl8152_get_tunable(struct net_device *netdev,
6288 const struct ethtool_tunable *tunable, void *d)
6290 struct r8152 *tp = netdev_priv(netdev);
6292 switch (tunable->id) {
6293 case ETHTOOL_RX_COPYBREAK:
6294 *(u32 *)d = tp->rx_copybreak;
6303 static int rtl8152_set_tunable(struct net_device *netdev,
6304 const struct ethtool_tunable *tunable,
6307 struct r8152 *tp = netdev_priv(netdev);
6310 switch (tunable->id) {
6311 case ETHTOOL_RX_COPYBREAK:
6313 if (val < ETH_ZLEN) {
6314 netif_err(tp, rx_err, netdev,
6315 "Invalid rx copy break value\n");
6319 if (tp->rx_copybreak != val) {
6320 if (netdev->flags & IFF_UP) {
6321 mutex_lock(&tp->control);
6322 napi_disable(&tp->napi);
6323 tp->rx_copybreak = val;
6324 napi_enable(&tp->napi);
6325 mutex_unlock(&tp->control);
6327 tp->rx_copybreak = val;
6338 static void rtl8152_get_ringparam(struct net_device *netdev,
6339 struct ethtool_ringparam *ring)
6341 struct r8152 *tp = netdev_priv(netdev);
6343 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6344 ring->rx_pending = tp->rx_pending;
6347 static int rtl8152_set_ringparam(struct net_device *netdev,
6348 struct ethtool_ringparam *ring)
6350 struct r8152 *tp = netdev_priv(netdev);
6352 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6355 if (tp->rx_pending != ring->rx_pending) {
6356 if (netdev->flags & IFF_UP) {
6357 mutex_lock(&tp->control);
6358 napi_disable(&tp->napi);
6359 tp->rx_pending = ring->rx_pending;
6360 napi_enable(&tp->napi);
6361 mutex_unlock(&tp->control);
6363 tp->rx_pending = ring->rx_pending;
6370 static const struct ethtool_ops ops = {
6371 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6372 .get_drvinfo = rtl8152_get_drvinfo,
6373 .get_link = ethtool_op_get_link,
6374 .nway_reset = rtl8152_nway_reset,
6375 .get_msglevel = rtl8152_get_msglevel,
6376 .set_msglevel = rtl8152_set_msglevel,
6377 .get_wol = rtl8152_get_wol,
6378 .set_wol = rtl8152_set_wol,
6379 .get_strings = rtl8152_get_strings,
6380 .get_sset_count = rtl8152_get_sset_count,
6381 .get_ethtool_stats = rtl8152_get_ethtool_stats,
6382 .get_coalesce = rtl8152_get_coalesce,
6383 .set_coalesce = rtl8152_set_coalesce,
6384 .get_eee = rtl_ethtool_get_eee,
6385 .set_eee = rtl_ethtool_set_eee,
6386 .get_link_ksettings = rtl8152_get_link_ksettings,
6387 .set_link_ksettings = rtl8152_set_link_ksettings,
6388 .get_tunable = rtl8152_get_tunable,
6389 .set_tunable = rtl8152_set_tunable,
6390 .get_ringparam = rtl8152_get_ringparam,
6391 .set_ringparam = rtl8152_set_ringparam,
6394 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6396 struct r8152 *tp = netdev_priv(netdev);
6397 struct mii_ioctl_data *data = if_mii(rq);
6400 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6403 res = usb_autopm_get_interface(tp->intf);
6409 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6413 mutex_lock(&tp->control);
6414 data->val_out = r8152_mdio_read(tp, data->reg_num);
6415 mutex_unlock(&tp->control);
6419 if (!capable(CAP_NET_ADMIN)) {
6423 mutex_lock(&tp->control);
6424 r8152_mdio_write(tp, data->reg_num, data->val_in);
6425 mutex_unlock(&tp->control);
6432 usb_autopm_put_interface(tp->intf);
6438 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6440 struct r8152 *tp = netdev_priv(dev);
6443 switch (tp->version) {
6453 ret = usb_autopm_get_interface(tp->intf);
6457 mutex_lock(&tp->control);
6461 if (netif_running(dev)) {
6462 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6464 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6466 if (netif_carrier_ok(dev))
6467 r8153_set_rx_early_size(tp);
6470 mutex_unlock(&tp->control);
6472 usb_autopm_put_interface(tp->intf);
6477 static const struct net_device_ops rtl8152_netdev_ops = {
6478 .ndo_open = rtl8152_open,
6479 .ndo_stop = rtl8152_close,
6480 .ndo_do_ioctl = rtl8152_ioctl,
6481 .ndo_start_xmit = rtl8152_start_xmit,
6482 .ndo_tx_timeout = rtl8152_tx_timeout,
6483 .ndo_set_features = rtl8152_set_features,
6484 .ndo_set_rx_mode = rtl8152_set_rx_mode,
6485 .ndo_set_mac_address = rtl8152_set_mac_address,
6486 .ndo_change_mtu = rtl8152_change_mtu,
6487 .ndo_validate_addr = eth_validate_addr,
6488 .ndo_features_check = rtl8152_features_check,
6491 static void rtl8152_unload(struct r8152 *tp)
6493 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6496 if (tp->version != RTL_VER_01)
6497 r8152_power_cut_en(tp, true);
6500 static void rtl8153_unload(struct r8152 *tp)
6502 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6505 r8153_power_cut_en(tp, false);
6508 static void rtl8153b_unload(struct r8152 *tp)
6510 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6513 r8153b_power_cut_en(tp, false);
6516 static int rtl_ops_init(struct r8152 *tp)
6518 struct rtl_ops *ops = &tp->rtl_ops;
6521 switch (tp->version) {
6525 ops->init = r8152b_init;
6526 ops->enable = rtl8152_enable;
6527 ops->disable = rtl8152_disable;
6528 ops->up = rtl8152_up;
6529 ops->down = rtl8152_down;
6530 ops->unload = rtl8152_unload;
6531 ops->eee_get = r8152_get_eee;
6532 ops->eee_set = r8152_set_eee;
6533 ops->in_nway = rtl8152_in_nway;
6534 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
6535 ops->autosuspend_en = rtl_runtime_suspend_enable;
6536 tp->rx_buf_sz = 16 * 1024;
6538 tp->eee_adv = MDIO_EEE_100TX;
6545 ops->init = r8153_init;
6546 ops->enable = rtl8153_enable;
6547 ops->disable = rtl8153_disable;
6548 ops->up = rtl8153_up;
6549 ops->down = rtl8153_down;
6550 ops->unload = rtl8153_unload;
6551 ops->eee_get = r8153_get_eee;
6552 ops->eee_set = r8152_set_eee;
6553 ops->in_nway = rtl8153_in_nway;
6554 ops->hw_phy_cfg = r8153_hw_phy_cfg;
6555 ops->autosuspend_en = rtl8153_runtime_enable;
6556 if (tp->udev->speed < USB_SPEED_SUPER)
6557 tp->rx_buf_sz = 16 * 1024;
6559 tp->rx_buf_sz = 32 * 1024;
6561 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6566 ops->init = r8153b_init;
6567 ops->enable = rtl8153_enable;
6568 ops->disable = rtl8153_disable;
6569 ops->up = rtl8153b_up;
6570 ops->down = rtl8153b_down;
6571 ops->unload = rtl8153b_unload;
6572 ops->eee_get = r8153_get_eee;
6573 ops->eee_set = r8152_set_eee;
6574 ops->in_nway = rtl8153_in_nway;
6575 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
6576 ops->autosuspend_en = rtl8153b_runtime_enable;
6577 tp->rx_buf_sz = 32 * 1024;
6579 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6584 dev_err(&tp->intf->dev, "Unknown Device\n");
6591 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
6592 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
6593 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
6594 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
6596 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6597 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6598 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6599 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6601 static int rtl_fw_init(struct r8152 *tp)
6603 struct rtl_fw *rtl_fw = &tp->rtl_fw;
6605 switch (tp->version) {
6607 rtl_fw->fw_name = FIRMWARE_8153A_2;
6608 rtl_fw->pre_fw = r8153_pre_firmware_1;
6609 rtl_fw->post_fw = r8153_post_firmware_1;
6612 rtl_fw->fw_name = FIRMWARE_8153A_3;
6613 rtl_fw->pre_fw = r8153_pre_firmware_2;
6614 rtl_fw->post_fw = r8153_post_firmware_2;
6617 rtl_fw->fw_name = FIRMWARE_8153A_4;
6618 rtl_fw->post_fw = r8153_post_firmware_3;
6621 rtl_fw->fw_name = FIRMWARE_8153B_2;
6622 rtl_fw->pre_fw = r8153b_pre_firmware_1;
6623 rtl_fw->post_fw = r8153b_post_firmware_1;
6632 u8 rtl8152_get_version(struct usb_interface *intf)
6634 struct usb_device *udev = interface_to_usbdev(intf);
6640 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6644 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6645 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6646 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6648 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6654 version = RTL_VER_01;
6657 version = RTL_VER_02;
6660 version = RTL_VER_03;
6663 version = RTL_VER_04;
6666 version = RTL_VER_05;
6669 version = RTL_VER_06;
6672 version = RTL_VER_07;
6675 version = RTL_VER_08;
6678 version = RTL_VER_09;
6681 version = RTL_VER_UNKNOWN;
6682 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6686 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6690 EXPORT_SYMBOL_GPL(rtl8152_get_version);
6692 static int rtl8152_probe(struct usb_interface *intf,
6693 const struct usb_device_id *id)
6695 struct usb_device *udev = interface_to_usbdev(intf);
6696 u8 version = rtl8152_get_version(intf);
6698 struct net_device *netdev;
6701 if (version == RTL_VER_UNKNOWN)
6704 if (udev->actconfig->desc.bConfigurationValue != 1) {
6705 usb_driver_set_configuration(udev, 1);
6709 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6712 usb_reset_device(udev);
6713 netdev = alloc_etherdev(sizeof(struct r8152));
6715 dev_err(&intf->dev, "Out of memory\n");
6719 SET_NETDEV_DEV(netdev, &intf->dev);
6720 tp = netdev_priv(netdev);
6721 tp->msg_enable = 0x7FFF;
6724 tp->netdev = netdev;
6726 tp->version = version;
6732 tp->mii.supports_gmii = 0;
6735 tp->mii.supports_gmii = 1;
6739 ret = rtl_ops_init(tp);
6745 mutex_init(&tp->control);
6746 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6747 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6748 tasklet_setup(&tp->tx_tl, bottom_half);
6749 tasklet_disable(&tp->tx_tl);
6751 netdev->netdev_ops = &rtl8152_netdev_ops;
6752 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6754 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6755 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6756 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6757 NETIF_F_HW_VLAN_CTAG_TX;
6758 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6759 NETIF_F_TSO | NETIF_F_FRAGLIST |
6760 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6761 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6762 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6763 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6764 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6766 if (tp->version == RTL_VER_01) {
6767 netdev->features &= ~NETIF_F_RXCSUM;
6768 netdev->hw_features &= ~NETIF_F_RXCSUM;
6771 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6772 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6773 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6774 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6775 set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6779 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6780 (!strcmp(udev->serial, "000001000000") ||
6781 !strcmp(udev->serial, "000002000000"))) {
6782 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6783 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6786 netdev->ethtool_ops = &ops;
6787 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6789 /* MTU range: 68 - 1500 or 9194 */
6790 netdev->min_mtu = ETH_MIN_MTU;
6791 switch (tp->version) {
6794 netdev->max_mtu = ETH_DATA_LEN;
6797 netdev->max_mtu = RTL8153_MAX_MTU;
6801 tp->mii.dev = netdev;
6802 tp->mii.mdio_read = read_mii_word;
6803 tp->mii.mdio_write = write_mii_word;
6804 tp->mii.phy_id_mask = 0x3f;
6805 tp->mii.reg_num_mask = 0x1f;
6806 tp->mii.phy_id = R8152_PHY_ID;
6808 tp->autoneg = AUTONEG_ENABLE;
6809 tp->speed = SPEED_100;
6810 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6811 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6812 if (tp->mii.supports_gmii) {
6813 tp->speed = SPEED_1000;
6814 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6816 tp->duplex = DUPLEX_FULL;
6818 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6819 tp->rx_pending = 10 * RTL8152_MAX_RX;
6821 intf->needs_remote_wakeup = 1;
6823 if (!rtl_can_wakeup(tp))
6824 __rtl_set_wol(tp, 0);
6826 tp->saved_wolopts = __rtl_get_wol(tp);
6828 tp->rtl_ops.init(tp);
6829 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6830 /* Retry in case request_firmware() is not ready yet. */
6831 tp->rtl_fw.retry = true;
6833 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6834 set_ethernet_addr(tp);
6836 usb_set_intfdata(intf, tp);
6837 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6839 ret = register_netdev(netdev);
6841 dev_err(&intf->dev, "couldn't register the device\n");
6845 if (tp->saved_wolopts)
6846 device_set_wakeup_enable(&udev->dev, true);
6848 device_set_wakeup_enable(&udev->dev, false);
6850 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6855 tasklet_kill(&tp->tx_tl);
6856 usb_set_intfdata(intf, NULL);
6858 free_netdev(netdev);
6862 static void rtl8152_disconnect(struct usb_interface *intf)
6864 struct r8152 *tp = usb_get_intfdata(intf);
6866 usb_set_intfdata(intf, NULL);
6870 unregister_netdev(tp->netdev);
6871 tasklet_kill(&tp->tx_tl);
6872 cancel_delayed_work_sync(&tp->hw_phy_work);
6873 tp->rtl_ops.unload(tp);
6874 rtl8152_release_firmware(tp);
6875 free_netdev(tp->netdev);
6879 #define REALTEK_USB_DEVICE(vend, prod) \
6880 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6881 USB_DEVICE_ID_MATCH_INT_CLASS, \
6882 .idVendor = (vend), \
6883 .idProduct = (prod), \
6884 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6887 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6888 USB_DEVICE_ID_MATCH_DEVICE, \
6889 .idVendor = (vend), \
6890 .idProduct = (prod), \
6891 .bInterfaceClass = USB_CLASS_COMM, \
6892 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6893 .bInterfaceProtocol = USB_CDC_PROTO_NONE
6895 /* table of devices that work with this driver */
6896 static const struct usb_device_id rtl8152_table[] = {
6897 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6898 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6899 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6900 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6901 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6902 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6903 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6904 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
6905 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
6906 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
6907 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)},
6908 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6909 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6910 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
6911 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
6912 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
6913 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6914 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
6915 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
6919 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6921 static struct usb_driver rtl8152_driver = {
6923 .id_table = rtl8152_table,
6924 .probe = rtl8152_probe,
6925 .disconnect = rtl8152_disconnect,
6926 .suspend = rtl8152_suspend,
6927 .resume = rtl8152_resume,
6928 .reset_resume = rtl8152_reset_resume,
6929 .pre_reset = rtl8152_pre_reset,
6930 .post_reset = rtl8152_post_reset,
6931 .supports_autosuspend = 1,
6932 .disable_hub_initiated_lpm = 1,
6935 module_usb_driver(rtl8152_driver);
6937 MODULE_AUTHOR(DRIVER_AUTHOR);
6938 MODULE_DESCRIPTION(DRIVER_DESC);
6939 MODULE_LICENSE("GPL");
6940 MODULE_VERSION(DRIVER_VERSION);