090ddd5fb9737c7c24b28bbd16386fdcdd4a7d3b
[linux-2.6-microblaze.git] / drivers / net / usb / r8152.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29
30 /* Information for net-next */
31 #define NETNEXT_VERSION         "11"
32
33 /* Information for net */
34 #define NET_VERSION             "10"
35
36 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
40
41 #define R8152_PHY_ID            32
42
43 #define PLA_IDR                 0xc000
44 #define PLA_RCR                 0xc010
45 #define PLA_RMS                 0xc016
46 #define PLA_RXFIFO_CTRL0        0xc0a0
47 #define PLA_RXFIFO_CTRL1        0xc0a4
48 #define PLA_RXFIFO_CTRL2        0xc0a8
49 #define PLA_DMY_REG0            0xc0b0
50 #define PLA_FMC                 0xc0b4
51 #define PLA_CFG_WOL             0xc0b6
52 #define PLA_TEREDO_CFG          0xc0bc
53 #define PLA_TEREDO_WAKE_BASE    0xc0c4
54 #define PLA_MAR                 0xcd00
55 #define PLA_BACKUP              0xd000
56 #define PLA_BDC_CR              0xd1a0
57 #define PLA_TEREDO_TIMER        0xd2cc
58 #define PLA_REALWOW_TIMER       0xd2e8
59 #define PLA_UPHY_TIMER          0xd388
60 #define PLA_SUSPEND_FLAG        0xd38a
61 #define PLA_INDICATE_FALG       0xd38c
62 #define PLA_MACDBG_PRE          0xd38c  /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST         0xd38e  /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS        0xd398
65 #define PLA_EFUSE_DATA          0xdd00
66 #define PLA_EFUSE_CMD           0xdd02
67 #define PLA_LEDSEL              0xdd90
68 #define PLA_LED_FEATURE         0xdd92
69 #define PLA_PHYAR               0xde00
70 #define PLA_BOOT_CTRL           0xe004
71 #define PLA_GPHY_INTR_IMR       0xe022
72 #define PLA_EEE_CR              0xe040
73 #define PLA_EEEP_CR             0xe080
74 #define PLA_MAC_PWR_CTRL        0xe0c0
75 #define PLA_MAC_PWR_CTRL2       0xe0ca
76 #define PLA_MAC_PWR_CTRL3       0xe0cc
77 #define PLA_MAC_PWR_CTRL4       0xe0ce
78 #define PLA_WDT6_CTRL           0xe428
79 #define PLA_TCR0                0xe610
80 #define PLA_TCR1                0xe612
81 #define PLA_MTPS                0xe615
82 #define PLA_TXFIFO_CTRL         0xe618
83 #define PLA_RSTTALLY            0xe800
84 #define PLA_CR                  0xe813
85 #define PLA_CRWECR              0xe81c
86 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
87 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
88 #define PLA_CONFIG5             0xe822
89 #define PLA_PHY_PWR             0xe84c
90 #define PLA_OOB_CTRL            0xe84f
91 #define PLA_CPCR                0xe854
92 #define PLA_MISC_0              0xe858
93 #define PLA_MISC_1              0xe85a
94 #define PLA_OCP_GPHY_BASE       0xe86c
95 #define PLA_TALLYCNT            0xe890
96 #define PLA_SFF_STS_7           0xe8de
97 #define PLA_PHYSTATUS           0xe908
98 #define PLA_BP_BA               0xfc26
99 #define PLA_BP_0                0xfc28
100 #define PLA_BP_1                0xfc2a
101 #define PLA_BP_2                0xfc2c
102 #define PLA_BP_3                0xfc2e
103 #define PLA_BP_4                0xfc30
104 #define PLA_BP_5                0xfc32
105 #define PLA_BP_6                0xfc34
106 #define PLA_BP_7                0xfc36
107 #define PLA_BP_EN               0xfc38
108
109 #define USB_USB2PHY             0xb41e
110 #define USB_SSPHYLINK2          0xb428
111 #define USB_U2P3_CTRL           0xb460
112 #define USB_CSR_DUMMY1          0xb464
113 #define USB_CSR_DUMMY2          0xb466
114 #define USB_DEV_STAT            0xb808
115 #define USB_CONNECT_TIMER       0xcbf8
116 #define USB_MSC_TIMER           0xcbfc
117 #define USB_BURST_SIZE          0xcfc0
118 #define USB_FW_FIX_EN0          0xcfca
119 #define USB_FW_FIX_EN1          0xcfcc
120 #define USB_LPM_CONFIG          0xcfd8
121 #define USB_CSTMR               0xcfef  /* RTL8153A */
122 #define USB_FW_CTRL             0xd334  /* RTL8153B */
123 #define USB_FC_TIMER            0xd340
124 #define USB_USB_CTRL            0xd406
125 #define USB_PHY_CTRL            0xd408
126 #define USB_TX_AGG              0xd40a
127 #define USB_RX_BUF_TH           0xd40c
128 #define USB_USB_TIMER           0xd428
129 #define USB_RX_EARLY_TIMEOUT    0xd42c
130 #define USB_RX_EARLY_SIZE       0xd42e
131 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
132 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
133 #define USB_TX_DMA              0xd434
134 #define USB_UPT_RXDMA_OWN       0xd437
135 #define USB_TOLERANCE           0xd490
136 #define USB_LPM_CTRL            0xd41a
137 #define USB_BMU_RESET           0xd4b0
138 #define USB_U1U2_TIMER          0xd4da
139 #define USB_FW_TASK             0xd4e8  /* RTL8153B */
140 #define USB_UPS_CTRL            0xd800
141 #define USB_POWER_CUT           0xd80a
142 #define USB_MISC_0              0xd81a
143 #define USB_MISC_1              0xd81f
144 #define USB_AFE_CTRL2           0xd824
145 #define USB_UPS_CFG             0xd842
146 #define USB_UPS_FLAGS           0xd848
147 #define USB_WDT1_CTRL           0xe404
148 #define USB_WDT11_CTRL          0xe43c
149 #define USB_BP_BA               PLA_BP_BA
150 #define USB_BP_0                PLA_BP_0
151 #define USB_BP_1                PLA_BP_1
152 #define USB_BP_2                PLA_BP_2
153 #define USB_BP_3                PLA_BP_3
154 #define USB_BP_4                PLA_BP_4
155 #define USB_BP_5                PLA_BP_5
156 #define USB_BP_6                PLA_BP_6
157 #define USB_BP_7                PLA_BP_7
158 #define USB_BP_EN               PLA_BP_EN       /* RTL8153A */
159 #define USB_BP_8                0xfc38          /* RTL8153B */
160 #define USB_BP_9                0xfc3a
161 #define USB_BP_10               0xfc3c
162 #define USB_BP_11               0xfc3e
163 #define USB_BP_12               0xfc40
164 #define USB_BP_13               0xfc42
165 #define USB_BP_14               0xfc44
166 #define USB_BP_15               0xfc46
167 #define USB_BP2_EN              0xfc48
168
169 /* OCP Registers */
170 #define OCP_ALDPS_CONFIG        0x2010
171 #define OCP_EEE_CONFIG1         0x2080
172 #define OCP_EEE_CONFIG2         0x2092
173 #define OCP_EEE_CONFIG3         0x2094
174 #define OCP_BASE_MII            0xa400
175 #define OCP_EEE_AR              0xa41a
176 #define OCP_EEE_DATA            0xa41c
177 #define OCP_PHY_STATUS          0xa420
178 #define OCP_NCTL_CFG            0xa42c
179 #define OCP_POWER_CFG           0xa430
180 #define OCP_EEE_CFG             0xa432
181 #define OCP_SRAM_ADDR           0xa436
182 #define OCP_SRAM_DATA           0xa438
183 #define OCP_DOWN_SPEED          0xa442
184 #define OCP_EEE_ABLE            0xa5c4
185 #define OCP_EEE_ADV             0xa5d0
186 #define OCP_EEE_LPABLE          0xa5d2
187 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
188 #define OCP_PHY_PATCH_STAT      0xb800
189 #define OCP_PHY_PATCH_CMD       0xb820
190 #define OCP_ADC_IOFFSET         0xbcfc
191 #define OCP_ADC_CFG             0xbc06
192 #define OCP_SYSCLK_CFG          0xc416
193
194 /* SRAM Register */
195 #define SRAM_GREEN_CFG          0x8011
196 #define SRAM_LPF_CFG            0x8012
197 #define SRAM_10M_AMP1           0x8080
198 #define SRAM_10M_AMP2           0x8082
199 #define SRAM_IMPEDANCE          0x8084
200
201 /* PLA_RCR */
202 #define RCR_AAP                 0x00000001
203 #define RCR_APM                 0x00000002
204 #define RCR_AM                  0x00000004
205 #define RCR_AB                  0x00000008
206 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
207
208 /* PLA_RXFIFO_CTRL0 */
209 #define RXFIFO_THR1_NORMAL      0x00080002
210 #define RXFIFO_THR1_OOB         0x01800003
211
212 /* PLA_RXFIFO_CTRL1 */
213 #define RXFIFO_THR2_FULL        0x00000060
214 #define RXFIFO_THR2_HIGH        0x00000038
215 #define RXFIFO_THR2_OOB         0x0000004a
216 #define RXFIFO_THR2_NORMAL      0x00a0
217
218 /* PLA_RXFIFO_CTRL2 */
219 #define RXFIFO_THR3_FULL        0x00000078
220 #define RXFIFO_THR3_HIGH        0x00000048
221 #define RXFIFO_THR3_OOB         0x0000005a
222 #define RXFIFO_THR3_NORMAL      0x0110
223
224 /* PLA_TXFIFO_CTRL */
225 #define TXFIFO_THR_NORMAL       0x00400008
226 #define TXFIFO_THR_NORMAL2      0x01000008
227
228 /* PLA_DMY_REG0 */
229 #define ECM_ALDPS               0x0002
230
231 /* PLA_FMC */
232 #define FMC_FCR_MCU_EN          0x0001
233
234 /* PLA_EEEP_CR */
235 #define EEEP_CR_EEEP_TX         0x0002
236
237 /* PLA_WDT6_CTRL */
238 #define WDT6_SET_MODE           0x0010
239
240 /* PLA_TCR0 */
241 #define TCR0_TX_EMPTY           0x0800
242 #define TCR0_AUTO_FIFO          0x0080
243
244 /* PLA_TCR1 */
245 #define VERSION_MASK            0x7cf0
246
247 /* PLA_MTPS */
248 #define MTPS_JUMBO              (12 * 1024 / 64)
249 #define MTPS_DEFAULT            (6 * 1024 / 64)
250
251 /* PLA_RSTTALLY */
252 #define TALLY_RESET             0x0001
253
254 /* PLA_CR */
255 #define CR_RST                  0x10
256 #define CR_RE                   0x08
257 #define CR_TE                   0x04
258
259 /* PLA_CRWECR */
260 #define CRWECR_NORAML           0x00
261 #define CRWECR_CONFIG           0xc0
262
263 /* PLA_OOB_CTRL */
264 #define NOW_IS_OOB              0x80
265 #define TXFIFO_EMPTY            0x20
266 #define RXFIFO_EMPTY            0x10
267 #define LINK_LIST_READY         0x02
268 #define DIS_MCU_CLROOB          0x01
269 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
270
271 /* PLA_MISC_1 */
272 #define RXDY_GATED_EN           0x0008
273
274 /* PLA_SFF_STS_7 */
275 #define RE_INIT_LL              0x8000
276 #define MCU_BORW_EN             0x4000
277
278 /* PLA_CPCR */
279 #define CPCR_RX_VLAN            0x0040
280
281 /* PLA_CFG_WOL */
282 #define MAGIC_EN                0x0001
283
284 /* PLA_TEREDO_CFG */
285 #define TEREDO_SEL              0x8000
286 #define TEREDO_WAKE_MASK        0x7f00
287 #define TEREDO_RS_EVENT_MASK    0x00fe
288 #define OOB_TEREDO_EN           0x0001
289
290 /* PLA_BDC_CR */
291 #define ALDPS_PROXY_MODE        0x0001
292
293 /* PLA_EFUSE_CMD */
294 #define EFUSE_READ_CMD          BIT(15)
295 #define EFUSE_DATA_BIT16        BIT(7)
296
297 /* PLA_CONFIG34 */
298 #define LINK_ON_WAKE_EN         0x0010
299 #define LINK_OFF_WAKE_EN        0x0008
300
301 /* PLA_CONFIG5 */
302 #define BWF_EN                  0x0040
303 #define MWF_EN                  0x0020
304 #define UWF_EN                  0x0010
305 #define LAN_WAKE_EN             0x0002
306
307 /* PLA_LED_FEATURE */
308 #define LED_MODE_MASK           0x0700
309
310 /* PLA_PHY_PWR */
311 #define TX_10M_IDLE_EN          0x0080
312 #define PFM_PWM_SWITCH          0x0040
313
314 /* PLA_MAC_PWR_CTRL */
315 #define D3_CLK_GATED_EN         0x00004000
316 #define MCU_CLK_RATIO           0x07010f07
317 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
318 #define ALDPS_SPDWN_RATIO       0x0f87
319
320 /* PLA_MAC_PWR_CTRL2 */
321 #define EEE_SPDWN_RATIO         0x8007
322 #define MAC_CLK_SPDWN_EN        BIT(15)
323
324 /* PLA_MAC_PWR_CTRL3 */
325 #define PKT_AVAIL_SPDWN_EN      0x0100
326 #define SUSPEND_SPDWN_EN        0x0004
327 #define U1U2_SPDWN_EN           0x0002
328 #define L1_SPDWN_EN             0x0001
329
330 /* PLA_MAC_PWR_CTRL4 */
331 #define PWRSAVE_SPDWN_EN        0x1000
332 #define RXDV_SPDWN_EN           0x0800
333 #define TX10MIDLE_EN            0x0100
334 #define TP100_SPDWN_EN          0x0020
335 #define TP500_SPDWN_EN          0x0010
336 #define TP1000_SPDWN_EN         0x0008
337 #define EEE_SPDWN_EN            0x0001
338
339 /* PLA_GPHY_INTR_IMR */
340 #define GPHY_STS_MSK            0x0001
341 #define SPEED_DOWN_MSK          0x0002
342 #define SPDWN_RXDV_MSK          0x0004
343 #define SPDWN_LINKCHG_MSK       0x0008
344
345 /* PLA_PHYAR */
346 #define PHYAR_FLAG              0x80000000
347
348 /* PLA_EEE_CR */
349 #define EEE_RX_EN               0x0001
350 #define EEE_TX_EN               0x0002
351
352 /* PLA_BOOT_CTRL */
353 #define AUTOLOAD_DONE           0x0002
354
355 /* PLA_SUSPEND_FLAG */
356 #define LINK_CHG_EVENT          BIT(0)
357
358 /* PLA_INDICATE_FALG */
359 #define UPCOMING_RUNTIME_D3     BIT(0)
360
361 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
362 #define DEBUG_OE                BIT(0)
363 #define DEBUG_LTSSM             0x0082
364
365 /* PLA_EXTRA_STATUS */
366 #define U3P3_CHECK_EN           BIT(7)  /* RTL_VER_05 only */
367 #define LINK_CHANGE_FLAG        BIT(8)
368
369 /* USB_USB2PHY */
370 #define USB2PHY_SUSPEND         0x0001
371 #define USB2PHY_L1              0x0002
372
373 /* USB_SSPHYLINK2 */
374 #define pwd_dn_scale_mask       0x3ffe
375 #define pwd_dn_scale(x)         ((x) << 1)
376
377 /* USB_CSR_DUMMY1 */
378 #define DYNAMIC_BURST           0x0001
379
380 /* USB_CSR_DUMMY2 */
381 #define EP4_FULL_FC             0x0001
382
383 /* USB_DEV_STAT */
384 #define STAT_SPEED_MASK         0x0006
385 #define STAT_SPEED_HIGH         0x0000
386 #define STAT_SPEED_FULL         0x0002
387
388 /* USB_FW_FIX_EN0 */
389 #define FW_FIX_SUSPEND          BIT(14)
390
391 /* USB_FW_FIX_EN1 */
392 #define FW_IP_RESET_EN          BIT(9)
393
394 /* USB_LPM_CONFIG */
395 #define LPM_U1U2_EN             BIT(0)
396
397 /* USB_TX_AGG */
398 #define TX_AGG_MAX_THRESHOLD    0x03
399
400 /* USB_RX_BUF_TH */
401 #define RX_THR_SUPPER           0x0c350180
402 #define RX_THR_HIGH             0x7a120180
403 #define RX_THR_SLOW             0xffff0180
404 #define RX_THR_B                0x00010001
405
406 /* USB_TX_DMA */
407 #define TEST_MODE_DISABLE       0x00000001
408 #define TX_SIZE_ADJUST1         0x00000100
409
410 /* USB_BMU_RESET */
411 #define BMU_RESET_EP_IN         0x01
412 #define BMU_RESET_EP_OUT        0x02
413
414 /* USB_UPT_RXDMA_OWN */
415 #define OWN_UPDATE              BIT(0)
416 #define OWN_CLEAR               BIT(1)
417
418 /* USB_FW_TASK */
419 #define FC_PATCH_TASK           BIT(1)
420
421 /* USB_UPS_CTRL */
422 #define POWER_CUT               0x0100
423
424 /* USB_PM_CTRL_STATUS */
425 #define RESUME_INDICATE         0x0001
426
427 /* USB_CSTMR */
428 #define FORCE_SUPER             BIT(0)
429
430 /* USB_FW_CTRL */
431 #define FLOW_CTRL_PATCH_OPT     BIT(1)
432
433 /* USB_FC_TIMER */
434 #define CTRL_TIMER_EN           BIT(15)
435
436 /* USB_USB_CTRL */
437 #define RX_AGG_DISABLE          0x0010
438 #define RX_ZERO_EN              0x0080
439
440 /* USB_U2P3_CTRL */
441 #define U2P3_ENABLE             0x0001
442
443 /* USB_POWER_CUT */
444 #define PWR_EN                  0x0001
445 #define PHASE2_EN               0x0008
446 #define UPS_EN                  BIT(4)
447 #define USP_PREWAKE             BIT(5)
448
449 /* USB_MISC_0 */
450 #define PCUT_STATUS             0x0001
451
452 /* USB_RX_EARLY_TIMEOUT */
453 #define COALESCE_SUPER           85000U
454 #define COALESCE_HIGH           250000U
455 #define COALESCE_SLOW           524280U
456
457 /* USB_WDT1_CTRL */
458 #define WTD1_EN                 BIT(0)
459
460 /* USB_WDT11_CTRL */
461 #define TIMER11_EN              0x0001
462
463 /* USB_LPM_CTRL */
464 /* bit 4 ~ 5: fifo empty boundary */
465 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
466 /* bit 2 ~ 3: LMP timer */
467 #define LPM_TIMER_MASK          0x0c
468 #define LPM_TIMER_500MS         0x04    /* 500 ms */
469 #define LPM_TIMER_500US         0x0c    /* 500 us */
470 #define ROK_EXIT_LPM            0x02
471
472 /* USB_AFE_CTRL2 */
473 #define SEN_VAL_MASK            0xf800
474 #define SEN_VAL_NORMAL          0xa000
475 #define SEL_RXIDLE              0x0100
476
477 /* USB_UPS_CFG */
478 #define SAW_CNT_1MS_MASK        0x0fff
479
480 /* USB_UPS_FLAGS */
481 #define UPS_FLAGS_R_TUNE                BIT(0)
482 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
483 #define UPS_FLAGS_250M_CKDIV            BIT(2)
484 #define UPS_FLAGS_EN_ALDPS              BIT(3)
485 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
486 #define ups_flags_speed(x)              ((x) << 16)
487 #define UPS_FLAGS_EN_EEE                BIT(20)
488 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
489 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
490 #define UPS_FLAGS_EEE_PLLOFF_100        BIT(23)
491 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
492 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
493 #define UPS_FLAGS_EN_GREEN              BIT(26)
494 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
495
496 enum spd_duplex {
497         NWAY_10M_HALF,
498         NWAY_10M_FULL,
499         NWAY_100M_HALF,
500         NWAY_100M_FULL,
501         NWAY_1000M_FULL,
502         FORCE_10M_HALF,
503         FORCE_10M_FULL,
504         FORCE_100M_HALF,
505         FORCE_100M_FULL,
506 };
507
508 /* OCP_ALDPS_CONFIG */
509 #define ENPWRSAVE               0x8000
510 #define ENPDNPS                 0x0200
511 #define LINKENA                 0x0100
512 #define DIS_SDSAVE              0x0010
513
514 /* OCP_PHY_STATUS */
515 #define PHY_STAT_MASK           0x0007
516 #define PHY_STAT_EXT_INIT       2
517 #define PHY_STAT_LAN_ON         3
518 #define PHY_STAT_PWRDN          5
519
520 /* OCP_NCTL_CFG */
521 #define PGA_RETURN_EN           BIT(1)
522
523 /* OCP_POWER_CFG */
524 #define EEE_CLKDIV_EN           0x8000
525 #define EN_ALDPS                0x0004
526 #define EN_10M_PLLOFF           0x0001
527
528 /* OCP_EEE_CONFIG1 */
529 #define RG_TXLPI_MSK_HFDUP      0x8000
530 #define RG_MATCLR_EN            0x4000
531 #define EEE_10_CAP              0x2000
532 #define EEE_NWAY_EN             0x1000
533 #define TX_QUIET_EN             0x0200
534 #define RX_QUIET_EN             0x0100
535 #define sd_rise_time_mask       0x0070
536 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
537 #define RG_RXLPI_MSK_HFDUP      0x0008
538 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
539
540 /* OCP_EEE_CONFIG2 */
541 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
542 #define RG_DACQUIET_EN          0x0400
543 #define RG_LDVQUIET_EN          0x0200
544 #define RG_CKRSEL               0x0020
545 #define RG_EEEPRG_EN            0x0010
546
547 /* OCP_EEE_CONFIG3 */
548 #define fast_snr_mask           0xff80
549 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
550 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
551 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
552
553 /* OCP_EEE_AR */
554 /* bit[15:14] function */
555 #define FUN_ADDR                0x0000
556 #define FUN_DATA                0x4000
557 /* bit[4:0] device addr */
558
559 /* OCP_EEE_CFG */
560 #define CTAP_SHORT_EN           0x0040
561 #define EEE10_EN                0x0010
562
563 /* OCP_DOWN_SPEED */
564 #define EN_EEE_CMODE            BIT(14)
565 #define EN_EEE_1000             BIT(13)
566 #define EN_EEE_100              BIT(12)
567 #define EN_10M_CLKDIV           BIT(11)
568 #define EN_10M_BGOFF            0x0080
569
570 /* OCP_PHY_STATE */
571 #define TXDIS_STATE             0x01
572 #define ABD_STATE               0x02
573
574 /* OCP_PHY_PATCH_STAT */
575 #define PATCH_READY             BIT(6)
576
577 /* OCP_PHY_PATCH_CMD */
578 #define PATCH_REQUEST           BIT(4)
579
580 /* OCP_ADC_CFG */
581 #define CKADSEL_L               0x0100
582 #define ADC_EN                  0x0080
583 #define EN_EMI_L                0x0040
584
585 /* OCP_SYSCLK_CFG */
586 #define clk_div_expo(x)         (min(x, 5) << 8)
587
588 /* SRAM_GREEN_CFG */
589 #define GREEN_ETH_EN            BIT(15)
590 #define R_TUNE_EN               BIT(11)
591
592 /* SRAM_LPF_CFG */
593 #define LPF_AUTO_TUNE           0x8000
594
595 /* SRAM_10M_AMP1 */
596 #define GDAC_IB_UPALL           0x0008
597
598 /* SRAM_10M_AMP2 */
599 #define AMP_DN                  0x0200
600
601 /* SRAM_IMPEDANCE */
602 #define RX_DRIVING_MASK         0x6000
603
604 /* MAC PASSTHRU */
605 #define AD_MASK                 0xfee0
606 #define BND_MASK                0x0004
607 #define BD_MASK                 0x0001
608 #define EFUSE                   0xcfdb
609 #define PASS_THRU_MASK          0x1
610
611 #define BP4_SUPER_ONLY          0x1578  /* RTL_VER_04 only */
612
613 enum rtl_register_content {
614         _1000bps        = 0x10,
615         _100bps         = 0x08,
616         _10bps          = 0x04,
617         LINK_STATUS     = 0x02,
618         FULL_DUP        = 0x01,
619 };
620
621 #define RTL8152_MAX_TX          4
622 #define RTL8152_MAX_RX          10
623 #define INTBUFSIZE              2
624 #define TX_ALIGN                4
625 #define RX_ALIGN                8
626
627 #define RTL8152_RX_MAX_PENDING  4096
628 #define RTL8152_RXFG_HEADSZ     256
629
630 #define INTR_LINK               0x0004
631
632 #define RTL8152_REQT_READ       0xc0
633 #define RTL8152_REQT_WRITE      0x40
634 #define RTL8152_REQ_GET_REGS    0x05
635 #define RTL8152_REQ_SET_REGS    0x05
636
637 #define BYTE_EN_DWORD           0xff
638 #define BYTE_EN_WORD            0x33
639 #define BYTE_EN_BYTE            0x11
640 #define BYTE_EN_SIX_BYTES       0x3f
641 #define BYTE_EN_START_MASK      0x0f
642 #define BYTE_EN_END_MASK        0xf0
643
644 #define RTL8153_MAX_PACKET      9216 /* 9K */
645 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
646                                  ETH_FCS_LEN)
647 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
648 #define RTL8153_RMS             RTL8153_MAX_PACKET
649 #define RTL8152_TX_TIMEOUT      (5 * HZ)
650 #define RTL8152_NAPI_WEIGHT     64
651 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
652                                  sizeof(struct rx_desc) + RX_ALIGN)
653
654 /* rtl8152 flags */
655 enum rtl8152_flags {
656         RTL8152_UNPLUG = 0,
657         RTL8152_SET_RX_MODE,
658         WORK_ENABLE,
659         RTL8152_LINK_CHG,
660         SELECTIVE_SUSPEND,
661         PHY_RESET,
662         SCHEDULE_TASKLET,
663         GREEN_ETHERNET,
664         DELL_TB_RX_AGG_BUG,
665 };
666
667 /* Define these values to match your device */
668 #define VENDOR_ID_REALTEK               0x0bda
669 #define VENDOR_ID_MICROSOFT             0x045e
670 #define VENDOR_ID_SAMSUNG               0x04e8
671 #define VENDOR_ID_LENOVO                0x17ef
672 #define VENDOR_ID_LINKSYS               0x13b1
673 #define VENDOR_ID_NVIDIA                0x0955
674 #define VENDOR_ID_TPLINK                0x2357
675
676 #define MCU_TYPE_PLA                    0x0100
677 #define MCU_TYPE_USB                    0x0000
678
679 struct tally_counter {
680         __le64  tx_packets;
681         __le64  rx_packets;
682         __le64  tx_errors;
683         __le32  rx_errors;
684         __le16  rx_missed;
685         __le16  align_errors;
686         __le32  tx_one_collision;
687         __le32  tx_multi_collision;
688         __le64  rx_unicast;
689         __le64  rx_broadcast;
690         __le32  rx_multicast;
691         __le16  tx_aborted;
692         __le16  tx_underrun;
693 };
694
695 struct rx_desc {
696         __le32 opts1;
697 #define RX_LEN_MASK                     0x7fff
698
699         __le32 opts2;
700 #define RD_UDP_CS                       BIT(23)
701 #define RD_TCP_CS                       BIT(22)
702 #define RD_IPV6_CS                      BIT(20)
703 #define RD_IPV4_CS                      BIT(19)
704
705         __le32 opts3;
706 #define IPF                             BIT(23) /* IP checksum fail */
707 #define UDPF                            BIT(22) /* UDP checksum fail */
708 #define TCPF                            BIT(21) /* TCP checksum fail */
709 #define RX_VLAN_TAG                     BIT(16)
710
711         __le32 opts4;
712         __le32 opts5;
713         __le32 opts6;
714 };
715
716 struct tx_desc {
717         __le32 opts1;
718 #define TX_FS                   BIT(31) /* First segment of a packet */
719 #define TX_LS                   BIT(30) /* Final segment of a packet */
720 #define GTSENDV4                BIT(28)
721 #define GTSENDV6                BIT(27)
722 #define GTTCPHO_SHIFT           18
723 #define GTTCPHO_MAX             0x7fU
724 #define TX_LEN_MAX              0x3ffffU
725
726         __le32 opts2;
727 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
728 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
729 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
730 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
731 #define MSS_SHIFT               17
732 #define MSS_MAX                 0x7ffU
733 #define TCPHO_SHIFT             17
734 #define TCPHO_MAX               0x7ffU
735 #define TX_VLAN_TAG             BIT(16)
736 };
737
738 struct r8152;
739
740 struct rx_agg {
741         struct list_head list, info_list;
742         struct urb *urb;
743         struct r8152 *context;
744         struct page *page;
745         void *buffer;
746 };
747
748 struct tx_agg {
749         struct list_head list;
750         struct urb *urb;
751         struct r8152 *context;
752         void *buffer;
753         void *head;
754         u32 skb_num;
755         u32 skb_len;
756 };
757
758 struct r8152 {
759         unsigned long flags;
760         struct usb_device *udev;
761         struct napi_struct napi;
762         struct usb_interface *intf;
763         struct net_device *netdev;
764         struct urb *intr_urb;
765         struct tx_agg tx_info[RTL8152_MAX_TX];
766         struct list_head rx_info, rx_used;
767         struct list_head rx_done, tx_free;
768         struct sk_buff_head tx_queue, rx_queue;
769         spinlock_t rx_lock, tx_lock;
770         struct delayed_work schedule, hw_phy_work;
771         struct mii_if_info mii;
772         struct mutex control;   /* use for hw setting */
773 #ifdef CONFIG_PM_SLEEP
774         struct notifier_block pm_notifier;
775 #endif
776         struct tasklet_struct tx_tl;
777
778         struct rtl_ops {
779                 void (*init)(struct r8152 *tp);
780                 int (*enable)(struct r8152 *tp);
781                 void (*disable)(struct r8152 *tp);
782                 void (*up)(struct r8152 *tp);
783                 void (*down)(struct r8152 *tp);
784                 void (*unload)(struct r8152 *tp);
785                 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
786                 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
787                 bool (*in_nway)(struct r8152 *tp);
788                 void (*hw_phy_cfg)(struct r8152 *tp);
789                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
790         } rtl_ops;
791
792         struct ups_info {
793                 u32 _10m_ckdiv:1;
794                 u32 _250m_ckdiv:1;
795                 u32 aldps:1;
796                 u32 lite_mode:2;
797                 u32 speed_duplex:4;
798                 u32 eee:1;
799                 u32 eee_lite:1;
800                 u32 eee_ckdiv:1;
801                 u32 eee_plloff_100:1;
802                 u32 eee_plloff_giga:1;
803                 u32 eee_cmod_lv:1;
804                 u32 green:1;
805                 u32 flow_control:1;
806                 u32 ctap_short_off:1;
807         } ups_info;
808
809 #define RTL_VER_SIZE            32
810
811         struct rtl_fw {
812                 const char *fw_name;
813                 const struct firmware *fw;
814
815                 char version[RTL_VER_SIZE];
816                 int (*pre_fw)(struct r8152 *tp);
817                 int (*post_fw)(struct r8152 *tp);
818
819                 bool retry;
820         } rtl_fw;
821
822         atomic_t rx_count;
823
824         bool eee_en;
825         int intr_interval;
826         u32 saved_wolopts;
827         u32 msg_enable;
828         u32 tx_qlen;
829         u32 coalesce;
830         u32 advertising;
831         u32 rx_buf_sz;
832         u32 rx_copybreak;
833         u32 rx_pending;
834
835         u16 ocp_base;
836         u16 speed;
837         u16 eee_adv;
838         u8 *intr_buff;
839         u8 version;
840         u8 duplex;
841         u8 autoneg;
842 };
843
844 /**
845  * struct fw_block - block type and total length
846  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
847  *      RTL_FW_USB and so on.
848  * @length: total length of the current block.
849  */
850 struct fw_block {
851         __le32 type;
852         __le32 length;
853 } __packed;
854
855 /**
856  * struct fw_header - header of the firmware file
857  * @checksum: checksum of sha256 which is calculated from the whole file
858  *      except the checksum field of the file. That is, calculate sha256
859  *      from the version field to the end of the file.
860  * @version: version of this firmware.
861  * @blocks: the first firmware block of the file
862  */
863 struct fw_header {
864         u8 checksum[32];
865         char version[RTL_VER_SIZE];
866         struct fw_block blocks[0];
867 } __packed;
868
869 /**
870  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
871  *      The layout of the firmware block is:
872  *      <struct fw_mac> + <info> + <firmware data>.
873  * @fw_offset: offset of the firmware binary data. The start address of
874  *      the data would be the address of struct fw_mac + @fw_offset.
875  * @fw_reg: the register to load the firmware. Depends on chip.
876  * @bp_ba_addr: the register to write break point base address. Depends on
877  *      chip.
878  * @bp_ba_value: break point base address. Depends on chip.
879  * @bp_en_addr: the register to write break point enabled mask. Depends
880  *      on chip.
881  * @bp_en_value: break point enabled mask. Depends on the firmware.
882  * @bp_start: the start register of break points. Depends on chip.
883  * @bp_num: the break point number which needs to be set for this firmware.
884  *      Depends on the firmware.
885  * @bp: break points. Depends on firmware.
886  * @fw_ver_reg: the register to store the fw version.
887  * @fw_ver_data: the firmware version of the current type.
888  * @info: additional information for debugging, and is followed by the
889  *      binary data of firmware.
890  */
891 struct fw_mac {
892         struct fw_block blk_hdr;
893         __le16 fw_offset;
894         __le16 fw_reg;
895         __le16 bp_ba_addr;
896         __le16 bp_ba_value;
897         __le16 bp_en_addr;
898         __le16 bp_en_value;
899         __le16 bp_start;
900         __le16 bp_num;
901         __le16 bp[16]; /* any value determined by firmware */
902         __le32 reserved;
903         __le16 fw_ver_reg;
904         u8 fw_ver_data;
905         char info[0];
906 } __packed;
907
908 enum rtl_fw_type {
909         RTL_FW_END = 0,
910         RTL_FW_PLA,
911         RTL_FW_USB,
912 };
913
914 enum rtl_version {
915         RTL_VER_UNKNOWN = 0,
916         RTL_VER_01,
917         RTL_VER_02,
918         RTL_VER_03,
919         RTL_VER_04,
920         RTL_VER_05,
921         RTL_VER_06,
922         RTL_VER_07,
923         RTL_VER_08,
924         RTL_VER_09,
925         RTL_VER_MAX
926 };
927
928 enum tx_csum_stat {
929         TX_CSUM_SUCCESS = 0,
930         TX_CSUM_TSO,
931         TX_CSUM_NONE
932 };
933
934 #define RTL_ADVERTISED_10_HALF                  BIT(0)
935 #define RTL_ADVERTISED_10_FULL                  BIT(1)
936 #define RTL_ADVERTISED_100_HALF                 BIT(2)
937 #define RTL_ADVERTISED_100_FULL                 BIT(3)
938 #define RTL_ADVERTISED_1000_HALF                BIT(4)
939 #define RTL_ADVERTISED_1000_FULL                BIT(5)
940
941 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
942  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
943  */
944 static const int multicast_filter_limit = 32;
945 static unsigned int agg_buf_sz = 16384;
946
947 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
948                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
949
950 static
951 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
952 {
953         int ret;
954         void *tmp;
955
956         tmp = kmalloc(size, GFP_KERNEL);
957         if (!tmp)
958                 return -ENOMEM;
959
960         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
961                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
962                               value, index, tmp, size, 500);
963         if (ret < 0)
964                 memset(data, 0xff, size);
965         else
966                 memcpy(data, tmp, size);
967
968         kfree(tmp);
969
970         return ret;
971 }
972
973 static
974 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
975 {
976         int ret;
977         void *tmp;
978
979         tmp = kmemdup(data, size, GFP_KERNEL);
980         if (!tmp)
981                 return -ENOMEM;
982
983         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
984                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
985                               value, index, tmp, size, 500);
986
987         kfree(tmp);
988
989         return ret;
990 }
991
992 static void rtl_set_unplug(struct r8152 *tp)
993 {
994         if (tp->udev->state == USB_STATE_NOTATTACHED) {
995                 set_bit(RTL8152_UNPLUG, &tp->flags);
996                 smp_mb__after_atomic();
997         }
998 }
999
1000 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1001                             void *data, u16 type)
1002 {
1003         u16 limit = 64;
1004         int ret = 0;
1005
1006         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1007                 return -ENODEV;
1008
1009         /* both size and indix must be 4 bytes align */
1010         if ((size & 3) || !size || (index & 3) || !data)
1011                 return -EPERM;
1012
1013         if ((u32)index + (u32)size > 0xffff)
1014                 return -EPERM;
1015
1016         while (size) {
1017                 if (size > limit) {
1018                         ret = get_registers(tp, index, type, limit, data);
1019                         if (ret < 0)
1020                                 break;
1021
1022                         index += limit;
1023                         data += limit;
1024                         size -= limit;
1025                 } else {
1026                         ret = get_registers(tp, index, type, size, data);
1027                         if (ret < 0)
1028                                 break;
1029
1030                         index += size;
1031                         data += size;
1032                         size = 0;
1033                         break;
1034                 }
1035         }
1036
1037         if (ret == -ENODEV)
1038                 rtl_set_unplug(tp);
1039
1040         return ret;
1041 }
1042
1043 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1044                              u16 size, void *data, u16 type)
1045 {
1046         int ret;
1047         u16 byteen_start, byteen_end, byen;
1048         u16 limit = 512;
1049
1050         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1051                 return -ENODEV;
1052
1053         /* both size and indix must be 4 bytes align */
1054         if ((size & 3) || !size || (index & 3) || !data)
1055                 return -EPERM;
1056
1057         if ((u32)index + (u32)size > 0xffff)
1058                 return -EPERM;
1059
1060         byteen_start = byteen & BYTE_EN_START_MASK;
1061         byteen_end = byteen & BYTE_EN_END_MASK;
1062
1063         byen = byteen_start | (byteen_start << 4);
1064         ret = set_registers(tp, index, type | byen, 4, data);
1065         if (ret < 0)
1066                 goto error1;
1067
1068         index += 4;
1069         data += 4;
1070         size -= 4;
1071
1072         if (size) {
1073                 size -= 4;
1074
1075                 while (size) {
1076                         if (size > limit) {
1077                                 ret = set_registers(tp, index,
1078                                                     type | BYTE_EN_DWORD,
1079                                                     limit, data);
1080                                 if (ret < 0)
1081                                         goto error1;
1082
1083                                 index += limit;
1084                                 data += limit;
1085                                 size -= limit;
1086                         } else {
1087                                 ret = set_registers(tp, index,
1088                                                     type | BYTE_EN_DWORD,
1089                                                     size, data);
1090                                 if (ret < 0)
1091                                         goto error1;
1092
1093                                 index += size;
1094                                 data += size;
1095                                 size = 0;
1096                                 break;
1097                         }
1098                 }
1099
1100                 byen = byteen_end | (byteen_end >> 4);
1101                 ret = set_registers(tp, index, type | byen, 4, data);
1102                 if (ret < 0)
1103                         goto error1;
1104         }
1105
1106 error1:
1107         if (ret == -ENODEV)
1108                 rtl_set_unplug(tp);
1109
1110         return ret;
1111 }
1112
1113 static inline
1114 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1115 {
1116         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1117 }
1118
1119 static inline
1120 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1121 {
1122         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1123 }
1124
1125 static inline
1126 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1127 {
1128         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1129 }
1130
1131 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1132 {
1133         __le32 data;
1134
1135         generic_ocp_read(tp, index, sizeof(data), &data, type);
1136
1137         return __le32_to_cpu(data);
1138 }
1139
1140 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1141 {
1142         __le32 tmp = __cpu_to_le32(data);
1143
1144         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1145 }
1146
1147 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1148 {
1149         u32 data;
1150         __le32 tmp;
1151         u16 byen = BYTE_EN_WORD;
1152         u8 shift = index & 2;
1153
1154         index &= ~3;
1155         byen <<= shift;
1156
1157         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1158
1159         data = __le32_to_cpu(tmp);
1160         data >>= (shift * 8);
1161         data &= 0xffff;
1162
1163         return (u16)data;
1164 }
1165
1166 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1167 {
1168         u32 mask = 0xffff;
1169         __le32 tmp;
1170         u16 byen = BYTE_EN_WORD;
1171         u8 shift = index & 2;
1172
1173         data &= mask;
1174
1175         if (index & 2) {
1176                 byen <<= shift;
1177                 mask <<= (shift * 8);
1178                 data <<= (shift * 8);
1179                 index &= ~3;
1180         }
1181
1182         tmp = __cpu_to_le32(data);
1183
1184         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1185 }
1186
1187 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1188 {
1189         u32 data;
1190         __le32 tmp;
1191         u8 shift = index & 3;
1192
1193         index &= ~3;
1194
1195         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1196
1197         data = __le32_to_cpu(tmp);
1198         data >>= (shift * 8);
1199         data &= 0xff;
1200
1201         return (u8)data;
1202 }
1203
1204 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1205 {
1206         u32 mask = 0xff;
1207         __le32 tmp;
1208         u16 byen = BYTE_EN_BYTE;
1209         u8 shift = index & 3;
1210
1211         data &= mask;
1212
1213         if (index & 3) {
1214                 byen <<= shift;
1215                 mask <<= (shift * 8);
1216                 data <<= (shift * 8);
1217                 index &= ~3;
1218         }
1219
1220         tmp = __cpu_to_le32(data);
1221
1222         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1223 }
1224
1225 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1226 {
1227         u16 ocp_base, ocp_index;
1228
1229         ocp_base = addr & 0xf000;
1230         if (ocp_base != tp->ocp_base) {
1231                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1232                 tp->ocp_base = ocp_base;
1233         }
1234
1235         ocp_index = (addr & 0x0fff) | 0xb000;
1236         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1237 }
1238
1239 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1240 {
1241         u16 ocp_base, ocp_index;
1242
1243         ocp_base = addr & 0xf000;
1244         if (ocp_base != tp->ocp_base) {
1245                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1246                 tp->ocp_base = ocp_base;
1247         }
1248
1249         ocp_index = (addr & 0x0fff) | 0xb000;
1250         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1251 }
1252
1253 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1254 {
1255         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1256 }
1257
1258 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1259 {
1260         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1261 }
1262
1263 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1264 {
1265         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1266         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1267 }
1268
1269 static u16 sram_read(struct r8152 *tp, u16 addr)
1270 {
1271         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1272         return ocp_reg_read(tp, OCP_SRAM_DATA);
1273 }
1274
1275 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1276 {
1277         struct r8152 *tp = netdev_priv(netdev);
1278         int ret;
1279
1280         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1281                 return -ENODEV;
1282
1283         if (phy_id != R8152_PHY_ID)
1284                 return -EINVAL;
1285
1286         ret = r8152_mdio_read(tp, reg);
1287
1288         return ret;
1289 }
1290
1291 static
1292 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1293 {
1294         struct r8152 *tp = netdev_priv(netdev);
1295
1296         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1297                 return;
1298
1299         if (phy_id != R8152_PHY_ID)
1300                 return;
1301
1302         r8152_mdio_write(tp, reg, val);
1303 }
1304
1305 static int
1306 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1307
1308 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1309 {
1310         struct r8152 *tp = netdev_priv(netdev);
1311         struct sockaddr *addr = p;
1312         int ret = -EADDRNOTAVAIL;
1313
1314         if (!is_valid_ether_addr(addr->sa_data))
1315                 goto out1;
1316
1317         ret = usb_autopm_get_interface(tp->intf);
1318         if (ret < 0)
1319                 goto out1;
1320
1321         mutex_lock(&tp->control);
1322
1323         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1324
1325         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1326         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1327         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1328
1329         mutex_unlock(&tp->control);
1330
1331         usb_autopm_put_interface(tp->intf);
1332 out1:
1333         return ret;
1334 }
1335
1336 /* Devices containing proper chips can support a persistent
1337  * host system provided MAC address.
1338  * Examples of this are Dell TB15 and Dell WD15 docks
1339  */
1340 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1341 {
1342         acpi_status status;
1343         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1344         union acpi_object *obj;
1345         int ret = -EINVAL;
1346         u32 ocp_data;
1347         unsigned char buf[6];
1348
1349         /* test for -AD variant of RTL8153 */
1350         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1351         if ((ocp_data & AD_MASK) == 0x1000) {
1352                 /* test for MAC address pass-through bit */
1353                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1354                 if ((ocp_data & PASS_THRU_MASK) != 1) {
1355                         netif_dbg(tp, probe, tp->netdev,
1356                                   "No efuse for RTL8153-AD MAC pass through\n");
1357                         return -ENODEV;
1358                 }
1359         } else {
1360                 /* test for RTL8153-BND and RTL8153-BD */
1361                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1362                 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1363                         netif_dbg(tp, probe, tp->netdev,
1364                                   "Invalid variant for MAC pass through\n");
1365                         return -ENODEV;
1366                 }
1367         }
1368
1369         /* returns _AUXMAC_#AABBCCDDEEFF# */
1370         status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1371         obj = (union acpi_object *)buffer.pointer;
1372         if (!ACPI_SUCCESS(status))
1373                 return -ENODEV;
1374         if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1375                 netif_warn(tp, probe, tp->netdev,
1376                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1377                            obj->type, obj->string.length);
1378                 goto amacout;
1379         }
1380         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1381             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1382                 netif_warn(tp, probe, tp->netdev,
1383                            "Invalid header when reading pass-thru MAC addr\n");
1384                 goto amacout;
1385         }
1386         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1387         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1388                 netif_warn(tp, probe, tp->netdev,
1389                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1390                            ret, buf);
1391                 ret = -EINVAL;
1392                 goto amacout;
1393         }
1394         memcpy(sa->sa_data, buf, 6);
1395         netif_info(tp, probe, tp->netdev,
1396                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1397
1398 amacout:
1399         kfree(obj);
1400         return ret;
1401 }
1402
1403 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1404 {
1405         struct net_device *dev = tp->netdev;
1406         int ret;
1407
1408         sa->sa_family = dev->type;
1409
1410         if (tp->version == RTL_VER_01) {
1411                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1412         } else {
1413                 /* if device doesn't support MAC pass through this will
1414                  * be expected to be non-zero
1415                  */
1416                 ret = vendor_mac_passthru_addr_read(tp, sa);
1417                 if (ret < 0)
1418                         ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1419         }
1420
1421         if (ret < 0) {
1422                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1423         } else if (!is_valid_ether_addr(sa->sa_data)) {
1424                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1425                           sa->sa_data);
1426                 eth_hw_addr_random(dev);
1427                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1428                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1429                            sa->sa_data);
1430                 return 0;
1431         }
1432
1433         return ret;
1434 }
1435
1436 static int set_ethernet_addr(struct r8152 *tp)
1437 {
1438         struct net_device *dev = tp->netdev;
1439         struct sockaddr sa;
1440         int ret;
1441
1442         ret = determine_ethernet_addr(tp, &sa);
1443         if (ret < 0)
1444                 return ret;
1445
1446         if (tp->version == RTL_VER_01)
1447                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1448         else
1449                 ret = rtl8152_set_mac_address(dev, &sa);
1450
1451         return ret;
1452 }
1453
1454 static void read_bulk_callback(struct urb *urb)
1455 {
1456         struct net_device *netdev;
1457         int status = urb->status;
1458         struct rx_agg *agg;
1459         struct r8152 *tp;
1460         unsigned long flags;
1461
1462         agg = urb->context;
1463         if (!agg)
1464                 return;
1465
1466         tp = agg->context;
1467         if (!tp)
1468                 return;
1469
1470         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1471                 return;
1472
1473         if (!test_bit(WORK_ENABLE, &tp->flags))
1474                 return;
1475
1476         netdev = tp->netdev;
1477
1478         /* When link down, the driver would cancel all bulks. */
1479         /* This avoid the re-submitting bulk */
1480         if (!netif_carrier_ok(netdev))
1481                 return;
1482
1483         usb_mark_last_busy(tp->udev);
1484
1485         switch (status) {
1486         case 0:
1487                 if (urb->actual_length < ETH_ZLEN)
1488                         break;
1489
1490                 spin_lock_irqsave(&tp->rx_lock, flags);
1491                 list_add_tail(&agg->list, &tp->rx_done);
1492                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1493                 napi_schedule(&tp->napi);
1494                 return;
1495         case -ESHUTDOWN:
1496                 rtl_set_unplug(tp);
1497                 netif_device_detach(tp->netdev);
1498                 return;
1499         case -ENOENT:
1500                 return; /* the urb is in unlink state */
1501         case -ETIME:
1502                 if (net_ratelimit())
1503                         netdev_warn(netdev, "maybe reset is needed?\n");
1504                 break;
1505         default:
1506                 if (net_ratelimit())
1507                         netdev_warn(netdev, "Rx status %d\n", status);
1508                 break;
1509         }
1510
1511         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1512 }
1513
1514 static void write_bulk_callback(struct urb *urb)
1515 {
1516         struct net_device_stats *stats;
1517         struct net_device *netdev;
1518         struct tx_agg *agg;
1519         struct r8152 *tp;
1520         unsigned long flags;
1521         int status = urb->status;
1522
1523         agg = urb->context;
1524         if (!agg)
1525                 return;
1526
1527         tp = agg->context;
1528         if (!tp)
1529                 return;
1530
1531         netdev = tp->netdev;
1532         stats = &netdev->stats;
1533         if (status) {
1534                 if (net_ratelimit())
1535                         netdev_warn(netdev, "Tx status %d\n", status);
1536                 stats->tx_errors += agg->skb_num;
1537         } else {
1538                 stats->tx_packets += agg->skb_num;
1539                 stats->tx_bytes += agg->skb_len;
1540         }
1541
1542         spin_lock_irqsave(&tp->tx_lock, flags);
1543         list_add_tail(&agg->list, &tp->tx_free);
1544         spin_unlock_irqrestore(&tp->tx_lock, flags);
1545
1546         usb_autopm_put_interface_async(tp->intf);
1547
1548         if (!netif_carrier_ok(netdev))
1549                 return;
1550
1551         if (!test_bit(WORK_ENABLE, &tp->flags))
1552                 return;
1553
1554         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1555                 return;
1556
1557         if (!skb_queue_empty(&tp->tx_queue))
1558                 tasklet_schedule(&tp->tx_tl);
1559 }
1560
1561 static void intr_callback(struct urb *urb)
1562 {
1563         struct r8152 *tp;
1564         __le16 *d;
1565         int status = urb->status;
1566         int res;
1567
1568         tp = urb->context;
1569         if (!tp)
1570                 return;
1571
1572         if (!test_bit(WORK_ENABLE, &tp->flags))
1573                 return;
1574
1575         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1576                 return;
1577
1578         switch (status) {
1579         case 0:                 /* success */
1580                 break;
1581         case -ECONNRESET:       /* unlink */
1582         case -ESHUTDOWN:
1583                 netif_device_detach(tp->netdev);
1584                 /* fall through */
1585         case -ENOENT:
1586         case -EPROTO:
1587                 netif_info(tp, intr, tp->netdev,
1588                            "Stop submitting intr, status %d\n", status);
1589                 return;
1590         case -EOVERFLOW:
1591                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1592                 goto resubmit;
1593         /* -EPIPE:  should clear the halt */
1594         default:
1595                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1596                 goto resubmit;
1597         }
1598
1599         d = urb->transfer_buffer;
1600         if (INTR_LINK & __le16_to_cpu(d[0])) {
1601                 if (!netif_carrier_ok(tp->netdev)) {
1602                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1603                         schedule_delayed_work(&tp->schedule, 0);
1604                 }
1605         } else {
1606                 if (netif_carrier_ok(tp->netdev)) {
1607                         netif_stop_queue(tp->netdev);
1608                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1609                         schedule_delayed_work(&tp->schedule, 0);
1610                 }
1611         }
1612
1613 resubmit:
1614         res = usb_submit_urb(urb, GFP_ATOMIC);
1615         if (res == -ENODEV) {
1616                 rtl_set_unplug(tp);
1617                 netif_device_detach(tp->netdev);
1618         } else if (res) {
1619                 netif_err(tp, intr, tp->netdev,
1620                           "can't resubmit intr, status %d\n", res);
1621         }
1622 }
1623
1624 static inline void *rx_agg_align(void *data)
1625 {
1626         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1627 }
1628
1629 static inline void *tx_agg_align(void *data)
1630 {
1631         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1632 }
1633
1634 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1635 {
1636         list_del(&agg->info_list);
1637
1638         usb_free_urb(agg->urb);
1639         put_page(agg->page);
1640         kfree(agg);
1641
1642         atomic_dec(&tp->rx_count);
1643 }
1644
1645 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1646 {
1647         struct net_device *netdev = tp->netdev;
1648         int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1649         unsigned int order = get_order(tp->rx_buf_sz);
1650         struct rx_agg *rx_agg;
1651         unsigned long flags;
1652
1653         rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1654         if (!rx_agg)
1655                 return NULL;
1656
1657         rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1658         if (!rx_agg->page)
1659                 goto free_rx;
1660
1661         rx_agg->buffer = page_address(rx_agg->page);
1662
1663         rx_agg->urb = usb_alloc_urb(0, mflags);
1664         if (!rx_agg->urb)
1665                 goto free_buf;
1666
1667         rx_agg->context = tp;
1668
1669         INIT_LIST_HEAD(&rx_agg->list);
1670         INIT_LIST_HEAD(&rx_agg->info_list);
1671         spin_lock_irqsave(&tp->rx_lock, flags);
1672         list_add_tail(&rx_agg->info_list, &tp->rx_info);
1673         spin_unlock_irqrestore(&tp->rx_lock, flags);
1674
1675         atomic_inc(&tp->rx_count);
1676
1677         return rx_agg;
1678
1679 free_buf:
1680         __free_pages(rx_agg->page, order);
1681 free_rx:
1682         kfree(rx_agg);
1683         return NULL;
1684 }
1685
1686 static void free_all_mem(struct r8152 *tp)
1687 {
1688         struct rx_agg *agg, *agg_next;
1689         unsigned long flags;
1690         int i;
1691
1692         spin_lock_irqsave(&tp->rx_lock, flags);
1693
1694         list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1695                 free_rx_agg(tp, agg);
1696
1697         spin_unlock_irqrestore(&tp->rx_lock, flags);
1698
1699         WARN_ON(atomic_read(&tp->rx_count));
1700
1701         for (i = 0; i < RTL8152_MAX_TX; i++) {
1702                 usb_free_urb(tp->tx_info[i].urb);
1703                 tp->tx_info[i].urb = NULL;
1704
1705                 kfree(tp->tx_info[i].buffer);
1706                 tp->tx_info[i].buffer = NULL;
1707                 tp->tx_info[i].head = NULL;
1708         }
1709
1710         usb_free_urb(tp->intr_urb);
1711         tp->intr_urb = NULL;
1712
1713         kfree(tp->intr_buff);
1714         tp->intr_buff = NULL;
1715 }
1716
1717 static int alloc_all_mem(struct r8152 *tp)
1718 {
1719         struct net_device *netdev = tp->netdev;
1720         struct usb_interface *intf = tp->intf;
1721         struct usb_host_interface *alt = intf->cur_altsetting;
1722         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1723         int node, i;
1724
1725         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1726
1727         spin_lock_init(&tp->rx_lock);
1728         spin_lock_init(&tp->tx_lock);
1729         INIT_LIST_HEAD(&tp->rx_info);
1730         INIT_LIST_HEAD(&tp->tx_free);
1731         INIT_LIST_HEAD(&tp->rx_done);
1732         skb_queue_head_init(&tp->tx_queue);
1733         skb_queue_head_init(&tp->rx_queue);
1734         atomic_set(&tp->rx_count, 0);
1735
1736         for (i = 0; i < RTL8152_MAX_RX; i++) {
1737                 if (!alloc_rx_agg(tp, GFP_KERNEL))
1738                         goto err1;
1739         }
1740
1741         for (i = 0; i < RTL8152_MAX_TX; i++) {
1742                 struct urb *urb;
1743                 u8 *buf;
1744
1745                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1746                 if (!buf)
1747                         goto err1;
1748
1749                 if (buf != tx_agg_align(buf)) {
1750                         kfree(buf);
1751                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1752                                            node);
1753                         if (!buf)
1754                                 goto err1;
1755                 }
1756
1757                 urb = usb_alloc_urb(0, GFP_KERNEL);
1758                 if (!urb) {
1759                         kfree(buf);
1760                         goto err1;
1761                 }
1762
1763                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1764                 tp->tx_info[i].context = tp;
1765                 tp->tx_info[i].urb = urb;
1766                 tp->tx_info[i].buffer = buf;
1767                 tp->tx_info[i].head = tx_agg_align(buf);
1768
1769                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1770         }
1771
1772         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1773         if (!tp->intr_urb)
1774                 goto err1;
1775
1776         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1777         if (!tp->intr_buff)
1778                 goto err1;
1779
1780         tp->intr_interval = (int)ep_intr->desc.bInterval;
1781         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1782                          tp->intr_buff, INTBUFSIZE, intr_callback,
1783                          tp, tp->intr_interval);
1784
1785         return 0;
1786
1787 err1:
1788         free_all_mem(tp);
1789         return -ENOMEM;
1790 }
1791
1792 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1793 {
1794         struct tx_agg *agg = NULL;
1795         unsigned long flags;
1796
1797         if (list_empty(&tp->tx_free))
1798                 return NULL;
1799
1800         spin_lock_irqsave(&tp->tx_lock, flags);
1801         if (!list_empty(&tp->tx_free)) {
1802                 struct list_head *cursor;
1803
1804                 cursor = tp->tx_free.next;
1805                 list_del_init(cursor);
1806                 agg = list_entry(cursor, struct tx_agg, list);
1807         }
1808         spin_unlock_irqrestore(&tp->tx_lock, flags);
1809
1810         return agg;
1811 }
1812
1813 /* r8152_csum_workaround()
1814  * The hw limits the value of the transport offset. When the offset is out of
1815  * range, calculate the checksum by sw.
1816  */
1817 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1818                                   struct sk_buff_head *list)
1819 {
1820         if (skb_shinfo(skb)->gso_size) {
1821                 netdev_features_t features = tp->netdev->features;
1822                 struct sk_buff_head seg_list;
1823                 struct sk_buff *segs, *nskb;
1824
1825                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1826                 segs = skb_gso_segment(skb, features);
1827                 if (IS_ERR(segs) || !segs)
1828                         goto drop;
1829
1830                 __skb_queue_head_init(&seg_list);
1831
1832                 do {
1833                         nskb = segs;
1834                         segs = segs->next;
1835                         nskb->next = NULL;
1836                         __skb_queue_tail(&seg_list, nskb);
1837                 } while (segs);
1838
1839                 skb_queue_splice(&seg_list, list);
1840                 dev_kfree_skb(skb);
1841         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1842                 if (skb_checksum_help(skb) < 0)
1843                         goto drop;
1844
1845                 __skb_queue_head(list, skb);
1846         } else {
1847                 struct net_device_stats *stats;
1848
1849 drop:
1850                 stats = &tp->netdev->stats;
1851                 stats->tx_dropped++;
1852                 dev_kfree_skb(skb);
1853         }
1854 }
1855
1856 /* msdn_giant_send_check()
1857  * According to the document of microsoft, the TCP Pseudo Header excludes the
1858  * packet length for IPv6 TCP large packets.
1859  */
1860 static int msdn_giant_send_check(struct sk_buff *skb)
1861 {
1862         const struct ipv6hdr *ipv6h;
1863         struct tcphdr *th;
1864         int ret;
1865
1866         ret = skb_cow_head(skb, 0);
1867         if (ret)
1868                 return ret;
1869
1870         ipv6h = ipv6_hdr(skb);
1871         th = tcp_hdr(skb);
1872
1873         th->check = 0;
1874         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1875
1876         return ret;
1877 }
1878
1879 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1880 {
1881         if (skb_vlan_tag_present(skb)) {
1882                 u32 opts2;
1883
1884                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1885                 desc->opts2 |= cpu_to_le32(opts2);
1886         }
1887 }
1888
1889 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1890 {
1891         u32 opts2 = le32_to_cpu(desc->opts2);
1892
1893         if (opts2 & RX_VLAN_TAG)
1894                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1895                                        swab16(opts2 & 0xffff));
1896 }
1897
1898 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1899                          struct sk_buff *skb, u32 len, u32 transport_offset)
1900 {
1901         u32 mss = skb_shinfo(skb)->gso_size;
1902         u32 opts1, opts2 = 0;
1903         int ret = TX_CSUM_SUCCESS;
1904
1905         WARN_ON_ONCE(len > TX_LEN_MAX);
1906
1907         opts1 = len | TX_FS | TX_LS;
1908
1909         if (mss) {
1910                 if (transport_offset > GTTCPHO_MAX) {
1911                         netif_warn(tp, tx_err, tp->netdev,
1912                                    "Invalid transport offset 0x%x for TSO\n",
1913                                    transport_offset);
1914                         ret = TX_CSUM_TSO;
1915                         goto unavailable;
1916                 }
1917
1918                 switch (vlan_get_protocol(skb)) {
1919                 case htons(ETH_P_IP):
1920                         opts1 |= GTSENDV4;
1921                         break;
1922
1923                 case htons(ETH_P_IPV6):
1924                         if (msdn_giant_send_check(skb)) {
1925                                 ret = TX_CSUM_TSO;
1926                                 goto unavailable;
1927                         }
1928                         opts1 |= GTSENDV6;
1929                         break;
1930
1931                 default:
1932                         WARN_ON_ONCE(1);
1933                         break;
1934                 }
1935
1936                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1937                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1938         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1939                 u8 ip_protocol;
1940
1941                 if (transport_offset > TCPHO_MAX) {
1942                         netif_warn(tp, tx_err, tp->netdev,
1943                                    "Invalid transport offset 0x%x\n",
1944                                    transport_offset);
1945                         ret = TX_CSUM_NONE;
1946                         goto unavailable;
1947                 }
1948
1949                 switch (vlan_get_protocol(skb)) {
1950                 case htons(ETH_P_IP):
1951                         opts2 |= IPV4_CS;
1952                         ip_protocol = ip_hdr(skb)->protocol;
1953                         break;
1954
1955                 case htons(ETH_P_IPV6):
1956                         opts2 |= IPV6_CS;
1957                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1958                         break;
1959
1960                 default:
1961                         ip_protocol = IPPROTO_RAW;
1962                         break;
1963                 }
1964
1965                 if (ip_protocol == IPPROTO_TCP)
1966                         opts2 |= TCP_CS;
1967                 else if (ip_protocol == IPPROTO_UDP)
1968                         opts2 |= UDP_CS;
1969                 else
1970                         WARN_ON_ONCE(1);
1971
1972                 opts2 |= transport_offset << TCPHO_SHIFT;
1973         }
1974
1975         desc->opts2 = cpu_to_le32(opts2);
1976         desc->opts1 = cpu_to_le32(opts1);
1977
1978 unavailable:
1979         return ret;
1980 }
1981
1982 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1983 {
1984         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1985         int remain, ret;
1986         u8 *tx_data;
1987
1988         __skb_queue_head_init(&skb_head);
1989         spin_lock(&tx_queue->lock);
1990         skb_queue_splice_init(tx_queue, &skb_head);
1991         spin_unlock(&tx_queue->lock);
1992
1993         tx_data = agg->head;
1994         agg->skb_num = 0;
1995         agg->skb_len = 0;
1996         remain = agg_buf_sz;
1997
1998         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1999                 struct tx_desc *tx_desc;
2000                 struct sk_buff *skb;
2001                 unsigned int len;
2002                 u32 offset;
2003
2004                 skb = __skb_dequeue(&skb_head);
2005                 if (!skb)
2006                         break;
2007
2008                 len = skb->len + sizeof(*tx_desc);
2009
2010                 if (len > remain) {
2011                         __skb_queue_head(&skb_head, skb);
2012                         break;
2013                 }
2014
2015                 tx_data = tx_agg_align(tx_data);
2016                 tx_desc = (struct tx_desc *)tx_data;
2017
2018                 offset = (u32)skb_transport_offset(skb);
2019
2020                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2021                         r8152_csum_workaround(tp, skb, &skb_head);
2022                         continue;
2023                 }
2024
2025                 rtl_tx_vlan_tag(tx_desc, skb);
2026
2027                 tx_data += sizeof(*tx_desc);
2028
2029                 len = skb->len;
2030                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2031                         struct net_device_stats *stats = &tp->netdev->stats;
2032
2033                         stats->tx_dropped++;
2034                         dev_kfree_skb_any(skb);
2035                         tx_data -= sizeof(*tx_desc);
2036                         continue;
2037                 }
2038
2039                 tx_data += len;
2040                 agg->skb_len += len;
2041                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2042
2043                 dev_kfree_skb_any(skb);
2044
2045                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2046
2047                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2048                         break;
2049         }
2050
2051         if (!skb_queue_empty(&skb_head)) {
2052                 spin_lock(&tx_queue->lock);
2053                 skb_queue_splice(&skb_head, tx_queue);
2054                 spin_unlock(&tx_queue->lock);
2055         }
2056
2057         netif_tx_lock(tp->netdev);
2058
2059         if (netif_queue_stopped(tp->netdev) &&
2060             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2061                 netif_wake_queue(tp->netdev);
2062
2063         netif_tx_unlock(tp->netdev);
2064
2065         ret = usb_autopm_get_interface_async(tp->intf);
2066         if (ret < 0)
2067                 goto out_tx_fill;
2068
2069         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2070                           agg->head, (int)(tx_data - (u8 *)agg->head),
2071                           (usb_complete_t)write_bulk_callback, agg);
2072
2073         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2074         if (ret < 0)
2075                 usb_autopm_put_interface_async(tp->intf);
2076
2077 out_tx_fill:
2078         return ret;
2079 }
2080
2081 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2082 {
2083         u8 checksum = CHECKSUM_NONE;
2084         u32 opts2, opts3;
2085
2086         if (!(tp->netdev->features & NETIF_F_RXCSUM))
2087                 goto return_result;
2088
2089         opts2 = le32_to_cpu(rx_desc->opts2);
2090         opts3 = le32_to_cpu(rx_desc->opts3);
2091
2092         if (opts2 & RD_IPV4_CS) {
2093                 if (opts3 & IPF)
2094                         checksum = CHECKSUM_NONE;
2095                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2096                         checksum = CHECKSUM_UNNECESSARY;
2097                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2098                         checksum = CHECKSUM_UNNECESSARY;
2099         } else if (opts2 & RD_IPV6_CS) {
2100                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2101                         checksum = CHECKSUM_UNNECESSARY;
2102                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2103                         checksum = CHECKSUM_UNNECESSARY;
2104         }
2105
2106 return_result:
2107         return checksum;
2108 }
2109
2110 static inline bool rx_count_exceed(struct r8152 *tp)
2111 {
2112         return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2113 }
2114
2115 static inline int agg_offset(struct rx_agg *agg, void *addr)
2116 {
2117         return (int)(addr - agg->buffer);
2118 }
2119
2120 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2121 {
2122         struct rx_agg *agg, *agg_next, *agg_free = NULL;
2123         unsigned long flags;
2124
2125         spin_lock_irqsave(&tp->rx_lock, flags);
2126
2127         list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2128                 if (page_count(agg->page) == 1) {
2129                         if (!agg_free) {
2130                                 list_del_init(&agg->list);
2131                                 agg_free = agg;
2132                                 continue;
2133                         }
2134                         if (rx_count_exceed(tp)) {
2135                                 list_del_init(&agg->list);
2136                                 free_rx_agg(tp, agg);
2137                         }
2138                         break;
2139                 }
2140         }
2141
2142         spin_unlock_irqrestore(&tp->rx_lock, flags);
2143
2144         if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2145                 agg_free = alloc_rx_agg(tp, mflags);
2146
2147         return agg_free;
2148 }
2149
2150 static int rx_bottom(struct r8152 *tp, int budget)
2151 {
2152         unsigned long flags;
2153         struct list_head *cursor, *next, rx_queue;
2154         int ret = 0, work_done = 0;
2155         struct napi_struct *napi = &tp->napi;
2156
2157         if (!skb_queue_empty(&tp->rx_queue)) {
2158                 while (work_done < budget) {
2159                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2160                         struct net_device *netdev = tp->netdev;
2161                         struct net_device_stats *stats = &netdev->stats;
2162                         unsigned int pkt_len;
2163
2164                         if (!skb)
2165                                 break;
2166
2167                         pkt_len = skb->len;
2168                         napi_gro_receive(napi, skb);
2169                         work_done++;
2170                         stats->rx_packets++;
2171                         stats->rx_bytes += pkt_len;
2172                 }
2173         }
2174
2175         if (list_empty(&tp->rx_done))
2176                 goto out1;
2177
2178         INIT_LIST_HEAD(&rx_queue);
2179         spin_lock_irqsave(&tp->rx_lock, flags);
2180         list_splice_init(&tp->rx_done, &rx_queue);
2181         spin_unlock_irqrestore(&tp->rx_lock, flags);
2182
2183         list_for_each_safe(cursor, next, &rx_queue) {
2184                 struct rx_desc *rx_desc;
2185                 struct rx_agg *agg, *agg_free;
2186                 int len_used = 0;
2187                 struct urb *urb;
2188                 u8 *rx_data;
2189
2190                 list_del_init(cursor);
2191
2192                 agg = list_entry(cursor, struct rx_agg, list);
2193                 urb = agg->urb;
2194                 if (urb->actual_length < ETH_ZLEN)
2195                         goto submit;
2196
2197                 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2198
2199                 rx_desc = agg->buffer;
2200                 rx_data = agg->buffer;
2201                 len_used += sizeof(struct rx_desc);
2202
2203                 while (urb->actual_length > len_used) {
2204                         struct net_device *netdev = tp->netdev;
2205                         struct net_device_stats *stats = &netdev->stats;
2206                         unsigned int pkt_len, rx_frag_head_sz;
2207                         struct sk_buff *skb;
2208
2209                         /* limite the skb numbers for rx_queue */
2210                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2211                                 break;
2212
2213                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2214                         if (pkt_len < ETH_ZLEN)
2215                                 break;
2216
2217                         len_used += pkt_len;
2218                         if (urb->actual_length < len_used)
2219                                 break;
2220
2221                         pkt_len -= ETH_FCS_LEN;
2222                         rx_data += sizeof(struct rx_desc);
2223
2224                         if (!agg_free || tp->rx_copybreak > pkt_len)
2225                                 rx_frag_head_sz = pkt_len;
2226                         else
2227                                 rx_frag_head_sz = tp->rx_copybreak;
2228
2229                         skb = napi_alloc_skb(napi, rx_frag_head_sz);
2230                         if (!skb) {
2231                                 stats->rx_dropped++;
2232                                 goto find_next_rx;
2233                         }
2234
2235                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2236                         memcpy(skb->data, rx_data, rx_frag_head_sz);
2237                         skb_put(skb, rx_frag_head_sz);
2238                         pkt_len -= rx_frag_head_sz;
2239                         rx_data += rx_frag_head_sz;
2240                         if (pkt_len) {
2241                                 skb_add_rx_frag(skb, 0, agg->page,
2242                                                 agg_offset(agg, rx_data),
2243                                                 pkt_len,
2244                                                 SKB_DATA_ALIGN(pkt_len));
2245                                 get_page(agg->page);
2246                         }
2247
2248                         skb->protocol = eth_type_trans(skb, netdev);
2249                         rtl_rx_vlan_tag(rx_desc, skb);
2250                         if (work_done < budget) {
2251                                 work_done++;
2252                                 stats->rx_packets++;
2253                                 stats->rx_bytes += skb->len;
2254                                 napi_gro_receive(napi, skb);
2255                         } else {
2256                                 __skb_queue_tail(&tp->rx_queue, skb);
2257                         }
2258
2259 find_next_rx:
2260                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2261                         rx_desc = (struct rx_desc *)rx_data;
2262                         len_used = agg_offset(agg, rx_data);
2263                         len_used += sizeof(struct rx_desc);
2264                 }
2265
2266                 WARN_ON(!agg_free && page_count(agg->page) > 1);
2267
2268                 if (agg_free) {
2269                         spin_lock_irqsave(&tp->rx_lock, flags);
2270                         if (page_count(agg->page) == 1) {
2271                                 list_add(&agg_free->list, &tp->rx_used);
2272                         } else {
2273                                 list_add_tail(&agg->list, &tp->rx_used);
2274                                 agg = agg_free;
2275                                 urb = agg->urb;
2276                         }
2277                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2278                 }
2279
2280 submit:
2281                 if (!ret) {
2282                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2283                 } else {
2284                         urb->actual_length = 0;
2285                         list_add_tail(&agg->list, next);
2286                 }
2287         }
2288
2289         if (!list_empty(&rx_queue)) {
2290                 spin_lock_irqsave(&tp->rx_lock, flags);
2291                 list_splice_tail(&rx_queue, &tp->rx_done);
2292                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2293         }
2294
2295 out1:
2296         return work_done;
2297 }
2298
2299 static void tx_bottom(struct r8152 *tp)
2300 {
2301         int res;
2302
2303         do {
2304                 struct net_device *netdev = tp->netdev;
2305                 struct tx_agg *agg;
2306
2307                 if (skb_queue_empty(&tp->tx_queue))
2308                         break;
2309
2310                 agg = r8152_get_tx_agg(tp);
2311                 if (!agg)
2312                         break;
2313
2314                 res = r8152_tx_agg_fill(tp, agg);
2315                 if (!res)
2316                         continue;
2317
2318                 if (res == -ENODEV) {
2319                         rtl_set_unplug(tp);
2320                         netif_device_detach(netdev);
2321                 } else {
2322                         struct net_device_stats *stats = &netdev->stats;
2323                         unsigned long flags;
2324
2325                         netif_warn(tp, tx_err, netdev,
2326                                    "failed tx_urb %d\n", res);
2327                         stats->tx_dropped += agg->skb_num;
2328
2329                         spin_lock_irqsave(&tp->tx_lock, flags);
2330                         list_add_tail(&agg->list, &tp->tx_free);
2331                         spin_unlock_irqrestore(&tp->tx_lock, flags);
2332                 }
2333         } while (res == 0);
2334 }
2335
2336 static void bottom_half(unsigned long data)
2337 {
2338         struct r8152 *tp;
2339
2340         tp = (struct r8152 *)data;
2341
2342         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2343                 return;
2344
2345         if (!test_bit(WORK_ENABLE, &tp->flags))
2346                 return;
2347
2348         /* When link down, the driver would cancel all bulks. */
2349         /* This avoid the re-submitting bulk */
2350         if (!netif_carrier_ok(tp->netdev))
2351                 return;
2352
2353         clear_bit(SCHEDULE_TASKLET, &tp->flags);
2354
2355         tx_bottom(tp);
2356 }
2357
2358 static int r8152_poll(struct napi_struct *napi, int budget)
2359 {
2360         struct r8152 *tp = container_of(napi, struct r8152, napi);
2361         int work_done;
2362
2363         work_done = rx_bottom(tp, budget);
2364
2365         if (work_done < budget) {
2366                 if (!napi_complete_done(napi, work_done))
2367                         goto out;
2368                 if (!list_empty(&tp->rx_done))
2369                         napi_schedule(napi);
2370         }
2371
2372 out:
2373         return work_done;
2374 }
2375
2376 static
2377 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2378 {
2379         int ret;
2380
2381         /* The rx would be stopped, so skip submitting */
2382         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2383             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2384                 return 0;
2385
2386         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2387                           agg->buffer, tp->rx_buf_sz,
2388                           (usb_complete_t)read_bulk_callback, agg);
2389
2390         ret = usb_submit_urb(agg->urb, mem_flags);
2391         if (ret == -ENODEV) {
2392                 rtl_set_unplug(tp);
2393                 netif_device_detach(tp->netdev);
2394         } else if (ret) {
2395                 struct urb *urb = agg->urb;
2396                 unsigned long flags;
2397
2398                 urb->actual_length = 0;
2399                 spin_lock_irqsave(&tp->rx_lock, flags);
2400                 list_add_tail(&agg->list, &tp->rx_done);
2401                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2402
2403                 netif_err(tp, rx_err, tp->netdev,
2404                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2405
2406                 napi_schedule(&tp->napi);
2407         }
2408
2409         return ret;
2410 }
2411
2412 static void rtl_drop_queued_tx(struct r8152 *tp)
2413 {
2414         struct net_device_stats *stats = &tp->netdev->stats;
2415         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2416         struct sk_buff *skb;
2417
2418         if (skb_queue_empty(tx_queue))
2419                 return;
2420
2421         __skb_queue_head_init(&skb_head);
2422         spin_lock_bh(&tx_queue->lock);
2423         skb_queue_splice_init(tx_queue, &skb_head);
2424         spin_unlock_bh(&tx_queue->lock);
2425
2426         while ((skb = __skb_dequeue(&skb_head))) {
2427                 dev_kfree_skb(skb);
2428                 stats->tx_dropped++;
2429         }
2430 }
2431
2432 static void rtl8152_tx_timeout(struct net_device *netdev)
2433 {
2434         struct r8152 *tp = netdev_priv(netdev);
2435
2436         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2437
2438         usb_queue_reset_device(tp->intf);
2439 }
2440
2441 static void rtl8152_set_rx_mode(struct net_device *netdev)
2442 {
2443         struct r8152 *tp = netdev_priv(netdev);
2444
2445         if (netif_carrier_ok(netdev)) {
2446                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2447                 schedule_delayed_work(&tp->schedule, 0);
2448         }
2449 }
2450
2451 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2452 {
2453         struct r8152 *tp = netdev_priv(netdev);
2454         u32 mc_filter[2];       /* Multicast hash filter */
2455         __le32 tmp[2];
2456         u32 ocp_data;
2457
2458         netif_stop_queue(netdev);
2459         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2460         ocp_data &= ~RCR_ACPT_ALL;
2461         ocp_data |= RCR_AB | RCR_APM;
2462
2463         if (netdev->flags & IFF_PROMISC) {
2464                 /* Unconditionally log net taps. */
2465                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2466                 ocp_data |= RCR_AM | RCR_AAP;
2467                 mc_filter[1] = 0xffffffff;
2468                 mc_filter[0] = 0xffffffff;
2469         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2470                    (netdev->flags & IFF_ALLMULTI)) {
2471                 /* Too many to filter perfectly -- accept all multicasts. */
2472                 ocp_data |= RCR_AM;
2473                 mc_filter[1] = 0xffffffff;
2474                 mc_filter[0] = 0xffffffff;
2475         } else {
2476                 struct netdev_hw_addr *ha;
2477
2478                 mc_filter[1] = 0;
2479                 mc_filter[0] = 0;
2480                 netdev_for_each_mc_addr(ha, netdev) {
2481                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2482
2483                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2484                         ocp_data |= RCR_AM;
2485                 }
2486         }
2487
2488         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2489         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2490
2491         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2492         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2493         netif_wake_queue(netdev);
2494 }
2495
2496 static netdev_features_t
2497 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2498                        netdev_features_t features)
2499 {
2500         u32 mss = skb_shinfo(skb)->gso_size;
2501         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2502         int offset = skb_transport_offset(skb);
2503
2504         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2505                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2506         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2507                 features &= ~NETIF_F_GSO_MASK;
2508
2509         return features;
2510 }
2511
2512 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2513                                       struct net_device *netdev)
2514 {
2515         struct r8152 *tp = netdev_priv(netdev);
2516
2517         skb_tx_timestamp(skb);
2518
2519         skb_queue_tail(&tp->tx_queue, skb);
2520
2521         if (!list_empty(&tp->tx_free)) {
2522                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2523                         set_bit(SCHEDULE_TASKLET, &tp->flags);
2524                         schedule_delayed_work(&tp->schedule, 0);
2525                 } else {
2526                         usb_mark_last_busy(tp->udev);
2527                         tasklet_schedule(&tp->tx_tl);
2528                 }
2529         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2530                 netif_stop_queue(netdev);
2531         }
2532
2533         return NETDEV_TX_OK;
2534 }
2535
2536 static void r8152b_reset_packet_filter(struct r8152 *tp)
2537 {
2538         u32     ocp_data;
2539
2540         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2541         ocp_data &= ~FMC_FCR_MCU_EN;
2542         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2543         ocp_data |= FMC_FCR_MCU_EN;
2544         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2545 }
2546
2547 static void rtl8152_nic_reset(struct r8152 *tp)
2548 {
2549         int     i;
2550
2551         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2552
2553         for (i = 0; i < 1000; i++) {
2554                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2555                         break;
2556                 usleep_range(100, 400);
2557         }
2558 }
2559
2560 static void set_tx_qlen(struct r8152 *tp)
2561 {
2562         struct net_device *netdev = tp->netdev;
2563
2564         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2565                                     sizeof(struct tx_desc));
2566 }
2567
2568 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2569 {
2570         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2571 }
2572
2573 static void rtl_set_eee_plus(struct r8152 *tp)
2574 {
2575         u32 ocp_data;
2576         u8 speed;
2577
2578         speed = rtl8152_get_speed(tp);
2579         if (speed & _10bps) {
2580                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2581                 ocp_data |= EEEP_CR_EEEP_TX;
2582                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2583         } else {
2584                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2585                 ocp_data &= ~EEEP_CR_EEEP_TX;
2586                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2587         }
2588 }
2589
2590 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2591 {
2592         u32 ocp_data;
2593
2594         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2595         if (enable)
2596                 ocp_data |= RXDY_GATED_EN;
2597         else
2598                 ocp_data &= ~RXDY_GATED_EN;
2599         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2600 }
2601
2602 static int rtl_start_rx(struct r8152 *tp)
2603 {
2604         struct rx_agg *agg, *agg_next;
2605         struct list_head tmp_list;
2606         unsigned long flags;
2607         int ret = 0, i = 0;
2608
2609         INIT_LIST_HEAD(&tmp_list);
2610
2611         spin_lock_irqsave(&tp->rx_lock, flags);
2612
2613         INIT_LIST_HEAD(&tp->rx_done);
2614         INIT_LIST_HEAD(&tp->rx_used);
2615
2616         list_splice_init(&tp->rx_info, &tmp_list);
2617
2618         spin_unlock_irqrestore(&tp->rx_lock, flags);
2619
2620         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2621                 INIT_LIST_HEAD(&agg->list);
2622
2623                 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2624                 if (++i > RTL8152_MAX_RX) {
2625                         spin_lock_irqsave(&tp->rx_lock, flags);
2626                         list_add_tail(&agg->list, &tp->rx_used);
2627                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2628                 } else if (unlikely(ret < 0)) {
2629                         spin_lock_irqsave(&tp->rx_lock, flags);
2630                         list_add_tail(&agg->list, &tp->rx_done);
2631                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2632                 } else {
2633                         ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2634                 }
2635         }
2636
2637         spin_lock_irqsave(&tp->rx_lock, flags);
2638         WARN_ON(!list_empty(&tp->rx_info));
2639         list_splice(&tmp_list, &tp->rx_info);
2640         spin_unlock_irqrestore(&tp->rx_lock, flags);
2641
2642         return ret;
2643 }
2644
2645 static int rtl_stop_rx(struct r8152 *tp)
2646 {
2647         struct rx_agg *agg, *agg_next;
2648         struct list_head tmp_list;
2649         unsigned long flags;
2650
2651         INIT_LIST_HEAD(&tmp_list);
2652
2653         /* The usb_kill_urb() couldn't be used in atomic.
2654          * Therefore, move the list of rx_info to a tmp one.
2655          * Then, list_for_each_entry_safe could be used without
2656          * spin lock.
2657          */
2658
2659         spin_lock_irqsave(&tp->rx_lock, flags);
2660         list_splice_init(&tp->rx_info, &tmp_list);
2661         spin_unlock_irqrestore(&tp->rx_lock, flags);
2662
2663         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2664                 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2665                  * equal to 1, so the other ones could be freed safely.
2666                  */
2667                 if (page_count(agg->page) > 1)
2668                         free_rx_agg(tp, agg);
2669                 else
2670                         usb_kill_urb(agg->urb);
2671         }
2672
2673         /* Move back the list of temp to the rx_info */
2674         spin_lock_irqsave(&tp->rx_lock, flags);
2675         WARN_ON(!list_empty(&tp->rx_info));
2676         list_splice(&tmp_list, &tp->rx_info);
2677         spin_unlock_irqrestore(&tp->rx_lock, flags);
2678
2679         while (!skb_queue_empty(&tp->rx_queue))
2680                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2681
2682         return 0;
2683 }
2684
2685 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2686 {
2687         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2688                        OWN_UPDATE | OWN_CLEAR);
2689 }
2690
2691 static int rtl_enable(struct r8152 *tp)
2692 {
2693         u32 ocp_data;
2694
2695         r8152b_reset_packet_filter(tp);
2696
2697         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2698         ocp_data |= CR_RE | CR_TE;
2699         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2700
2701         switch (tp->version) {
2702         case RTL_VER_08:
2703         case RTL_VER_09:
2704                 r8153b_rx_agg_chg_indicate(tp);
2705                 break;
2706         default:
2707                 break;
2708         }
2709
2710         rxdy_gated_en(tp, false);
2711
2712         return 0;
2713 }
2714
2715 static int rtl8152_enable(struct r8152 *tp)
2716 {
2717         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2718                 return -ENODEV;
2719
2720         set_tx_qlen(tp);
2721         rtl_set_eee_plus(tp);
2722
2723         return rtl_enable(tp);
2724 }
2725
2726 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2727 {
2728         u32 ocp_data = tp->coalesce / 8;
2729
2730         switch (tp->version) {
2731         case RTL_VER_03:
2732         case RTL_VER_04:
2733         case RTL_VER_05:
2734         case RTL_VER_06:
2735                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2736                                ocp_data);
2737                 break;
2738
2739         case RTL_VER_08:
2740         case RTL_VER_09:
2741                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2742                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2743                  */
2744                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2745                                128 / 8);
2746                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2747                                ocp_data);
2748                 break;
2749
2750         default:
2751                 break;
2752         }
2753 }
2754
2755 static void r8153_set_rx_early_size(struct r8152 *tp)
2756 {
2757         u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2758
2759         switch (tp->version) {
2760         case RTL_VER_03:
2761         case RTL_VER_04:
2762         case RTL_VER_05:
2763         case RTL_VER_06:
2764                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2765                                ocp_data / 4);
2766                 break;
2767         case RTL_VER_08:
2768         case RTL_VER_09:
2769                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2770                                ocp_data / 8);
2771                 break;
2772         default:
2773                 WARN_ON_ONCE(1);
2774                 break;
2775         }
2776 }
2777
2778 static int rtl8153_enable(struct r8152 *tp)
2779 {
2780         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2781                 return -ENODEV;
2782
2783         set_tx_qlen(tp);
2784         rtl_set_eee_plus(tp);
2785         r8153_set_rx_early_timeout(tp);
2786         r8153_set_rx_early_size(tp);
2787
2788         return rtl_enable(tp);
2789 }
2790
2791 static void rtl_disable(struct r8152 *tp)
2792 {
2793         u32 ocp_data;
2794         int i;
2795
2796         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2797                 rtl_drop_queued_tx(tp);
2798                 return;
2799         }
2800
2801         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2802         ocp_data &= ~RCR_ACPT_ALL;
2803         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2804
2805         rtl_drop_queued_tx(tp);
2806
2807         for (i = 0; i < RTL8152_MAX_TX; i++)
2808                 usb_kill_urb(tp->tx_info[i].urb);
2809
2810         rxdy_gated_en(tp, true);
2811
2812         for (i = 0; i < 1000; i++) {
2813                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2814                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2815                         break;
2816                 usleep_range(1000, 2000);
2817         }
2818
2819         for (i = 0; i < 1000; i++) {
2820                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2821                         break;
2822                 usleep_range(1000, 2000);
2823         }
2824
2825         rtl_stop_rx(tp);
2826
2827         rtl8152_nic_reset(tp);
2828 }
2829
2830 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2831 {
2832         u32 ocp_data;
2833
2834         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2835         if (enable)
2836                 ocp_data |= POWER_CUT;
2837         else
2838                 ocp_data &= ~POWER_CUT;
2839         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2840
2841         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2842         ocp_data &= ~RESUME_INDICATE;
2843         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2844 }
2845
2846 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2847 {
2848         u32 ocp_data;
2849
2850         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2851         if (enable)
2852                 ocp_data |= CPCR_RX_VLAN;
2853         else
2854                 ocp_data &= ~CPCR_RX_VLAN;
2855         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2856 }
2857
2858 static int rtl8152_set_features(struct net_device *dev,
2859                                 netdev_features_t features)
2860 {
2861         netdev_features_t changed = features ^ dev->features;
2862         struct r8152 *tp = netdev_priv(dev);
2863         int ret;
2864
2865         ret = usb_autopm_get_interface(tp->intf);
2866         if (ret < 0)
2867                 goto out;
2868
2869         mutex_lock(&tp->control);
2870
2871         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2872                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2873                         rtl_rx_vlan_en(tp, true);
2874                 else
2875                         rtl_rx_vlan_en(tp, false);
2876         }
2877
2878         mutex_unlock(&tp->control);
2879
2880         usb_autopm_put_interface(tp->intf);
2881
2882 out:
2883         return ret;
2884 }
2885
2886 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2887
2888 static u32 __rtl_get_wol(struct r8152 *tp)
2889 {
2890         u32 ocp_data;
2891         u32 wolopts = 0;
2892
2893         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2894         if (ocp_data & LINK_ON_WAKE_EN)
2895                 wolopts |= WAKE_PHY;
2896
2897         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2898         if (ocp_data & UWF_EN)
2899                 wolopts |= WAKE_UCAST;
2900         if (ocp_data & BWF_EN)
2901                 wolopts |= WAKE_BCAST;
2902         if (ocp_data & MWF_EN)
2903                 wolopts |= WAKE_MCAST;
2904
2905         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2906         if (ocp_data & MAGIC_EN)
2907                 wolopts |= WAKE_MAGIC;
2908
2909         return wolopts;
2910 }
2911
2912 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2913 {
2914         u32 ocp_data;
2915
2916         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2917
2918         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2919         ocp_data &= ~LINK_ON_WAKE_EN;
2920         if (wolopts & WAKE_PHY)
2921                 ocp_data |= LINK_ON_WAKE_EN;
2922         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2923
2924         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2925         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2926         if (wolopts & WAKE_UCAST)
2927                 ocp_data |= UWF_EN;
2928         if (wolopts & WAKE_BCAST)
2929                 ocp_data |= BWF_EN;
2930         if (wolopts & WAKE_MCAST)
2931                 ocp_data |= MWF_EN;
2932         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2933
2934         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2935
2936         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2937         ocp_data &= ~MAGIC_EN;
2938         if (wolopts & WAKE_MAGIC)
2939                 ocp_data |= MAGIC_EN;
2940         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2941
2942         if (wolopts & WAKE_ANY)
2943                 device_set_wakeup_enable(&tp->udev->dev, true);
2944         else
2945                 device_set_wakeup_enable(&tp->udev->dev, false);
2946 }
2947
2948 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2949 {
2950         /* MAC clock speed down */
2951         if (enable) {
2952                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2953                                ALDPS_SPDWN_RATIO);
2954                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2955                                EEE_SPDWN_RATIO);
2956                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2957                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2958                                U1U2_SPDWN_EN | L1_SPDWN_EN);
2959                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2960                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2961                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2962                                TP1000_SPDWN_EN);
2963         } else {
2964                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2965                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2966                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2967                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2968         }
2969 }
2970
2971 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2972 {
2973         u8 u1u2[8];
2974
2975         if (enable)
2976                 memset(u1u2, 0xff, sizeof(u1u2));
2977         else
2978                 memset(u1u2, 0x00, sizeof(u1u2));
2979
2980         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2981 }
2982
2983 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2984 {
2985         u32 ocp_data;
2986
2987         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2988         if (enable)
2989                 ocp_data |= LPM_U1U2_EN;
2990         else
2991                 ocp_data &= ~LPM_U1U2_EN;
2992
2993         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2994 }
2995
2996 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2997 {
2998         u32 ocp_data;
2999
3000         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3001         if (enable)
3002                 ocp_data |= U2P3_ENABLE;
3003         else
3004                 ocp_data &= ~U2P3_ENABLE;
3005         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3006 }
3007
3008 static void r8153b_ups_flags(struct r8152 *tp)
3009 {
3010         u32 ups_flags = 0;
3011
3012         if (tp->ups_info.green)
3013                 ups_flags |= UPS_FLAGS_EN_GREEN;
3014
3015         if (tp->ups_info.aldps)
3016                 ups_flags |= UPS_FLAGS_EN_ALDPS;
3017
3018         if (tp->ups_info.eee)
3019                 ups_flags |= UPS_FLAGS_EN_EEE;
3020
3021         if (tp->ups_info.flow_control)
3022                 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3023
3024         if (tp->ups_info.eee_ckdiv)
3025                 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3026
3027         if (tp->ups_info.eee_cmod_lv)
3028                 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3029
3030         if (tp->ups_info._10m_ckdiv)
3031                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3032
3033         if (tp->ups_info.eee_plloff_100)
3034                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3035
3036         if (tp->ups_info.eee_plloff_giga)
3037                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3038
3039         if (tp->ups_info._250m_ckdiv)
3040                 ups_flags |= UPS_FLAGS_250M_CKDIV;
3041
3042         if (tp->ups_info.ctap_short_off)
3043                 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3044
3045         switch (tp->ups_info.speed_duplex) {
3046         case NWAY_10M_HALF:
3047                 ups_flags |= ups_flags_speed(1);
3048                 break;
3049         case NWAY_10M_FULL:
3050                 ups_flags |= ups_flags_speed(2);
3051                 break;
3052         case NWAY_100M_HALF:
3053                 ups_flags |= ups_flags_speed(3);
3054                 break;
3055         case NWAY_100M_FULL:
3056                 ups_flags |= ups_flags_speed(4);
3057                 break;
3058         case NWAY_1000M_FULL:
3059                 ups_flags |= ups_flags_speed(5);
3060                 break;
3061         case FORCE_10M_HALF:
3062                 ups_flags |= ups_flags_speed(6);
3063                 break;
3064         case FORCE_10M_FULL:
3065                 ups_flags |= ups_flags_speed(7);
3066                 break;
3067         case FORCE_100M_HALF:
3068                 ups_flags |= ups_flags_speed(8);
3069                 break;
3070         case FORCE_100M_FULL:
3071                 ups_flags |= ups_flags_speed(9);
3072                 break;
3073         default:
3074                 break;
3075         }
3076
3077         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3078 }
3079
3080 static void r8153b_green_en(struct r8152 *tp, bool enable)
3081 {
3082         u16 data;
3083
3084         if (enable) {
3085                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
3086                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3087                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3088         } else {
3089                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3090                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3091                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3092         }
3093
3094         data = sram_read(tp, SRAM_GREEN_CFG);
3095         data |= GREEN_ETH_EN;
3096         sram_write(tp, SRAM_GREEN_CFG, data);
3097
3098         tp->ups_info.green = enable;
3099 }
3100
3101 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3102 {
3103         u16 data;
3104         int i;
3105
3106         for (i = 0; i < 500; i++) {
3107                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3108                 data &= PHY_STAT_MASK;
3109                 if (desired) {
3110                         if (data == desired)
3111                                 break;
3112                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3113                            data == PHY_STAT_EXT_INIT) {
3114                         break;
3115                 }
3116
3117                 msleep(20);
3118         }
3119
3120         return data;
3121 }
3122
3123 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3124 {
3125         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3126
3127         if (enable) {
3128                 r8153b_ups_flags(tp);
3129
3130                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3131                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3132
3133                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3134                 ocp_data |= BIT(0);
3135                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3136         } else {
3137                 u16 data;
3138
3139                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3140                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3141
3142                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3143                 ocp_data &= ~BIT(0);
3144                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3145
3146                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3147                 ocp_data &= ~PCUT_STATUS;
3148                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3149
3150                 data = r8153_phy_status(tp, 0);
3151
3152                 switch (data) {
3153                 case PHY_STAT_PWRDN:
3154                 case PHY_STAT_EXT_INIT:
3155                         r8153b_green_en(tp,
3156                                         test_bit(GREEN_ETHERNET, &tp->flags));
3157
3158                         data = r8152_mdio_read(tp, MII_BMCR);
3159                         data &= ~BMCR_PDOWN;
3160                         data |= BMCR_RESET;
3161                         r8152_mdio_write(tp, MII_BMCR, data);
3162
3163                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3164                         /* fall through */
3165
3166                 default:
3167                         if (data != PHY_STAT_LAN_ON)
3168                                 netif_warn(tp, link, tp->netdev,
3169                                            "PHY not ready");
3170                         break;
3171                 }
3172         }
3173 }
3174
3175 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3176 {
3177         u32 ocp_data;
3178
3179         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3180         if (enable)
3181                 ocp_data |= PWR_EN | PHASE2_EN;
3182         else
3183                 ocp_data &= ~(PWR_EN | PHASE2_EN);
3184         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3185
3186         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3187         ocp_data &= ~PCUT_STATUS;
3188         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3189 }
3190
3191 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3192 {
3193         u32 ocp_data;
3194
3195         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3196         if (enable)
3197                 ocp_data |= PWR_EN | PHASE2_EN;
3198         else
3199                 ocp_data &= ~PWR_EN;
3200         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3201
3202         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3203         ocp_data &= ~PCUT_STATUS;
3204         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3205 }
3206
3207 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3208 {
3209         u32 ocp_data;
3210
3211         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3212         if (enable)
3213                 ocp_data |= UPCOMING_RUNTIME_D3;
3214         else
3215                 ocp_data &= ~UPCOMING_RUNTIME_D3;
3216         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3217
3218         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3219         ocp_data &= ~LINK_CHG_EVENT;
3220         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3221
3222         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3223         ocp_data &= ~LINK_CHANGE_FLAG;
3224         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3225 }
3226
3227 static bool rtl_can_wakeup(struct r8152 *tp)
3228 {
3229         struct usb_device *udev = tp->udev;
3230
3231         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3232 }
3233
3234 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3235 {
3236         if (enable) {
3237                 u32 ocp_data;
3238
3239                 __rtl_set_wol(tp, WAKE_ANY);
3240
3241                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3242
3243                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3244                 ocp_data |= LINK_OFF_WAKE_EN;
3245                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3246
3247                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3248         } else {
3249                 u32 ocp_data;
3250
3251                 __rtl_set_wol(tp, tp->saved_wolopts);
3252
3253                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3254
3255                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3256                 ocp_data &= ~LINK_OFF_WAKE_EN;
3257                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3258
3259                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3260         }
3261 }
3262
3263 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3264 {
3265         if (enable) {
3266                 r8153_u1u2en(tp, false);
3267                 r8153_u2p3en(tp, false);
3268                 r8153_mac_clk_spd(tp, true);
3269                 rtl_runtime_suspend_enable(tp, true);
3270         } else {
3271                 rtl_runtime_suspend_enable(tp, false);
3272                 r8153_mac_clk_spd(tp, false);
3273
3274                 switch (tp->version) {
3275                 case RTL_VER_03:
3276                 case RTL_VER_04:
3277                         break;
3278                 case RTL_VER_05:
3279                 case RTL_VER_06:
3280                 default:
3281                         r8153_u2p3en(tp, true);
3282                         break;
3283                 }
3284
3285                 r8153_u1u2en(tp, true);
3286         }
3287 }
3288
3289 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3290 {
3291         if (enable) {
3292                 r8153_queue_wake(tp, true);
3293                 r8153b_u1u2en(tp, false);
3294                 r8153_u2p3en(tp, false);
3295                 rtl_runtime_suspend_enable(tp, true);
3296                 r8153b_ups_en(tp, true);
3297         } else {
3298                 r8153b_ups_en(tp, false);
3299                 r8153_queue_wake(tp, false);
3300                 rtl_runtime_suspend_enable(tp, false);
3301                 r8153_u2p3en(tp, true);
3302                 r8153b_u1u2en(tp, true);
3303         }
3304 }
3305
3306 static void r8153_teredo_off(struct r8152 *tp)
3307 {
3308         u32 ocp_data;
3309
3310         switch (tp->version) {
3311         case RTL_VER_01:
3312         case RTL_VER_02:
3313         case RTL_VER_03:
3314         case RTL_VER_04:
3315         case RTL_VER_05:
3316         case RTL_VER_06:
3317         case RTL_VER_07:
3318                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3319                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3320                               OOB_TEREDO_EN);
3321                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3322                 break;
3323
3324         case RTL_VER_08:
3325         case RTL_VER_09:
3326                 /* The bit 0 ~ 7 are relative with teredo settings. They are
3327                  * W1C (write 1 to clear), so set all 1 to disable it.
3328                  */
3329                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3330                 break;
3331
3332         default:
3333                 break;
3334         }
3335
3336         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3337         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3338         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3339 }
3340
3341 static void rtl_reset_bmu(struct r8152 *tp)
3342 {
3343         u32 ocp_data;
3344
3345         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3346         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3347         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3348         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3349         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3350 }
3351
3352 /* Clear the bp to stop the firmware before loading a new one */
3353 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3354 {
3355         switch (tp->version) {
3356         case RTL_VER_01:
3357         case RTL_VER_02:
3358         case RTL_VER_07:
3359                 break;
3360         case RTL_VER_03:
3361         case RTL_VER_04:
3362         case RTL_VER_05:
3363         case RTL_VER_06:
3364                 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3365                 break;
3366         case RTL_VER_08:
3367         case RTL_VER_09:
3368         default:
3369                 if (type == MCU_TYPE_USB) {
3370                         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3371
3372                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3373                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3374                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3375                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3376                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3377                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3378                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3379                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3380                 } else {
3381                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3382                 }
3383                 break;
3384         }
3385
3386         ocp_write_word(tp, type, PLA_BP_0, 0);
3387         ocp_write_word(tp, type, PLA_BP_1, 0);
3388         ocp_write_word(tp, type, PLA_BP_2, 0);
3389         ocp_write_word(tp, type, PLA_BP_3, 0);
3390         ocp_write_word(tp, type, PLA_BP_4, 0);
3391         ocp_write_word(tp, type, PLA_BP_5, 0);
3392         ocp_write_word(tp, type, PLA_BP_6, 0);
3393         ocp_write_word(tp, type, PLA_BP_7, 0);
3394
3395         /* wait 3 ms to make sure the firmware is stopped */
3396         usleep_range(3000, 6000);
3397         ocp_write_word(tp, type, PLA_BP_BA, 0);
3398 }
3399
3400 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3401 {
3402         u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3403         bool rc = false;
3404         u32 length, type;
3405         int i, max_bp;
3406
3407         type = __le32_to_cpu(mac->blk_hdr.type);
3408         if (type == RTL_FW_PLA) {
3409                 switch (tp->version) {
3410                 case RTL_VER_01:
3411                 case RTL_VER_02:
3412                 case RTL_VER_07:
3413                         fw_reg = 0xf800;
3414                         bp_ba_addr = PLA_BP_BA;
3415                         bp_en_addr = 0;
3416                         bp_start = PLA_BP_0;
3417                         max_bp = 8;
3418                         break;
3419                 case RTL_VER_03:
3420                 case RTL_VER_04:
3421                 case RTL_VER_05:
3422                 case RTL_VER_06:
3423                 case RTL_VER_08:
3424                 case RTL_VER_09:
3425                         fw_reg = 0xf800;
3426                         bp_ba_addr = PLA_BP_BA;
3427                         bp_en_addr = PLA_BP_EN;
3428                         bp_start = PLA_BP_0;
3429                         max_bp = 8;
3430                         break;
3431                 default:
3432                         goto out;
3433                 }
3434         } else if (type == RTL_FW_USB) {
3435                 switch (tp->version) {
3436                 case RTL_VER_03:
3437                 case RTL_VER_04:
3438                 case RTL_VER_05:
3439                 case RTL_VER_06:
3440                         fw_reg = 0xf800;
3441                         bp_ba_addr = USB_BP_BA;
3442                         bp_en_addr = USB_BP_EN;
3443                         bp_start = USB_BP_0;
3444                         max_bp = 8;
3445                         break;
3446                 case RTL_VER_08:
3447                 case RTL_VER_09:
3448                         fw_reg = 0xe600;
3449                         bp_ba_addr = USB_BP_BA;
3450                         bp_en_addr = USB_BP2_EN;
3451                         bp_start = USB_BP_0;
3452                         max_bp = 16;
3453                         break;
3454                 case RTL_VER_01:
3455                 case RTL_VER_02:
3456                 case RTL_VER_07:
3457                 default:
3458                         goto out;
3459                 }
3460         } else {
3461                 goto out;
3462         }
3463
3464         fw_offset = __le16_to_cpu(mac->fw_offset);
3465         if (fw_offset < sizeof(*mac)) {
3466                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3467                 goto out;
3468         }
3469
3470         length = __le32_to_cpu(mac->blk_hdr.length);
3471         if (length < fw_offset) {
3472                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3473                 goto out;
3474         }
3475
3476         length -= fw_offset;
3477         if (length < 4 || (length & 3)) {
3478                 dev_err(&tp->intf->dev, "invalid block length\n");
3479                 goto out;
3480         }
3481
3482         if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3483                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3484                 goto out;
3485         }
3486
3487         if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3488                 dev_err(&tp->intf->dev, "invalid base address register\n");
3489                 goto out;
3490         }
3491
3492         if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3493                 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3494                 goto out;
3495         }
3496
3497         if (__le16_to_cpu(mac->bp_start) != bp_start) {
3498                 dev_err(&tp->intf->dev,
3499                         "invalid start register of break point\n");
3500                 goto out;
3501         }
3502
3503         if (__le16_to_cpu(mac->bp_num) > max_bp) {
3504                 dev_err(&tp->intf->dev, "invalid break point number\n");
3505                 goto out;
3506         }
3507
3508         for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3509                 if (mac->bp[i]) {
3510                         dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3511                         goto out;
3512                 }
3513         }
3514
3515         rc = true;
3516 out:
3517         return rc;
3518 }
3519
3520 /* Verify the checksum for the firmware file. It is calculated from the version
3521  * field to the end of the file. Compare the result with the checksum field to
3522  * make sure the file is correct.
3523  */
3524 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3525                                        struct fw_header *fw_hdr, size_t size)
3526 {
3527         unsigned char checksum[sizeof(fw_hdr->checksum)];
3528         struct crypto_shash *alg;
3529         struct shash_desc *sdesc;
3530         size_t len;
3531         long rc;
3532
3533         alg = crypto_alloc_shash("sha256", 0, 0);
3534         if (IS_ERR(alg)) {
3535                 rc = PTR_ERR(alg);
3536                 goto out;
3537         }
3538
3539         if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3540                 rc = -EFAULT;
3541                 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3542                         crypto_shash_digestsize(alg));
3543                 goto free_shash;
3544         }
3545
3546         len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3547         sdesc = kmalloc(len, GFP_KERNEL);
3548         if (!sdesc) {
3549                 rc = -ENOMEM;
3550                 goto free_shash;
3551         }
3552         sdesc->tfm = alg;
3553
3554         len = size - sizeof(fw_hdr->checksum);
3555         rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3556         kfree(sdesc);
3557         if (rc)
3558                 goto free_shash;
3559
3560         if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3561                 dev_err(&tp->intf->dev, "checksum fail\n");
3562                 rc = -EFAULT;
3563         }
3564
3565 free_shash:
3566         crypto_free_shash(alg);
3567 out:
3568         return rc;
3569 }
3570
3571 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3572 {
3573         const struct firmware *fw = rtl_fw->fw;
3574         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3575         struct fw_mac *pla = NULL, *usb = NULL;
3576         long ret = -EFAULT;
3577         int i;
3578
3579         if (fw->size < sizeof(*fw_hdr)) {
3580                 dev_err(&tp->intf->dev, "file too small\n");
3581                 goto fail;
3582         }
3583
3584         ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3585         if (ret)
3586                 goto fail;
3587
3588         ret = -EFAULT;
3589
3590         for (i = sizeof(*fw_hdr); i < fw->size;) {
3591                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3592                 u32 type;
3593
3594                 if ((i + sizeof(*block)) > fw->size)
3595                         goto fail;
3596
3597                 type = __le32_to_cpu(block->type);
3598                 switch (type) {
3599                 case RTL_FW_END:
3600                         if (__le32_to_cpu(block->length) != sizeof(*block))
3601                                 goto fail;
3602                         goto success;
3603                 case RTL_FW_PLA:
3604                         if (pla) {
3605                                 dev_err(&tp->intf->dev,
3606                                         "multiple PLA firmware encountered");
3607                                 goto fail;
3608                         }
3609
3610                         pla = (struct fw_mac *)block;
3611                         if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3612                                 dev_err(&tp->intf->dev,
3613                                         "check PLA firmware failed\n");
3614                                 goto fail;
3615                         }
3616                         break;
3617                 case RTL_FW_USB:
3618                         if (usb) {
3619                                 dev_err(&tp->intf->dev,
3620                                         "multiple USB firmware encountered");
3621                                 goto fail;
3622                         }
3623
3624                         usb = (struct fw_mac *)block;
3625                         if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3626                                 dev_err(&tp->intf->dev,
3627                                         "check USB firmware failed\n");
3628                                 goto fail;
3629                         }
3630                         break;
3631                 default:
3632                         dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3633                                  type);
3634                         break;
3635                 }
3636
3637                 /* next block */
3638                 i += ALIGN(__le32_to_cpu(block->length), 8);
3639         }
3640
3641 success:
3642         return 0;
3643 fail:
3644         return ret;
3645 }
3646
3647 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3648 {
3649         u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3650         u32 length;
3651         u8 *data;
3652         int i;
3653
3654         switch (__le32_to_cpu(mac->blk_hdr.type)) {
3655         case RTL_FW_PLA:
3656                 type = MCU_TYPE_PLA;
3657                 break;
3658         case RTL_FW_USB:
3659                 type = MCU_TYPE_USB;
3660                 break;
3661         default:
3662                 return;
3663         }
3664
3665         rtl_clear_bp(tp, type);
3666
3667         /* Enable backup/restore of MACDBG. This is required after clearing PLA
3668          * break points and before applying the PLA firmware.
3669          */
3670         if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3671             !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3672                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3673                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3674         }
3675
3676         length = __le32_to_cpu(mac->blk_hdr.length);
3677         length -= __le16_to_cpu(mac->fw_offset);
3678
3679         data = (u8 *)mac;
3680         data += __le16_to_cpu(mac->fw_offset);
3681
3682         generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3683                           type);
3684
3685         ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3686                        __le16_to_cpu(mac->bp_ba_value));
3687
3688         bp_index = __le16_to_cpu(mac->bp_start);
3689         bp_num = __le16_to_cpu(mac->bp_num);
3690         for (i = 0; i < bp_num; i++) {
3691                 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3692                 bp_index += 2;
3693         }
3694
3695         bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3696         if (bp_en_addr)
3697                 ocp_write_word(tp, type, bp_en_addr,
3698                                __le16_to_cpu(mac->bp_en_value));
3699
3700         fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
3701         if (fw_ver_reg)
3702                 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
3703                                mac->fw_ver_data);
3704
3705         dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
3706 }
3707
3708 static void rtl8152_apply_firmware(struct r8152 *tp)
3709 {
3710         struct rtl_fw *rtl_fw = &tp->rtl_fw;
3711         const struct firmware *fw = rtl_fw->fw;
3712         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3713         int i;
3714
3715         if (IS_ERR_OR_NULL(rtl_fw->fw))
3716                 return;
3717
3718         if (rtl_fw->pre_fw)
3719                 rtl_fw->pre_fw(tp);
3720
3721         for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
3722                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3723
3724                 switch (__le32_to_cpu(block->type)) {
3725                 case RTL_FW_END:
3726                         goto post_fw;
3727                 case RTL_FW_PLA:
3728                 case RTL_FW_USB:
3729                         rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
3730                         break;
3731                 default:
3732                         break;
3733                 }
3734
3735                 i += ALIGN(__le32_to_cpu(block->length), 8);
3736         }
3737
3738 post_fw:
3739         if (rtl_fw->post_fw)
3740                 rtl_fw->post_fw(tp);
3741
3742         strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
3743         dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
3744 }
3745
3746 static void rtl8152_release_firmware(struct r8152 *tp)
3747 {
3748         struct rtl_fw *rtl_fw = &tp->rtl_fw;
3749
3750         if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
3751                 release_firmware(rtl_fw->fw);
3752                 rtl_fw->fw = NULL;
3753         }
3754 }
3755
3756 static int rtl8152_request_firmware(struct r8152 *tp)
3757 {
3758         struct rtl_fw *rtl_fw = &tp->rtl_fw;
3759         long rc;
3760
3761         if (rtl_fw->fw || !rtl_fw->fw_name) {
3762                 dev_info(&tp->intf->dev, "skip request firmware\n");
3763                 rc = 0;
3764                 goto result;
3765         }
3766
3767         rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
3768         if (rc < 0)
3769                 goto result;
3770
3771         rc = rtl8152_check_firmware(tp, rtl_fw);
3772         if (rc < 0)
3773                 release_firmware(rtl_fw->fw);
3774
3775 result:
3776         if (rc) {
3777                 rtl_fw->fw = ERR_PTR(rc);
3778
3779                 dev_warn(&tp->intf->dev,
3780                          "unable to load firmware patch %s (%ld)\n",
3781                          rtl_fw->fw_name, rc);
3782         }
3783
3784         return rc;
3785 }
3786
3787 static void r8152_aldps_en(struct r8152 *tp, bool enable)
3788 {
3789         if (enable) {
3790                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
3791                                                     LINKENA | DIS_SDSAVE);
3792         } else {
3793                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
3794                                                     DIS_SDSAVE);
3795                 msleep(20);
3796         }
3797 }
3798
3799 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3800 {
3801         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3802         ocp_reg_write(tp, OCP_EEE_DATA, reg);
3803         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3804 }
3805
3806 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3807 {
3808         u16 data;
3809
3810         r8152_mmd_indirect(tp, dev, reg);
3811         data = ocp_reg_read(tp, OCP_EEE_DATA);
3812         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3813
3814         return data;
3815 }
3816
3817 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3818 {
3819         r8152_mmd_indirect(tp, dev, reg);
3820         ocp_reg_write(tp, OCP_EEE_DATA, data);
3821         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3822 }
3823
3824 static void r8152_eee_en(struct r8152 *tp, bool enable)
3825 {
3826         u16 config1, config2, config3;
3827         u32 ocp_data;
3828
3829         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3830         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3831         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3832         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3833
3834         if (enable) {
3835                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3836                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3837                 config1 |= sd_rise_time(1);
3838                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3839                 config3 |= fast_snr(42);
3840         } else {
3841                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3842                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3843                              RX_QUIET_EN);
3844                 config1 |= sd_rise_time(7);
3845                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3846                 config3 |= fast_snr(511);
3847         }
3848
3849         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3850         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3851         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3852         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3853 }
3854
3855 static void r8153_eee_en(struct r8152 *tp, bool enable)
3856 {
3857         u32 ocp_data;
3858         u16 config;
3859
3860         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3861         config = ocp_reg_read(tp, OCP_EEE_CFG);
3862
3863         if (enable) {
3864                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3865                 config |= EEE10_EN;
3866         } else {
3867                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3868                 config &= ~EEE10_EN;
3869         }
3870
3871         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3872         ocp_reg_write(tp, OCP_EEE_CFG, config);
3873
3874         tp->ups_info.eee = enable;
3875 }
3876
3877 static void rtl_eee_enable(struct r8152 *tp, bool enable)
3878 {
3879         switch (tp->version) {
3880         case RTL_VER_01:
3881         case RTL_VER_02:
3882         case RTL_VER_07:
3883                 if (enable) {
3884                         r8152_eee_en(tp, true);
3885                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
3886                                         tp->eee_adv);
3887                 } else {
3888                         r8152_eee_en(tp, false);
3889                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
3890                 }
3891                 break;
3892         case RTL_VER_03:
3893         case RTL_VER_04:
3894         case RTL_VER_05:
3895         case RTL_VER_06:
3896         case RTL_VER_08:
3897         case RTL_VER_09:
3898                 if (enable) {
3899                         r8153_eee_en(tp, true);
3900                         ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
3901                 } else {
3902                         r8153_eee_en(tp, false);
3903                         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3904                 }
3905                 break;
3906         default:
3907                 break;
3908         }
3909 }
3910
3911 static void r8152b_enable_fc(struct r8152 *tp)
3912 {
3913         u16 anar;
3914
3915         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3916         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3917         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3918
3919         tp->ups_info.flow_control = true;
3920 }
3921
3922 static void rtl8152_disable(struct r8152 *tp)
3923 {
3924         r8152_aldps_en(tp, false);
3925         rtl_disable(tp);
3926         r8152_aldps_en(tp, true);
3927 }
3928
3929 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3930 {
3931         rtl8152_apply_firmware(tp);
3932         rtl_eee_enable(tp, tp->eee_en);
3933         r8152_aldps_en(tp, true);
3934         r8152b_enable_fc(tp);
3935
3936         set_bit(PHY_RESET, &tp->flags);
3937 }
3938
3939 static void wait_oob_link_list_ready(struct r8152 *tp)
3940 {
3941         u32 ocp_data;
3942         int i;
3943
3944         for (i = 0; i < 1000; i++) {
3945                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3946                 if (ocp_data & LINK_LIST_READY)
3947                         break;
3948                 usleep_range(1000, 2000);
3949         }
3950 }
3951
3952 static void r8152b_exit_oob(struct r8152 *tp)
3953 {
3954         u32 ocp_data;
3955
3956         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3957         ocp_data &= ~RCR_ACPT_ALL;
3958         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3959
3960         rxdy_gated_en(tp, true);
3961         r8153_teredo_off(tp);
3962         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3963         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3964
3965         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3966         ocp_data &= ~NOW_IS_OOB;
3967         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3968
3969         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3970         ocp_data &= ~MCU_BORW_EN;
3971         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3972
3973         wait_oob_link_list_ready(tp);
3974
3975         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3976         ocp_data |= RE_INIT_LL;
3977         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3978
3979         wait_oob_link_list_ready(tp);
3980
3981         rtl8152_nic_reset(tp);
3982
3983         /* rx share fifo credit full threshold */
3984         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3985
3986         if (tp->udev->speed == USB_SPEED_FULL ||
3987             tp->udev->speed == USB_SPEED_LOW) {
3988                 /* rx share fifo credit near full threshold */
3989                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3990                                 RXFIFO_THR2_FULL);
3991                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3992                                 RXFIFO_THR3_FULL);
3993         } else {
3994                 /* rx share fifo credit near full threshold */
3995                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3996                                 RXFIFO_THR2_HIGH);
3997                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3998                                 RXFIFO_THR3_HIGH);
3999         }
4000
4001         /* TX share fifo free credit full threshold */
4002         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4003
4004         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4005         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4006         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4007                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4008
4009         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4010
4011         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4012
4013         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4014         ocp_data |= TCR0_AUTO_FIFO;
4015         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4016 }
4017
4018 static void r8152b_enter_oob(struct r8152 *tp)
4019 {
4020         u32 ocp_data;
4021
4022         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4023         ocp_data &= ~NOW_IS_OOB;
4024         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4025
4026         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4027         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4028         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4029
4030         rtl_disable(tp);
4031
4032         wait_oob_link_list_ready(tp);
4033
4034         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4035         ocp_data |= RE_INIT_LL;
4036         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4037
4038         wait_oob_link_list_ready(tp);
4039
4040         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4041
4042         rtl_rx_vlan_en(tp, true);
4043
4044         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4045         ocp_data |= ALDPS_PROXY_MODE;
4046         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4047
4048         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4049         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4050         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4051
4052         rxdy_gated_en(tp, false);
4053
4054         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4055         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4056         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4057 }
4058
4059 static int r8153_patch_request(struct r8152 *tp, bool request)
4060 {
4061         u16 data;
4062         int i;
4063
4064         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4065         if (request)
4066                 data |= PATCH_REQUEST;
4067         else
4068                 data &= ~PATCH_REQUEST;
4069         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4070
4071         for (i = 0; request && i < 5000; i++) {
4072                 usleep_range(1000, 2000);
4073                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
4074                         break;
4075         }
4076
4077         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4078                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
4079                 r8153_patch_request(tp, false);
4080                 return -ETIME;
4081         } else {
4082                 return 0;
4083         }
4084 }
4085
4086 static int r8153_pre_firmware_1(struct r8152 *tp)
4087 {
4088         int i;
4089
4090         /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4091         for (i = 0; i < 104; i++) {
4092                 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4093
4094                 if (!(ocp_data & WTD1_EN))
4095                         break;
4096                 usleep_range(1000, 2000);
4097         }
4098
4099         return 0;
4100 }
4101
4102 static int r8153_post_firmware_1(struct r8152 *tp)
4103 {
4104         /* set USB_BP_4 to support USB_SPEED_SUPER only */
4105         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4106                 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4107
4108         /* reset UPHY timer to 36 ms */
4109         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4110
4111         return 0;
4112 }
4113
4114 static int r8153_pre_firmware_2(struct r8152 *tp)
4115 {
4116         u32 ocp_data;
4117
4118         r8153_pre_firmware_1(tp);
4119
4120         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4121         ocp_data &= ~FW_FIX_SUSPEND;
4122         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4123
4124         return 0;
4125 }
4126
4127 static int r8153_post_firmware_2(struct r8152 *tp)
4128 {
4129         u32 ocp_data;
4130
4131         /* enable bp0 if support USB_SPEED_SUPER only */
4132         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4133                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4134                 ocp_data |= BIT(0);
4135                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4136         }
4137
4138         /* reset UPHY timer to 36 ms */
4139         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4140
4141         /* enable U3P3 check, set the counter to 4 */
4142         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4143
4144         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4145         ocp_data |= FW_FIX_SUSPEND;
4146         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4147
4148         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4149         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4150         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4151
4152         return 0;
4153 }
4154
4155 static int r8153_post_firmware_3(struct r8152 *tp)
4156 {
4157         u32 ocp_data;
4158
4159         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4160         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4161         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4162
4163         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4164         ocp_data |= FW_IP_RESET_EN;
4165         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4166
4167         return 0;
4168 }
4169
4170 static int r8153b_pre_firmware_1(struct r8152 *tp)
4171 {
4172         /* enable fc timer and set timer to 1 second. */
4173         ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4174                        CTRL_TIMER_EN | (1000 / 8));
4175
4176         return 0;
4177 }
4178
4179 static int r8153b_post_firmware_1(struct r8152 *tp)
4180 {
4181         u32 ocp_data;
4182
4183         /* enable bp0 for RTL8153-BND */
4184         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4185         if (ocp_data & BND_MASK) {
4186                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4187                 ocp_data |= BIT(0);
4188                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4189         }
4190
4191         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4192         ocp_data |= FLOW_CTRL_PATCH_OPT;
4193         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4194
4195         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4196         ocp_data |= FC_PATCH_TASK;
4197         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4198
4199         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4200         ocp_data |= FW_IP_RESET_EN;
4201         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4202
4203         return 0;
4204 }
4205
4206 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4207 {
4208         u16 data;
4209
4210         data = ocp_reg_read(tp, OCP_POWER_CFG);
4211         if (enable) {
4212                 data |= EN_ALDPS;
4213                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4214         } else {
4215                 int i;
4216
4217                 data &= ~EN_ALDPS;
4218                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4219                 for (i = 0; i < 20; i++) {
4220                         usleep_range(1000, 2000);
4221                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4222                                 break;
4223                 }
4224         }
4225
4226         tp->ups_info.aldps = enable;
4227 }
4228
4229 static void r8153_hw_phy_cfg(struct r8152 *tp)
4230 {
4231         u32 ocp_data;
4232         u16 data;
4233
4234         /* disable ALDPS before updating the PHY parameters */
4235         r8153_aldps_en(tp, false);
4236
4237         /* disable EEE before updating the PHY parameters */
4238         rtl_eee_enable(tp, false);
4239
4240         rtl8152_apply_firmware(tp);
4241
4242         if (tp->version == RTL_VER_03) {
4243                 data = ocp_reg_read(tp, OCP_EEE_CFG);
4244                 data &= ~CTAP_SHORT_EN;
4245                 ocp_reg_write(tp, OCP_EEE_CFG, data);
4246         }
4247
4248         data = ocp_reg_read(tp, OCP_POWER_CFG);
4249         data |= EEE_CLKDIV_EN;
4250         ocp_reg_write(tp, OCP_POWER_CFG, data);
4251
4252         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4253         data |= EN_10M_BGOFF;
4254         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4255         data = ocp_reg_read(tp, OCP_POWER_CFG);
4256         data |= EN_10M_PLLOFF;
4257         ocp_reg_write(tp, OCP_POWER_CFG, data);
4258         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4259
4260         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4261         ocp_data |= PFM_PWM_SWITCH;
4262         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4263
4264         /* Enable LPF corner auto tune */
4265         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4266
4267         /* Adjust 10M Amplitude */
4268         sram_write(tp, SRAM_10M_AMP1, 0x00af);
4269         sram_write(tp, SRAM_10M_AMP2, 0x0208);
4270
4271         if (tp->eee_en)
4272                 rtl_eee_enable(tp, true);
4273
4274         r8153_aldps_en(tp, true);
4275         r8152b_enable_fc(tp);
4276
4277         switch (tp->version) {
4278         case RTL_VER_03:
4279         case RTL_VER_04:
4280                 break;
4281         case RTL_VER_05:
4282         case RTL_VER_06:
4283         default:
4284                 r8153_u2p3en(tp, true);
4285                 break;
4286         }
4287
4288         set_bit(PHY_RESET, &tp->flags);
4289 }
4290
4291 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4292 {
4293         u32 ocp_data;
4294
4295         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4296         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4297         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
4298         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4299
4300         return ocp_data;
4301 }
4302
4303 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4304 {
4305         u32 ocp_data;
4306         u16 data;
4307
4308         /* disable ALDPS before updating the PHY parameters */
4309         r8153_aldps_en(tp, false);
4310
4311         /* disable EEE before updating the PHY parameters */
4312         rtl_eee_enable(tp, false);
4313
4314         rtl8152_apply_firmware(tp);
4315
4316         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4317
4318         data = sram_read(tp, SRAM_GREEN_CFG);
4319         data |= R_TUNE_EN;
4320         sram_write(tp, SRAM_GREEN_CFG, data);
4321         data = ocp_reg_read(tp, OCP_NCTL_CFG);
4322         data |= PGA_RETURN_EN;
4323         ocp_reg_write(tp, OCP_NCTL_CFG, data);
4324
4325         /* ADC Bias Calibration:
4326          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4327          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4328          * ADC ioffset.
4329          */
4330         ocp_data = r8152_efuse_read(tp, 0x7d);
4331         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4332         if (data != 0xffff)
4333                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4334
4335         /* ups mode tx-link-pulse timing adjustment:
4336          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4337          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4338          */
4339         ocp_data = ocp_reg_read(tp, 0xc426);
4340         ocp_data &= 0x3fff;
4341         if (ocp_data) {
4342                 u32 swr_cnt_1ms_ini;
4343
4344                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4345                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4346                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4347                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4348         }
4349
4350         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4351         ocp_data |= PFM_PWM_SWITCH;
4352         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4353
4354         /* Advnace EEE */
4355         if (!r8153_patch_request(tp, true)) {
4356                 data = ocp_reg_read(tp, OCP_POWER_CFG);
4357                 data |= EEE_CLKDIV_EN;
4358                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4359                 tp->ups_info.eee_ckdiv = true;
4360
4361                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4362                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4363                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4364                 tp->ups_info.eee_cmod_lv = true;
4365                 tp->ups_info._10m_ckdiv = true;
4366                 tp->ups_info.eee_plloff_giga = true;
4367
4368                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4369                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4370                 tp->ups_info._250m_ckdiv = true;
4371
4372                 r8153_patch_request(tp, false);
4373         }
4374
4375         if (tp->eee_en)
4376                 rtl_eee_enable(tp, true);
4377
4378         r8153_aldps_en(tp, true);
4379         r8152b_enable_fc(tp);
4380         r8153_u2p3en(tp, true);
4381
4382         set_bit(PHY_RESET, &tp->flags);
4383 }
4384
4385 static void r8153_first_init(struct r8152 *tp)
4386 {
4387         u32 ocp_data;
4388
4389         r8153_mac_clk_spd(tp, false);
4390         rxdy_gated_en(tp, true);
4391         r8153_teredo_off(tp);
4392
4393         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4394         ocp_data &= ~RCR_ACPT_ALL;
4395         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4396
4397         rtl8152_nic_reset(tp);
4398         rtl_reset_bmu(tp);
4399
4400         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4401         ocp_data &= ~NOW_IS_OOB;
4402         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4403
4404         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4405         ocp_data &= ~MCU_BORW_EN;
4406         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4407
4408         wait_oob_link_list_ready(tp);
4409
4410         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4411         ocp_data |= RE_INIT_LL;
4412         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4413
4414         wait_oob_link_list_ready(tp);
4415
4416         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4417
4418         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4419         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4420         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4421
4422         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4423         ocp_data |= TCR0_AUTO_FIFO;
4424         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4425
4426         rtl8152_nic_reset(tp);
4427
4428         /* rx share fifo credit full threshold */
4429         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4430         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4431         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4432         /* TX share fifo free credit full threshold */
4433         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4434 }
4435
4436 static void r8153_enter_oob(struct r8152 *tp)
4437 {
4438         u32 ocp_data;
4439
4440         r8153_mac_clk_spd(tp, true);
4441
4442         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4443         ocp_data &= ~NOW_IS_OOB;
4444         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4445
4446         rtl_disable(tp);
4447         rtl_reset_bmu(tp);
4448
4449         wait_oob_link_list_ready(tp);
4450
4451         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4452         ocp_data |= RE_INIT_LL;
4453         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4454
4455         wait_oob_link_list_ready(tp);
4456
4457         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4458         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4459
4460         switch (tp->version) {
4461         case RTL_VER_03:
4462         case RTL_VER_04:
4463         case RTL_VER_05:
4464         case RTL_VER_06:
4465                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4466                 ocp_data &= ~TEREDO_WAKE_MASK;
4467                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4468                 break;
4469
4470         case RTL_VER_08:
4471         case RTL_VER_09:
4472                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4473                  * type. Set it to zero. bits[7:0] are the W1C bits about
4474                  * the events. Set them to all 1 to clear them.
4475                  */
4476                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4477                 break;
4478
4479         default:
4480                 break;
4481         }
4482
4483         rtl_rx_vlan_en(tp, true);
4484
4485         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4486         ocp_data |= ALDPS_PROXY_MODE;
4487         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4488
4489         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4490         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4491         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4492
4493         rxdy_gated_en(tp, false);
4494
4495         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4496         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4497         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4498 }
4499
4500 static void rtl8153_disable(struct r8152 *tp)
4501 {
4502         r8153_aldps_en(tp, false);
4503         rtl_disable(tp);
4504         rtl_reset_bmu(tp);
4505         r8153_aldps_en(tp, true);
4506 }
4507
4508 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4509                              u32 advertising)
4510 {
4511         u16 bmcr;
4512         int ret = 0;
4513
4514         if (autoneg == AUTONEG_DISABLE) {
4515                 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4516                         return -EINVAL;
4517
4518                 switch (speed) {
4519                 case SPEED_10:
4520                         bmcr = BMCR_SPEED10;
4521                         if (duplex == DUPLEX_FULL) {
4522                                 bmcr |= BMCR_FULLDPLX;
4523                                 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4524                         } else {
4525                                 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4526                         }
4527                         break;
4528                 case SPEED_100:
4529                         bmcr = BMCR_SPEED100;
4530                         if (duplex == DUPLEX_FULL) {
4531                                 bmcr |= BMCR_FULLDPLX;
4532                                 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4533                         } else {
4534                                 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4535                         }
4536                         break;
4537                 case SPEED_1000:
4538                         if (tp->mii.supports_gmii) {
4539                                 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4540                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4541                                 break;
4542                         }
4543                         /* fall through */
4544                 default:
4545                         ret = -EINVAL;
4546                         goto out;
4547                 }
4548
4549                 if (duplex == DUPLEX_FULL)
4550                         tp->mii.full_duplex = 1;
4551                 else
4552                         tp->mii.full_duplex = 0;
4553
4554                 tp->mii.force_media = 1;
4555         } else {
4556                 u16 anar, tmp1;
4557                 u32 support;
4558
4559                 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4560                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4561
4562                 if (tp->mii.supports_gmii)
4563                         support |= RTL_ADVERTISED_1000_FULL;
4564
4565                 if (!(advertising & support))
4566                         return -EINVAL;
4567
4568                 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4569                 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4570                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
4571                 if (advertising & RTL_ADVERTISED_10_HALF) {
4572                         tmp1 |= ADVERTISE_10HALF;
4573                         tp->ups_info.speed_duplex = NWAY_10M_HALF;
4574                 }
4575                 if (advertising & RTL_ADVERTISED_10_FULL) {
4576                         tmp1 |= ADVERTISE_10FULL;
4577                         tp->ups_info.speed_duplex = NWAY_10M_FULL;
4578                 }
4579
4580                 if (advertising & RTL_ADVERTISED_100_HALF) {
4581                         tmp1 |= ADVERTISE_100HALF;
4582                         tp->ups_info.speed_duplex = NWAY_100M_HALF;
4583                 }
4584                 if (advertising & RTL_ADVERTISED_100_FULL) {
4585                         tmp1 |= ADVERTISE_100FULL;
4586                         tp->ups_info.speed_duplex = NWAY_100M_FULL;
4587                 }
4588
4589                 if (anar != tmp1) {
4590                         r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4591                         tp->mii.advertising = tmp1;
4592                 }
4593
4594                 if (tp->mii.supports_gmii) {
4595                         u16 gbcr;
4596
4597                         gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4598                         tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4599                                         ADVERTISE_1000HALF);
4600
4601                         if (advertising & RTL_ADVERTISED_1000_FULL) {
4602                                 tmp1 |= ADVERTISE_1000FULL;
4603                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4604                         }
4605
4606                         if (gbcr != tmp1)
4607                                 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4608                 }
4609
4610                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4611
4612                 tp->mii.force_media = 0;
4613         }
4614
4615         if (test_and_clear_bit(PHY_RESET, &tp->flags))
4616                 bmcr |= BMCR_RESET;
4617
4618         r8152_mdio_write(tp, MII_BMCR, bmcr);
4619
4620         if (bmcr & BMCR_RESET) {
4621                 int i;
4622
4623                 for (i = 0; i < 50; i++) {
4624                         msleep(20);
4625                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4626                                 break;
4627                 }
4628         }
4629
4630 out:
4631         return ret;
4632 }
4633
4634 static void rtl8152_up(struct r8152 *tp)
4635 {
4636         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4637                 return;
4638
4639         r8152_aldps_en(tp, false);
4640         r8152b_exit_oob(tp);
4641         r8152_aldps_en(tp, true);
4642 }
4643
4644 static void rtl8152_down(struct r8152 *tp)
4645 {
4646         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4647                 rtl_drop_queued_tx(tp);
4648                 return;
4649         }
4650
4651         r8152_power_cut_en(tp, false);
4652         r8152_aldps_en(tp, false);
4653         r8152b_enter_oob(tp);
4654         r8152_aldps_en(tp, true);
4655 }
4656
4657 static void rtl8153_up(struct r8152 *tp)
4658 {
4659         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4660                 return;
4661
4662         r8153_u1u2en(tp, false);
4663         r8153_u2p3en(tp, false);
4664         r8153_aldps_en(tp, false);
4665         r8153_first_init(tp);
4666         r8153_aldps_en(tp, true);
4667
4668         switch (tp->version) {
4669         case RTL_VER_03:
4670         case RTL_VER_04:
4671                 break;
4672         case RTL_VER_05:
4673         case RTL_VER_06:
4674         default:
4675                 r8153_u2p3en(tp, true);
4676                 break;
4677         }
4678
4679         r8153_u1u2en(tp, true);
4680 }
4681
4682 static void rtl8153_down(struct r8152 *tp)
4683 {
4684         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4685                 rtl_drop_queued_tx(tp);
4686                 return;
4687         }
4688
4689         r8153_u1u2en(tp, false);
4690         r8153_u2p3en(tp, false);
4691         r8153_power_cut_en(tp, false);
4692         r8153_aldps_en(tp, false);
4693         r8153_enter_oob(tp);
4694         r8153_aldps_en(tp, true);
4695 }
4696
4697 static void rtl8153b_up(struct r8152 *tp)
4698 {
4699         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4700                 return;
4701
4702         r8153b_u1u2en(tp, false);
4703         r8153_u2p3en(tp, false);
4704         r8153_aldps_en(tp, false);
4705
4706         r8153_first_init(tp);
4707         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
4708
4709         r8153_aldps_en(tp, true);
4710         r8153_u2p3en(tp, true);
4711         r8153b_u1u2en(tp, true);
4712 }
4713
4714 static void rtl8153b_down(struct r8152 *tp)
4715 {
4716         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4717                 rtl_drop_queued_tx(tp);
4718                 return;
4719         }
4720
4721         r8153b_u1u2en(tp, false);
4722         r8153_u2p3en(tp, false);
4723         r8153b_power_cut_en(tp, false);
4724         r8153_aldps_en(tp, false);
4725         r8153_enter_oob(tp);
4726         r8153_aldps_en(tp, true);
4727 }
4728
4729 static bool rtl8152_in_nway(struct r8152 *tp)
4730 {
4731         u16 nway_state;
4732
4733         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
4734         tp->ocp_base = 0x2000;
4735         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
4736         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
4737
4738         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
4739         if (nway_state & 0xc000)
4740                 return false;
4741         else
4742                 return true;
4743 }
4744
4745 static bool rtl8153_in_nway(struct r8152 *tp)
4746 {
4747         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
4748
4749         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
4750                 return false;
4751         else
4752                 return true;
4753 }
4754
4755 static void set_carrier(struct r8152 *tp)
4756 {
4757         struct net_device *netdev = tp->netdev;
4758         struct napi_struct *napi = &tp->napi;
4759         u8 speed;
4760
4761         speed = rtl8152_get_speed(tp);
4762
4763         if (speed & LINK_STATUS) {
4764                 if (!netif_carrier_ok(netdev)) {
4765                         tp->rtl_ops.enable(tp);
4766                         netif_stop_queue(netdev);
4767                         napi_disable(napi);
4768                         netif_carrier_on(netdev);
4769                         rtl_start_rx(tp);
4770                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
4771                         _rtl8152_set_rx_mode(netdev);
4772                         napi_enable(&tp->napi);
4773                         netif_wake_queue(netdev);
4774                         netif_info(tp, link, netdev, "carrier on\n");
4775                 } else if (netif_queue_stopped(netdev) &&
4776                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
4777                         netif_wake_queue(netdev);
4778                 }
4779         } else {
4780                 if (netif_carrier_ok(netdev)) {
4781                         netif_carrier_off(netdev);
4782                         tasklet_disable(&tp->tx_tl);
4783                         napi_disable(napi);
4784                         tp->rtl_ops.disable(tp);
4785                         napi_enable(napi);
4786                         tasklet_enable(&tp->tx_tl);
4787                         netif_info(tp, link, netdev, "carrier off\n");
4788                 }
4789         }
4790 }
4791
4792 static void rtl_work_func_t(struct work_struct *work)
4793 {
4794         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
4795
4796         /* If the device is unplugged or !netif_running(), the workqueue
4797          * doesn't need to wake the device, and could return directly.
4798          */
4799         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
4800                 return;
4801
4802         if (usb_autopm_get_interface(tp->intf) < 0)
4803                 return;
4804
4805         if (!test_bit(WORK_ENABLE, &tp->flags))
4806                 goto out1;
4807
4808         if (!mutex_trylock(&tp->control)) {
4809                 schedule_delayed_work(&tp->schedule, 0);
4810                 goto out1;
4811         }
4812
4813         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
4814                 set_carrier(tp);
4815
4816         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
4817                 _rtl8152_set_rx_mode(tp->netdev);
4818
4819         /* don't schedule tasket before linking */
4820         if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
4821             netif_carrier_ok(tp->netdev))
4822                 tasklet_schedule(&tp->tx_tl);
4823
4824         mutex_unlock(&tp->control);
4825
4826 out1:
4827         usb_autopm_put_interface(tp->intf);
4828 }
4829
4830 static void rtl_hw_phy_work_func_t(struct work_struct *work)
4831 {
4832         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
4833
4834         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4835                 return;
4836
4837         if (usb_autopm_get_interface(tp->intf) < 0)
4838                 return;
4839
4840         mutex_lock(&tp->control);
4841
4842         if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
4843                 tp->rtl_fw.retry = false;
4844                 tp->rtl_fw.fw = NULL;
4845
4846                 /* Delay execution in case request_firmware() is not ready yet.
4847                  */
4848                 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
4849                 goto ignore_once;
4850         }
4851
4852         tp->rtl_ops.hw_phy_cfg(tp);
4853
4854         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
4855                           tp->advertising);
4856
4857 ignore_once:
4858         mutex_unlock(&tp->control);
4859
4860         usb_autopm_put_interface(tp->intf);
4861 }
4862
4863 #ifdef CONFIG_PM_SLEEP
4864 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
4865                         void *data)
4866 {
4867         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
4868
4869         switch (action) {
4870         case PM_HIBERNATION_PREPARE:
4871         case PM_SUSPEND_PREPARE:
4872                 usb_autopm_get_interface(tp->intf);
4873                 break;
4874
4875         case PM_POST_HIBERNATION:
4876         case PM_POST_SUSPEND:
4877                 usb_autopm_put_interface(tp->intf);
4878                 break;
4879
4880         case PM_POST_RESTORE:
4881         case PM_RESTORE_PREPARE:
4882         default:
4883                 break;
4884         }
4885
4886         return NOTIFY_DONE;
4887 }
4888 #endif
4889
4890 static int rtl8152_open(struct net_device *netdev)
4891 {
4892         struct r8152 *tp = netdev_priv(netdev);
4893         int res = 0;
4894
4895         if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
4896                 cancel_delayed_work_sync(&tp->hw_phy_work);
4897                 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
4898         }
4899
4900         res = alloc_all_mem(tp);
4901         if (res)
4902                 goto out;
4903
4904         res = usb_autopm_get_interface(tp->intf);
4905         if (res < 0)
4906                 goto out_free;
4907
4908         mutex_lock(&tp->control);
4909
4910         tp->rtl_ops.up(tp);
4911
4912         netif_carrier_off(netdev);
4913         netif_start_queue(netdev);
4914         set_bit(WORK_ENABLE, &tp->flags);
4915
4916         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4917         if (res) {
4918                 if (res == -ENODEV)
4919                         netif_device_detach(tp->netdev);
4920                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
4921                            res);
4922                 goto out_unlock;
4923         }
4924         napi_enable(&tp->napi);
4925         tasklet_enable(&tp->tx_tl);
4926
4927         mutex_unlock(&tp->control);
4928
4929         usb_autopm_put_interface(tp->intf);
4930 #ifdef CONFIG_PM_SLEEP
4931         tp->pm_notifier.notifier_call = rtl_notifier;
4932         register_pm_notifier(&tp->pm_notifier);
4933 #endif
4934         return 0;
4935
4936 out_unlock:
4937         mutex_unlock(&tp->control);
4938         usb_autopm_put_interface(tp->intf);
4939 out_free:
4940         free_all_mem(tp);
4941 out:
4942         return res;
4943 }
4944
4945 static int rtl8152_close(struct net_device *netdev)
4946 {
4947         struct r8152 *tp = netdev_priv(netdev);
4948         int res = 0;
4949
4950 #ifdef CONFIG_PM_SLEEP
4951         unregister_pm_notifier(&tp->pm_notifier);
4952 #endif
4953         tasklet_disable(&tp->tx_tl);
4954         napi_disable(&tp->napi);
4955         clear_bit(WORK_ENABLE, &tp->flags);
4956         usb_kill_urb(tp->intr_urb);
4957         cancel_delayed_work_sync(&tp->schedule);
4958         netif_stop_queue(netdev);
4959
4960         res = usb_autopm_get_interface(tp->intf);
4961         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
4962                 rtl_drop_queued_tx(tp);
4963                 rtl_stop_rx(tp);
4964         } else {
4965                 mutex_lock(&tp->control);
4966
4967                 tp->rtl_ops.down(tp);
4968
4969                 mutex_unlock(&tp->control);
4970
4971                 usb_autopm_put_interface(tp->intf);
4972         }
4973
4974         free_all_mem(tp);
4975
4976         return res;
4977 }
4978
4979 static void rtl_tally_reset(struct r8152 *tp)
4980 {
4981         u32 ocp_data;
4982
4983         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4984         ocp_data |= TALLY_RESET;
4985         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4986 }
4987
4988 static void r8152b_init(struct r8152 *tp)
4989 {
4990         u32 ocp_data;
4991         u16 data;
4992
4993         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4994                 return;
4995
4996         data = r8152_mdio_read(tp, MII_BMCR);
4997         if (data & BMCR_PDOWN) {
4998                 data &= ~BMCR_PDOWN;
4999                 r8152_mdio_write(tp, MII_BMCR, data);
5000         }
5001
5002         r8152_aldps_en(tp, false);
5003
5004         if (tp->version == RTL_VER_01) {
5005                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5006                 ocp_data &= ~LED_MODE_MASK;
5007                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5008         }
5009
5010         r8152_power_cut_en(tp, false);
5011
5012         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5013         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5014         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5015         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5016         ocp_data &= ~MCU_CLK_RATIO_MASK;
5017         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5018         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5019         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5020                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5021         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5022
5023         rtl_tally_reset(tp);
5024
5025         /* enable rx aggregation */
5026         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5027         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5028         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5029 }
5030
5031 static void r8153_init(struct r8152 *tp)
5032 {
5033         u32 ocp_data;
5034         u16 data;
5035         int i;
5036
5037         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5038                 return;
5039
5040         r8153_u1u2en(tp, false);
5041
5042         for (i = 0; i < 500; i++) {
5043                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5044                     AUTOLOAD_DONE)
5045                         break;
5046                 msleep(20);
5047         }
5048
5049         data = r8153_phy_status(tp, 0);
5050
5051         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5052             tp->version == RTL_VER_05)
5053                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5054
5055         data = r8152_mdio_read(tp, MII_BMCR);
5056         if (data & BMCR_PDOWN) {
5057                 data &= ~BMCR_PDOWN;
5058                 r8152_mdio_write(tp, MII_BMCR, data);
5059         }
5060
5061         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5062
5063         r8153_u2p3en(tp, false);
5064
5065         if (tp->version == RTL_VER_04) {
5066                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5067                 ocp_data &= ~pwd_dn_scale_mask;
5068                 ocp_data |= pwd_dn_scale(96);
5069                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5070
5071                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5072                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5073                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5074         } else if (tp->version == RTL_VER_05) {
5075                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5076                 ocp_data &= ~ECM_ALDPS;
5077                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5078
5079                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5080                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5081                         ocp_data &= ~DYNAMIC_BURST;
5082                 else
5083                         ocp_data |= DYNAMIC_BURST;
5084                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5085         } else if (tp->version == RTL_VER_06) {
5086                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5087                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5088                         ocp_data &= ~DYNAMIC_BURST;
5089                 else
5090                         ocp_data |= DYNAMIC_BURST;
5091                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5092         }
5093
5094         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5095         ocp_data |= EP4_FULL_FC;
5096         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5097
5098         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5099         ocp_data &= ~TIMER11_EN;
5100         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5101
5102         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5103         ocp_data &= ~LED_MODE_MASK;
5104         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5105
5106         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5107         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5108                 ocp_data |= LPM_TIMER_500MS;
5109         else
5110                 ocp_data |= LPM_TIMER_500US;
5111         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5112
5113         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5114         ocp_data &= ~SEN_VAL_MASK;
5115         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5116         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5117
5118         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5119
5120         r8153_power_cut_en(tp, false);
5121         r8153_u1u2en(tp, true);
5122         r8153_mac_clk_spd(tp, false);
5123         usb_enable_lpm(tp->udev);
5124
5125         /* rx aggregation */
5126         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5127         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5128         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5129                 ocp_data |= RX_AGG_DISABLE;
5130
5131         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5132
5133         rtl_tally_reset(tp);
5134
5135         switch (tp->udev->speed) {
5136         case USB_SPEED_SUPER:
5137         case USB_SPEED_SUPER_PLUS:
5138                 tp->coalesce = COALESCE_SUPER;
5139                 break;
5140         case USB_SPEED_HIGH:
5141                 tp->coalesce = COALESCE_HIGH;
5142                 break;
5143         default:
5144                 tp->coalesce = COALESCE_SLOW;
5145                 break;
5146         }
5147 }
5148
5149 static void r8153b_init(struct r8152 *tp)
5150 {
5151         u32 ocp_data;
5152         u16 data;
5153         int i;
5154
5155         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5156                 return;
5157
5158         r8153b_u1u2en(tp, false);
5159
5160         for (i = 0; i < 500; i++) {
5161                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5162                     AUTOLOAD_DONE)
5163                         break;
5164                 msleep(20);
5165         }
5166
5167         data = r8153_phy_status(tp, 0);
5168
5169         data = r8152_mdio_read(tp, MII_BMCR);
5170         if (data & BMCR_PDOWN) {
5171                 data &= ~BMCR_PDOWN;
5172                 r8152_mdio_write(tp, MII_BMCR, data);
5173         }
5174
5175         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5176
5177         r8153_u2p3en(tp, false);
5178
5179         /* MSC timer = 0xfff * 8ms = 32760 ms */
5180         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5181
5182         /* U1/U2/L1 idle timer. 500 us */
5183         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5184
5185         r8153b_power_cut_en(tp, false);
5186         r8153b_ups_en(tp, false);
5187         r8153_queue_wake(tp, false);
5188         rtl_runtime_suspend_enable(tp, false);
5189         r8153b_u1u2en(tp, true);
5190         usb_enable_lpm(tp->udev);
5191
5192         /* MAC clock speed down */
5193         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5194         ocp_data |= MAC_CLK_SPDWN_EN;
5195         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5196
5197         set_bit(GREEN_ETHERNET, &tp->flags);
5198
5199         /* rx aggregation */
5200         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5201         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5202         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5203
5204         rtl_tally_reset(tp);
5205
5206         tp->coalesce = 15000;   /* 15 us */
5207 }
5208
5209 static int rtl8152_pre_reset(struct usb_interface *intf)
5210 {
5211         struct r8152 *tp = usb_get_intfdata(intf);
5212         struct net_device *netdev;
5213
5214         if (!tp)
5215                 return 0;
5216
5217         netdev = tp->netdev;
5218         if (!netif_running(netdev))
5219                 return 0;
5220
5221         netif_stop_queue(netdev);
5222         tasklet_disable(&tp->tx_tl);
5223         napi_disable(&tp->napi);
5224         clear_bit(WORK_ENABLE, &tp->flags);
5225         usb_kill_urb(tp->intr_urb);
5226         cancel_delayed_work_sync(&tp->schedule);
5227         if (netif_carrier_ok(netdev)) {
5228                 mutex_lock(&tp->control);
5229                 tp->rtl_ops.disable(tp);
5230                 mutex_unlock(&tp->control);
5231         }
5232
5233         return 0;
5234 }
5235
5236 static int rtl8152_post_reset(struct usb_interface *intf)
5237 {
5238         struct r8152 *tp = usb_get_intfdata(intf);
5239         struct net_device *netdev;
5240         struct sockaddr sa;
5241
5242         if (!tp)
5243                 return 0;
5244
5245         /* reset the MAC adddress in case of policy change */
5246         if (determine_ethernet_addr(tp, &sa) >= 0) {
5247                 rtnl_lock();
5248                 dev_set_mac_address (tp->netdev, &sa, NULL);
5249                 rtnl_unlock();
5250         }
5251
5252         netdev = tp->netdev;
5253         if (!netif_running(netdev))
5254                 return 0;
5255
5256         set_bit(WORK_ENABLE, &tp->flags);
5257         if (netif_carrier_ok(netdev)) {
5258                 mutex_lock(&tp->control);
5259                 tp->rtl_ops.enable(tp);
5260                 rtl_start_rx(tp);
5261                 _rtl8152_set_rx_mode(netdev);
5262                 mutex_unlock(&tp->control);
5263         }
5264
5265         napi_enable(&tp->napi);
5266         tasklet_enable(&tp->tx_tl);
5267         netif_wake_queue(netdev);
5268         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5269
5270         if (!list_empty(&tp->rx_done))
5271                 napi_schedule(&tp->napi);
5272
5273         return 0;
5274 }
5275
5276 static bool delay_autosuspend(struct r8152 *tp)
5277 {
5278         bool sw_linking = !!netif_carrier_ok(tp->netdev);
5279         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5280
5281         /* This means a linking change occurs and the driver doesn't detect it,
5282          * yet. If the driver has disabled tx/rx and hw is linking on, the
5283          * device wouldn't wake up by receiving any packet.
5284          */
5285         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5286                 return true;
5287
5288         /* If the linking down is occurred by nway, the device may miss the
5289          * linking change event. And it wouldn't wake when linking on.
5290          */
5291         if (!sw_linking && tp->rtl_ops.in_nway(tp))
5292                 return true;
5293         else if (!skb_queue_empty(&tp->tx_queue))
5294                 return true;
5295         else
5296                 return false;
5297 }
5298
5299 static int rtl8152_runtime_resume(struct r8152 *tp)
5300 {
5301         struct net_device *netdev = tp->netdev;
5302
5303         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5304                 struct napi_struct *napi = &tp->napi;
5305
5306                 tp->rtl_ops.autosuspend_en(tp, false);
5307                 napi_disable(napi);
5308                 set_bit(WORK_ENABLE, &tp->flags);
5309
5310                 if (netif_carrier_ok(netdev)) {
5311                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
5312                                 rtl_start_rx(tp);
5313                         } else {
5314                                 netif_carrier_off(netdev);
5315                                 tp->rtl_ops.disable(tp);
5316                                 netif_info(tp, link, netdev, "linking down\n");
5317                         }
5318                 }
5319
5320                 napi_enable(napi);
5321                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5322                 smp_mb__after_atomic();
5323
5324                 if (!list_empty(&tp->rx_done))
5325                         napi_schedule(&tp->napi);
5326
5327                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5328         } else {
5329                 if (netdev->flags & IFF_UP)
5330                         tp->rtl_ops.autosuspend_en(tp, false);
5331
5332                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5333         }
5334
5335         return 0;
5336 }
5337
5338 static int rtl8152_system_resume(struct r8152 *tp)
5339 {
5340         struct net_device *netdev = tp->netdev;
5341
5342         netif_device_attach(netdev);
5343
5344         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5345                 tp->rtl_ops.up(tp);
5346                 netif_carrier_off(netdev);
5347                 set_bit(WORK_ENABLE, &tp->flags);
5348                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5349         }
5350
5351         return 0;
5352 }
5353
5354 static int rtl8152_runtime_suspend(struct r8152 *tp)
5355 {
5356         struct net_device *netdev = tp->netdev;
5357         int ret = 0;
5358
5359         set_bit(SELECTIVE_SUSPEND, &tp->flags);
5360         smp_mb__after_atomic();
5361
5362         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5363                 u32 rcr = 0;
5364
5365                 if (netif_carrier_ok(netdev)) {
5366                         u32 ocp_data;
5367
5368                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5369                         ocp_data = rcr & ~RCR_ACPT_ALL;
5370                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5371                         rxdy_gated_en(tp, true);
5372                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5373                                                  PLA_OOB_CTRL);
5374                         if (!(ocp_data & RXFIFO_EMPTY)) {
5375                                 rxdy_gated_en(tp, false);
5376                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5377                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5378                                 smp_mb__after_atomic();
5379                                 ret = -EBUSY;
5380                                 goto out1;
5381                         }
5382                 }
5383
5384                 clear_bit(WORK_ENABLE, &tp->flags);
5385                 usb_kill_urb(tp->intr_urb);
5386
5387                 tp->rtl_ops.autosuspend_en(tp, true);
5388
5389                 if (netif_carrier_ok(netdev)) {
5390                         struct napi_struct *napi = &tp->napi;
5391
5392                         napi_disable(napi);
5393                         rtl_stop_rx(tp);
5394                         rxdy_gated_en(tp, false);
5395                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5396                         napi_enable(napi);
5397                 }
5398
5399                 if (delay_autosuspend(tp)) {
5400                         rtl8152_runtime_resume(tp);
5401                         ret = -EBUSY;
5402                 }
5403         }
5404
5405 out1:
5406         return ret;
5407 }
5408
5409 static int rtl8152_system_suspend(struct r8152 *tp)
5410 {
5411         struct net_device *netdev = tp->netdev;
5412
5413         netif_device_detach(netdev);
5414
5415         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5416                 struct napi_struct *napi = &tp->napi;
5417
5418                 clear_bit(WORK_ENABLE, &tp->flags);
5419                 usb_kill_urb(tp->intr_urb);
5420                 tasklet_disable(&tp->tx_tl);
5421                 napi_disable(napi);
5422                 cancel_delayed_work_sync(&tp->schedule);
5423                 tp->rtl_ops.down(tp);
5424                 napi_enable(napi);
5425                 tasklet_enable(&tp->tx_tl);
5426         }
5427
5428         return 0;
5429 }
5430
5431 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5432 {
5433         struct r8152 *tp = usb_get_intfdata(intf);
5434         int ret;
5435
5436         mutex_lock(&tp->control);
5437
5438         if (PMSG_IS_AUTO(message))
5439                 ret = rtl8152_runtime_suspend(tp);
5440         else
5441                 ret = rtl8152_system_suspend(tp);
5442
5443         mutex_unlock(&tp->control);
5444
5445         return ret;
5446 }
5447
5448 static int rtl8152_resume(struct usb_interface *intf)
5449 {
5450         struct r8152 *tp = usb_get_intfdata(intf);
5451         int ret;
5452
5453         mutex_lock(&tp->control);
5454
5455         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5456                 ret = rtl8152_runtime_resume(tp);
5457         else
5458                 ret = rtl8152_system_resume(tp);
5459
5460         mutex_unlock(&tp->control);
5461
5462         return ret;
5463 }
5464
5465 static int rtl8152_reset_resume(struct usb_interface *intf)
5466 {
5467         struct r8152 *tp = usb_get_intfdata(intf);
5468
5469         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5470         tp->rtl_ops.init(tp);
5471         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5472         set_ethernet_addr(tp);
5473         return rtl8152_resume(intf);
5474 }
5475
5476 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5477 {
5478         struct r8152 *tp = netdev_priv(dev);
5479
5480         if (usb_autopm_get_interface(tp->intf) < 0)
5481                 return;
5482
5483         if (!rtl_can_wakeup(tp)) {
5484                 wol->supported = 0;
5485                 wol->wolopts = 0;
5486         } else {
5487                 mutex_lock(&tp->control);
5488                 wol->supported = WAKE_ANY;
5489                 wol->wolopts = __rtl_get_wol(tp);
5490                 mutex_unlock(&tp->control);
5491         }
5492
5493         usb_autopm_put_interface(tp->intf);
5494 }
5495
5496 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5497 {
5498         struct r8152 *tp = netdev_priv(dev);
5499         int ret;
5500
5501         if (!rtl_can_wakeup(tp))
5502                 return -EOPNOTSUPP;
5503
5504         if (wol->wolopts & ~WAKE_ANY)
5505                 return -EINVAL;
5506
5507         ret = usb_autopm_get_interface(tp->intf);
5508         if (ret < 0)
5509                 goto out_set_wol;
5510
5511         mutex_lock(&tp->control);
5512
5513         __rtl_set_wol(tp, wol->wolopts);
5514         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5515
5516         mutex_unlock(&tp->control);
5517
5518         usb_autopm_put_interface(tp->intf);
5519
5520 out_set_wol:
5521         return ret;
5522 }
5523
5524 static u32 rtl8152_get_msglevel(struct net_device *dev)
5525 {
5526         struct r8152 *tp = netdev_priv(dev);
5527
5528         return tp->msg_enable;
5529 }
5530
5531 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5532 {
5533         struct r8152 *tp = netdev_priv(dev);
5534
5535         tp->msg_enable = value;
5536 }
5537
5538 static void rtl8152_get_drvinfo(struct net_device *netdev,
5539                                 struct ethtool_drvinfo *info)
5540 {
5541         struct r8152 *tp = netdev_priv(netdev);
5542
5543         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5544         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5545         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5546         if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5547                 strlcpy(info->fw_version, tp->rtl_fw.version,
5548                         sizeof(info->fw_version));
5549 }
5550
5551 static
5552 int rtl8152_get_link_ksettings(struct net_device *netdev,
5553                                struct ethtool_link_ksettings *cmd)
5554 {
5555         struct r8152 *tp = netdev_priv(netdev);
5556         int ret;
5557
5558         if (!tp->mii.mdio_read)
5559                 return -EOPNOTSUPP;
5560
5561         ret = usb_autopm_get_interface(tp->intf);
5562         if (ret < 0)
5563                 goto out;
5564
5565         mutex_lock(&tp->control);
5566
5567         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5568
5569         mutex_unlock(&tp->control);
5570
5571         usb_autopm_put_interface(tp->intf);
5572
5573 out:
5574         return ret;
5575 }
5576
5577 static int rtl8152_set_link_ksettings(struct net_device *dev,
5578                                       const struct ethtool_link_ksettings *cmd)
5579 {
5580         struct r8152 *tp = netdev_priv(dev);
5581         u32 advertising = 0;
5582         int ret;
5583
5584         ret = usb_autopm_get_interface(tp->intf);
5585         if (ret < 0)
5586                 goto out;
5587
5588         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5589                      cmd->link_modes.advertising))
5590                 advertising |= RTL_ADVERTISED_10_HALF;
5591
5592         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5593                      cmd->link_modes.advertising))
5594                 advertising |= RTL_ADVERTISED_10_FULL;
5595
5596         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5597                      cmd->link_modes.advertising))
5598                 advertising |= RTL_ADVERTISED_100_HALF;
5599
5600         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5601                      cmd->link_modes.advertising))
5602                 advertising |= RTL_ADVERTISED_100_FULL;
5603
5604         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5605                      cmd->link_modes.advertising))
5606                 advertising |= RTL_ADVERTISED_1000_HALF;
5607
5608         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5609                      cmd->link_modes.advertising))
5610                 advertising |= RTL_ADVERTISED_1000_FULL;
5611
5612         mutex_lock(&tp->control);
5613
5614         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5615                                 cmd->base.duplex, advertising);
5616         if (!ret) {
5617                 tp->autoneg = cmd->base.autoneg;
5618                 tp->speed = cmd->base.speed;
5619                 tp->duplex = cmd->base.duplex;
5620                 tp->advertising = advertising;
5621         }
5622
5623         mutex_unlock(&tp->control);
5624
5625         usb_autopm_put_interface(tp->intf);
5626
5627 out:
5628         return ret;
5629 }
5630
5631 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
5632         "tx_packets",
5633         "rx_packets",
5634         "tx_errors",
5635         "rx_errors",
5636         "rx_missed",
5637         "align_errors",
5638         "tx_single_collisions",
5639         "tx_multi_collisions",
5640         "rx_unicast",
5641         "rx_broadcast",
5642         "rx_multicast",
5643         "tx_aborted",
5644         "tx_underrun",
5645 };
5646
5647 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
5648 {
5649         switch (sset) {
5650         case ETH_SS_STATS:
5651                 return ARRAY_SIZE(rtl8152_gstrings);
5652         default:
5653                 return -EOPNOTSUPP;
5654         }
5655 }
5656
5657 static void rtl8152_get_ethtool_stats(struct net_device *dev,
5658                                       struct ethtool_stats *stats, u64 *data)
5659 {
5660         struct r8152 *tp = netdev_priv(dev);
5661         struct tally_counter tally;
5662
5663         if (usb_autopm_get_interface(tp->intf) < 0)
5664                 return;
5665
5666         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
5667
5668         usb_autopm_put_interface(tp->intf);
5669
5670         data[0] = le64_to_cpu(tally.tx_packets);
5671         data[1] = le64_to_cpu(tally.rx_packets);
5672         data[2] = le64_to_cpu(tally.tx_errors);
5673         data[3] = le32_to_cpu(tally.rx_errors);
5674         data[4] = le16_to_cpu(tally.rx_missed);
5675         data[5] = le16_to_cpu(tally.align_errors);
5676         data[6] = le32_to_cpu(tally.tx_one_collision);
5677         data[7] = le32_to_cpu(tally.tx_multi_collision);
5678         data[8] = le64_to_cpu(tally.rx_unicast);
5679         data[9] = le64_to_cpu(tally.rx_broadcast);
5680         data[10] = le32_to_cpu(tally.rx_multicast);
5681         data[11] = le16_to_cpu(tally.tx_aborted);
5682         data[12] = le16_to_cpu(tally.tx_underrun);
5683 }
5684
5685 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5686 {
5687         switch (stringset) {
5688         case ETH_SS_STATS:
5689                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
5690                 break;
5691         }
5692 }
5693
5694 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
5695 {
5696         u32 lp, adv, supported = 0;
5697         u16 val;
5698
5699         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
5700         supported = mmd_eee_cap_to_ethtool_sup_t(val);
5701
5702         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
5703         adv = mmd_eee_adv_to_ethtool_adv_t(val);
5704
5705         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
5706         lp = mmd_eee_adv_to_ethtool_adv_t(val);
5707
5708         eee->eee_enabled = tp->eee_en;
5709         eee->eee_active = !!(supported & adv & lp);
5710         eee->supported = supported;
5711         eee->advertised = tp->eee_adv;
5712         eee->lp_advertised = lp;
5713
5714         return 0;
5715 }
5716
5717 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
5718 {
5719         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
5720
5721         tp->eee_en = eee->eee_enabled;
5722         tp->eee_adv = val;
5723
5724         rtl_eee_enable(tp, tp->eee_en);
5725
5726         return 0;
5727 }
5728
5729 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
5730 {
5731         u32 lp, adv, supported = 0;
5732         u16 val;
5733
5734         val = ocp_reg_read(tp, OCP_EEE_ABLE);
5735         supported = mmd_eee_cap_to_ethtool_sup_t(val);
5736
5737         val = ocp_reg_read(tp, OCP_EEE_ADV);
5738         adv = mmd_eee_adv_to_ethtool_adv_t(val);
5739
5740         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
5741         lp = mmd_eee_adv_to_ethtool_adv_t(val);
5742
5743         eee->eee_enabled = tp->eee_en;
5744         eee->eee_active = !!(supported & adv & lp);
5745         eee->supported = supported;
5746         eee->advertised = tp->eee_adv;
5747         eee->lp_advertised = lp;
5748
5749         return 0;
5750 }
5751
5752 static int
5753 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
5754 {
5755         struct r8152 *tp = netdev_priv(net);
5756         int ret;
5757
5758         ret = usb_autopm_get_interface(tp->intf);
5759         if (ret < 0)
5760                 goto out;
5761
5762         mutex_lock(&tp->control);
5763
5764         ret = tp->rtl_ops.eee_get(tp, edata);
5765
5766         mutex_unlock(&tp->control);
5767
5768         usb_autopm_put_interface(tp->intf);
5769
5770 out:
5771         return ret;
5772 }
5773
5774 static int
5775 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
5776 {
5777         struct r8152 *tp = netdev_priv(net);
5778         int ret;
5779
5780         ret = usb_autopm_get_interface(tp->intf);
5781         if (ret < 0)
5782                 goto out;
5783
5784         mutex_lock(&tp->control);
5785
5786         ret = tp->rtl_ops.eee_set(tp, edata);
5787         if (!ret)
5788                 ret = mii_nway_restart(&tp->mii);
5789
5790         mutex_unlock(&tp->control);
5791
5792         usb_autopm_put_interface(tp->intf);
5793
5794 out:
5795         return ret;
5796 }
5797
5798 static int rtl8152_nway_reset(struct net_device *dev)
5799 {
5800         struct r8152 *tp = netdev_priv(dev);
5801         int ret;
5802
5803         ret = usb_autopm_get_interface(tp->intf);
5804         if (ret < 0)
5805                 goto out;
5806
5807         mutex_lock(&tp->control);
5808
5809         ret = mii_nway_restart(&tp->mii);
5810
5811         mutex_unlock(&tp->control);
5812
5813         usb_autopm_put_interface(tp->intf);
5814
5815 out:
5816         return ret;
5817 }
5818
5819 static int rtl8152_get_coalesce(struct net_device *netdev,
5820                                 struct ethtool_coalesce *coalesce)
5821 {
5822         struct r8152 *tp = netdev_priv(netdev);
5823
5824         switch (tp->version) {
5825         case RTL_VER_01:
5826         case RTL_VER_02:
5827         case RTL_VER_07:
5828                 return -EOPNOTSUPP;
5829         default:
5830                 break;
5831         }
5832
5833         coalesce->rx_coalesce_usecs = tp->coalesce;
5834
5835         return 0;
5836 }
5837
5838 static int rtl8152_set_coalesce(struct net_device *netdev,
5839                                 struct ethtool_coalesce *coalesce)
5840 {
5841         struct r8152 *tp = netdev_priv(netdev);
5842         int ret;
5843
5844         switch (tp->version) {
5845         case RTL_VER_01:
5846         case RTL_VER_02:
5847         case RTL_VER_07:
5848                 return -EOPNOTSUPP;
5849         default:
5850                 break;
5851         }
5852
5853         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
5854                 return -EINVAL;
5855
5856         ret = usb_autopm_get_interface(tp->intf);
5857         if (ret < 0)
5858                 return ret;
5859
5860         mutex_lock(&tp->control);
5861
5862         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
5863                 tp->coalesce = coalesce->rx_coalesce_usecs;
5864
5865                 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
5866                         netif_stop_queue(netdev);
5867                         napi_disable(&tp->napi);
5868                         tp->rtl_ops.disable(tp);
5869                         tp->rtl_ops.enable(tp);
5870                         rtl_start_rx(tp);
5871                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5872                         _rtl8152_set_rx_mode(netdev);
5873                         napi_enable(&tp->napi);
5874                         netif_wake_queue(netdev);
5875                 }
5876         }
5877
5878         mutex_unlock(&tp->control);
5879
5880         usb_autopm_put_interface(tp->intf);
5881
5882         return ret;
5883 }
5884
5885 static int rtl8152_get_tunable(struct net_device *netdev,
5886                                const struct ethtool_tunable *tunable, void *d)
5887 {
5888         struct r8152 *tp = netdev_priv(netdev);
5889
5890         switch (tunable->id) {
5891         case ETHTOOL_RX_COPYBREAK:
5892                 *(u32 *)d = tp->rx_copybreak;
5893                 break;
5894         default:
5895                 return -EOPNOTSUPP;
5896         }
5897
5898         return 0;
5899 }
5900
5901 static int rtl8152_set_tunable(struct net_device *netdev,
5902                                const struct ethtool_tunable *tunable,
5903                                const void *d)
5904 {
5905         struct r8152 *tp = netdev_priv(netdev);
5906         u32 val;
5907
5908         switch (tunable->id) {
5909         case ETHTOOL_RX_COPYBREAK:
5910                 val = *(u32 *)d;
5911                 if (val < ETH_ZLEN) {
5912                         netif_err(tp, rx_err, netdev,
5913                                   "Invalid rx copy break value\n");
5914                         return -EINVAL;
5915                 }
5916
5917                 if (tp->rx_copybreak != val) {
5918                         napi_disable(&tp->napi);
5919                         tp->rx_copybreak = val;
5920                         napi_enable(&tp->napi);
5921                 }
5922                 break;
5923         default:
5924                 return -EOPNOTSUPP;
5925         }
5926
5927         return 0;
5928 }
5929
5930 static void rtl8152_get_ringparam(struct net_device *netdev,
5931                                   struct ethtool_ringparam *ring)
5932 {
5933         struct r8152 *tp = netdev_priv(netdev);
5934
5935         ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
5936         ring->rx_pending = tp->rx_pending;
5937 }
5938
5939 static int rtl8152_set_ringparam(struct net_device *netdev,
5940                                  struct ethtool_ringparam *ring)
5941 {
5942         struct r8152 *tp = netdev_priv(netdev);
5943
5944         if (ring->rx_pending < (RTL8152_MAX_RX * 2))
5945                 return -EINVAL;
5946
5947         if (tp->rx_pending != ring->rx_pending) {
5948                 napi_disable(&tp->napi);
5949                 tp->rx_pending = ring->rx_pending;
5950                 napi_enable(&tp->napi);
5951         }
5952
5953         return 0;
5954 }
5955
5956 static const struct ethtool_ops ops = {
5957         .get_drvinfo = rtl8152_get_drvinfo,
5958         .get_link = ethtool_op_get_link,
5959         .nway_reset = rtl8152_nway_reset,
5960         .get_msglevel = rtl8152_get_msglevel,
5961         .set_msglevel = rtl8152_set_msglevel,
5962         .get_wol = rtl8152_get_wol,
5963         .set_wol = rtl8152_set_wol,
5964         .get_strings = rtl8152_get_strings,
5965         .get_sset_count = rtl8152_get_sset_count,
5966         .get_ethtool_stats = rtl8152_get_ethtool_stats,
5967         .get_coalesce = rtl8152_get_coalesce,
5968         .set_coalesce = rtl8152_set_coalesce,
5969         .get_eee = rtl_ethtool_get_eee,
5970         .set_eee = rtl_ethtool_set_eee,
5971         .get_link_ksettings = rtl8152_get_link_ksettings,
5972         .set_link_ksettings = rtl8152_set_link_ksettings,
5973         .get_tunable = rtl8152_get_tunable,
5974         .set_tunable = rtl8152_set_tunable,
5975         .get_ringparam = rtl8152_get_ringparam,
5976         .set_ringparam = rtl8152_set_ringparam,
5977 };
5978
5979 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
5980 {
5981         struct r8152 *tp = netdev_priv(netdev);
5982         struct mii_ioctl_data *data = if_mii(rq);
5983         int res;
5984
5985         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5986                 return -ENODEV;
5987
5988         res = usb_autopm_get_interface(tp->intf);
5989         if (res < 0)
5990                 goto out;
5991
5992         switch (cmd) {
5993         case SIOCGMIIPHY:
5994                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
5995                 break;
5996
5997         case SIOCGMIIREG:
5998                 mutex_lock(&tp->control);
5999                 data->val_out = r8152_mdio_read(tp, data->reg_num);
6000                 mutex_unlock(&tp->control);
6001                 break;
6002
6003         case SIOCSMIIREG:
6004                 if (!capable(CAP_NET_ADMIN)) {
6005                         res = -EPERM;
6006                         break;
6007                 }
6008                 mutex_lock(&tp->control);
6009                 r8152_mdio_write(tp, data->reg_num, data->val_in);
6010                 mutex_unlock(&tp->control);
6011                 break;
6012
6013         default:
6014                 res = -EOPNOTSUPP;
6015         }
6016
6017         usb_autopm_put_interface(tp->intf);
6018
6019 out:
6020         return res;
6021 }
6022
6023 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6024 {
6025         struct r8152 *tp = netdev_priv(dev);
6026         int ret;
6027
6028         switch (tp->version) {
6029         case RTL_VER_01:
6030         case RTL_VER_02:
6031         case RTL_VER_07:
6032                 dev->mtu = new_mtu;
6033                 return 0;
6034         default:
6035                 break;
6036         }
6037
6038         ret = usb_autopm_get_interface(tp->intf);
6039         if (ret < 0)
6040                 return ret;
6041
6042         mutex_lock(&tp->control);
6043
6044         dev->mtu = new_mtu;
6045
6046         if (netif_running(dev)) {
6047                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6048
6049                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6050
6051                 if (netif_carrier_ok(dev))
6052                         r8153_set_rx_early_size(tp);
6053         }
6054
6055         mutex_unlock(&tp->control);
6056
6057         usb_autopm_put_interface(tp->intf);
6058
6059         return ret;
6060 }
6061
6062 static const struct net_device_ops rtl8152_netdev_ops = {
6063         .ndo_open               = rtl8152_open,
6064         .ndo_stop               = rtl8152_close,
6065         .ndo_do_ioctl           = rtl8152_ioctl,
6066         .ndo_start_xmit         = rtl8152_start_xmit,
6067         .ndo_tx_timeout         = rtl8152_tx_timeout,
6068         .ndo_set_features       = rtl8152_set_features,
6069         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
6070         .ndo_set_mac_address    = rtl8152_set_mac_address,
6071         .ndo_change_mtu         = rtl8152_change_mtu,
6072         .ndo_validate_addr      = eth_validate_addr,
6073         .ndo_features_check     = rtl8152_features_check,
6074 };
6075
6076 static void rtl8152_unload(struct r8152 *tp)
6077 {
6078         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6079                 return;
6080
6081         if (tp->version != RTL_VER_01)
6082                 r8152_power_cut_en(tp, true);
6083 }
6084
6085 static void rtl8153_unload(struct r8152 *tp)
6086 {
6087         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6088                 return;
6089
6090         r8153_power_cut_en(tp, false);
6091 }
6092
6093 static void rtl8153b_unload(struct r8152 *tp)
6094 {
6095         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6096                 return;
6097
6098         r8153b_power_cut_en(tp, false);
6099 }
6100
6101 static int rtl_ops_init(struct r8152 *tp)
6102 {
6103         struct rtl_ops *ops = &tp->rtl_ops;
6104         int ret = 0;
6105
6106         switch (tp->version) {
6107         case RTL_VER_01:
6108         case RTL_VER_02:
6109         case RTL_VER_07:
6110                 ops->init               = r8152b_init;
6111                 ops->enable             = rtl8152_enable;
6112                 ops->disable            = rtl8152_disable;
6113                 ops->up                 = rtl8152_up;
6114                 ops->down               = rtl8152_down;
6115                 ops->unload             = rtl8152_unload;
6116                 ops->eee_get            = r8152_get_eee;
6117                 ops->eee_set            = r8152_set_eee;
6118                 ops->in_nway            = rtl8152_in_nway;
6119                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
6120                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
6121                 tp->rx_buf_sz           = 16 * 1024;
6122                 tp->eee_en              = true;
6123                 tp->eee_adv             = MDIO_EEE_100TX;
6124                 break;
6125
6126         case RTL_VER_03:
6127         case RTL_VER_04:
6128         case RTL_VER_05:
6129         case RTL_VER_06:
6130                 ops->init               = r8153_init;
6131                 ops->enable             = rtl8153_enable;
6132                 ops->disable            = rtl8153_disable;
6133                 ops->up                 = rtl8153_up;
6134                 ops->down               = rtl8153_down;
6135                 ops->unload             = rtl8153_unload;
6136                 ops->eee_get            = r8153_get_eee;
6137                 ops->eee_set            = r8152_set_eee;
6138                 ops->in_nway            = rtl8153_in_nway;
6139                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
6140                 ops->autosuspend_en     = rtl8153_runtime_enable;
6141                 tp->rx_buf_sz           = 32 * 1024;
6142                 tp->eee_en              = true;
6143                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6144                 break;
6145
6146         case RTL_VER_08:
6147         case RTL_VER_09:
6148                 ops->init               = r8153b_init;
6149                 ops->enable             = rtl8153_enable;
6150                 ops->disable            = rtl8153_disable;
6151                 ops->up                 = rtl8153b_up;
6152                 ops->down               = rtl8153b_down;
6153                 ops->unload             = rtl8153b_unload;
6154                 ops->eee_get            = r8153_get_eee;
6155                 ops->eee_set            = r8152_set_eee;
6156                 ops->in_nway            = rtl8153_in_nway;
6157                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
6158                 ops->autosuspend_en     = rtl8153b_runtime_enable;
6159                 tp->rx_buf_sz           = 32 * 1024;
6160                 tp->eee_en              = true;
6161                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6162                 break;
6163
6164         default:
6165                 ret = -ENODEV;
6166                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6167                 break;
6168         }
6169
6170         return ret;
6171 }
6172
6173 #define FIRMWARE_8153A_2        "rtl_nic/rtl8153a-2.fw"
6174 #define FIRMWARE_8153A_3        "rtl_nic/rtl8153a-3.fw"
6175 #define FIRMWARE_8153A_4        "rtl_nic/rtl8153a-4.fw"
6176 #define FIRMWARE_8153B_2        "rtl_nic/rtl8153b-2.fw"
6177
6178 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6179 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6180 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6181 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6182
6183 static int rtl_fw_init(struct r8152 *tp)
6184 {
6185         struct rtl_fw *rtl_fw = &tp->rtl_fw;
6186
6187         switch (tp->version) {
6188         case RTL_VER_04:
6189                 rtl_fw->fw_name         = FIRMWARE_8153A_2;
6190                 rtl_fw->pre_fw          = r8153_pre_firmware_1;
6191                 rtl_fw->post_fw         = r8153_post_firmware_1;
6192                 break;
6193         case RTL_VER_05:
6194                 rtl_fw->fw_name         = FIRMWARE_8153A_3;
6195                 rtl_fw->pre_fw          = r8153_pre_firmware_2;
6196                 rtl_fw->post_fw         = r8153_post_firmware_2;
6197                 break;
6198         case RTL_VER_06:
6199                 rtl_fw->fw_name         = FIRMWARE_8153A_4;
6200                 rtl_fw->post_fw         = r8153_post_firmware_3;
6201                 break;
6202         case RTL_VER_09:
6203                 rtl_fw->fw_name         = FIRMWARE_8153B_2;
6204                 rtl_fw->pre_fw          = r8153b_pre_firmware_1;
6205                 rtl_fw->post_fw         = r8153b_post_firmware_1;
6206                 break;
6207         default:
6208                 break;
6209         }
6210
6211         return 0;
6212 }
6213
6214 static u8 rtl_get_version(struct usb_interface *intf)
6215 {
6216         struct usb_device *udev = interface_to_usbdev(intf);
6217         u32 ocp_data = 0;
6218         __le32 *tmp;
6219         u8 version;
6220         int ret;
6221
6222         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6223         if (!tmp)
6224                 return 0;
6225
6226         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6227                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6228                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6229         if (ret > 0)
6230                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6231
6232         kfree(tmp);
6233
6234         switch (ocp_data) {
6235         case 0x4c00:
6236                 version = RTL_VER_01;
6237                 break;
6238         case 0x4c10:
6239                 version = RTL_VER_02;
6240                 break;
6241         case 0x5c00:
6242                 version = RTL_VER_03;
6243                 break;
6244         case 0x5c10:
6245                 version = RTL_VER_04;
6246                 break;
6247         case 0x5c20:
6248                 version = RTL_VER_05;
6249                 break;
6250         case 0x5c30:
6251                 version = RTL_VER_06;
6252                 break;
6253         case 0x4800:
6254                 version = RTL_VER_07;
6255                 break;
6256         case 0x6000:
6257                 version = RTL_VER_08;
6258                 break;
6259         case 0x6010:
6260                 version = RTL_VER_09;
6261                 break;
6262         default:
6263                 version = RTL_VER_UNKNOWN;
6264                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6265                 break;
6266         }
6267
6268         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6269
6270         return version;
6271 }
6272
6273 static int rtl8152_probe(struct usb_interface *intf,
6274                          const struct usb_device_id *id)
6275 {
6276         struct usb_device *udev = interface_to_usbdev(intf);
6277         u8 version = rtl_get_version(intf);
6278         struct r8152 *tp;
6279         struct net_device *netdev;
6280         int ret;
6281
6282         if (version == RTL_VER_UNKNOWN)
6283                 return -ENODEV;
6284
6285         if (udev->actconfig->desc.bConfigurationValue != 1) {
6286                 usb_driver_set_configuration(udev, 1);
6287                 return -ENODEV;
6288         }
6289
6290         usb_reset_device(udev);
6291         netdev = alloc_etherdev(sizeof(struct r8152));
6292         if (!netdev) {
6293                 dev_err(&intf->dev, "Out of memory\n");
6294                 return -ENOMEM;
6295         }
6296
6297         SET_NETDEV_DEV(netdev, &intf->dev);
6298         tp = netdev_priv(netdev);
6299         tp->msg_enable = 0x7FFF;
6300
6301         tp->udev = udev;
6302         tp->netdev = netdev;
6303         tp->intf = intf;
6304         tp->version = version;
6305
6306         switch (version) {
6307         case RTL_VER_01:
6308         case RTL_VER_02:
6309         case RTL_VER_07:
6310                 tp->mii.supports_gmii = 0;
6311                 break;
6312         default:
6313                 tp->mii.supports_gmii = 1;
6314                 break;
6315         }
6316
6317         ret = rtl_ops_init(tp);
6318         if (ret)
6319                 goto out;
6320
6321         rtl_fw_init(tp);
6322
6323         mutex_init(&tp->control);
6324         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6325         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6326         tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6327         tasklet_disable(&tp->tx_tl);
6328
6329         netdev->netdev_ops = &rtl8152_netdev_ops;
6330         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6331
6332         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6333                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6334                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6335                             NETIF_F_HW_VLAN_CTAG_TX;
6336         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6337                               NETIF_F_TSO | NETIF_F_FRAGLIST |
6338                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6339                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6340         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6341                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6342                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6343
6344         if (tp->version == RTL_VER_01) {
6345                 netdev->features &= ~NETIF_F_RXCSUM;
6346                 netdev->hw_features &= ~NETIF_F_RXCSUM;
6347         }
6348
6349         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6350             (!strcmp(udev->serial, "000001000000") ||
6351              !strcmp(udev->serial, "000002000000"))) {
6352                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6353                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6354         }
6355
6356         netdev->ethtool_ops = &ops;
6357         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6358
6359         /* MTU range: 68 - 1500 or 9194 */
6360         netdev->min_mtu = ETH_MIN_MTU;
6361         switch (tp->version) {
6362         case RTL_VER_01:
6363         case RTL_VER_02:
6364                 netdev->max_mtu = ETH_DATA_LEN;
6365                 break;
6366         default:
6367                 netdev->max_mtu = RTL8153_MAX_MTU;
6368                 break;
6369         }
6370
6371         tp->mii.dev = netdev;
6372         tp->mii.mdio_read = read_mii_word;
6373         tp->mii.mdio_write = write_mii_word;
6374         tp->mii.phy_id_mask = 0x3f;
6375         tp->mii.reg_num_mask = 0x1f;
6376         tp->mii.phy_id = R8152_PHY_ID;
6377
6378         tp->autoneg = AUTONEG_ENABLE;
6379         tp->speed = SPEED_100;
6380         tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6381                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6382         if (tp->mii.supports_gmii) {
6383                 tp->speed = SPEED_1000;
6384                 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6385         }
6386         tp->duplex = DUPLEX_FULL;
6387
6388         tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6389         tp->rx_pending = 10 * RTL8152_MAX_RX;
6390
6391         intf->needs_remote_wakeup = 1;
6392
6393         tp->rtl_ops.init(tp);
6394 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6395         /* Retry in case request_firmware() is not ready yet. */
6396         tp->rtl_fw.retry = true;
6397 #endif
6398         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6399         set_ethernet_addr(tp);
6400
6401         usb_set_intfdata(intf, tp);
6402         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6403
6404         ret = register_netdev(netdev);
6405         if (ret != 0) {
6406                 netif_err(tp, probe, netdev, "couldn't register the device\n");
6407                 goto out1;
6408         }
6409
6410         if (!rtl_can_wakeup(tp))
6411                 __rtl_set_wol(tp, 0);
6412
6413         tp->saved_wolopts = __rtl_get_wol(tp);
6414         if (tp->saved_wolopts)
6415                 device_set_wakeup_enable(&udev->dev, true);
6416         else
6417                 device_set_wakeup_enable(&udev->dev, false);
6418
6419         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6420
6421         return 0;
6422
6423 out1:
6424         tasklet_kill(&tp->tx_tl);
6425         usb_set_intfdata(intf, NULL);
6426 out:
6427         free_netdev(netdev);
6428         return ret;
6429 }
6430
6431 static void rtl8152_disconnect(struct usb_interface *intf)
6432 {
6433         struct r8152 *tp = usb_get_intfdata(intf);
6434
6435         usb_set_intfdata(intf, NULL);
6436         if (tp) {
6437                 rtl_set_unplug(tp);
6438
6439                 unregister_netdev(tp->netdev);
6440                 tasklet_kill(&tp->tx_tl);
6441                 cancel_delayed_work_sync(&tp->hw_phy_work);
6442                 tp->rtl_ops.unload(tp);
6443                 rtl8152_release_firmware(tp);
6444                 free_netdev(tp->netdev);
6445         }
6446 }
6447
6448 #define REALTEK_USB_DEVICE(vend, prod)  \
6449         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6450                        USB_DEVICE_ID_MATCH_INT_CLASS, \
6451         .idVendor = (vend), \
6452         .idProduct = (prod), \
6453         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6454 }, \
6455 { \
6456         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6457                        USB_DEVICE_ID_MATCH_DEVICE, \
6458         .idVendor = (vend), \
6459         .idProduct = (prod), \
6460         .bInterfaceClass = USB_CLASS_COMM, \
6461         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6462         .bInterfaceProtocol = USB_CDC_PROTO_NONE
6463
6464 /* table of devices that work with this driver */
6465 static const struct usb_device_id rtl8152_table[] = {
6466         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6467         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6468         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6469         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6470         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6471         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6472         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6473         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6474         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6475         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6476         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6477         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6478         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6479         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6480         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6481         {}
6482 };
6483
6484 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6485
6486 static struct usb_driver rtl8152_driver = {
6487         .name =         MODULENAME,
6488         .id_table =     rtl8152_table,
6489         .probe =        rtl8152_probe,
6490         .disconnect =   rtl8152_disconnect,
6491         .suspend =      rtl8152_suspend,
6492         .resume =       rtl8152_resume,
6493         .reset_resume = rtl8152_reset_resume,
6494         .pre_reset =    rtl8152_pre_reset,
6495         .post_reset =   rtl8152_post_reset,
6496         .supports_autosuspend = 1,
6497         .disable_hub_initiated_lpm = 1,
6498 };
6499
6500 module_usb_driver(rtl8152_driver);
6501
6502 MODULE_AUTHOR(DRIVER_AUTHOR);
6503 MODULE_DESCRIPTION(DRIVER_DESC);
6504 MODULE_LICENSE("GPL");
6505 MODULE_VERSION(DRIVER_VERSION);