drivers/net/usb/asix_devices.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * ASIX AX8817X based USB 2.0 Ethernet Devices
   4  * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
   5  * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
   6  * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
   7  * Copyright (c) 2002-2003 TiVo Inc.
   8  */
   9
  10 #include "asix.h"
  11
  12 #define PHY_MODE_MARVELL        0x0000
  13 #define MII_MARVELL_LED_CTRL    0x0018
  14 #define MII_MARVELL_STATUS      0x001b
  15 #define MII_MARVELL_CTRL        0x0014
  16
  17 #define MARVELL_LED_MANUAL      0x0019
  18
  19 #define MARVELL_STATUS_HWCFG    0x0004
  20
  21 #define MARVELL_CTRL_TXDELAY    0x0002
  22 #define MARVELL_CTRL_RXDELAY    0x0080
  23
  24 #define PHY_MODE_RTL8211CL      0x000C
  25
  26 #define AX88772A_PHY14H         0x14
  27 #define AX88772A_PHY14H_DEFAULT 0x442C
  28
  29 #define AX88772A_PHY15H         0x15
  30 #define AX88772A_PHY15H_DEFAULT 0x03C8
  31
  32 #define AX88772A_PHY16H         0x16
  33 #define AX88772A_PHY16H_DEFAULT 0x4044
  34
  35 struct ax88172_int_data {
  36         __le16 res1;
  37         u8 link;
  38         __le16 res2;
  39         u8 status;
  40         __le16 res3;
  41 } __packed;
  42
  43 static void asix_status(struct usbnet *dev, struct urb *urb)
  44 {
  45         struct ax88172_int_data *event;
  46         int link;
  47
  48         if (urb->actual_length < 8)
  49                 return;
  50
  51         event = urb->transfer_buffer;
  52         link = event->link & 0x01;
  53         if (netif_carrier_ok(dev->net) != link) {
  54                 usbnet_link_change(dev, link, 1);
  55                 netdev_dbg(dev->net, "Link Status is: %d\n", link);
  56         }
  57 }
  58
  59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
  60 {
  61         if (is_valid_ether_addr(addr)) {
  62                 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
  63         } else {
  64                 netdev_info(dev->net, "invalid hw address, using random\n");
  65                 eth_hw_addr_random(dev->net);
  66         }
  67 }
  68
  69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
  70 static u32 asix_get_phyid(struct usbnet *dev)
  71 {
  72         int phy_reg;
  73         u32 phy_id;
  74         int i;
  75
  76         /* Poll for the rare case the FW or phy isn't ready yet.  */
  77         for (i = 0; i < 100; i++) {
  78                 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
  79                 if (phy_reg < 0)
  80                         return 0;
  81                 if (phy_reg != 0 && phy_reg != 0xFFFF)
  82                         break;
  83                 mdelay(1);
  84         }
  85
  86         if (phy_reg <= 0 || phy_reg == 0xFFFF)
  87                 return 0;
  88
  89         phy_id = (phy_reg & 0xffff) << 16;
  90
  91         phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
  92         if (phy_reg < 0)
  93                 return 0;
  94
  95         phy_id |= (phy_reg & 0xffff);
  96
  97         return phy_id;
  98 }
  99
 100 static u32 asix_get_link(struct net_device *net)
 101 {
 102         struct usbnet *dev = netdev_priv(net);
 103
 104         return mii_link_ok(&dev->mii);
 105 }
 106
 107 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
 108 {
 109         struct usbnet *dev = netdev_priv(net);
 110
 111         return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
 112 }
 113
 114 /* We need to override some ethtool_ops so we require our
 115    own structure so we don't interfere with other usbnet
 116    devices that may be connected at the same time. */
 117 static const struct ethtool_ops ax88172_ethtool_ops = {
 118         .get_drvinfo            = asix_get_drvinfo,
 119         .get_link               = asix_get_link,
 120         .get_msglevel           = usbnet_get_msglevel,
 121         .set_msglevel           = usbnet_set_msglevel,
 122         .get_wol                = asix_get_wol,
 123         .set_wol                = asix_set_wol,
 124         .get_eeprom_len         = asix_get_eeprom_len,
 125         .get_eeprom             = asix_get_eeprom,
 126         .set_eeprom             = asix_set_eeprom,
 127         .nway_reset             = usbnet_nway_reset,
 128         .get_link_ksettings     = usbnet_get_link_ksettings_mii,
 129         .set_link_ksettings     = usbnet_set_link_ksettings_mii,
 130 };
 131
 132 static void ax88172_set_multicast(struct net_device *net)
 133 {
 134         struct usbnet *dev = netdev_priv(net);
 135         struct asix_data *data = (struct asix_data *)&dev->data;
 136         u8 rx_ctl = 0x8c;
 137
 138         if (net->flags & IFF_PROMISC) {
 139                 rx_ctl |= 0x01;
 140         } else if (net->flags & IFF_ALLMULTI ||
 141                    netdev_mc_count(net) > AX_MAX_MCAST) {
 142                 rx_ctl |= 0x02;
 143         } else if (netdev_mc_empty(net)) {
 144                 /* just broadcast and directed */
 145         } else {
 146                 /* We use the 20 byte dev->data
 147                  * for our 8 byte filter buffer
 148                  * to avoid allocating memory that
 149                  * is tricky to free later */
 150                 struct netdev_hw_addr *ha;
 151                 u32 crc_bits;
 152
 153                 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
 154
 155                 /* Build the multicast hash filter. */
 156                 netdev_for_each_mc_addr(ha, net) {
 157                         crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
 158                         data->multi_filter[crc_bits >> 3] |=
 159                             1 << (crc_bits & 7);
 160                 }
 161
 162                 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
 163                                    AX_MCAST_FILTER_SIZE, data->multi_filter);
 164
 165                 rx_ctl |= 0x10;
 166         }
 167
 168         asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
 169 }
 170
 171 static int ax88172_link_reset(struct usbnet *dev)
 172 {
 173         u8 mode;
 174         struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
 175
 176         mii_check_media(&dev->mii, 1, 1);
 177         mii_ethtool_gset(&dev->mii, &ecmd);
 178         mode = AX88172_MEDIUM_DEFAULT;
 179
 180         if (ecmd.duplex != DUPLEX_FULL)
 181                 mode |= ~AX88172_MEDIUM_FD;
 182
 183         netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
 184                    ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
 185
 186         asix_write_medium_mode(dev, mode, 0);
 187
 188         return 0;
 189 }
 190
 191 static const struct net_device_ops ax88172_netdev_ops = {
 192         .ndo_open               = usbnet_open,
 193         .ndo_stop               = usbnet_stop,
 194         .ndo_start_xmit         = usbnet_start_xmit,
 195         .ndo_tx_timeout         = usbnet_tx_timeout,
 196         .ndo_change_mtu         = usbnet_change_mtu,
 197         .ndo_get_stats64        = dev_get_tstats64,
 198         .ndo_set_mac_address    = eth_mac_addr,
 199         .ndo_validate_addr      = eth_validate_addr,
 200         .ndo_do_ioctl           = asix_ioctl,
 201         .ndo_set_rx_mode        = ax88172_set_multicast,
 202 };
 203
 204 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
 205 {
 206         unsigned int timeout = 5000;
 207
 208         asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
 209
 210         /* give phy_id a chance to process reset */
 211         udelay(500);
 212
 213         /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
 214         while (timeout--) {
 215                 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
 216                                                         & BMCR_RESET)
 217                         udelay(100);
 218                 else
 219                         return;
 220         }
 221
 222         netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
 223                    dev->mii.phy_id);
 224 }
 225
 226 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
 227 {
 228         int ret = 0;
 229         u8 buf[ETH_ALEN] = {0};
 230         int i;
 231         unsigned long gpio_bits = dev->driver_info->data;
 232
 233         usbnet_get_endpoints(dev,intf);
 234
 235         /* Toggle the GPIOs in a manufacturer/model specific way */
 236         for (i = 2; i >= 0; i--) {
 237                 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
 238                                 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
 239                 if (ret < 0)
 240                         goto out;
 241                 msleep(5);
 242         }
 243
 244         ret = asix_write_rx_ctl(dev, 0x80, 0);
 245         if (ret < 0)
 246                 goto out;
 247
 248         /* Get the MAC address */
 249         ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
 250                             0, 0, ETH_ALEN, buf, 0);
 251         if (ret < 0) {
 252                 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
 253                            ret);
 254                 goto out;
 255         }
 256
 257         asix_set_netdev_dev_addr(dev, buf);
 258
 259         /* Initialize MII structure */
 260         dev->mii.dev = dev->net;
 261         dev->mii.mdio_read = asix_mdio_read;
 262         dev->mii.mdio_write = asix_mdio_write;
 263         dev->mii.phy_id_mask = 0x3f;
 264         dev->mii.reg_num_mask = 0x1f;
 265
 266         dev->mii.phy_id = asix_read_phy_addr(dev, true);
 267         if (dev->mii.phy_id < 0)
 268                 return dev->mii.phy_id;
 269
 270         dev->net->netdev_ops = &ax88172_netdev_ops;
 271         dev->net->ethtool_ops = &ax88172_ethtool_ops;
 272         dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
 273         dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
 274
 275         asix_phy_reset(dev, BMCR_RESET);
 276         asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
 277                 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
 278         mii_nway_restart(&dev->mii);
 279
 280         return 0;
 281
 282 out:
 283         return ret;
 284 }
 285
 286 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset,
 287                                         u8 *data)
 288 {
 289         switch (sset) {
 290         case ETH_SS_TEST:
 291                 net_selftest_get_strings(data);
 292                 break;
 293         }
 294 }
 295
 296 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset)
 297 {
 298         switch (sset) {
 299         case ETH_SS_TEST:
 300                 return net_selftest_get_count();
 301         default:
 302                 return -EOPNOTSUPP;
 303         }
 304 }
 305
 306 static const struct ethtool_ops ax88772_ethtool_ops = {
 307         .get_drvinfo            = asix_get_drvinfo,
 308         .get_link               = usbnet_get_link,
 309         .get_msglevel           = usbnet_get_msglevel,
 310         .set_msglevel           = usbnet_set_msglevel,
 311         .get_wol                = asix_get_wol,
 312         .set_wol                = asix_set_wol,
 313         .get_eeprom_len         = asix_get_eeprom_len,
 314         .get_eeprom             = asix_get_eeprom,
 315         .set_eeprom             = asix_set_eeprom,
 316         .nway_reset             = phy_ethtool_nway_reset,
 317         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 318         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 319         .self_test              = net_selftest,
 320         .get_strings            = ax88772_ethtool_get_strings,
 321         .get_sset_count         = ax88772_ethtool_get_sset_count,
 322 };
 323
 324 static int ax88772_reset(struct usbnet *dev)
 325 {
 326         struct asix_data *data = (struct asix_data *)&dev->data;
 327         struct asix_common_private *priv = dev->driver_priv;
 328         int ret;
 329
 330         /* Rewrite MAC address */
 331         ether_addr_copy(data->mac_addr, dev->net->dev_addr);
 332         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
 333                              ETH_ALEN, data->mac_addr, 0);
 334         if (ret < 0)
 335                 goto out;
 336
 337         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 338         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
 339         if (ret < 0)
 340                 goto out;
 341
 342         ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
 343         if (ret < 0)
 344                 goto out;
 345
 346         phy_start(priv->phydev);
 347
 348         return 0;
 349
 350 out:
 351         return ret;
 352 }
 353
 354 static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
 355 {
 356         struct asix_data *data = (struct asix_data *)&dev->data;
 357         int ret, embd_phy;
 358         u16 rx_ctl;
 359
 360         ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
 361                               AX_GPIO_GPO2EN, 5, in_pm);
 362         if (ret < 0)
 363                 goto out;
 364
 365         embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
 366
 367         ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
 368                              0, 0, NULL, in_pm);
 369         if (ret < 0) {
 370                 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
 371                 goto out;
 372         }
 373
 374         if (embd_phy) {
 375                 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
 376                 if (ret < 0)
 377                         goto out;
 378
 379                 usleep_range(10000, 11000);
 380
 381                 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
 382                 if (ret < 0)
 383                         goto out;
 384
 385                 msleep(60);
 386
 387                 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
 388                                     in_pm);
 389                 if (ret < 0)
 390                         goto out;
 391         } else {
 392                 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
 393                                     in_pm);
 394                 if (ret < 0)
 395                         goto out;
 396         }
 397
 398         msleep(150);
 399
 400         if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 401                                            MII_PHYSID1))){
 402                 ret = -EIO;
 403                 goto out;
 404         }
 405
 406         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 407         if (ret < 0)
 408                 goto out;
 409
 410         ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
 411         if (ret < 0)
 412                 goto out;
 413
 414         ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
 415                              AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
 416                              AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
 417         if (ret < 0) {
 418                 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
 419                 goto out;
 420         }
 421
 422         /* Rewrite MAC address */
 423         ether_addr_copy(data->mac_addr, dev->net->dev_addr);
 424         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
 425                              ETH_ALEN, data->mac_addr, in_pm);
 426         if (ret < 0)
 427                 goto out;
 428
 429         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 430         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 431         if (ret < 0)
 432                 goto out;
 433
 434         rx_ctl = asix_read_rx_ctl(dev, in_pm);
 435         netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
 436                    rx_ctl);
 437
 438         rx_ctl = asix_read_medium_status(dev, in_pm);
 439         netdev_dbg(dev->net,
 440                    "Medium Status is 0x%04x after all initializations\n",
 441                    rx_ctl);
 442
 443         return 0;
 444
 445 out:
 446         return ret;
 447 }
 448
 449 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
 450 {
 451         struct asix_data *data = (struct asix_data *)&dev->data;
 452         int ret, embd_phy;
 453         u16 rx_ctl, phy14h, phy15h, phy16h;
 454         u8 chipcode = 0;
 455
 456         ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
 457         if (ret < 0)
 458                 goto out;
 459
 460         embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
 461
 462         ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
 463                              AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
 464         if (ret < 0) {
 465                 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
 466                 goto out;
 467         }
 468         usleep_range(10000, 11000);
 469
 470         ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
 471         if (ret < 0)
 472                 goto out;
 473
 474         usleep_range(10000, 11000);
 475
 476         ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
 477         if (ret < 0)
 478                 goto out;
 479
 480         msleep(160);
 481
 482         ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
 483         if (ret < 0)
 484                 goto out;
 485
 486         ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
 487         if (ret < 0)
 488                 goto out;
 489
 490         msleep(200);
 491
 492         if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 493                                            MII_PHYSID1))) {
 494                 ret = -1;
 495                 goto out;
 496         }
 497
 498         ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
 499                             0, 1, &chipcode, in_pm);
 500         if (ret < 0)
 501                 goto out;
 502
 503         if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
 504                 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
 505                                      0, NULL, in_pm);
 506                 if (ret < 0) {
 507                         netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
 508                                    ret);
 509                         goto out;
 510                 }
 511         } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
 512                 /* Check if the PHY registers have default settings */
 513                 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 514                                              AX88772A_PHY14H);
 515                 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 516                                              AX88772A_PHY15H);
 517                 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 518                                              AX88772A_PHY16H);
 519
 520                 netdev_dbg(dev->net,
 521                            "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
 522                            phy14h, phy15h, phy16h);
 523
 524                 /* Restore PHY registers default setting if not */
 525                 if (phy14h != AX88772A_PHY14H_DEFAULT)
 526                         asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
 527                                              AX88772A_PHY14H,
 528                                              AX88772A_PHY14H_DEFAULT);
 529                 if (phy15h != AX88772A_PHY15H_DEFAULT)
 530                         asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
 531                                              AX88772A_PHY15H,
 532                                              AX88772A_PHY15H_DEFAULT);
 533                 if (phy16h != AX88772A_PHY16H_DEFAULT)
 534                         asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
 535                                              AX88772A_PHY16H,
 536                                              AX88772A_PHY16H_DEFAULT);
 537         }
 538
 539         ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
 540                                 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
 541                                 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
 542         if (ret < 0) {
 543                 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
 544                 goto out;
 545         }
 546
 547         /* Rewrite MAC address */
 548         memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
 549         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
 550                                                         data->mac_addr, in_pm);
 551         if (ret < 0)
 552                 goto out;
 553
 554         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 555         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 556         if (ret < 0)
 557                 goto out;
 558
 559         ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
 560         if (ret < 0)
 561                 return ret;
 562
 563         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 564         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 565         if (ret < 0)
 566                 goto out;
 567
 568         rx_ctl = asix_read_rx_ctl(dev, in_pm);
 569         netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
 570                    rx_ctl);
 571
 572         rx_ctl = asix_read_medium_status(dev, in_pm);
 573         netdev_dbg(dev->net,
 574                    "Medium Status is 0x%04x after all initializations\n",
 575                    rx_ctl);
 576
 577         return 0;
 578
 579 out:
 580         return ret;
 581 }
 582
 583 static const struct net_device_ops ax88772_netdev_ops = {
 584         .ndo_open               = usbnet_open,
 585         .ndo_stop               = usbnet_stop,
 586         .ndo_start_xmit         = usbnet_start_xmit,
 587         .ndo_tx_timeout         = usbnet_tx_timeout,
 588         .ndo_change_mtu         = usbnet_change_mtu,
 589         .ndo_get_stats64        = dev_get_tstats64,
 590         .ndo_set_mac_address    = asix_set_mac_address,
 591         .ndo_validate_addr      = eth_validate_addr,
 592         .ndo_do_ioctl           = phy_do_ioctl_running,
 593         .ndo_set_rx_mode        = asix_set_multicast,
 594 };
 595
 596 static void ax88772_suspend(struct usbnet *dev)
 597 {
 598         struct asix_common_private *priv = dev->driver_priv;
 599         u16 medium;
 600
 601         if (netif_running(dev->net))
 602                 phy_stop(priv->phydev);
 603
 604         /* Stop MAC operation */
 605         medium = asix_read_medium_status(dev, 1);
 606         medium &= ~AX_MEDIUM_RE;
 607         asix_write_medium_mode(dev, medium, 1);
 608
 609         netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
 610                    asix_read_medium_status(dev, 1));
 611 }
 612
 613 static int asix_suspend(struct usb_interface *intf, pm_message_t message)
 614 {
 615         struct usbnet *dev = usb_get_intfdata(intf);
 616         struct asix_common_private *priv = dev->driver_priv;
 617
 618         if (priv && priv->suspend)
 619                 priv->suspend(dev);
 620
 621         return usbnet_suspend(intf, message);
 622 }
 623
 624 static void ax88772_resume(struct usbnet *dev)
 625 {
 626         struct asix_common_private *priv = dev->driver_priv;
 627         int i;
 628
 629         for (i = 0; i < 3; i++)
 630                 if (!ax88772_hw_reset(dev, 1))
 631                         break;
 632
 633         if (netif_running(dev->net))
 634                 phy_start(priv->phydev);
 635 }
 636
 637 static void ax88772a_resume(struct usbnet *dev)
 638 {
 639         struct asix_common_private *priv = dev->driver_priv;
 640         int i;
 641
 642         for (i = 0; i < 3; i++) {
 643                 if (!ax88772a_hw_reset(dev, 1))
 644                         break;
 645         }
 646
 647         if (netif_running(dev->net))
 648                 phy_start(priv->phydev);
 649 }
 650
 651 static int asix_resume(struct usb_interface *intf)
 652 {
 653         struct usbnet *dev = usb_get_intfdata(intf);
 654         struct asix_common_private *priv = dev->driver_priv;
 655
 656         if (priv && priv->resume)
 657                 priv->resume(dev);
 658
 659         return usbnet_resume(intf);
 660 }
 661
 662 static int ax88772_init_mdio(struct usbnet *dev)
 663 {
 664         struct asix_common_private *priv = dev->driver_priv;
 665
 666         priv->mdio = devm_mdiobus_alloc(&dev->udev->dev);
 667         if (!priv->mdio)
 668                 return -ENOMEM;
 669
 670         priv->mdio->priv = dev;
 671         priv->mdio->read = &asix_mdio_bus_read;
 672         priv->mdio->write = &asix_mdio_bus_write;
 673         priv->mdio->name = "Asix MDIO Bus";
 674         /* mii bus name is usb-<usb bus number>-<usb device number> */
 675         snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
 676                  dev->udev->bus->busnum, dev->udev->devnum);
 677
 678         return devm_mdiobus_register(&dev->udev->dev, priv->mdio);
 679 }
 680
 681 static int ax88772_init_phy(struct usbnet *dev)
 682 {
 683         struct asix_common_private *priv = dev->driver_priv;
 684         int ret;
 685
 686         ret = asix_read_phy_addr(dev, true);
 687         if (ret < 0)
 688                 return ret;
 689
 690         priv->phy_addr = ret;
 691
 692         snprintf(priv->phy_name, sizeof(priv->phy_name), PHY_ID_FMT,
 693                  priv->mdio->id, priv->phy_addr);
 694
 695         priv->phydev = phy_connect(dev->net, priv->phy_name, &asix_adjust_link,
 696                                    PHY_INTERFACE_MODE_INTERNAL);
 697         if (IS_ERR(priv->phydev)) {
 698                 netdev_err(dev->net, "Could not connect to PHY device %s\n",
 699                            priv->phy_name);
 700                 ret = PTR_ERR(priv->phydev);
 701                 return ret;
 702         }
 703
 704         phy_suspend(priv->phydev);
 705         priv->phydev->mac_managed_pm = 1;
 706
 707         phy_attached_info(priv->phydev);
 708
 709         return 0;
 710 }
 711
 712 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
 713 {
 714         u8 buf[ETH_ALEN] = {0}, chipcode = 0;
 715         struct asix_common_private *priv;
 716         int ret, i;
 717         u32 phyid;
 718
 719         usbnet_get_endpoints(dev, intf);
 720
 721         /* Maybe the boot loader passed the MAC address via device tree */
 722         if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) {
 723                 netif_dbg(dev, ifup, dev->net,
 724                           "MAC address read from device tree");
 725         } else {
 726                 /* Try getting the MAC address from EEPROM */
 727                 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
 728                         for (i = 0; i < (ETH_ALEN >> 1); i++) {
 729                                 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM,
 730                                                     0x04 + i, 0, 2, buf + i * 2,
 731                                                     0);
 732                                 if (ret < 0)
 733                                         break;
 734                         }
 735                 } else {
 736                         ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
 737                                             0, 0, ETH_ALEN, buf, 0);
 738                 }
 739
 740                 if (ret < 0) {
 741                         netdev_dbg(dev->net, "Failed to read MAC address: %d\n",
 742                                    ret);
 743                         return ret;
 744                 }
 745         }
 746
 747         asix_set_netdev_dev_addr(dev, buf);
 748
 749         dev->net->netdev_ops = &ax88772_netdev_ops;
 750         dev->net->ethtool_ops = &ax88772_ethtool_ops;
 751         dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
 752         dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
 753
 754         asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
 755         chipcode &= AX_CHIPCODE_MASK;
 756
 757         ret = (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
 758                                                   ax88772a_hw_reset(dev, 0);
 759
 760         if (ret < 0) {
 761                 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret);
 762                 return ret;
 763         }
 764
 765         /* Read PHYID register *AFTER* the PHY was reset properly */
 766         phyid = asix_get_phyid(dev);
 767         netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
 768
 769         /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
 770         if (dev->driver_info->flags & FLAG_FRAMING_AX) {
 771                 /* hard_mtu  is still the default - the device does not support
 772                    jumbo eth frames */
 773                 dev->rx_urb_size = 2048;
 774         }
 775
 776         priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL);
 777         if (!priv)
 778                 return -ENOMEM;
 779
 780         dev->driver_priv = priv;
 781
 782         priv->presvd_phy_bmcr = 0;
 783         priv->presvd_phy_advertise = 0;
 784         if (chipcode == AX_AX88772_CHIPCODE) {
 785                 priv->resume = ax88772_resume;
 786                 priv->suspend = ax88772_suspend;
 787         } else {
 788                 priv->resume = ax88772a_resume;
 789                 priv->suspend = ax88772_suspend;
 790         }
 791
 792         ret = ax88772_init_mdio(dev);
 793         if (ret)
 794                 return ret;
 795
 796         return ax88772_init_phy(dev);
 797 }
 798
 799 static int ax88772_stop(struct usbnet *dev)
 800 {
 801         struct asix_common_private *priv = dev->driver_priv;
 802
 803         /* On unplugged USB, we will get MDIO communication errors and the
 804          * PHY will be set in to PHY_HALTED state.
 805          */
 806         if (priv->phydev->state != PHY_HALTED)
 807                 phy_stop(priv->phydev);
 808
 809         return 0;
 810 }
 811
 812 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
 813 {
 814         struct asix_common_private *priv = dev->driver_priv;
 815
 816         phy_disconnect(priv->phydev);
 817         asix_rx_fixup_common_free(dev->driver_priv);
 818 }
 819
 820 static const struct ethtool_ops ax88178_ethtool_ops = {
 821         .get_drvinfo            = asix_get_drvinfo,
 822         .get_link               = asix_get_link,
 823         .get_msglevel           = usbnet_get_msglevel,
 824         .set_msglevel           = usbnet_set_msglevel,
 825         .get_wol                = asix_get_wol,
 826         .set_wol                = asix_set_wol,
 827         .get_eeprom_len         = asix_get_eeprom_len,
 828         .get_eeprom             = asix_get_eeprom,
 829         .set_eeprom             = asix_set_eeprom,
 830         .nway_reset             = usbnet_nway_reset,
 831         .get_link_ksettings     = usbnet_get_link_ksettings_mii,
 832         .set_link_ksettings     = usbnet_set_link_ksettings_mii,
 833 };
 834
 835 static int marvell_phy_init(struct usbnet *dev)
 836 {
 837         struct asix_data *data = (struct asix_data *)&dev->data;
 838         u16 reg;
 839
 840         netdev_dbg(dev->net, "marvell_phy_init()\n");
 841
 842         reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
 843         netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
 844
 845         asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
 846                         MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
 847
 848         if (data->ledmode) {
 849                 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
 850                         MII_MARVELL_LED_CTRL);
 851                 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
 852
 853                 reg &= 0xf8ff;
 854                 reg |= (1 + 0x0100);
 855                 asix_mdio_write(dev->net, dev->mii.phy_id,
 856                         MII_MARVELL_LED_CTRL, reg);
 857
 858                 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
 859                         MII_MARVELL_LED_CTRL);
 860                 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
 861                 reg &= 0xfc0f;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static int rtl8211cl_phy_init(struct usbnet *dev)
 868 {
 869         struct asix_data *data = (struct asix_data *)&dev->data;
 870
 871         netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
 872
 873         asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
 874         asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
 875         asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
 876                 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
 877         asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
 878
 879         if (data->ledmode == 12) {
 880                 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
 881                 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
 882                 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int marvell_led_status(struct usbnet *dev, u16 speed)
 889 {
 890         u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
 891
 892         netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
 893
 894         /* Clear out the center LED bits - 0x03F0 */
 895         reg &= 0xfc0f;
 896
 897         switch (speed) {
 898                 case SPEED_1000:
 899                         reg |= 0x03e0;
 900                         break;
 901                 case SPEED_100:
 902                         reg |= 0x03b0;
 903                         break;
 904                 default:
 905                         reg |= 0x02f0;
 906         }
 907
 908         netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
 909         asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
 910
 911         return 0;
 912 }
 913
 914 static int ax88178_reset(struct usbnet *dev)
 915 {
 916         struct asix_data *data = (struct asix_data *)&dev->data;
 917         int ret;
 918         __le16 eeprom;
 919         u8 status;
 920         int gpio0 = 0;
 921         u32 phyid;
 922
 923         asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
 924         netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
 925
 926         asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
 927         asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
 928         asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
 929
 930         netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
 931
 932         if (eeprom == cpu_to_le16(0xffff)) {
 933                 data->phymode = PHY_MODE_MARVELL;
 934                 data->ledmode = 0;
 935                 gpio0 = 1;
 936         } else {
 937                 data->phymode = le16_to_cpu(eeprom) & 0x7F;
 938                 data->ledmode = le16_to_cpu(eeprom) >> 8;
 939                 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
 940         }
 941         netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
 942
 943         /* Power up external GigaPHY through AX88178 GPIO pin */
 944         asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
 945                         AX_GPIO_GPO1EN, 40, 0);
 946         if ((le16_to_cpu(eeprom) >> 8) != 1) {
 947                 asix_write_gpio(dev, 0x003c, 30, 0);
 948                 asix_write_gpio(dev, 0x001c, 300, 0);
 949                 asix_write_gpio(dev, 0x003c, 30, 0);
 950         } else {
 951                 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
 952                 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
 953                 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
 954         }
 955
 956         /* Read PHYID register *AFTER* powering up PHY */
 957         phyid = asix_get_phyid(dev);
 958         netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
 959
 960         /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
 961         asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
 962
 963         asix_sw_reset(dev, 0, 0);
 964         msleep(150);
 965
 966         asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
 967         msleep(150);
 968
 969         asix_write_rx_ctl(dev, 0, 0);
 970
 971         if (data->phymode == PHY_MODE_MARVELL) {
 972                 marvell_phy_init(dev);
 973                 msleep(60);
 974         } else if (data->phymode == PHY_MODE_RTL8211CL)
 975                 rtl8211cl_phy_init(dev);
 976
 977         asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
 978         asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
 979                         ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
 980         asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
 981                         ADVERTISE_1000FULL);
 982
 983         asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
 984         mii_nway_restart(&dev->mii);
 985
 986         /* Rewrite MAC address */
 987         memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
 988         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
 989                                                         data->mac_addr, 0);
 990         if (ret < 0)
 991                 return ret;
 992
 993         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
 994         if (ret < 0)
 995                 return ret;
 996
 997         return 0;
 998 }
 999
1000 static int ax88178_link_reset(struct usbnet *dev)
1001 {
1002         u16 mode;
1003         struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
1004         struct asix_data *data = (struct asix_data *)&dev->data;
1005         u32 speed;
1006
1007         netdev_dbg(dev->net, "ax88178_link_reset()\n");
1008
1009         mii_check_media(&dev->mii, 1, 1);
1010         mii_ethtool_gset(&dev->mii, &ecmd);
1011         mode = AX88178_MEDIUM_DEFAULT;
1012         speed = ethtool_cmd_speed(&ecmd);
1013
1014         if (speed == SPEED_1000)
1015                 mode |= AX_MEDIUM_GM;
1016         else if (speed == SPEED_100)
1017                 mode |= AX_MEDIUM_PS;
1018         else
1019                 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1020
1021         mode |= AX_MEDIUM_ENCK;
1022
1023         if (ecmd.duplex == DUPLEX_FULL)
1024                 mode |= AX_MEDIUM_FD;
1025         else
1026                 mode &= ~AX_MEDIUM_FD;
1027
1028         netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
1029                    speed, ecmd.duplex, mode);
1030
1031         asix_write_medium_mode(dev, mode, 0);
1032
1033         if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1034                 marvell_led_status(dev, speed);
1035
1036         return 0;
1037 }
1038
1039 static void ax88178_set_mfb(struct usbnet *dev)
1040 {
1041         u16 mfb = AX_RX_CTL_MFB_16384;
1042         u16 rxctl;
1043         u16 medium;
1044         int old_rx_urb_size = dev->rx_urb_size;
1045
1046         if (dev->hard_mtu < 2048) {
1047                 dev->rx_urb_size = 2048;
1048                 mfb = AX_RX_CTL_MFB_2048;
1049         } else if (dev->hard_mtu < 4096) {
1050                 dev->rx_urb_size = 4096;
1051                 mfb = AX_RX_CTL_MFB_4096;
1052         } else if (dev->hard_mtu < 8192) {
1053                 dev->rx_urb_size = 8192;
1054                 mfb = AX_RX_CTL_MFB_8192;
1055         } else if (dev->hard_mtu < 16384) {
1056                 dev->rx_urb_size = 16384;
1057                 mfb = AX_RX_CTL_MFB_16384;
1058         }
1059
1060         rxctl = asix_read_rx_ctl(dev, 0);
1061         asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
1062
1063         medium = asix_read_medium_status(dev, 0);
1064         if (dev->net->mtu > 1500)
1065                 medium |= AX_MEDIUM_JFE;
1066         else
1067                 medium &= ~AX_MEDIUM_JFE;
1068         asix_write_medium_mode(dev, medium, 0);
1069
1070         if (dev->rx_urb_size > old_rx_urb_size)
1071                 usbnet_unlink_rx_urbs(dev);
1072 }
1073
1074 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1075 {
1076         struct usbnet *dev = netdev_priv(net);
1077         int ll_mtu = new_mtu + net->hard_header_len + 4;
1078
1079         netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1080
1081         if ((ll_mtu % dev->maxpacket) == 0)
1082                 return -EDOM;
1083
1084         net->mtu = new_mtu;
1085         dev->hard_mtu = net->mtu + net->hard_header_len;
1086         ax88178_set_mfb(dev);
1087
1088         /* max qlen depend on hard_mtu and rx_urb_size */
1089         usbnet_update_max_qlen(dev);
1090
1091         return 0;
1092 }
1093
1094 static const struct net_device_ops ax88178_netdev_ops = {
1095         .ndo_open               = usbnet_open,
1096         .ndo_stop               = usbnet_stop,
1097         .ndo_start_xmit         = usbnet_start_xmit,
1098         .ndo_tx_timeout         = usbnet_tx_timeout,
1099         .ndo_get_stats64        = dev_get_tstats64,
1100         .ndo_set_mac_address    = asix_set_mac_address,
1101         .ndo_validate_addr      = eth_validate_addr,
1102         .ndo_set_rx_mode        = asix_set_multicast,
1103         .ndo_do_ioctl           = asix_ioctl,
1104         .ndo_change_mtu         = ax88178_change_mtu,
1105 };
1106
1107 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1108 {
1109         int ret;
1110         u8 buf[ETH_ALEN] = {0};
1111
1112         usbnet_get_endpoints(dev,intf);
1113
1114         /* Get the MAC address */
1115         ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
1116         if (ret < 0) {
1117                 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
1118                 return ret;
1119         }
1120
1121         asix_set_netdev_dev_addr(dev, buf);
1122
1123         /* Initialize MII structure */
1124         dev->mii.dev = dev->net;
1125         dev->mii.mdio_read = asix_mdio_read;
1126         dev->mii.mdio_write = asix_mdio_write;
1127         dev->mii.phy_id_mask = 0x1f;
1128         dev->mii.reg_num_mask = 0xff;
1129         dev->mii.supports_gmii = 1;
1130
1131         dev->mii.phy_id = asix_read_phy_addr(dev, true);
1132         if (dev->mii.phy_id < 0)
1133                 return dev->mii.phy_id;
1134
1135         dev->net->netdev_ops = &ax88178_netdev_ops;
1136         dev->net->ethtool_ops = &ax88178_ethtool_ops;
1137         dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
1138
1139         /* Blink LEDS so users know driver saw dongle */
1140         asix_sw_reset(dev, 0, 0);
1141         msleep(150);
1142
1143         asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1144         msleep(150);
1145
1146         /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1147         if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1148                 /* hard_mtu  is still the default - the device does not support
1149                    jumbo eth frames */
1150                 dev->rx_urb_size = 2048;
1151         }
1152
1153         dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1154         if (!dev->driver_priv)
1155                         return -ENOMEM;
1156
1157         return 0;
1158 }
1159
1160 static const struct driver_info ax8817x_info = {
1161         .description = "ASIX AX8817x USB 2.0 Ethernet",
1162         .bind = ax88172_bind,
1163         .status = asix_status,
1164         .link_reset = ax88172_link_reset,
1165         .reset = ax88172_link_reset,
1166         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1167         .data = 0x00130103,
1168 };
1169
1170 static const struct driver_info dlink_dub_e100_info = {
1171         .description = "DLink DUB-E100 USB Ethernet",
1172         .bind = ax88172_bind,
1173         .status = asix_status,
1174         .link_reset = ax88172_link_reset,
1175         .reset = ax88172_link_reset,
1176         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1177         .data = 0x009f9d9f,
1178 };
1179
1180 static const struct driver_info netgear_fa120_info = {
1181         .description = "Netgear FA-120 USB Ethernet",
1182         .bind = ax88172_bind,
1183         .status = asix_status,
1184         .link_reset = ax88172_link_reset,
1185         .reset = ax88172_link_reset,
1186         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1187         .data = 0x00130103,
1188 };
1189
1190 static const struct driver_info hawking_uf200_info = {
1191         .description = "Hawking UF200 USB Ethernet",
1192         .bind = ax88172_bind,
1193         .status = asix_status,
1194         .link_reset = ax88172_link_reset,
1195         .reset = ax88172_link_reset,
1196         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1197         .data = 0x001f1d1f,
1198 };
1199
1200 static const struct driver_info ax88772_info = {
1201         .description = "ASIX AX88772 USB 2.0 Ethernet",
1202         .bind = ax88772_bind,
1203         .unbind = ax88772_unbind,
1204         .status = asix_status,
1205         .reset = ax88772_reset,
1206         .stop = ax88772_stop,
1207         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
1208         .rx_fixup = asix_rx_fixup_common,
1209         .tx_fixup = asix_tx_fixup,
1210 };
1211
1212 static const struct driver_info ax88772b_info = {
1213         .description = "ASIX AX88772B USB 2.0 Ethernet",
1214         .bind = ax88772_bind,
1215         .unbind = ax88772_unbind,
1216         .status = asix_status,
1217         .reset = ax88772_reset,
1218         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1219                  FLAG_MULTI_PACKET,
1220         .rx_fixup = asix_rx_fixup_common,
1221         .tx_fixup = asix_tx_fixup,
1222         .data = FLAG_EEPROM_MAC,
1223 };
1224
1225 static const struct driver_info ax88178_info = {
1226         .description = "ASIX AX88178 USB 2.0 Ethernet",
1227         .bind = ax88178_bind,
1228         .unbind = ax88772_unbind,
1229         .status = asix_status,
1230         .link_reset = ax88178_link_reset,
1231         .reset = ax88178_reset,
1232         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1233                  FLAG_MULTI_PACKET,
1234         .rx_fixup = asix_rx_fixup_common,
1235         .tx_fixup = asix_tx_fixup,
1236 };
1237
1238 /*
1239  * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1240  * no-name packaging.
1241  * USB device strings are:
1242  *   1: Manufacturer: USBLINK
1243  *   2: Product: HG20F9 USB2.0
1244  *   3: Serial: 000003
1245  * Appears to be compatible with Asix 88772B.
1246  */
1247 static const struct driver_info hg20f9_info = {
1248         .description = "HG20F9 USB 2.0 Ethernet",
1249         .bind = ax88772_bind,
1250         .unbind = ax88772_unbind,
1251         .status = asix_status,
1252         .reset = ax88772_reset,
1253         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1254                  FLAG_MULTI_PACKET,
1255         .rx_fixup = asix_rx_fixup_common,
1256         .tx_fixup = asix_tx_fixup,
1257         .data = FLAG_EEPROM_MAC,
1258 };
1259
1260 static const struct usb_device_id       products [] = {
1261 {
1262         // Linksys USB200M
1263         USB_DEVICE (0x077b, 0x2226),
1264         .driver_info =  (unsigned long) &ax8817x_info,
1265 }, {
1266         // Netgear FA120
1267         USB_DEVICE (0x0846, 0x1040),
1268         .driver_info =  (unsigned long) &netgear_fa120_info,
1269 }, {
1270         // DLink DUB-E100
1271         USB_DEVICE (0x2001, 0x1a00),
1272         .driver_info =  (unsigned long) &dlink_dub_e100_info,
1273 }, {
1274         // Intellinet, ST Lab USB Ethernet
1275         USB_DEVICE (0x0b95, 0x1720),
1276         .driver_info =  (unsigned long) &ax8817x_info,
1277 }, {
1278         // Hawking UF200, TrendNet TU2-ET100
1279         USB_DEVICE (0x07b8, 0x420a),
1280         .driver_info =  (unsigned long) &hawking_uf200_info,
1281 }, {
1282         // Billionton Systems, USB2AR
1283         USB_DEVICE (0x08dd, 0x90ff),
1284         .driver_info =  (unsigned long) &ax8817x_info,
1285 }, {
1286         // Billionton Systems, GUSB2AM-1G-B
1287         USB_DEVICE(0x08dd, 0x0114),
1288         .driver_info =  (unsigned long) &ax88178_info,
1289 }, {
1290         // ATEN UC210T
1291         USB_DEVICE (0x0557, 0x2009),
1292         .driver_info =  (unsigned long) &ax8817x_info,
1293 }, {
1294         // Buffalo LUA-U2-KTX
1295         USB_DEVICE (0x0411, 0x003d),
1296         .driver_info =  (unsigned long) &ax8817x_info,
1297 }, {
1298         // Buffalo LUA-U2-GT 10/100/1000
1299         USB_DEVICE (0x0411, 0x006e),
1300         .driver_info =  (unsigned long) &ax88178_info,
1301 }, {
1302         // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1303         USB_DEVICE (0x6189, 0x182d),
1304         .driver_info =  (unsigned long) &ax8817x_info,
1305 }, {
1306         // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1307         USB_DEVICE (0x0df6, 0x0056),
1308         .driver_info =  (unsigned long) &ax88178_info,
1309 }, {
1310         // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1311         USB_DEVICE (0x0df6, 0x061c),
1312         .driver_info =  (unsigned long) &ax88178_info,
1313 }, {
1314         // corega FEther USB2-TX
1315         USB_DEVICE (0x07aa, 0x0017),
1316         .driver_info =  (unsigned long) &ax8817x_info,
1317 }, {
1318         // Surecom EP-1427X-2
1319         USB_DEVICE (0x1189, 0x0893),
1320         .driver_info = (unsigned long) &ax8817x_info,
1321 }, {
1322         // goodway corp usb gwusb2e
1323         USB_DEVICE (0x1631, 0x6200),
1324         .driver_info = (unsigned long) &ax8817x_info,
1325 }, {
1326         // JVC MP-PRX1 Port Replicator
1327         USB_DEVICE (0x04f1, 0x3008),
1328         .driver_info = (unsigned long) &ax8817x_info,
1329 }, {
1330         // Lenovo U2L100P 10/100
1331         USB_DEVICE (0x17ef, 0x7203),
1332         .driver_info = (unsigned long)&ax88772b_info,
1333 }, {
1334         // ASIX AX88772B 10/100
1335         USB_DEVICE (0x0b95, 0x772b),
1336         .driver_info = (unsigned long) &ax88772b_info,
1337 }, {
1338         // ASIX AX88772 10/100
1339         USB_DEVICE (0x0b95, 0x7720),
1340         .driver_info = (unsigned long) &ax88772_info,
1341 }, {
1342         // ASIX AX88178 10/100/1000
1343         USB_DEVICE (0x0b95, 0x1780),
1344         .driver_info = (unsigned long) &ax88178_info,
1345 }, {
1346         // Logitec LAN-GTJ/U2A
1347         USB_DEVICE (0x0789, 0x0160),
1348         .driver_info = (unsigned long) &ax88178_info,
1349 }, {
1350         // Linksys USB200M Rev 2
1351         USB_DEVICE (0x13b1, 0x0018),
1352         .driver_info = (unsigned long) &ax88772_info,
1353 }, {
1354         // 0Q0 cable ethernet
1355         USB_DEVICE (0x1557, 0x7720),
1356         .driver_info = (unsigned long) &ax88772_info,
1357 }, {
1358         // DLink DUB-E100 H/W Ver B1
1359         USB_DEVICE (0x07d1, 0x3c05),
1360         .driver_info = (unsigned long) &ax88772_info,
1361 }, {
1362         // DLink DUB-E100 H/W Ver B1 Alternate
1363         USB_DEVICE (0x2001, 0x3c05),
1364         .driver_info = (unsigned long) &ax88772_info,
1365 }, {
1366        // DLink DUB-E100 H/W Ver C1
1367        USB_DEVICE (0x2001, 0x1a02),
1368        .driver_info = (unsigned long) &ax88772_info,
1369 }, {
1370         // Linksys USB1000
1371         USB_DEVICE (0x1737, 0x0039),
1372         .driver_info = (unsigned long) &ax88178_info,
1373 }, {
1374         // IO-DATA ETG-US2
1375         USB_DEVICE (0x04bb, 0x0930),
1376         .driver_info = (unsigned long) &ax88178_info,
1377 }, {
1378         // Belkin F5D5055
1379         USB_DEVICE(0x050d, 0x5055),
1380         .driver_info = (unsigned long) &ax88178_info,
1381 }, {
1382         // Apple USB Ethernet Adapter
1383         USB_DEVICE(0x05ac, 0x1402),
1384         .driver_info = (unsigned long) &ax88772_info,
1385 }, {
1386         // Cables-to-Go USB Ethernet Adapter
1387         USB_DEVICE(0x0b95, 0x772a),
1388         .driver_info = (unsigned long) &ax88772_info,
1389 }, {
1390         // ABOCOM for pci
1391         USB_DEVICE(0x14ea, 0xab11),
1392         .driver_info = (unsigned long) &ax88178_info,
1393 }, {
1394         // ASIX 88772a
1395         USB_DEVICE(0x0db0, 0xa877),
1396         .driver_info = (unsigned long) &ax88772_info,
1397 }, {
1398         // Asus USB Ethernet Adapter
1399         USB_DEVICE (0x0b95, 0x7e2b),
1400         .driver_info = (unsigned long)&ax88772b_info,
1401 }, {
1402         /* ASIX 88172a demo board */
1403         USB_DEVICE(0x0b95, 0x172a),
1404         .driver_info = (unsigned long) &ax88172a_info,
1405 }, {
1406         /*
1407          * USBLINK HG20F9 "USB 2.0 LAN"
1408          * Appears to have gazumped Linksys's manufacturer ID but
1409          * doesn't (yet) conflict with any known Linksys product.
1410          */
1411         USB_DEVICE(0x066b, 0x20f9),
1412         .driver_info = (unsigned long) &hg20f9_info,
1413 },
1414         { },            // END
1415 };
1416 MODULE_DEVICE_TABLE(usb, products);
1417
1418 static struct usb_driver asix_driver = {
1419         .name =         DRIVER_NAME,
1420         .id_table =     products,
1421         .probe =        usbnet_probe,
1422         .suspend =      asix_suspend,
1423         .resume =       asix_resume,
1424         .reset_resume = asix_resume,
1425         .disconnect =   usbnet_disconnect,
1426         .supports_autosuspend = 1,
1427         .disable_hub_initiated_lpm = 1,
1428 };
1429
1430 module_usb_driver(asix_driver);
1431
1432 MODULE_AUTHOR("David Hollis");
1433 MODULE_VERSION(DRIVER_VERSION);
1434 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1435 MODULE_LICENSE("GPL");
1436