2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
157 "Supreme", /* 0xb9 */
160 static void sky2_set_multicast(struct net_device *dev);
162 /* Access to PHY via serial interconnect */
163 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
171 for (i = 0; i < PHY_RETRIES; i++) {
172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
176 if (!(ctrl & GM_SMI_CT_BUSY))
182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
190 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
197 for (i = 0; i < PHY_RETRIES; i++) {
198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
202 if (ctrl & GM_SMI_CT_RD_VAL) {
203 *val = gma_read16(hw, port, GM_SMI_DATA);
210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
217 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
220 __gm_phy_read(hw, port, reg, &v);
225 static void sky2_power_on(struct sky2_hw *hw)
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
265 sky2_read32(hw, B2_GP_IO);
269 static void sky2_power_aux(struct sky2_hw *hw)
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
287 static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
289 u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
290 int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
293 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
310 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
311 /* additional power saving measurements */
312 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
314 /* set gating core clock for LTSSM in L1 state */
315 reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
316 /* auto clock gated scheme controlled by CLKREQ */
317 P_ASPM_A1_MODE_SELECT |
318 /* enable Gate Root Core Clock */
319 P_CLK_GATE_ROOT_COR_ENA;
321 if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
322 /* enable Clock Power Management (CLKREQ) */
323 u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
325 ctrl |= PCI_EXP_DEVCTL_AUX_PME;
326 sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
328 /* force CLKREQ Enable in Our4 (A1b only) */
329 reg |= P_ASPM_FORCE_CLKREQ_ENA;
331 /* set Mask Register for Release/Gate Clock */
332 sky2_pci_write32(hw, PCI_DEV_REG5,
333 P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
334 P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
335 P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
337 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
339 /* put CPU into reset state */
340 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
341 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
342 /* put CPU into halt state */
343 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
345 if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
346 reg = sky2_pci_read32(hw, PCI_DEV_REG1);
347 /* force to PCIe L1 */
348 reg |= PCI_FORCE_PEX_L1;
349 sky2_pci_write32(hw, PCI_DEV_REG1, reg);
354 dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
359 power_control |= PCI_PM_CTRL_PME_ENABLE;
360 /* Finally, set the new power state. */
361 sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
363 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
364 sky2_pci_read32(hw, B0_CTST);
367 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
371 /* disable all GMAC IRQ's */
372 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
374 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
375 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
376 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
377 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
379 reg = gma_read16(hw, port, GM_RX_CTRL);
380 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
381 gma_write16(hw, port, GM_RX_CTRL, reg);
384 /* flow control to advertise bits */
385 static const u16 copper_fc_adv[] = {
387 [FC_TX] = PHY_M_AN_ASP,
388 [FC_RX] = PHY_M_AN_PC,
389 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
392 /* flow control to advertise bits when using 1000BaseX */
393 static const u16 fiber_fc_adv[] = {
394 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
395 [FC_TX] = PHY_M_P_ASYM_MD_X,
396 [FC_RX] = PHY_M_P_SYM_MD_X,
397 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
400 /* flow control to GMA disable bits */
401 static const u16 gm_fc_disable[] = {
402 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
403 [FC_TX] = GM_GPCR_FC_RX_DIS,
404 [FC_RX] = GM_GPCR_FC_TX_DIS,
409 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
411 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
412 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
414 if (sky2->autoneg == AUTONEG_ENABLE &&
415 !(hw->flags & SKY2_HW_NEWER_PHY)) {
416 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
418 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
420 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
422 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
423 if (hw->chip_id == CHIP_ID_YUKON_EC)
424 /* set downshift counter to 3x and enable downshift */
425 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
427 /* set master & slave downshift counter to 1x */
428 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
430 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
433 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
434 if (sky2_is_copper(hw)) {
435 if (!(hw->flags & SKY2_HW_GIGABIT)) {
436 /* enable automatic crossover */
437 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
439 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
440 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
443 /* Enable Class A driver for FE+ A0 */
444 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
445 spec |= PHY_M_FESC_SEL_CL_A;
446 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
449 /* disable energy detect */
450 ctrl &= ~PHY_M_PC_EN_DET_MSK;
452 /* enable automatic crossover */
453 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
455 /* downshift on PHY 88E1112 and 88E1149 is changed */
456 if (sky2->autoneg == AUTONEG_ENABLE
457 && (hw->flags & SKY2_HW_NEWER_PHY)) {
458 /* set downshift counter to 3x and enable downshift */
459 ctrl &= ~PHY_M_PC_DSC_MSK;
460 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
464 /* workaround for deviation #4.88 (CRC errors) */
465 /* disable Automatic Crossover */
467 ctrl &= ~PHY_M_PC_MDIX_MSK;
470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
472 /* special setup for PHY 88E1112 Fiber */
473 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
474 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
476 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
477 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
478 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
479 ctrl &= ~PHY_M_MAC_MD_MSK;
480 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
483 if (hw->pmd_type == 'P') {
484 /* select page 1 to access Fiber registers */
485 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
487 /* for SFP-module set SIGDET polarity to low */
488 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
489 ctrl |= PHY_M_FIB_SIGD_POL;
490 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
501 if (sky2->autoneg == AUTONEG_ENABLE) {
502 if (sky2_is_copper(hw)) {
503 if (sky2->advertising & ADVERTISED_1000baseT_Full)
504 ct1000 |= PHY_M_1000C_AFD;
505 if (sky2->advertising & ADVERTISED_1000baseT_Half)
506 ct1000 |= PHY_M_1000C_AHD;
507 if (sky2->advertising & ADVERTISED_100baseT_Full)
508 adv |= PHY_M_AN_100_FD;
509 if (sky2->advertising & ADVERTISED_100baseT_Half)
510 adv |= PHY_M_AN_100_HD;
511 if (sky2->advertising & ADVERTISED_10baseT_Full)
512 adv |= PHY_M_AN_10_FD;
513 if (sky2->advertising & ADVERTISED_10baseT_Half)
514 adv |= PHY_M_AN_10_HD;
516 adv |= copper_fc_adv[sky2->flow_mode];
517 } else { /* special defines for FIBER (88E1040S only) */
518 if (sky2->advertising & ADVERTISED_1000baseT_Full)
519 adv |= PHY_M_AN_1000X_AFD;
520 if (sky2->advertising & ADVERTISED_1000baseT_Half)
521 adv |= PHY_M_AN_1000X_AHD;
523 adv |= fiber_fc_adv[sky2->flow_mode];
526 /* Restart Auto-negotiation */
527 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
529 /* forced speed/duplex settings */
530 ct1000 = PHY_M_1000C_MSE;
532 /* Disable auto update for duplex flow control and speed */
533 reg |= GM_GPCR_AU_ALL_DIS;
535 switch (sky2->speed) {
537 ctrl |= PHY_CT_SP1000;
538 reg |= GM_GPCR_SPEED_1000;
541 ctrl |= PHY_CT_SP100;
542 reg |= GM_GPCR_SPEED_100;
546 if (sky2->duplex == DUPLEX_FULL) {
547 reg |= GM_GPCR_DUP_FULL;
548 ctrl |= PHY_CT_DUP_MD;
549 } else if (sky2->speed < SPEED_1000)
550 sky2->flow_mode = FC_NONE;
553 reg |= gm_fc_disable[sky2->flow_mode];
555 /* Forward pause packets to GMAC? */
556 if (sky2->flow_mode & FC_RX)
557 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
559 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
562 gma_write16(hw, port, GM_GP_CTRL, reg);
564 if (hw->flags & SKY2_HW_GIGABIT)
565 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
567 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
568 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
570 /* Setup Phy LED's */
571 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
574 switch (hw->chip_id) {
575 case CHIP_ID_YUKON_FE:
576 /* on 88E3082 these bits are at 11..9 (shifted left) */
577 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
579 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
581 /* delete ACT LED control bits */
582 ctrl &= ~PHY_M_FELP_LED1_MSK;
583 /* change ACT LED control to blink mode */
584 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
585 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
588 case CHIP_ID_YUKON_FE_P:
589 /* Enable Link Partner Next Page */
590 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
591 ctrl |= PHY_M_PC_ENA_LIP_NP;
593 /* disable Energy Detect and enable scrambler */
594 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
595 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
597 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
598 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
599 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
600 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
602 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
605 case CHIP_ID_YUKON_XL:
606 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
608 /* select page 3 to access LED control register */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
611 /* set LED Function Control register */
612 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
613 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
614 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
615 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
616 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
618 /* set Polarity Control register */
619 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
620 (PHY_M_POLC_LS1_P_MIX(4) |
621 PHY_M_POLC_IS0_P_MIX(4) |
622 PHY_M_POLC_LOS_CTRL(2) |
623 PHY_M_POLC_INIT_CTRL(2) |
624 PHY_M_POLC_STA1_CTRL(2) |
625 PHY_M_POLC_STA0_CTRL(2)));
627 /* restore page register */
628 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
631 case CHIP_ID_YUKON_EC_U:
632 case CHIP_ID_YUKON_EX:
633 case CHIP_ID_YUKON_SUPR:
634 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
636 /* select page 3 to access LED control register */
637 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
639 /* set LED Function Control register */
640 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
641 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
642 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
643 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
644 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
646 /* set Blink Rate in LED Timer Control Register */
647 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
648 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
649 /* restore page register */
650 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
654 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
655 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
657 /* turn off the Rx LED (LED_RX) */
658 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
661 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
662 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
663 /* apply fixes in PHY AFE */
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
666 /* increase differential signal amplitude in 10BASE-T */
667 gm_phy_write(hw, port, 0x18, 0xaa99);
668 gm_phy_write(hw, port, 0x17, 0x2011);
670 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
671 gm_phy_write(hw, port, 0x18, 0xa204);
672 gm_phy_write(hw, port, 0x17, 0x2002);
674 /* set page register to 0 */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
676 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
677 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
678 /* apply workaround for integrated resistors calibration */
679 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
680 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
681 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
682 /* no effect on Yukon-XL */
683 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
685 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
686 /* turn on 100 Mbps LED (LED_LINK100) */
687 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
691 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
695 /* Enable phy interrupt on auto-negotiation complete (or link up) */
696 if (sky2->autoneg == AUTONEG_ENABLE)
697 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
699 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
702 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
703 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
705 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
709 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
711 reg1 &= ~phy_power[port];
713 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
714 reg1 |= coma_mode[port];
716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
718 sky2_pci_read32(hw, PCI_DEV_REG1);
721 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
726 /* release GPHY Control reset */
727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
729 /* release GMAC reset */
730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
732 if (hw->flags & SKY2_HW_NEWER_PHY) {
733 /* select page 2 to access MAC control register */
734 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
736 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
737 /* allow GMII Power Down */
738 ctrl &= ~PHY_M_MAC_GMIF_PUP;
739 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
741 /* set page register back to 0 */
742 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
745 /* setup General Purpose Control Register */
746 gma_write16(hw, port, GM_GP_CTRL,
747 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
749 if (hw->chip_id != CHIP_ID_YUKON_EC) {
750 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
751 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
753 /* enable Power Down */
754 ctrl |= PHY_M_PC_POW_D_ENA;
755 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
758 /* set IEEE compatible Power Down Mode (dev. #4.99) */
759 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
762 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
763 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
764 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
765 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
766 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
769 /* Force a renegotiation */
770 static void sky2_phy_reinit(struct sky2_port *sky2)
772 spin_lock_bh(&sky2->phy_lock);
773 sky2_phy_init(sky2->hw, sky2->port);
774 spin_unlock_bh(&sky2->phy_lock);
777 /* Put device in state to listen for Wake On Lan */
778 static void sky2_wol_init(struct sky2_port *sky2)
780 struct sky2_hw *hw = sky2->hw;
781 unsigned port = sky2->port;
782 enum flow_control save_mode;
786 /* Bring hardware out of reset */
787 sky2_write16(hw, B0_CTST, CS_RST_CLR);
788 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
790 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
791 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
794 * sky2_reset will re-enable on resume
796 save_mode = sky2->flow_mode;
797 ctrl = sky2->advertising;
799 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
800 sky2->flow_mode = FC_NONE;
802 spin_lock_bh(&sky2->phy_lock);
803 sky2_phy_power_up(hw, port);
804 sky2_phy_init(hw, port);
805 spin_unlock_bh(&sky2->phy_lock);
807 sky2->flow_mode = save_mode;
808 sky2->advertising = ctrl;
810 /* Set GMAC to no flow control and auto update for speed/duplex */
811 gma_write16(hw, port, GM_GP_CTRL,
812 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
813 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
815 /* Set WOL address */
816 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
817 sky2->netdev->dev_addr, ETH_ALEN);
819 /* Turn on appropriate WOL control bits */
820 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
822 if (sky2->wol & WAKE_PHY)
823 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
825 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
827 if (sky2->wol & WAKE_MAGIC)
828 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
830 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
832 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
833 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
835 /* Turn on legacy PCI-Express PME mode */
836 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
837 reg1 |= PCI_Y2_PME_LEGACY;
838 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
841 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
845 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
847 struct net_device *dev = hw->dev[port];
849 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
850 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
851 hw->chip_id == CHIP_ID_YUKON_FE_P ||
852 hw->chip_id == CHIP_ID_YUKON_SUPR) {
853 /* Yukon-Extreme B0 and further Extreme devices */
854 /* enable Store & Forward mode for TX */
856 if (dev->mtu <= ETH_DATA_LEN)
857 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
858 TX_JUMBO_DIS | TX_STFW_ENA);
861 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
862 TX_JUMBO_ENA| TX_STFW_ENA);
864 if (dev->mtu <= ETH_DATA_LEN)
865 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
867 /* set Tx GMAC FIFO Almost Empty Threshold */
868 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
869 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
871 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
873 /* Can't do offload because of lack of store/forward */
874 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
879 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
881 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
885 const u8 *addr = hw->dev[port]->dev_addr;
887 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
888 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
890 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
892 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
893 /* WA DEV_472 -- looks like crossed wires on port 2 */
894 /* clear GMAC 1 Control reset */
895 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
897 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
898 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
899 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
900 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
901 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
904 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
906 /* Enable Transmit FIFO Underrun */
907 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
909 spin_lock_bh(&sky2->phy_lock);
910 sky2_phy_power_up(hw, port);
911 sky2_phy_init(hw, port);
912 spin_unlock_bh(&sky2->phy_lock);
915 reg = gma_read16(hw, port, GM_PHY_ADDR);
916 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
918 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
919 gma_read16(hw, port, i);
920 gma_write16(hw, port, GM_PHY_ADDR, reg);
922 /* transmit control */
923 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
925 /* receive control reg: unicast + multicast + no FCS */
926 gma_write16(hw, port, GM_RX_CTRL,
927 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
929 /* transmit flow control */
930 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
932 /* transmit parameter */
933 gma_write16(hw, port, GM_TX_PARAM,
934 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
935 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
936 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
937 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
939 /* serial mode register */
940 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
941 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
943 if (hw->dev[port]->mtu > ETH_DATA_LEN)
944 reg |= GM_SMOD_JUMBO_ENA;
946 gma_write16(hw, port, GM_SERIAL_MODE, reg);
948 /* virtual address for data */
949 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
951 /* physical address: used for pause frames */
952 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
954 /* ignore counter overflows */
955 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
956 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
957 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
959 /* Configure Rx MAC FIFO */
960 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
961 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
962 if (hw->chip_id == CHIP_ID_YUKON_EX ||
963 hw->chip_id == CHIP_ID_YUKON_FE_P)
964 rx_reg |= GMF_RX_OVER_ON;
966 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
968 if (hw->chip_id == CHIP_ID_YUKON_XL) {
969 /* Hardware errata - clear flush mask */
970 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
972 /* Flush Rx MAC FIFO on any flow control or error */
973 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
976 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
977 reg = RX_GMF_FL_THR_DEF + 1;
978 /* Another magic mystery workaround from sk98lin */
979 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
980 hw->chip_rev == CHIP_REV_YU_FE2_A0)
982 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
984 /* Configure Tx MAC FIFO */
985 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
986 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
988 /* On chips without ram buffer, pause is controled by MAC level */
989 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
990 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
991 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
993 sky2_set_tx_stfwd(hw, port);
996 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
997 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
998 /* disable dynamic watermark */
999 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1000 reg &= ~TX_DYN_WM_ENA;
1001 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1005 /* Assign Ram Buffer allocation to queue */
1006 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1010 /* convert from K bytes to qwords used for hw register */
1013 end = start + space - 1;
1015 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1016 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1017 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1018 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1019 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1021 if (q == Q_R1 || q == Q_R2) {
1022 u32 tp = space - space/4;
1024 /* On receive queue's set the thresholds
1025 * give receiver priority when > 3/4 full
1026 * send pause when down to 2K
1028 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1029 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1031 tp = space - 2048/8;
1032 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1033 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1035 /* Enable store & forward on Tx queue's because
1036 * Tx FIFO is only 1K on Yukon
1038 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1041 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1042 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1045 /* Setup Bus Memory Interface */
1046 static void sky2_qset(struct sky2_hw *hw, u16 q)
1048 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1049 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1050 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1051 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1054 /* Setup prefetch unit registers. This is the interface between
1055 * hardware and driver list elements
1057 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1060 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1061 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1062 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
1063 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
1064 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1065 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1067 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1070 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
1072 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
1074 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
1079 static void tx_init(struct sky2_port *sky2)
1081 struct sky2_tx_le *le;
1083 sky2->tx_prod = sky2->tx_cons = 0;
1084 sky2->tx_tcpsum = 0;
1085 sky2->tx_last_mss = 0;
1087 le = get_tx_le(sky2);
1089 le->opcode = OP_ADDR64 | HW_OWNER;
1092 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1093 struct sky2_tx_le *le)
1095 return sky2->tx_ring + (le - sky2->tx_le);
1098 /* Update chip's next pointer */
1099 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1101 /* Make sure write' to descriptors are complete before we tell hardware */
1103 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1105 /* Synchronize I/O on since next processor may write to tail */
1110 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1112 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1113 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1118 /* Build description to hardware for one receive segment */
1119 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1120 dma_addr_t map, unsigned len)
1122 struct sky2_rx_le *le;
1124 if (sizeof(dma_addr_t) > sizeof(u32)) {
1125 le = sky2_next_rx(sky2);
1126 le->addr = cpu_to_le32(upper_32_bits(map));
1127 le->opcode = OP_ADDR64 | HW_OWNER;
1130 le = sky2_next_rx(sky2);
1131 le->addr = cpu_to_le32((u32) map);
1132 le->length = cpu_to_le16(len);
1133 le->opcode = op | HW_OWNER;
1136 /* Build description to hardware for one possibly fragmented skb */
1137 static void sky2_rx_submit(struct sky2_port *sky2,
1138 const struct rx_ring_info *re)
1142 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1144 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1145 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1149 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1152 struct sk_buff *skb = re->skb;
1155 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1156 pci_unmap_len_set(re, data_size, size);
1158 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1159 re->frag_addr[i] = pci_map_page(pdev,
1160 skb_shinfo(skb)->frags[i].page,
1161 skb_shinfo(skb)->frags[i].page_offset,
1162 skb_shinfo(skb)->frags[i].size,
1163 PCI_DMA_FROMDEVICE);
1166 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1168 struct sk_buff *skb = re->skb;
1171 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1172 PCI_DMA_FROMDEVICE);
1174 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1175 pci_unmap_page(pdev, re->frag_addr[i],
1176 skb_shinfo(skb)->frags[i].size,
1177 PCI_DMA_FROMDEVICE);
1180 /* Tell chip where to start receive checksum.
1181 * Actually has two checksums, but set both same to avoid possible byte
1184 static void rx_set_checksum(struct sky2_port *sky2)
1186 struct sky2_rx_le *le = sky2_next_rx(sky2);
1188 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1190 le->opcode = OP_TCPSTART | HW_OWNER;
1192 sky2_write32(sky2->hw,
1193 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1194 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1198 * The RX Stop command will not work for Yukon-2 if the BMU does not
1199 * reach the end of packet and since we can't make sure that we have
1200 * incoming data, we must reset the BMU while it is not doing a DMA
1201 * transfer. Since it is possible that the RX path is still active,
1202 * the RX RAM buffer will be stopped first, so any possible incoming
1203 * data will not trigger a DMA. After the RAM buffer is stopped, the
1204 * BMU is polled until any DMA in progress is ended and only then it
1207 static void sky2_rx_stop(struct sky2_port *sky2)
1209 struct sky2_hw *hw = sky2->hw;
1210 unsigned rxq = rxqaddr[sky2->port];
1213 /* disable the RAM Buffer receive queue */
1214 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1216 for (i = 0; i < 0xffff; i++)
1217 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1218 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1221 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1222 sky2->netdev->name);
1224 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1226 /* reset the Rx prefetch unit */
1227 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1231 /* Clean out receive buffer area, assumes receiver hardware stopped */
1232 static void sky2_rx_clean(struct sky2_port *sky2)
1236 memset(sky2->rx_le, 0, RX_LE_BYTES);
1237 for (i = 0; i < sky2->rx_pending; i++) {
1238 struct rx_ring_info *re = sky2->rx_ring + i;
1241 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1248 /* Basic MII support */
1249 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1251 struct mii_ioctl_data *data = if_mii(ifr);
1252 struct sky2_port *sky2 = netdev_priv(dev);
1253 struct sky2_hw *hw = sky2->hw;
1254 int err = -EOPNOTSUPP;
1256 if (!netif_running(dev))
1257 return -ENODEV; /* Phy still in reset */
1261 data->phy_id = PHY_ADDR_MARV;
1267 spin_lock_bh(&sky2->phy_lock);
1268 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1269 spin_unlock_bh(&sky2->phy_lock);
1271 data->val_out = val;
1276 if (!capable(CAP_NET_ADMIN))
1279 spin_lock_bh(&sky2->phy_lock);
1280 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1282 spin_unlock_bh(&sky2->phy_lock);
1288 #ifdef SKY2_VLAN_TAG_USED
1289 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1292 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1294 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1297 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1299 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1304 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1306 struct sky2_port *sky2 = netdev_priv(dev);
1307 struct sky2_hw *hw = sky2->hw;
1308 u16 port = sky2->port;
1310 netif_tx_lock_bh(dev);
1311 napi_disable(&hw->napi);
1314 sky2_set_vlan_mode(hw, port, grp != NULL);
1316 sky2_read32(hw, B0_Y2_SP_LISR);
1317 napi_enable(&hw->napi);
1318 netif_tx_unlock_bh(dev);
1323 * Allocate an skb for receiving. If the MTU is large enough
1324 * make the skb non-linear with a fragment list of pages.
1326 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1328 struct sk_buff *skb;
1331 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1332 unsigned char *start;
1334 * Workaround for a bug in FIFO that cause hang
1335 * if the FIFO if the receive buffer is not 64 byte aligned.
1336 * The buffer returned from netdev_alloc_skb is
1337 * aligned except if slab debugging is enabled.
1339 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1342 start = PTR_ALIGN(skb->data, 8);
1343 skb_reserve(skb, start - skb->data);
1345 skb = netdev_alloc_skb(sky2->netdev,
1346 sky2->rx_data_size + NET_IP_ALIGN);
1349 skb_reserve(skb, NET_IP_ALIGN);
1352 for (i = 0; i < sky2->rx_nfrags; i++) {
1353 struct page *page = alloc_page(GFP_ATOMIC);
1357 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1367 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1369 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1373 * Allocate and setup receiver buffer pool.
1374 * Normal case this ends up creating one list element for skb
1375 * in the receive ring. Worst case if using large MTU and each
1376 * allocation falls on a different 64 bit region, that results
1377 * in 6 list elements per ring entry.
1378 * One element is used for checksum enable/disable, and one
1379 * extra to avoid wrap.
1381 static int sky2_rx_start(struct sky2_port *sky2)
1383 struct sky2_hw *hw = sky2->hw;
1384 struct rx_ring_info *re;
1385 unsigned rxq = rxqaddr[sky2->port];
1386 unsigned i, size, thresh;
1388 sky2->rx_put = sky2->rx_next = 0;
1391 /* On PCI express lowering the watermark gives better performance */
1392 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1393 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1395 /* These chips have no ram buffer?
1396 * MAC Rx RAM Read is controlled by hardware */
1397 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1398 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1399 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1400 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1402 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1404 if (!(hw->flags & SKY2_HW_NEW_LE))
1405 rx_set_checksum(sky2);
1407 /* Space needed for frame data + headers rounded up */
1408 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1410 /* Stopping point for hardware truncation */
1411 thresh = (size - 8) / sizeof(u32);
1413 sky2->rx_nfrags = size >> PAGE_SHIFT;
1414 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1416 /* Compute residue after pages */
1417 size -= sky2->rx_nfrags << PAGE_SHIFT;
1419 /* Optimize to handle small packets and headers */
1420 if (size < copybreak)
1422 if (size < ETH_HLEN)
1425 sky2->rx_data_size = size;
1428 for (i = 0; i < sky2->rx_pending; i++) {
1429 re = sky2->rx_ring + i;
1431 re->skb = sky2_rx_alloc(sky2);
1435 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1436 sky2_rx_submit(sky2, re);
1440 * The receiver hangs if it receives frames larger than the
1441 * packet buffer. As a workaround, truncate oversize frames, but
1442 * the register is limited to 9 bits, so if you do frames > 2052
1443 * you better get the MTU right!
1446 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1448 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1449 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1452 /* Tell chip about available buffers */
1453 sky2_rx_update(sky2, rxq);
1456 sky2_rx_clean(sky2);
1460 /* Bring up network interface. */
1461 static int sky2_up(struct net_device *dev)
1463 struct sky2_port *sky2 = netdev_priv(dev);
1464 struct sky2_hw *hw = sky2->hw;
1465 unsigned port = sky2->port;
1467 int cap, err = -ENOMEM;
1468 struct net_device *otherdev = hw->dev[sky2->port^1];
1471 * On dual port PCI-X card, there is an problem where status
1472 * can be received out of order due to split transactions
1474 if (otherdev && netif_running(otherdev) &&
1475 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1478 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1479 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1480 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1484 if (netif_msg_ifup(sky2))
1485 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1487 netif_carrier_off(dev);
1489 /* must be power of 2 */
1490 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1492 sizeof(struct sky2_tx_le),
1497 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1504 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1508 memset(sky2->rx_le, 0, RX_LE_BYTES);
1510 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1515 sky2_mac_init(hw, port);
1517 /* Register is number of 4K blocks on internal RAM buffer. */
1518 ramsize = sky2_read8(hw, B2_E_0) * 4;
1522 hw->flags |= SKY2_HW_RAM_BUFFER;
1523 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1525 rxspace = ramsize / 2;
1527 rxspace = 8 + (2*(ramsize - 16))/3;
1529 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1530 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1532 /* Make sure SyncQ is disabled */
1533 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1537 sky2_qset(hw, txqaddr[port]);
1539 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1540 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1541 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1543 /* Set almost empty threshold */
1544 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1545 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1546 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1548 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1551 #ifdef SKY2_VLAN_TAG_USED
1552 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1555 err = sky2_rx_start(sky2);
1559 /* Enable interrupts from phy/mac for port */
1560 imask = sky2_read32(hw, B0_IMSK);
1561 imask |= portirq_msk[port];
1562 sky2_write32(hw, B0_IMSK, imask);
1564 sky2_set_multicast(dev);
1569 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1570 sky2->rx_le, sky2->rx_le_map);
1574 pci_free_consistent(hw->pdev,
1575 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1576 sky2->tx_le, sky2->tx_le_map);
1579 kfree(sky2->tx_ring);
1580 kfree(sky2->rx_ring);
1582 sky2->tx_ring = NULL;
1583 sky2->rx_ring = NULL;
1587 /* Modular subtraction in ring */
1588 static inline int tx_dist(unsigned tail, unsigned head)
1590 return (head - tail) & (TX_RING_SIZE - 1);
1593 /* Number of list elements available for next tx */
1594 static inline int tx_avail(const struct sky2_port *sky2)
1596 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1599 /* Estimate of number of transmit list elements required */
1600 static unsigned tx_le_req(const struct sk_buff *skb)
1604 count = sizeof(dma_addr_t) / sizeof(u32);
1605 count += skb_shinfo(skb)->nr_frags * count;
1607 if (skb_is_gso(skb))
1610 if (skb->ip_summed == CHECKSUM_PARTIAL)
1617 * Put one packet in ring for transmit.
1618 * A single packet can generate multiple list elements, and
1619 * the number of ring elements will probably be less than the number
1620 * of list elements used.
1622 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1624 struct sky2_port *sky2 = netdev_priv(dev);
1625 struct sky2_hw *hw = sky2->hw;
1626 struct sky2_tx_le *le = NULL;
1627 struct tx_ring_info *re;
1633 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1634 return NETDEV_TX_BUSY;
1636 if (unlikely(netif_msg_tx_queued(sky2)))
1637 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1638 dev->name, sky2->tx_prod, skb->len);
1640 len = skb_headlen(skb);
1641 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1643 /* Send high bits if needed */
1644 if (sizeof(dma_addr_t) > sizeof(u32)) {
1645 le = get_tx_le(sky2);
1646 le->addr = cpu_to_le32(upper_32_bits(mapping));
1647 le->opcode = OP_ADDR64 | HW_OWNER;
1650 /* Check for TCP Segmentation Offload */
1651 mss = skb_shinfo(skb)->gso_size;
1654 if (!(hw->flags & SKY2_HW_NEW_LE))
1655 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1657 if (mss != sky2->tx_last_mss) {
1658 le = get_tx_le(sky2);
1659 le->addr = cpu_to_le32(mss);
1661 if (hw->flags & SKY2_HW_NEW_LE)
1662 le->opcode = OP_MSS | HW_OWNER;
1664 le->opcode = OP_LRGLEN | HW_OWNER;
1665 sky2->tx_last_mss = mss;
1670 #ifdef SKY2_VLAN_TAG_USED
1671 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1672 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1674 le = get_tx_le(sky2);
1676 le->opcode = OP_VLAN|HW_OWNER;
1678 le->opcode |= OP_VLAN;
1679 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1684 /* Handle TCP checksum offload */
1685 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1686 /* On Yukon EX (some versions) encoding change. */
1687 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1688 ctrl |= CALSUM; /* auto checksum */
1690 const unsigned offset = skb_transport_offset(skb);
1693 tcpsum = offset << 16; /* sum start */
1694 tcpsum |= offset + skb->csum_offset; /* sum write */
1696 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1697 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1700 if (tcpsum != sky2->tx_tcpsum) {
1701 sky2->tx_tcpsum = tcpsum;
1703 le = get_tx_le(sky2);
1704 le->addr = cpu_to_le32(tcpsum);
1705 le->length = 0; /* initial checksum value */
1706 le->ctrl = 1; /* one packet */
1707 le->opcode = OP_TCPLISW | HW_OWNER;
1712 le = get_tx_le(sky2);
1713 le->addr = cpu_to_le32((u32) mapping);
1714 le->length = cpu_to_le16(len);
1716 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1718 re = tx_le_re(sky2, le);
1720 pci_unmap_addr_set(re, mapaddr, mapping);
1721 pci_unmap_len_set(re, maplen, len);
1723 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1724 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1726 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1727 frag->size, PCI_DMA_TODEVICE);
1729 if (sizeof(dma_addr_t) > sizeof(u32)) {
1730 le = get_tx_le(sky2);
1731 le->addr = cpu_to_le32(upper_32_bits(mapping));
1733 le->opcode = OP_ADDR64 | HW_OWNER;
1736 le = get_tx_le(sky2);
1737 le->addr = cpu_to_le32((u32) mapping);
1738 le->length = cpu_to_le16(frag->size);
1740 le->opcode = OP_BUFFER | HW_OWNER;
1742 re = tx_le_re(sky2, le);
1744 pci_unmap_addr_set(re, mapaddr, mapping);
1745 pci_unmap_len_set(re, maplen, frag->size);
1750 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1751 netif_stop_queue(dev);
1753 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1755 dev->trans_start = jiffies;
1756 return NETDEV_TX_OK;
1760 * Free ring elements from starting at tx_cons until "done"
1762 * NB: the hardware will tell us about partial completion of multi-part
1763 * buffers so make sure not to free skb to early.
1765 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1767 struct net_device *dev = sky2->netdev;
1768 struct pci_dev *pdev = sky2->hw->pdev;
1771 BUG_ON(done >= TX_RING_SIZE);
1773 for (idx = sky2->tx_cons; idx != done;
1774 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1775 struct sky2_tx_le *le = sky2->tx_le + idx;
1776 struct tx_ring_info *re = sky2->tx_ring + idx;
1778 switch(le->opcode & ~HW_OWNER) {
1781 pci_unmap_single(pdev,
1782 pci_unmap_addr(re, mapaddr),
1783 pci_unmap_len(re, maplen),
1787 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1788 pci_unmap_len(re, maplen),
1793 if (le->ctrl & EOP) {
1794 if (unlikely(netif_msg_tx_done(sky2)))
1795 printk(KERN_DEBUG "%s: tx done %u\n",
1798 dev->stats.tx_packets++;
1799 dev->stats.tx_bytes += re->skb->len;
1801 dev_kfree_skb_any(re->skb);
1802 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1806 sky2->tx_cons = idx;
1809 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1810 netif_wake_queue(dev);
1813 /* Cleanup all untransmitted buffers, assume transmitter not running */
1814 static void sky2_tx_clean(struct net_device *dev)
1816 struct sky2_port *sky2 = netdev_priv(dev);
1818 netif_tx_lock_bh(dev);
1819 sky2_tx_complete(sky2, sky2->tx_prod);
1820 netif_tx_unlock_bh(dev);
1823 /* Network shutdown */
1824 static int sky2_down(struct net_device *dev)
1826 struct sky2_port *sky2 = netdev_priv(dev);
1827 struct sky2_hw *hw = sky2->hw;
1828 unsigned port = sky2->port;
1832 /* Never really got started! */
1836 if (netif_msg_ifdown(sky2))
1837 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1839 /* Stop more packets from being queued */
1840 netif_stop_queue(dev);
1842 /* Disable port IRQ */
1843 imask = sky2_read32(hw, B0_IMSK);
1844 imask &= ~portirq_msk[port];
1845 sky2_write32(hw, B0_IMSK, imask);
1847 synchronize_irq(hw->pdev->irq);
1849 sky2_gmac_reset(hw, port);
1851 /* Stop transmitter */
1852 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1853 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1855 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1856 RB_RST_SET | RB_DIS_OP_MD);
1858 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1859 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1860 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1862 /* Make sure no packets are pending */
1863 napi_synchronize(&hw->napi);
1865 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1867 /* Workaround shared GMAC reset */
1868 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1869 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1870 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1872 /* Disable Force Sync bit and Enable Alloc bit */
1873 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1874 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1876 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1877 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1878 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1880 /* Reset the PCI FIFO of the async Tx queue */
1881 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1882 BMU_RST_SET | BMU_FIFO_RST);
1884 /* Reset the Tx prefetch units */
1885 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1888 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1892 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1893 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1895 sky2_phy_power_down(hw, port);
1897 netif_carrier_off(dev);
1899 /* turn off LED's */
1900 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1903 sky2_rx_clean(sky2);
1905 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1906 sky2->rx_le, sky2->rx_le_map);
1907 kfree(sky2->rx_ring);
1909 pci_free_consistent(hw->pdev,
1910 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1911 sky2->tx_le, sky2->tx_le_map);
1912 kfree(sky2->tx_ring);
1917 sky2->rx_ring = NULL;
1918 sky2->tx_ring = NULL;
1923 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1925 if (hw->flags & SKY2_HW_FIBRE_PHY)
1928 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1929 if (aux & PHY_M_PS_SPEED_100)
1935 switch (aux & PHY_M_PS_SPEED_MSK) {
1936 case PHY_M_PS_SPEED_1000:
1938 case PHY_M_PS_SPEED_100:
1945 static void sky2_link_up(struct sky2_port *sky2)
1947 struct sky2_hw *hw = sky2->hw;
1948 unsigned port = sky2->port;
1950 static const char *fc_name[] = {
1958 reg = gma_read16(hw, port, GM_GP_CTRL);
1959 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1960 gma_write16(hw, port, GM_GP_CTRL, reg);
1962 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1964 netif_carrier_on(sky2->netdev);
1966 mod_timer(&hw->watchdog_timer, jiffies + 1);
1968 /* Turn on link LED */
1969 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1970 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1972 if (netif_msg_link(sky2))
1973 printk(KERN_INFO PFX
1974 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1975 sky2->netdev->name, sky2->speed,
1976 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1977 fc_name[sky2->flow_status]);
1980 static void sky2_link_down(struct sky2_port *sky2)
1982 struct sky2_hw *hw = sky2->hw;
1983 unsigned port = sky2->port;
1986 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1988 reg = gma_read16(hw, port, GM_GP_CTRL);
1989 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1990 gma_write16(hw, port, GM_GP_CTRL, reg);
1992 netif_carrier_off(sky2->netdev);
1994 /* Turn on link LED */
1995 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1997 if (netif_msg_link(sky2))
1998 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2000 sky2_phy_init(hw, port);
2003 static enum flow_control sky2_flow(int rx, int tx)
2006 return tx ? FC_BOTH : FC_RX;
2008 return tx ? FC_TX : FC_NONE;
2011 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2013 struct sky2_hw *hw = sky2->hw;
2014 unsigned port = sky2->port;
2017 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2018 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2019 if (lpa & PHY_M_AN_RF) {
2020 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2024 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2025 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2026 sky2->netdev->name);
2030 sky2->speed = sky2_phy_speed(hw, aux);
2031 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2033 /* Since the pause result bits seem to in different positions on
2034 * different chips. look at registers.
2036 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2037 /* Shift for bits in fiber PHY */
2038 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2039 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2041 if (advert & ADVERTISE_1000XPAUSE)
2042 advert |= ADVERTISE_PAUSE_CAP;
2043 if (advert & ADVERTISE_1000XPSE_ASYM)
2044 advert |= ADVERTISE_PAUSE_ASYM;
2045 if (lpa & LPA_1000XPAUSE)
2046 lpa |= LPA_PAUSE_CAP;
2047 if (lpa & LPA_1000XPAUSE_ASYM)
2048 lpa |= LPA_PAUSE_ASYM;
2051 sky2->flow_status = FC_NONE;
2052 if (advert & ADVERTISE_PAUSE_CAP) {
2053 if (lpa & LPA_PAUSE_CAP)
2054 sky2->flow_status = FC_BOTH;
2055 else if (advert & ADVERTISE_PAUSE_ASYM)
2056 sky2->flow_status = FC_RX;
2057 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2058 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2059 sky2->flow_status = FC_TX;
2062 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2063 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2064 sky2->flow_status = FC_NONE;
2066 if (sky2->flow_status & FC_TX)
2067 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2069 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2074 /* Interrupt from PHY */
2075 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2077 struct net_device *dev = hw->dev[port];
2078 struct sky2_port *sky2 = netdev_priv(dev);
2079 u16 istatus, phystat;
2081 if (!netif_running(dev))
2084 spin_lock(&sky2->phy_lock);
2085 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2086 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2088 if (netif_msg_intr(sky2))
2089 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2090 sky2->netdev->name, istatus, phystat);
2092 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2093 if (sky2_autoneg_done(sky2, phystat) == 0)
2098 if (istatus & PHY_M_IS_LSP_CHANGE)
2099 sky2->speed = sky2_phy_speed(hw, phystat);
2101 if (istatus & PHY_M_IS_DUP_CHANGE)
2103 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2105 if (istatus & PHY_M_IS_LST_CHANGE) {
2106 if (phystat & PHY_M_PS_LINK_UP)
2109 sky2_link_down(sky2);
2112 spin_unlock(&sky2->phy_lock);
2115 /* Transmit timeout is only called if we are running, carrier is up
2116 * and tx queue is full (stopped).
2118 static void sky2_tx_timeout(struct net_device *dev)
2120 struct sky2_port *sky2 = netdev_priv(dev);
2121 struct sky2_hw *hw = sky2->hw;
2123 if (netif_msg_timer(sky2))
2124 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2126 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2127 dev->name, sky2->tx_cons, sky2->tx_prod,
2128 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2129 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2131 /* can't restart safely under softirq */
2132 schedule_work(&hw->restart_work);
2135 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2137 struct sky2_port *sky2 = netdev_priv(dev);
2138 struct sky2_hw *hw = sky2->hw;
2139 unsigned port = sky2->port;
2144 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2147 if (new_mtu > ETH_DATA_LEN &&
2148 (hw->chip_id == CHIP_ID_YUKON_FE ||
2149 hw->chip_id == CHIP_ID_YUKON_FE_P))
2152 if (!netif_running(dev)) {
2157 imask = sky2_read32(hw, B0_IMSK);
2158 sky2_write32(hw, B0_IMSK, 0);
2160 dev->trans_start = jiffies; /* prevent tx timeout */
2161 netif_stop_queue(dev);
2162 napi_disable(&hw->napi);
2164 synchronize_irq(hw->pdev->irq);
2166 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2167 sky2_set_tx_stfwd(hw, port);
2169 ctl = gma_read16(hw, port, GM_GP_CTRL);
2170 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2172 sky2_rx_clean(sky2);
2176 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2177 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2179 if (dev->mtu > ETH_DATA_LEN)
2180 mode |= GM_SMOD_JUMBO_ENA;
2182 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2184 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2186 err = sky2_rx_start(sky2);
2187 sky2_write32(hw, B0_IMSK, imask);
2189 sky2_read32(hw, B0_Y2_SP_LISR);
2190 napi_enable(&hw->napi);
2195 gma_write16(hw, port, GM_GP_CTRL, ctl);
2197 netif_wake_queue(dev);
2203 /* For small just reuse existing skb for next receive */
2204 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2205 const struct rx_ring_info *re,
2208 struct sk_buff *skb;
2210 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2212 skb_reserve(skb, 2);
2213 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2214 length, PCI_DMA_FROMDEVICE);
2215 skb_copy_from_linear_data(re->skb, skb->data, length);
2216 skb->ip_summed = re->skb->ip_summed;
2217 skb->csum = re->skb->csum;
2218 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2219 length, PCI_DMA_FROMDEVICE);
2220 re->skb->ip_summed = CHECKSUM_NONE;
2221 skb_put(skb, length);
2226 /* Adjust length of skb with fragments to match received data */
2227 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2228 unsigned int length)
2233 /* put header into skb */
2234 size = min(length, hdr_space);
2239 num_frags = skb_shinfo(skb)->nr_frags;
2240 for (i = 0; i < num_frags; i++) {
2241 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2244 /* don't need this page */
2245 __free_page(frag->page);
2246 --skb_shinfo(skb)->nr_frags;
2248 size = min(length, (unsigned) PAGE_SIZE);
2251 skb->data_len += size;
2252 skb->truesize += size;
2259 /* Normal packet - take skb from ring element and put in a new one */
2260 static struct sk_buff *receive_new(struct sky2_port *sky2,
2261 struct rx_ring_info *re,
2262 unsigned int length)
2264 struct sk_buff *skb, *nskb;
2265 unsigned hdr_space = sky2->rx_data_size;
2267 /* Don't be tricky about reusing pages (yet) */
2268 nskb = sky2_rx_alloc(sky2);
2269 if (unlikely(!nskb))
2273 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2275 prefetch(skb->data);
2277 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2279 if (skb_shinfo(skb)->nr_frags)
2280 skb_put_frags(skb, hdr_space, length);
2282 skb_put(skb, length);
2287 * Receive one packet.
2288 * For larger packets, get new buffer.
2290 static struct sk_buff *sky2_receive(struct net_device *dev,
2291 u16 length, u32 status)
2293 struct sky2_port *sky2 = netdev_priv(dev);
2294 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2295 struct sk_buff *skb = NULL;
2296 u16 count = (status & GMR_FS_LEN) >> 16;
2298 #ifdef SKY2_VLAN_TAG_USED
2299 /* Account for vlan tag */
2300 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2304 if (unlikely(netif_msg_rx_status(sky2)))
2305 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2306 dev->name, sky2->rx_next, status, length);
2308 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2309 prefetch(sky2->rx_ring + sky2->rx_next);
2311 /* This chip has hardware problems that generates bogus status.
2312 * So do only marginal checking and expect higher level protocols
2313 * to handle crap frames.
2315 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2316 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2320 if (status & GMR_FS_ANY_ERR)
2323 if (!(status & GMR_FS_RX_OK))
2326 /* if length reported by DMA does not match PHY, packet was truncated */
2327 if (length != count)
2331 if (length < copybreak)
2332 skb = receive_copy(sky2, re, length);
2334 skb = receive_new(sky2, re, length);
2336 sky2_rx_submit(sky2, re);
2341 /* Truncation of overlength packets
2342 causes PHY length to not match MAC length */
2343 ++dev->stats.rx_length_errors;
2344 if (netif_msg_rx_err(sky2) && net_ratelimit())
2345 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2346 dev->name, status, length);
2350 ++dev->stats.rx_errors;
2351 if (status & GMR_FS_RX_FF_OV) {
2352 dev->stats.rx_over_errors++;
2356 if (netif_msg_rx_err(sky2) && net_ratelimit())
2357 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2358 dev->name, status, length);
2360 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2361 dev->stats.rx_length_errors++;
2362 if (status & GMR_FS_FRAGMENT)
2363 dev->stats.rx_frame_errors++;
2364 if (status & GMR_FS_CRC_ERR)
2365 dev->stats.rx_crc_errors++;
2370 /* Transmit complete */
2371 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2373 struct sky2_port *sky2 = netdev_priv(dev);
2375 if (netif_running(dev)) {
2377 sky2_tx_complete(sky2, last);
2378 netif_tx_unlock(dev);
2382 /* Process status response ring */
2383 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2386 unsigned rx[2] = { 0, 0 };
2390 struct sky2_port *sky2;
2391 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2393 struct net_device *dev;
2394 struct sk_buff *skb;
2397 u8 opcode = le->opcode;
2399 if (!(opcode & HW_OWNER))
2402 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2404 port = le->css & CSS_LINK_BIT;
2405 dev = hw->dev[port];
2406 sky2 = netdev_priv(dev);
2407 length = le16_to_cpu(le->length);
2408 status = le32_to_cpu(le->status);
2411 switch (opcode & ~HW_OWNER) {
2414 skb = sky2_receive(dev, length, status);
2415 if (unlikely(!skb)) {
2416 dev->stats.rx_dropped++;
2420 /* This chip reports checksum status differently */
2421 if (hw->flags & SKY2_HW_NEW_LE) {
2422 if (sky2->rx_csum &&
2423 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2424 (le->css & CSS_TCPUDPCSOK))
2425 skb->ip_summed = CHECKSUM_UNNECESSARY;
2427 skb->ip_summed = CHECKSUM_NONE;
2430 skb->protocol = eth_type_trans(skb, dev);
2431 dev->stats.rx_packets++;
2432 dev->stats.rx_bytes += skb->len;
2433 dev->last_rx = jiffies;
2435 #ifdef SKY2_VLAN_TAG_USED
2436 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2437 vlan_hwaccel_receive_skb(skb,
2439 be16_to_cpu(sky2->rx_tag));
2442 netif_receive_skb(skb);
2444 /* Stop after net poll weight */
2445 if (++work_done >= to_do)
2449 #ifdef SKY2_VLAN_TAG_USED
2451 sky2->rx_tag = length;
2455 sky2->rx_tag = length;
2462 /* If this happens then driver assuming wrong format */
2463 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2464 if (net_ratelimit())
2465 printk(KERN_NOTICE "%s: unexpected"
2466 " checksum status\n",
2471 /* Both checksum counters are programmed to start at
2472 * the same offset, so unless there is a problem they
2473 * should match. This failure is an early indication that
2474 * hardware receive checksumming won't work.
2476 if (likely(status >> 16 == (status & 0xffff))) {
2477 skb = sky2->rx_ring[sky2->rx_next].skb;
2478 skb->ip_summed = CHECKSUM_COMPLETE;
2479 skb->csum = status & 0xffff;
2481 printk(KERN_NOTICE PFX "%s: hardware receive "
2482 "checksum problem (status = %#x)\n",
2485 sky2_write32(sky2->hw,
2486 Q_ADDR(rxqaddr[port], Q_CSR),
2492 /* TX index reports status for both ports */
2493 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2494 sky2_tx_done(hw->dev[0], status & 0xfff);
2496 sky2_tx_done(hw->dev[1],
2497 ((status >> 24) & 0xff)
2498 | (u16)(length & 0xf) << 8);
2502 if (net_ratelimit())
2503 printk(KERN_WARNING PFX
2504 "unknown status opcode 0x%x\n", opcode);
2506 } while (hw->st_idx != idx);
2508 /* Fully processed status ring so clear irq */
2509 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2513 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2516 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2521 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2523 struct net_device *dev = hw->dev[port];
2525 if (net_ratelimit())
2526 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2529 if (status & Y2_IS_PAR_RD1) {
2530 if (net_ratelimit())
2531 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2534 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2537 if (status & Y2_IS_PAR_WR1) {
2538 if (net_ratelimit())
2539 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2542 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2545 if (status & Y2_IS_PAR_MAC1) {
2546 if (net_ratelimit())
2547 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2548 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2551 if (status & Y2_IS_PAR_RX1) {
2552 if (net_ratelimit())
2553 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2554 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2557 if (status & Y2_IS_TCP_TXA1) {
2558 if (net_ratelimit())
2559 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2561 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2565 static void sky2_hw_intr(struct sky2_hw *hw)
2567 struct pci_dev *pdev = hw->pdev;
2568 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2569 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2573 if (status & Y2_IS_TIST_OV)
2574 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2576 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2579 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2580 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2581 if (net_ratelimit())
2582 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2585 sky2_pci_write16(hw, PCI_STATUS,
2586 pci_err | PCI_STATUS_ERROR_BITS);
2587 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2590 if (status & Y2_IS_PCI_EXP) {
2591 /* PCI-Express uncorrectable Error occurred */
2594 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2595 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2596 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2598 if (net_ratelimit())
2599 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2601 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2602 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2605 if (status & Y2_HWE_L1_MASK)
2606 sky2_hw_error(hw, 0, status);
2608 if (status & Y2_HWE_L1_MASK)
2609 sky2_hw_error(hw, 1, status);
2612 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2614 struct net_device *dev = hw->dev[port];
2615 struct sky2_port *sky2 = netdev_priv(dev);
2616 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2618 if (netif_msg_intr(sky2))
2619 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2622 if (status & GM_IS_RX_CO_OV)
2623 gma_read16(hw, port, GM_RX_IRQ_SRC);
2625 if (status & GM_IS_TX_CO_OV)
2626 gma_read16(hw, port, GM_TX_IRQ_SRC);
2628 if (status & GM_IS_RX_FF_OR) {
2629 ++dev->stats.rx_fifo_errors;
2630 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2633 if (status & GM_IS_TX_FF_UR) {
2634 ++dev->stats.tx_fifo_errors;
2635 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2639 /* This should never happen it is a bug. */
2640 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2641 u16 q, unsigned ring_size)
2643 struct net_device *dev = hw->dev[port];
2644 struct sky2_port *sky2 = netdev_priv(dev);
2646 const u64 *le = (q == Q_R1 || q == Q_R2)
2647 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2649 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2650 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2651 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2652 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2654 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2657 static int sky2_rx_hung(struct net_device *dev)
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660 struct sky2_hw *hw = sky2->hw;
2661 unsigned port = sky2->port;
2662 unsigned rxq = rxqaddr[port];
2663 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2664 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2665 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2666 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2668 /* If idle and MAC or PCI is stuck */
2669 if (sky2->check.last == dev->last_rx &&
2670 ((mac_rp == sky2->check.mac_rp &&
2671 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2672 /* Check if the PCI RX hang */
2673 (fifo_rp == sky2->check.fifo_rp &&
2674 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2675 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2676 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2677 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2680 sky2->check.last = dev->last_rx;
2681 sky2->check.mac_rp = mac_rp;
2682 sky2->check.mac_lev = mac_lev;
2683 sky2->check.fifo_rp = fifo_rp;
2684 sky2->check.fifo_lev = fifo_lev;
2689 static void sky2_watchdog(unsigned long arg)
2691 struct sky2_hw *hw = (struct sky2_hw *) arg;
2693 /* Check for lost IRQ once a second */
2694 if (sky2_read32(hw, B0_ISRC)) {
2695 napi_schedule(&hw->napi);
2699 for (i = 0; i < hw->ports; i++) {
2700 struct net_device *dev = hw->dev[i];
2701 if (!netif_running(dev))
2705 /* For chips with Rx FIFO, check if stuck */
2706 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2707 sky2_rx_hung(dev)) {
2708 pr_info(PFX "%s: receiver hang detected\n",
2710 schedule_work(&hw->restart_work);
2719 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2722 /* Hardware/software error handling */
2723 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2725 if (net_ratelimit())
2726 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2728 if (status & Y2_IS_HW_ERR)
2731 if (status & Y2_IS_IRQ_MAC1)
2732 sky2_mac_intr(hw, 0);
2734 if (status & Y2_IS_IRQ_MAC2)
2735 sky2_mac_intr(hw, 1);
2737 if (status & Y2_IS_CHK_RX1)
2738 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2740 if (status & Y2_IS_CHK_RX2)
2741 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2743 if (status & Y2_IS_CHK_TXA1)
2744 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2746 if (status & Y2_IS_CHK_TXA2)
2747 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2750 static int sky2_poll(struct napi_struct *napi, int work_limit)
2752 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2753 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2757 if (unlikely(status & Y2_IS_ERROR))
2758 sky2_err_intr(hw, status);
2760 if (status & Y2_IS_IRQ_PHY1)
2761 sky2_phy_intr(hw, 0);
2763 if (status & Y2_IS_IRQ_PHY2)
2764 sky2_phy_intr(hw, 1);
2766 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2767 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2769 if (work_done >= work_limit)
2773 /* Bug/Errata workaround?
2774 * Need to kick the TX irq moderation timer.
2776 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2777 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2778 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2780 napi_complete(napi);
2781 sky2_read32(hw, B0_Y2_SP_LISR);
2787 static irqreturn_t sky2_intr(int irq, void *dev_id)
2789 struct sky2_hw *hw = dev_id;
2792 /* Reading this mask interrupts as side effect */
2793 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2794 if (status == 0 || status == ~0)
2797 prefetch(&hw->st_le[hw->st_idx]);
2799 napi_schedule(&hw->napi);
2804 #ifdef CONFIG_NET_POLL_CONTROLLER
2805 static void sky2_netpoll(struct net_device *dev)
2807 struct sky2_port *sky2 = netdev_priv(dev);
2809 napi_schedule(&sky2->hw->napi);
2813 /* Chip internal frequency for clock calculations */
2814 static u32 sky2_mhz(const struct sky2_hw *hw)
2816 switch (hw->chip_id) {
2817 case CHIP_ID_YUKON_EC:
2818 case CHIP_ID_YUKON_EC_U:
2819 case CHIP_ID_YUKON_EX:
2820 case CHIP_ID_YUKON_SUPR:
2823 case CHIP_ID_YUKON_FE:
2826 case CHIP_ID_YUKON_FE_P:
2829 case CHIP_ID_YUKON_XL:
2837 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2839 return sky2_mhz(hw) * us;
2842 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2844 return clk / sky2_mhz(hw);
2848 static int __devinit sky2_init(struct sky2_hw *hw)
2852 /* Enable all clocks and check for bad PCI access */
2853 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2855 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2857 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2858 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2860 switch(hw->chip_id) {
2861 case CHIP_ID_YUKON_XL:
2862 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2865 case CHIP_ID_YUKON_EC_U:
2866 hw->flags = SKY2_HW_GIGABIT
2868 | SKY2_HW_ADV_POWER_CTL;
2870 /* check for Rev. A1 dev 4200 */
2871 if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
2872 hw->flags |= SKY2_HW_CLK_POWER;
2875 case CHIP_ID_YUKON_EX:
2876 hw->flags = SKY2_HW_GIGABIT
2879 | SKY2_HW_ADV_POWER_CTL;
2881 /* New transmit checksum */
2882 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2883 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2886 case CHIP_ID_YUKON_EC:
2887 /* This rev is really old, and requires untested workarounds */
2888 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2889 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2892 hw->flags = SKY2_HW_GIGABIT;
2895 case CHIP_ID_YUKON_FE:
2898 case CHIP_ID_YUKON_FE_P:
2899 hw->flags = SKY2_HW_NEWER_PHY
2901 | SKY2_HW_AUTO_TX_SUM
2902 | SKY2_HW_ADV_POWER_CTL;
2905 case CHIP_ID_YUKON_SUPR:
2906 hw->flags = SKY2_HW_GIGABIT
2909 | SKY2_HW_AUTO_TX_SUM
2910 | SKY2_HW_ADV_POWER_CTL;
2914 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2919 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2920 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2921 hw->flags |= SKY2_HW_FIBRE_PHY;
2923 hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
2924 if (hw->pm_cap == 0) {
2925 dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
2930 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2931 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2932 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2939 static void sky2_reset(struct sky2_hw *hw)
2941 struct pci_dev *pdev = hw->pdev;
2944 u32 hwe_mask = Y2_HWE_ALL_MASK;
2947 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2948 status = sky2_read16(hw, HCU_CCSR);
2949 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2950 HCU_CCSR_UC_STATE_MSK);
2951 sky2_write16(hw, HCU_CCSR, status);
2953 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2954 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2957 sky2_write8(hw, B0_CTST, CS_RST_SET);
2958 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2960 /* allow writes to PCI config */
2961 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2963 /* clear PCI errors, if any */
2964 status = sky2_pci_read16(hw, PCI_STATUS);
2965 status |= PCI_STATUS_ERROR_BITS;
2966 sky2_pci_write16(hw, PCI_STATUS, status);
2968 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2970 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2972 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2975 /* If error bit is stuck on ignore it */
2976 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2977 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2979 hwe_mask |= Y2_IS_PCI_EXP;
2983 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2985 for (i = 0; i < hw->ports; i++) {
2986 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2987 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2989 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2990 hw->chip_id == CHIP_ID_YUKON_SUPR)
2991 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2992 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2996 /* Clear I2C IRQ noise */
2997 sky2_write32(hw, B2_I2C_IRQ, 1);
2999 /* turn off hardware timer (unused) */
3000 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3001 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3003 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3005 /* Turn off descriptor polling */
3006 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3008 /* Turn off receive timestamp */
3009 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3010 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3012 /* enable the Tx Arbiters */
3013 for (i = 0; i < hw->ports; i++)
3014 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3016 /* Initialize ram interface */
3017 for (i = 0; i < hw->ports; i++) {
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3024 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3025 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3026 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3027 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3034 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3036 for (i = 0; i < hw->ports; i++)
3037 sky2_gmac_reset(hw, i);
3039 memset(hw->st_le, 0, STATUS_LE_BYTES);
3042 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3043 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3045 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3046 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3048 /* Set the list last index */
3049 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3051 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3052 sky2_write8(hw, STAT_FIFO_WM, 16);
3054 /* set Status-FIFO ISR watermark */
3055 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3056 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3058 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3060 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3061 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3062 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3064 /* enable status unit */
3065 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3067 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3068 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3069 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3072 static void sky2_restart(struct work_struct *work)
3074 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3075 struct net_device *dev;
3079 for (i = 0; i < hw->ports; i++) {
3081 if (netif_running(dev))
3085 napi_disable(&hw->napi);
3086 sky2_write32(hw, B0_IMSK, 0);
3088 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3089 napi_enable(&hw->napi);
3091 for (i = 0; i < hw->ports; i++) {
3093 if (netif_running(dev)) {
3096 printk(KERN_INFO PFX "%s: could not restart %d\n",
3106 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3108 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3111 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3113 const struct sky2_port *sky2 = netdev_priv(dev);
3115 wol->supported = sky2_wol_supported(sky2->hw);
3116 wol->wolopts = sky2->wol;
3119 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3121 struct sky2_port *sky2 = netdev_priv(dev);
3122 struct sky2_hw *hw = sky2->hw;
3124 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3127 sky2->wol = wol->wolopts;
3129 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3130 hw->chip_id == CHIP_ID_YUKON_EX ||
3131 hw->chip_id == CHIP_ID_YUKON_FE_P)
3132 sky2_write32(hw, B0_CTST, sky2->wol
3133 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3135 if (!netif_running(dev))
3136 sky2_wol_init(sky2);
3140 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3142 if (sky2_is_copper(hw)) {
3143 u32 modes = SUPPORTED_10baseT_Half
3144 | SUPPORTED_10baseT_Full
3145 | SUPPORTED_100baseT_Half
3146 | SUPPORTED_100baseT_Full
3147 | SUPPORTED_Autoneg | SUPPORTED_TP;
3149 if (hw->flags & SKY2_HW_GIGABIT)
3150 modes |= SUPPORTED_1000baseT_Half
3151 | SUPPORTED_1000baseT_Full;
3154 return SUPPORTED_1000baseT_Half
3155 | SUPPORTED_1000baseT_Full
3160 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3162 struct sky2_port *sky2 = netdev_priv(dev);
3163 struct sky2_hw *hw = sky2->hw;
3165 ecmd->transceiver = XCVR_INTERNAL;
3166 ecmd->supported = sky2_supported_modes(hw);
3167 ecmd->phy_address = PHY_ADDR_MARV;
3168 if (sky2_is_copper(hw)) {
3169 ecmd->port = PORT_TP;
3170 ecmd->speed = sky2->speed;
3172 ecmd->speed = SPEED_1000;
3173 ecmd->port = PORT_FIBRE;
3176 ecmd->advertising = sky2->advertising;
3177 ecmd->autoneg = sky2->autoneg;
3178 ecmd->duplex = sky2->duplex;
3182 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3184 struct sky2_port *sky2 = netdev_priv(dev);
3185 const struct sky2_hw *hw = sky2->hw;
3186 u32 supported = sky2_supported_modes(hw);
3188 if (ecmd->autoneg == AUTONEG_ENABLE) {
3189 ecmd->advertising = supported;
3195 switch (ecmd->speed) {
3197 if (ecmd->duplex == DUPLEX_FULL)
3198 setting = SUPPORTED_1000baseT_Full;
3199 else if (ecmd->duplex == DUPLEX_HALF)
3200 setting = SUPPORTED_1000baseT_Half;
3205 if (ecmd->duplex == DUPLEX_FULL)
3206 setting = SUPPORTED_100baseT_Full;
3207 else if (ecmd->duplex == DUPLEX_HALF)
3208 setting = SUPPORTED_100baseT_Half;
3214 if (ecmd->duplex == DUPLEX_FULL)
3215 setting = SUPPORTED_10baseT_Full;
3216 else if (ecmd->duplex == DUPLEX_HALF)
3217 setting = SUPPORTED_10baseT_Half;
3225 if ((setting & supported) == 0)
3228 sky2->speed = ecmd->speed;
3229 sky2->duplex = ecmd->duplex;
3232 sky2->autoneg = ecmd->autoneg;
3233 sky2->advertising = ecmd->advertising;
3235 if (netif_running(dev)) {
3236 sky2_phy_reinit(sky2);
3237 sky2_set_multicast(dev);
3243 static void sky2_get_drvinfo(struct net_device *dev,
3244 struct ethtool_drvinfo *info)
3246 struct sky2_port *sky2 = netdev_priv(dev);
3248 strcpy(info->driver, DRV_NAME);
3249 strcpy(info->version, DRV_VERSION);
3250 strcpy(info->fw_version, "N/A");
3251 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3254 static const struct sky2_stat {
3255 char name[ETH_GSTRING_LEN];
3258 { "tx_bytes", GM_TXO_OK_HI },
3259 { "rx_bytes", GM_RXO_OK_HI },
3260 { "tx_broadcast", GM_TXF_BC_OK },
3261 { "rx_broadcast", GM_RXF_BC_OK },
3262 { "tx_multicast", GM_TXF_MC_OK },
3263 { "rx_multicast", GM_RXF_MC_OK },
3264 { "tx_unicast", GM_TXF_UC_OK },
3265 { "rx_unicast", GM_RXF_UC_OK },
3266 { "tx_mac_pause", GM_TXF_MPAUSE },
3267 { "rx_mac_pause", GM_RXF_MPAUSE },
3268 { "collisions", GM_TXF_COL },
3269 { "late_collision",GM_TXF_LAT_COL },
3270 { "aborted", GM_TXF_ABO_COL },
3271 { "single_collisions", GM_TXF_SNG_COL },
3272 { "multi_collisions", GM_TXF_MUL_COL },
3274 { "rx_short", GM_RXF_SHT },
3275 { "rx_runt", GM_RXE_FRAG },
3276 { "rx_64_byte_packets", GM_RXF_64B },
3277 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3278 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3279 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3280 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3281 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3282 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3283 { "rx_too_long", GM_RXF_LNG_ERR },
3284 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3285 { "rx_jabber", GM_RXF_JAB_PKT },
3286 { "rx_fcs_error", GM_RXF_FCS_ERR },
3288 { "tx_64_byte_packets", GM_TXF_64B },
3289 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3290 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3291 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3292 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3293 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3294 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3295 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3298 static u32 sky2_get_rx_csum(struct net_device *dev)
3300 struct sky2_port *sky2 = netdev_priv(dev);
3302 return sky2->rx_csum;
3305 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3307 struct sky2_port *sky2 = netdev_priv(dev);
3309 sky2->rx_csum = data;
3311 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3312 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3317 static u32 sky2_get_msglevel(struct net_device *netdev)
3319 struct sky2_port *sky2 = netdev_priv(netdev);
3320 return sky2->msg_enable;
3323 static int sky2_nway_reset(struct net_device *dev)
3325 struct sky2_port *sky2 = netdev_priv(dev);
3327 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3330 sky2_phy_reinit(sky2);
3331 sky2_set_multicast(dev);
3336 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3338 struct sky2_hw *hw = sky2->hw;
3339 unsigned port = sky2->port;
3342 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3343 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3344 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3345 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3347 for (i = 2; i < count; i++)
3348 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3351 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3353 struct sky2_port *sky2 = netdev_priv(netdev);
3354 sky2->msg_enable = value;
3357 static int sky2_get_sset_count(struct net_device *dev, int sset)
3361 return ARRAY_SIZE(sky2_stats);
3367 static void sky2_get_ethtool_stats(struct net_device *dev,
3368 struct ethtool_stats *stats, u64 * data)
3370 struct sky2_port *sky2 = netdev_priv(dev);
3372 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3375 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3379 switch (stringset) {
3381 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3382 memcpy(data + i * ETH_GSTRING_LEN,
3383 sky2_stats[i].name, ETH_GSTRING_LEN);
3388 static int sky2_set_mac_address(struct net_device *dev, void *p)
3390 struct sky2_port *sky2 = netdev_priv(dev);
3391 struct sky2_hw *hw = sky2->hw;
3392 unsigned port = sky2->port;
3393 const struct sockaddr *addr = p;
3395 if (!is_valid_ether_addr(addr->sa_data))
3396 return -EADDRNOTAVAIL;
3398 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3399 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3400 dev->dev_addr, ETH_ALEN);
3401 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3402 dev->dev_addr, ETH_ALEN);
3404 /* virtual address for data */
3405 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3407 /* physical address: used for pause frames */
3408 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3413 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3417 bit = ether_crc(ETH_ALEN, addr) & 63;
3418 filter[bit >> 3] |= 1 << (bit & 7);
3421 static void sky2_set_multicast(struct net_device *dev)
3423 struct sky2_port *sky2 = netdev_priv(dev);
3424 struct sky2_hw *hw = sky2->hw;
3425 unsigned port = sky2->port;
3426 struct dev_mc_list *list = dev->mc_list;
3430 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3432 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3433 memset(filter, 0, sizeof(filter));
3435 reg = gma_read16(hw, port, GM_RX_CTRL);
3436 reg |= GM_RXCR_UCF_ENA;
3438 if (dev->flags & IFF_PROMISC) /* promiscuous */
3439 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3440 else if (dev->flags & IFF_ALLMULTI)
3441 memset(filter, 0xff, sizeof(filter));
3442 else if (dev->mc_count == 0 && !rx_pause)
3443 reg &= ~GM_RXCR_MCF_ENA;
3446 reg |= GM_RXCR_MCF_ENA;
3449 sky2_add_filter(filter, pause_mc_addr);
3451 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3452 sky2_add_filter(filter, list->dmi_addr);
3455 gma_write16(hw, port, GM_MC_ADDR_H1,
3456 (u16) filter[0] | ((u16) filter[1] << 8));
3457 gma_write16(hw, port, GM_MC_ADDR_H2,
3458 (u16) filter[2] | ((u16) filter[3] << 8));
3459 gma_write16(hw, port, GM_MC_ADDR_H3,
3460 (u16) filter[4] | ((u16) filter[5] << 8));
3461 gma_write16(hw, port, GM_MC_ADDR_H4,
3462 (u16) filter[6] | ((u16) filter[7] << 8));
3464 gma_write16(hw, port, GM_RX_CTRL, reg);
3467 /* Can have one global because blinking is controlled by
3468 * ethtool and that is always under RTNL mutex
3470 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3472 struct sky2_hw *hw = sky2->hw;
3473 unsigned port = sky2->port;
3475 spin_lock_bh(&sky2->phy_lock);
3476 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3477 hw->chip_id == CHIP_ID_YUKON_EX ||
3478 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3480 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3485 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3486 PHY_M_LEDC_LOS_CTRL(8) |
3487 PHY_M_LEDC_INIT_CTRL(8) |
3488 PHY_M_LEDC_STA1_CTRL(8) |
3489 PHY_M_LEDC_STA0_CTRL(8));
3492 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3493 PHY_M_LEDC_LOS_CTRL(9) |
3494 PHY_M_LEDC_INIT_CTRL(9) |
3495 PHY_M_LEDC_STA1_CTRL(9) |
3496 PHY_M_LEDC_STA0_CTRL(9));
3499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3500 PHY_M_LEDC_LOS_CTRL(0xa) |
3501 PHY_M_LEDC_INIT_CTRL(0xa) |
3502 PHY_M_LEDC_STA1_CTRL(0xa) |
3503 PHY_M_LEDC_STA0_CTRL(0xa));
3506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3507 PHY_M_LEDC_LOS_CTRL(1) |
3508 PHY_M_LEDC_INIT_CTRL(8) |
3509 PHY_M_LEDC_STA1_CTRL(7) |
3510 PHY_M_LEDC_STA0_CTRL(7));
3513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3515 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3516 PHY_M_LED_MO_DUP(mode) |
3517 PHY_M_LED_MO_10(mode) |
3518 PHY_M_LED_MO_100(mode) |
3519 PHY_M_LED_MO_1000(mode) |
3520 PHY_M_LED_MO_RX(mode) |
3521 PHY_M_LED_MO_TX(mode));
3523 spin_unlock_bh(&sky2->phy_lock);
3526 /* blink LED's for finding board */
3527 static int sky2_phys_id(struct net_device *dev, u32 data)
3529 struct sky2_port *sky2 = netdev_priv(dev);
3535 for (i = 0; i < data; i++) {
3536 sky2_led(sky2, MO_LED_ON);
3537 if (msleep_interruptible(500))
3539 sky2_led(sky2, MO_LED_OFF);
3540 if (msleep_interruptible(500))
3543 sky2_led(sky2, MO_LED_NORM);
3548 static void sky2_get_pauseparam(struct net_device *dev,
3549 struct ethtool_pauseparam *ecmd)
3551 struct sky2_port *sky2 = netdev_priv(dev);
3553 switch (sky2->flow_mode) {
3555 ecmd->tx_pause = ecmd->rx_pause = 0;
3558 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3561 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3564 ecmd->tx_pause = ecmd->rx_pause = 1;
3567 ecmd->autoneg = sky2->autoneg;
3570 static int sky2_set_pauseparam(struct net_device *dev,
3571 struct ethtool_pauseparam *ecmd)
3573 struct sky2_port *sky2 = netdev_priv(dev);
3575 sky2->autoneg = ecmd->autoneg;
3576 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3578 if (netif_running(dev))
3579 sky2_phy_reinit(sky2);
3584 static int sky2_get_coalesce(struct net_device *dev,
3585 struct ethtool_coalesce *ecmd)
3587 struct sky2_port *sky2 = netdev_priv(dev);
3588 struct sky2_hw *hw = sky2->hw;
3590 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3591 ecmd->tx_coalesce_usecs = 0;
3593 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3594 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3596 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3598 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3599 ecmd->rx_coalesce_usecs = 0;
3601 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3602 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3604 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3606 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3607 ecmd->rx_coalesce_usecs_irq = 0;
3609 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3610 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3613 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3618 /* Note: this affect both ports */
3619 static int sky2_set_coalesce(struct net_device *dev,
3620 struct ethtool_coalesce *ecmd)
3622 struct sky2_port *sky2 = netdev_priv(dev);
3623 struct sky2_hw *hw = sky2->hw;
3624 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3626 if (ecmd->tx_coalesce_usecs > tmax ||
3627 ecmd->rx_coalesce_usecs > tmax ||
3628 ecmd->rx_coalesce_usecs_irq > tmax)
3631 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3633 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3635 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3638 if (ecmd->tx_coalesce_usecs == 0)
3639 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3641 sky2_write32(hw, STAT_TX_TIMER_INI,
3642 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3643 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3645 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3647 if (ecmd->rx_coalesce_usecs == 0)
3648 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3650 sky2_write32(hw, STAT_LEV_TIMER_INI,
3651 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3652 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3654 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3656 if (ecmd->rx_coalesce_usecs_irq == 0)
3657 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3659 sky2_write32(hw, STAT_ISR_TIMER_INI,
3660 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3661 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3663 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3667 static void sky2_get_ringparam(struct net_device *dev,
3668 struct ethtool_ringparam *ering)
3670 struct sky2_port *sky2 = netdev_priv(dev);
3672 ering->rx_max_pending = RX_MAX_PENDING;
3673 ering->rx_mini_max_pending = 0;
3674 ering->rx_jumbo_max_pending = 0;
3675 ering->tx_max_pending = TX_RING_SIZE - 1;
3677 ering->rx_pending = sky2->rx_pending;
3678 ering->rx_mini_pending = 0;
3679 ering->rx_jumbo_pending = 0;
3680 ering->tx_pending = sky2->tx_pending;
3683 static int sky2_set_ringparam(struct net_device *dev,
3684 struct ethtool_ringparam *ering)
3686 struct sky2_port *sky2 = netdev_priv(dev);
3689 if (ering->rx_pending > RX_MAX_PENDING ||
3690 ering->rx_pending < 8 ||
3691 ering->tx_pending < MAX_SKB_TX_LE ||
3692 ering->tx_pending > TX_RING_SIZE - 1)
3695 if (netif_running(dev))
3698 sky2->rx_pending = ering->rx_pending;
3699 sky2->tx_pending = ering->tx_pending;
3701 if (netif_running(dev)) {
3710 static int sky2_get_regs_len(struct net_device *dev)
3716 * Returns copy of control register region
3717 * Note: ethtool_get_regs always provides full size (16k) buffer
3719 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3722 const struct sky2_port *sky2 = netdev_priv(dev);
3723 const void __iomem *io = sky2->hw->regs;
3728 for (b = 0; b < 128; b++) {
3729 /* This complicated switch statement is to make sure and
3730 * only access regions that are unreserved.
3731 * Some blocks are only valid on dual port cards.
3732 * and block 3 has some special diagnostic registers that
3737 /* skip diagnostic ram region */
3738 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3741 /* dual port cards only */
3742 case 5: /* Tx Arbiter 2 */
3744 case 14 ... 15: /* TX2 */
3745 case 17: case 19: /* Ram Buffer 2 */
3746 case 22 ... 23: /* Tx Ram Buffer 2 */
3747 case 25: /* Rx MAC Fifo 1 */
3748 case 27: /* Tx MAC Fifo 2 */
3749 case 31: /* GPHY 2 */
3750 case 40 ... 47: /* Pattern Ram 2 */
3751 case 52: case 54: /* TCP Segmentation 2 */
3752 case 112 ... 116: /* GMAC 2 */
3753 if (sky2->hw->ports == 1)
3756 case 0: /* Control */
3757 case 2: /* Mac address */
3758 case 4: /* Tx Arbiter 1 */
3759 case 7: /* PCI express reg */
3761 case 12 ... 13: /* TX1 */
3762 case 16: case 18:/* Rx Ram Buffer 1 */
3763 case 20 ... 21: /* Tx Ram Buffer 1 */
3764 case 24: /* Rx MAC Fifo 1 */
3765 case 26: /* Tx MAC Fifo 1 */
3766 case 28 ... 29: /* Descriptor and status unit */
3767 case 30: /* GPHY 1*/
3768 case 32 ... 39: /* Pattern Ram 1 */
3769 case 48: case 50: /* TCP Segmentation 1 */
3770 case 56 ... 60: /* PCI space */
3771 case 80 ... 84: /* GMAC 1 */
3772 memcpy_fromio(p, io, 128);
3784 /* In order to do Jumbo packets on these chips, need to turn off the
3785 * transmit store/forward. Therefore checksum offload won't work.
3787 static int no_tx_offload(struct net_device *dev)
3789 const struct sky2_port *sky2 = netdev_priv(dev);
3790 const struct sky2_hw *hw = sky2->hw;
3792 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3795 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3797 if (data && no_tx_offload(dev))
3800 return ethtool_op_set_tx_csum(dev, data);
3804 static int sky2_set_tso(struct net_device *dev, u32 data)
3806 if (data && no_tx_offload(dev))
3809 return ethtool_op_set_tso(dev, data);
3812 static int sky2_get_eeprom_len(struct net_device *dev)
3814 struct sky2_port *sky2 = netdev_priv(dev);
3815 struct sky2_hw *hw = sky2->hw;
3818 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3819 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3822 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3826 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3829 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3830 } while (!(offset & PCI_VPD_ADDR_F));
3832 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3836 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3838 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3839 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3841 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3842 } while (offset & PCI_VPD_ADDR_F);
3845 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3848 struct sky2_port *sky2 = netdev_priv(dev);
3849 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3850 int length = eeprom->len;
3851 u16 offset = eeprom->offset;
3856 eeprom->magic = SKY2_EEPROM_MAGIC;
3858 while (length > 0) {
3859 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3860 int n = min_t(int, length, sizeof(val));
3862 memcpy(data, &val, n);
3870 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3873 struct sky2_port *sky2 = netdev_priv(dev);
3874 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3875 int length = eeprom->len;
3876 u16 offset = eeprom->offset;
3881 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3884 while (length > 0) {
3886 int n = min_t(int, length, sizeof(val));
3888 if (n < sizeof(val))
3889 val = sky2_vpd_read(sky2->hw, cap, offset);
3890 memcpy(&val, data, n);
3892 sky2_vpd_write(sky2->hw, cap, offset, val);
3902 static const struct ethtool_ops sky2_ethtool_ops = {
3903 .get_settings = sky2_get_settings,
3904 .set_settings = sky2_set_settings,
3905 .get_drvinfo = sky2_get_drvinfo,
3906 .get_wol = sky2_get_wol,
3907 .set_wol = sky2_set_wol,
3908 .get_msglevel = sky2_get_msglevel,
3909 .set_msglevel = sky2_set_msglevel,
3910 .nway_reset = sky2_nway_reset,
3911 .get_regs_len = sky2_get_regs_len,
3912 .get_regs = sky2_get_regs,
3913 .get_link = ethtool_op_get_link,
3914 .get_eeprom_len = sky2_get_eeprom_len,
3915 .get_eeprom = sky2_get_eeprom,
3916 .set_eeprom = sky2_set_eeprom,
3917 .set_sg = ethtool_op_set_sg,
3918 .set_tx_csum = sky2_set_tx_csum,
3919 .set_tso = sky2_set_tso,
3920 .get_rx_csum = sky2_get_rx_csum,
3921 .set_rx_csum = sky2_set_rx_csum,
3922 .get_strings = sky2_get_strings,
3923 .get_coalesce = sky2_get_coalesce,
3924 .set_coalesce = sky2_set_coalesce,
3925 .get_ringparam = sky2_get_ringparam,
3926 .set_ringparam = sky2_set_ringparam,
3927 .get_pauseparam = sky2_get_pauseparam,
3928 .set_pauseparam = sky2_set_pauseparam,
3929 .phys_id = sky2_phys_id,
3930 .get_sset_count = sky2_get_sset_count,
3931 .get_ethtool_stats = sky2_get_ethtool_stats,
3934 #ifdef CONFIG_SKY2_DEBUG
3936 static struct dentry *sky2_debug;
3938 static int sky2_debug_show(struct seq_file *seq, void *v)
3940 struct net_device *dev = seq->private;
3941 const struct sky2_port *sky2 = netdev_priv(dev);
3942 struct sky2_hw *hw = sky2->hw;
3943 unsigned port = sky2->port;
3947 if (!netif_running(dev))
3950 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3951 sky2_read32(hw, B0_ISRC),
3952 sky2_read32(hw, B0_IMSK),
3953 sky2_read32(hw, B0_Y2_SP_ICR));
3955 napi_disable(&hw->napi);
3956 last = sky2_read16(hw, STAT_PUT_IDX);
3958 if (hw->st_idx == last)
3959 seq_puts(seq, "Status ring (empty)\n");
3961 seq_puts(seq, "Status ring\n");
3962 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3963 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3964 const struct sky2_status_le *le = hw->st_le + idx;
3965 seq_printf(seq, "[%d] %#x %d %#x\n",
3966 idx, le->opcode, le->length, le->status);
3968 seq_puts(seq, "\n");
3971 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3972 sky2->tx_cons, sky2->tx_prod,
3973 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3974 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3976 /* Dump contents of tx ring */
3978 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3979 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3980 const struct sky2_tx_le *le = sky2->tx_le + idx;
3981 u32 a = le32_to_cpu(le->addr);
3984 seq_printf(seq, "%u:", idx);
3987 switch(le->opcode & ~HW_OWNER) {
3989 seq_printf(seq, " %#x:", a);
3992 seq_printf(seq, " mtu=%d", a);
3995 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3998 seq_printf(seq, " csum=%#x", a);
4001 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4004 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4007 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4010 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4011 a, le16_to_cpu(le->length));
4014 if (le->ctrl & EOP) {
4015 seq_putc(seq, '\n');
4020 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4021 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4022 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4023 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4025 sky2_read32(hw, B0_Y2_SP_LISR);
4026 napi_enable(&hw->napi);
4030 static int sky2_debug_open(struct inode *inode, struct file *file)
4032 return single_open(file, sky2_debug_show, inode->i_private);
4035 static const struct file_operations sky2_debug_fops = {
4036 .owner = THIS_MODULE,
4037 .open = sky2_debug_open,
4039 .llseek = seq_lseek,
4040 .release = single_release,
4044 * Use network device events to create/remove/rename
4045 * debugfs file entries
4047 static int sky2_device_event(struct notifier_block *unused,
4048 unsigned long event, void *ptr)
4050 struct net_device *dev = ptr;
4051 struct sky2_port *sky2 = netdev_priv(dev);
4053 if (dev->open != sky2_up || !sky2_debug)
4057 case NETDEV_CHANGENAME:
4058 if (sky2->debugfs) {
4059 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4060 sky2_debug, dev->name);
4064 case NETDEV_GOING_DOWN:
4065 if (sky2->debugfs) {
4066 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4068 debugfs_remove(sky2->debugfs);
4069 sky2->debugfs = NULL;
4074 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4077 if (IS_ERR(sky2->debugfs))
4078 sky2->debugfs = NULL;
4084 static struct notifier_block sky2_notifier = {
4085 .notifier_call = sky2_device_event,
4089 static __init void sky2_debug_init(void)
4093 ent = debugfs_create_dir("sky2", NULL);
4094 if (!ent || IS_ERR(ent))
4098 register_netdevice_notifier(&sky2_notifier);
4101 static __exit void sky2_debug_cleanup(void)
4104 unregister_netdevice_notifier(&sky2_notifier);
4105 debugfs_remove(sky2_debug);
4111 #define sky2_debug_init()
4112 #define sky2_debug_cleanup()
4116 /* Initialize network device */
4117 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4119 int highmem, int wol)
4121 struct sky2_port *sky2;
4122 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4125 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4129 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4130 dev->irq = hw->pdev->irq;
4131 dev->open = sky2_up;
4132 dev->stop = sky2_down;
4133 dev->do_ioctl = sky2_ioctl;
4134 dev->hard_start_xmit = sky2_xmit_frame;
4135 dev->set_multicast_list = sky2_set_multicast;
4136 dev->set_mac_address = sky2_set_mac_address;
4137 dev->change_mtu = sky2_change_mtu;
4138 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4139 dev->tx_timeout = sky2_tx_timeout;
4140 dev->watchdog_timeo = TX_WATCHDOG;
4141 #ifdef CONFIG_NET_POLL_CONTROLLER
4143 dev->poll_controller = sky2_netpoll;
4146 sky2 = netdev_priv(dev);
4149 sky2->msg_enable = netif_msg_init(debug, default_msg);
4151 /* Auto speed and flow control */
4152 sky2->autoneg = AUTONEG_ENABLE;
4153 sky2->flow_mode = FC_BOTH;
4157 sky2->advertising = sky2_supported_modes(hw);
4158 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4161 spin_lock_init(&sky2->phy_lock);
4162 sky2->tx_pending = TX_DEF_PENDING;
4163 sky2->rx_pending = RX_DEF_PENDING;
4165 hw->dev[port] = dev;
4169 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4171 dev->features |= NETIF_F_HIGHDMA;
4173 #ifdef SKY2_VLAN_TAG_USED
4174 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4175 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4176 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4177 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4178 dev->vlan_rx_register = sky2_vlan_rx_register;
4182 /* read the mac address */
4183 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4184 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4189 static void __devinit sky2_show_addr(struct net_device *dev)
4191 const struct sky2_port *sky2 = netdev_priv(dev);
4192 DECLARE_MAC_BUF(mac);
4194 if (netif_msg_probe(sky2))
4195 printk(KERN_INFO PFX "%s: addr %s\n",
4196 dev->name, print_mac(mac, dev->dev_addr));
4199 /* Handle software interrupt used during MSI test */
4200 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4202 struct sky2_hw *hw = dev_id;
4203 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4208 if (status & Y2_IS_IRQ_SW) {
4209 hw->flags |= SKY2_HW_USE_MSI;
4210 wake_up(&hw->msi_wait);
4211 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4213 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4218 /* Test interrupt path by forcing a a software IRQ */
4219 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4221 struct pci_dev *pdev = hw->pdev;
4224 init_waitqueue_head (&hw->msi_wait);
4226 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4228 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4230 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4234 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4235 sky2_read8(hw, B0_CTST);
4237 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4239 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4240 /* MSI test failed, go back to INTx mode */
4241 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4242 "switching to INTx mode.\n");
4245 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4248 sky2_write32(hw, B0_IMSK, 0);
4249 sky2_read32(hw, B0_IMSK);
4251 free_irq(pdev->irq, hw);
4256 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4258 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4263 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4265 return value & PCI_PM_CTRL_PME_ENABLE;
4268 static int __devinit sky2_probe(struct pci_dev *pdev,
4269 const struct pci_device_id *ent)
4271 struct net_device *dev;
4273 int err, using_dac = 0, wol_default;
4275 err = pci_enable_device(pdev);
4277 dev_err(&pdev->dev, "cannot enable PCI device\n");
4281 err = pci_request_regions(pdev, DRV_NAME);
4283 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4284 goto err_out_disable;
4287 pci_set_master(pdev);
4289 if (sizeof(dma_addr_t) > sizeof(u32) &&
4290 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4292 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4294 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4295 "for consistent allocations\n");
4296 goto err_out_free_regions;
4299 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4301 dev_err(&pdev->dev, "no usable DMA configuration\n");
4302 goto err_out_free_regions;
4306 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4309 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4311 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4312 goto err_out_free_regions;
4317 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4319 dev_err(&pdev->dev, "cannot map device registers\n");
4320 goto err_out_free_hw;
4324 /* The sk98lin vendor driver uses hardware byte swapping but
4325 * this driver uses software swapping.
4329 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4330 reg &= ~PCI_REV_DESC;
4331 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4335 /* ring for status responses */
4336 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4338 goto err_out_iounmap;
4340 err = sky2_init(hw);
4342 goto err_out_iounmap;
4344 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4345 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4346 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4347 hw->chip_id, hw->chip_rev);
4351 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4354 goto err_out_free_pci;
4357 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4358 err = sky2_test_msi(hw);
4359 if (err == -EOPNOTSUPP)
4360 pci_disable_msi(pdev);
4362 goto err_out_free_netdev;
4365 err = register_netdev(dev);
4367 dev_err(&pdev->dev, "cannot register net device\n");
4368 goto err_out_free_netdev;
4371 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4373 err = request_irq(pdev->irq, sky2_intr,
4374 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4377 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4378 goto err_out_unregister;
4380 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4381 napi_enable(&hw->napi);
4383 sky2_show_addr(dev);
4385 if (hw->ports > 1) {
4386 struct net_device *dev1;
4388 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4390 dev_warn(&pdev->dev, "allocation for second device failed\n");
4391 else if ((err = register_netdev(dev1))) {
4392 dev_warn(&pdev->dev,
4393 "register of second port failed (%d)\n", err);
4397 sky2_show_addr(dev1);
4400 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4401 INIT_WORK(&hw->restart_work, sky2_restart);
4403 pci_set_drvdata(pdev, hw);
4408 if (hw->flags & SKY2_HW_USE_MSI)
4409 pci_disable_msi(pdev);
4410 unregister_netdev(dev);
4411 err_out_free_netdev:
4414 sky2_write8(hw, B0_CTST, CS_RST_SET);
4415 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4420 err_out_free_regions:
4421 pci_release_regions(pdev);
4423 pci_disable_device(pdev);
4425 pci_set_drvdata(pdev, NULL);
4429 static void __devexit sky2_remove(struct pci_dev *pdev)
4431 struct sky2_hw *hw = pci_get_drvdata(pdev);
4437 del_timer_sync(&hw->watchdog_timer);
4438 cancel_work_sync(&hw->restart_work);
4440 for (i = hw->ports-1; i >= 0; --i)
4441 unregister_netdev(hw->dev[i]);
4443 sky2_write32(hw, B0_IMSK, 0);
4447 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4448 sky2_write8(hw, B0_CTST, CS_RST_SET);
4449 sky2_read8(hw, B0_CTST);
4451 free_irq(pdev->irq, hw);
4452 if (hw->flags & SKY2_HW_USE_MSI)
4453 pci_disable_msi(pdev);
4454 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4455 pci_release_regions(pdev);
4456 pci_disable_device(pdev);
4458 for (i = hw->ports-1; i >= 0; --i)
4459 free_netdev(hw->dev[i]);
4464 pci_set_drvdata(pdev, NULL);
4468 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4470 struct sky2_hw *hw = pci_get_drvdata(pdev);
4476 del_timer_sync(&hw->watchdog_timer);
4477 cancel_work_sync(&hw->restart_work);
4479 for (i = 0; i < hw->ports; i++) {
4480 struct net_device *dev = hw->dev[i];
4481 struct sky2_port *sky2 = netdev_priv(dev);
4483 netif_device_detach(dev);
4484 if (netif_running(dev))
4488 sky2_wol_init(sky2);
4493 sky2_write32(hw, B0_IMSK, 0);
4494 napi_disable(&hw->napi);
4497 pci_save_state(pdev);
4498 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4499 sky2_power_state(hw, pci_choose_state(pdev, state));
4504 static int sky2_resume(struct pci_dev *pdev)
4506 struct sky2_hw *hw = pci_get_drvdata(pdev);
4512 sky2_power_state(hw, PCI_D0);
4514 err = pci_restore_state(pdev);
4518 pci_enable_wake(pdev, PCI_D0, 0);
4520 /* Re-enable all clocks */
4521 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4522 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4523 hw->chip_id == CHIP_ID_YUKON_FE_P)
4524 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4527 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4528 napi_enable(&hw->napi);
4530 for (i = 0; i < hw->ports; i++) {
4531 struct net_device *dev = hw->dev[i];
4533 netif_device_attach(dev);
4534 if (netif_running(dev)) {
4537 printk(KERN_ERR PFX "%s: could not up: %d\n",
4547 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4548 pci_disable_device(pdev);
4553 static void sky2_shutdown(struct pci_dev *pdev)
4555 struct sky2_hw *hw = pci_get_drvdata(pdev);
4561 del_timer_sync(&hw->watchdog_timer);
4563 for (i = 0; i < hw->ports; i++) {
4564 struct net_device *dev = hw->dev[i];
4565 struct sky2_port *sky2 = netdev_priv(dev);
4569 sky2_wol_init(sky2);
4576 pci_enable_wake(pdev, PCI_D3hot, wol);
4577 pci_enable_wake(pdev, PCI_D3cold, wol);
4579 pci_disable_device(pdev);
4580 sky2_power_state(hw, PCI_D3hot);
4583 static struct pci_driver sky2_driver = {
4585 .id_table = sky2_id_table,
4586 .probe = sky2_probe,
4587 .remove = __devexit_p(sky2_remove),
4589 .suspend = sky2_suspend,
4590 .resume = sky2_resume,
4592 .shutdown = sky2_shutdown,
4595 static int __init sky2_init_module(void)
4598 return pci_register_driver(&sky2_driver);
4601 static void __exit sky2_cleanup_module(void)
4603 pci_unregister_driver(&sky2_driver);
4604 sky2_debug_cleanup();
4607 module_init(sky2_init_module);
4608 module_exit(sky2_cleanup_module);
4610 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4611 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4612 MODULE_LICENSE("GPL");
4613 MODULE_VERSION(DRV_VERSION);