2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
113 RTL_GIGA_MAC_VER_21 = 0x15 // 8168C
116 #define _R(NAME,MAC,MASK) \
117 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
119 static const struct {
122 u32 RxConfigMask; /* Clears the bits supported by this chip */
123 } rtl_chip_info[] = {
124 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
125 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
126 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
127 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
129 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
130 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
131 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
132 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
133 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
135 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
136 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
137 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
138 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
141 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
142 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
143 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
144 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880) // PCI-E
154 static void rtl_hw_start_8169(struct net_device *);
155 static void rtl_hw_start_8168(struct net_device *);
156 static void rtl_hw_start_8101(struct net_device *);
158 static struct pci_device_id rtl8169_pci_tbl[] = {
159 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
160 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
164 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
165 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
167 { PCI_VENDOR_ID_LINKSYS, 0x1032,
168 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
170 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
174 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176 static int rx_copybreak = 200;
183 MAC0 = 0, /* Ethernet hardware address. */
185 MAR0 = 8, /* Multicast filter. */
186 CounterAddrLow = 0x10,
187 CounterAddrHigh = 0x14,
188 TxDescStartAddrLow = 0x20,
189 TxDescStartAddrHigh = 0x24,
190 TxHDescStartAddrLow = 0x28,
191 TxHDescStartAddrHigh = 0x2c,
214 RxDescAddrLow = 0xe4,
215 RxDescAddrHigh = 0xe8,
218 FuncEventMask = 0xf4,
219 FuncPresetState = 0xf8,
220 FuncForceEvent = 0xfc,
223 enum rtl8110_registers {
229 enum rtl8168_8101_registers {
232 #define CSIAR_FLAG 0x80000000
233 #define CSIAR_WRITE_CMD 0x80000000
234 #define CSIAR_BYTE_ENABLE 0x0f
235 #define CSIAR_BYTE_ENABLE_SHIFT 12
236 #define CSIAR_ADDR_MASK 0x0fff
239 #define EPHYAR_FLAG 0x80000000
240 #define EPHYAR_WRITE_CMD 0x80000000
241 #define EPHYAR_REG_MASK 0x1f
242 #define EPHYAR_REG_SHIFT 16
243 #define EPHYAR_DATA_MASK 0xffff
245 #define FIX_NAK_1 (1 << 4)
246 #define FIX_NAK_2 (1 << 3)
249 enum rtl_register_content {
250 /* InterruptStatusBits */
254 TxDescUnavail = 0x0080,
276 /* TXPoll register p.5 */
277 HPQ = 0x80, /* Poll cmd on the high prio queue */
278 NPQ = 0x40, /* Poll cmd on the low prio queue */
279 FSWInt = 0x01, /* Forced software interrupt */
283 Cfg9346_Unlock = 0xc0,
288 AcceptBroadcast = 0x08,
289 AcceptMulticast = 0x04,
291 AcceptAllPhys = 0x01,
298 TxInterFrameGapShift = 24,
299 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
301 /* Config1 register p.24 */
304 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
305 Speed_down = (1 << 4),
309 PMEnable = (1 << 0), /* Power Management Enable */
311 /* Config2 register p. 25 */
312 PCI_Clock_66MHz = 0x01,
313 PCI_Clock_33MHz = 0x00,
315 /* Config3 register p.25 */
316 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
317 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
318 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
320 /* Config5 register p.27 */
321 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
322 MWF = (1 << 5), /* Accept Multicast wakeup frame */
323 UWF = (1 << 4), /* Accept Unicast wakeup frame */
324 LanWake = (1 << 1), /* LanWake enable/disable */
325 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
328 TBIReset = 0x80000000,
329 TBILoopback = 0x40000000,
330 TBINwEnable = 0x20000000,
331 TBINwRestart = 0x10000000,
332 TBILinkOk = 0x02000000,
333 TBINwComplete = 0x01000000,
336 EnableBist = (1 << 15), // 8168 8101
337 Mac_dbgo_oe = (1 << 14), // 8168 8101
338 Normal_mode = (1 << 13), // unused
339 Force_half_dup = (1 << 12), // 8168 8101
340 Force_rxflow_en = (1 << 11), // 8168 8101
341 Force_txflow_en = (1 << 10), // 8168 8101
342 Cxpl_dbg_sel = (1 << 9), // 8168 8101
343 ASF = (1 << 8), // 8168 8101
344 PktCntrDisable = (1 << 7), // 8168 8101
345 Mac_dbgo_sel = 0x001c, // 8168
350 INTT_0 = 0x0000, // 8168
351 INTT_1 = 0x0001, // 8168
352 INTT_2 = 0x0002, // 8168
353 INTT_3 = 0x0003, // 8168
355 /* rtl8169_PHYstatus */
366 TBILinkOK = 0x02000000,
368 /* DumpCounterCommand */
372 enum desc_status_bit {
373 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
374 RingEnd = (1 << 30), /* End of descriptor ring */
375 FirstFrag = (1 << 29), /* First segment of a packet */
376 LastFrag = (1 << 28), /* Final segment of a packet */
379 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
380 MSSShift = 16, /* MSS value position */
381 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
382 IPCS = (1 << 18), /* Calculate IP checksum */
383 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
384 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
385 TxVlanTag = (1 << 17), /* Add VLAN tag */
388 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
389 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
391 #define RxProtoUDP (PID1)
392 #define RxProtoTCP (PID0)
393 #define RxProtoIP (PID1 | PID0)
394 #define RxProtoMask RxProtoIP
396 IPFail = (1 << 16), /* IP checksum failed */
397 UDPFail = (1 << 15), /* UDP/IP checksum failed */
398 TCPFail = (1 << 14), /* TCP/IP checksum failed */
399 RxVlanTag = (1 << 16), /* VLAN tag available */
402 #define RsvdMask 0x3fffc000
419 u8 __pad[sizeof(void *) - sizeof(u32)];
423 RTL_FEATURE_WOL = (1 << 0),
424 RTL_FEATURE_MSI = (1 << 1),
425 RTL_FEATURE_GMII = (1 << 2),
428 struct rtl8169_private {
429 void __iomem *mmio_addr; /* memory map physical address */
430 struct pci_dev *pci_dev; /* Index of PCI device */
431 struct net_device *dev;
432 struct napi_struct napi;
433 spinlock_t lock; /* spin lock flag */
437 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
438 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
441 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
442 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
443 dma_addr_t TxPhyAddr;
444 dma_addr_t RxPhyAddr;
445 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
446 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
449 struct timer_list timer;
454 int phy_auto_nego_reg;
455 int phy_1000_ctrl_reg;
456 #ifdef CONFIG_R8169_VLAN
457 struct vlan_group *vlgrp;
459 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
460 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
461 void (*phy_reset_enable)(void __iomem *);
462 void (*hw_start)(struct net_device *);
463 unsigned int (*phy_reset_pending)(void __iomem *);
464 unsigned int (*link_ok)(void __iomem *);
466 struct delayed_work task;
469 struct mii_if_info mii;
472 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
473 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
474 module_param(rx_copybreak, int, 0);
475 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
476 module_param(use_dac, int, 0);
477 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
478 module_param_named(debug, debug.msg_enable, int, 0);
479 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
480 MODULE_LICENSE("GPL");
481 MODULE_VERSION(RTL8169_VERSION);
483 static int rtl8169_open(struct net_device *dev);
484 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
485 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
486 static int rtl8169_init_ring(struct net_device *dev);
487 static void rtl_hw_start(struct net_device *dev);
488 static int rtl8169_close(struct net_device *dev);
489 static void rtl_set_rx_mode(struct net_device *dev);
490 static void rtl8169_tx_timeout(struct net_device *dev);
491 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
492 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
493 void __iomem *, u32 budget);
494 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
495 static void rtl8169_down(struct net_device *dev);
496 static void rtl8169_rx_clear(struct rtl8169_private *tp);
497 static int rtl8169_poll(struct napi_struct *napi, int budget);
499 static const unsigned int rtl8169_rx_config =
500 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
502 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
506 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
508 for (i = 20; i > 0; i--) {
510 * Check if the RTL8169 has completed writing to the specified
513 if (!(RTL_R32(PHYAR) & 0x80000000))
519 static int mdio_read(void __iomem *ioaddr, int reg_addr)
523 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
525 for (i = 20; i > 0; i--) {
527 * Check if the RTL8169 has completed retrieving data from
528 * the specified MII register.
530 if (RTL_R32(PHYAR) & 0x80000000) {
531 value = RTL_R32(PHYAR) & 0xffff;
539 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
541 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
544 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
547 struct rtl8169_private *tp = netdev_priv(dev);
548 void __iomem *ioaddr = tp->mmio_addr;
550 mdio_write(ioaddr, location, val);
553 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
555 struct rtl8169_private *tp = netdev_priv(dev);
556 void __iomem *ioaddr = tp->mmio_addr;
558 return mdio_read(ioaddr, location);
561 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
565 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
566 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
568 for (i = 0; i < 100; i++) {
569 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
575 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
580 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
582 for (i = 0; i < 100; i++) {
583 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
584 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
593 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
597 RTL_W32(CSIDR, value);
598 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
599 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
601 for (i = 0; i < 100; i++) {
602 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
608 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
613 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
614 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
616 for (i = 0; i < 100; i++) {
617 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
618 value = RTL_R32(CSIDR);
627 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
629 RTL_W16(IntrMask, 0x0000);
631 RTL_W16(IntrStatus, 0xffff);
634 static void rtl8169_asic_down(void __iomem *ioaddr)
636 RTL_W8(ChipCmd, 0x00);
637 rtl8169_irq_mask_and_ack(ioaddr);
641 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
643 return RTL_R32(TBICSR) & TBIReset;
646 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
648 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
651 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
653 return RTL_R32(TBICSR) & TBILinkOk;
656 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
658 return RTL_R8(PHYstatus) & LinkStatus;
661 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
663 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
666 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
670 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
671 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
674 static void rtl8169_check_link_status(struct net_device *dev,
675 struct rtl8169_private *tp,
676 void __iomem *ioaddr)
680 spin_lock_irqsave(&tp->lock, flags);
681 if (tp->link_ok(ioaddr)) {
682 netif_carrier_on(dev);
683 if (netif_msg_ifup(tp))
684 printk(KERN_INFO PFX "%s: link up\n", dev->name);
686 if (netif_msg_ifdown(tp))
687 printk(KERN_INFO PFX "%s: link down\n", dev->name);
688 netif_carrier_off(dev);
690 spin_unlock_irqrestore(&tp->lock, flags);
693 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
695 struct rtl8169_private *tp = netdev_priv(dev);
696 void __iomem *ioaddr = tp->mmio_addr;
701 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
702 wol->supported = WAKE_ANY;
704 spin_lock_irq(&tp->lock);
706 options = RTL_R8(Config1);
707 if (!(options & PMEnable))
710 options = RTL_R8(Config3);
711 if (options & LinkUp)
712 wol->wolopts |= WAKE_PHY;
713 if (options & MagicPacket)
714 wol->wolopts |= WAKE_MAGIC;
716 options = RTL_R8(Config5);
718 wol->wolopts |= WAKE_UCAST;
720 wol->wolopts |= WAKE_BCAST;
722 wol->wolopts |= WAKE_MCAST;
725 spin_unlock_irq(&tp->lock);
728 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
730 struct rtl8169_private *tp = netdev_priv(dev);
731 void __iomem *ioaddr = tp->mmio_addr;
738 { WAKE_ANY, Config1, PMEnable },
739 { WAKE_PHY, Config3, LinkUp },
740 { WAKE_MAGIC, Config3, MagicPacket },
741 { WAKE_UCAST, Config5, UWF },
742 { WAKE_BCAST, Config5, BWF },
743 { WAKE_MCAST, Config5, MWF },
744 { WAKE_ANY, Config5, LanWake }
747 spin_lock_irq(&tp->lock);
749 RTL_W8(Cfg9346, Cfg9346_Unlock);
751 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
752 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
753 if (wol->wolopts & cfg[i].opt)
754 options |= cfg[i].mask;
755 RTL_W8(cfg[i].reg, options);
758 RTL_W8(Cfg9346, Cfg9346_Lock);
761 tp->features |= RTL_FEATURE_WOL;
763 tp->features &= ~RTL_FEATURE_WOL;
764 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
766 spin_unlock_irq(&tp->lock);
771 static void rtl8169_get_drvinfo(struct net_device *dev,
772 struct ethtool_drvinfo *info)
774 struct rtl8169_private *tp = netdev_priv(dev);
776 strcpy(info->driver, MODULENAME);
777 strcpy(info->version, RTL8169_VERSION);
778 strcpy(info->bus_info, pci_name(tp->pci_dev));
781 static int rtl8169_get_regs_len(struct net_device *dev)
783 return R8169_REGS_SIZE;
786 static int rtl8169_set_speed_tbi(struct net_device *dev,
787 u8 autoneg, u16 speed, u8 duplex)
789 struct rtl8169_private *tp = netdev_priv(dev);
790 void __iomem *ioaddr = tp->mmio_addr;
794 reg = RTL_R32(TBICSR);
795 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
796 (duplex == DUPLEX_FULL)) {
797 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
798 } else if (autoneg == AUTONEG_ENABLE)
799 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
801 if (netif_msg_link(tp)) {
802 printk(KERN_WARNING "%s: "
803 "incorrect speed setting refused in TBI mode\n",
812 static int rtl8169_set_speed_xmii(struct net_device *dev,
813 u8 autoneg, u16 speed, u8 duplex)
815 struct rtl8169_private *tp = netdev_priv(dev);
816 void __iomem *ioaddr = tp->mmio_addr;
817 int auto_nego, giga_ctrl;
819 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
820 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
821 ADVERTISE_100HALF | ADVERTISE_100FULL);
822 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
823 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
825 if (autoneg == AUTONEG_ENABLE) {
826 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
827 ADVERTISE_100HALF | ADVERTISE_100FULL);
828 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
830 if (speed == SPEED_10)
831 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
832 else if (speed == SPEED_100)
833 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
834 else if (speed == SPEED_1000)
835 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
837 if (duplex == DUPLEX_HALF)
838 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
840 if (duplex == DUPLEX_FULL)
841 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
843 /* This tweak comes straight from Realtek's driver. */
844 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
845 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
846 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
847 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
851 /* The 8100e/8101e/8102e do Fast Ethernet only. */
852 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
853 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
854 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
855 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
856 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
858 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
859 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
860 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
861 netif_msg_link(tp)) {
862 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
865 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
868 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
870 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
871 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
872 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
875 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
877 mdio_write(ioaddr, 0x1f, 0x0000);
878 mdio_write(ioaddr, 0x0e, 0x0000);
881 tp->phy_auto_nego_reg = auto_nego;
882 tp->phy_1000_ctrl_reg = giga_ctrl;
884 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
885 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
886 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
890 static int rtl8169_set_speed(struct net_device *dev,
891 u8 autoneg, u16 speed, u8 duplex)
893 struct rtl8169_private *tp = netdev_priv(dev);
896 ret = tp->set_speed(dev, autoneg, speed, duplex);
898 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
899 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
904 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
906 struct rtl8169_private *tp = netdev_priv(dev);
910 spin_lock_irqsave(&tp->lock, flags);
911 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
912 spin_unlock_irqrestore(&tp->lock, flags);
917 static u32 rtl8169_get_rx_csum(struct net_device *dev)
919 struct rtl8169_private *tp = netdev_priv(dev);
921 return tp->cp_cmd & RxChkSum;
924 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
926 struct rtl8169_private *tp = netdev_priv(dev);
927 void __iomem *ioaddr = tp->mmio_addr;
930 spin_lock_irqsave(&tp->lock, flags);
933 tp->cp_cmd |= RxChkSum;
935 tp->cp_cmd &= ~RxChkSum;
937 RTL_W16(CPlusCmd, tp->cp_cmd);
940 spin_unlock_irqrestore(&tp->lock, flags);
945 #ifdef CONFIG_R8169_VLAN
947 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
950 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
951 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
954 static void rtl8169_vlan_rx_register(struct net_device *dev,
955 struct vlan_group *grp)
957 struct rtl8169_private *tp = netdev_priv(dev);
958 void __iomem *ioaddr = tp->mmio_addr;
961 spin_lock_irqsave(&tp->lock, flags);
964 tp->cp_cmd |= RxVlan;
966 tp->cp_cmd &= ~RxVlan;
967 RTL_W16(CPlusCmd, tp->cp_cmd);
969 spin_unlock_irqrestore(&tp->lock, flags);
972 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
975 u32 opts2 = le32_to_cpu(desc->opts2);
976 struct vlan_group *vlgrp = tp->vlgrp;
979 if (vlgrp && (opts2 & RxVlanTag)) {
980 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
988 #else /* !CONFIG_R8169_VLAN */
990 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
996 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1004 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1006 struct rtl8169_private *tp = netdev_priv(dev);
1007 void __iomem *ioaddr = tp->mmio_addr;
1011 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1012 cmd->port = PORT_FIBRE;
1013 cmd->transceiver = XCVR_INTERNAL;
1015 status = RTL_R32(TBICSR);
1016 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1017 cmd->autoneg = !!(status & TBINwEnable);
1019 cmd->speed = SPEED_1000;
1020 cmd->duplex = DUPLEX_FULL; /* Always set */
1025 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1027 struct rtl8169_private *tp = netdev_priv(dev);
1029 return mii_ethtool_gset(&tp->mii, cmd);
1032 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1034 struct rtl8169_private *tp = netdev_priv(dev);
1035 unsigned long flags;
1038 spin_lock_irqsave(&tp->lock, flags);
1040 rc = tp->get_settings(dev, cmd);
1042 spin_unlock_irqrestore(&tp->lock, flags);
1046 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1049 struct rtl8169_private *tp = netdev_priv(dev);
1050 unsigned long flags;
1052 if (regs->len > R8169_REGS_SIZE)
1053 regs->len = R8169_REGS_SIZE;
1055 spin_lock_irqsave(&tp->lock, flags);
1056 memcpy_fromio(p, tp->mmio_addr, regs->len);
1057 spin_unlock_irqrestore(&tp->lock, flags);
1060 static u32 rtl8169_get_msglevel(struct net_device *dev)
1062 struct rtl8169_private *tp = netdev_priv(dev);
1064 return tp->msg_enable;
1067 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1069 struct rtl8169_private *tp = netdev_priv(dev);
1071 tp->msg_enable = value;
1074 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1081 "tx_single_collisions",
1082 "tx_multi_collisions",
1090 struct rtl8169_counters {
1096 __le16 align_errors;
1097 __le32 tx_one_collision;
1098 __le32 tx_multi_collision;
1100 __le64 rx_broadcast;
1101 __le32 rx_multicast;
1106 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1110 return ARRAY_SIZE(rtl8169_gstrings);
1116 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1117 struct ethtool_stats *stats, u64 *data)
1119 struct rtl8169_private *tp = netdev_priv(dev);
1120 void __iomem *ioaddr = tp->mmio_addr;
1121 struct rtl8169_counters *counters;
1127 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1131 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1132 cmd = (u64)paddr & DMA_32BIT_MASK;
1133 RTL_W32(CounterAddrLow, cmd);
1134 RTL_W32(CounterAddrLow, cmd | CounterDump);
1136 while (RTL_R32(CounterAddrLow) & CounterDump) {
1137 if (msleep_interruptible(1))
1141 RTL_W32(CounterAddrLow, 0);
1142 RTL_W32(CounterAddrHigh, 0);
1144 data[0] = le64_to_cpu(counters->tx_packets);
1145 data[1] = le64_to_cpu(counters->rx_packets);
1146 data[2] = le64_to_cpu(counters->tx_errors);
1147 data[3] = le32_to_cpu(counters->rx_errors);
1148 data[4] = le16_to_cpu(counters->rx_missed);
1149 data[5] = le16_to_cpu(counters->align_errors);
1150 data[6] = le32_to_cpu(counters->tx_one_collision);
1151 data[7] = le32_to_cpu(counters->tx_multi_collision);
1152 data[8] = le64_to_cpu(counters->rx_unicast);
1153 data[9] = le64_to_cpu(counters->rx_broadcast);
1154 data[10] = le32_to_cpu(counters->rx_multicast);
1155 data[11] = le16_to_cpu(counters->tx_aborted);
1156 data[12] = le16_to_cpu(counters->tx_underun);
1158 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1161 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1165 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1170 static const struct ethtool_ops rtl8169_ethtool_ops = {
1171 .get_drvinfo = rtl8169_get_drvinfo,
1172 .get_regs_len = rtl8169_get_regs_len,
1173 .get_link = ethtool_op_get_link,
1174 .get_settings = rtl8169_get_settings,
1175 .set_settings = rtl8169_set_settings,
1176 .get_msglevel = rtl8169_get_msglevel,
1177 .set_msglevel = rtl8169_set_msglevel,
1178 .get_rx_csum = rtl8169_get_rx_csum,
1179 .set_rx_csum = rtl8169_set_rx_csum,
1180 .set_tx_csum = ethtool_op_set_tx_csum,
1181 .set_sg = ethtool_op_set_sg,
1182 .set_tso = ethtool_op_set_tso,
1183 .get_regs = rtl8169_get_regs,
1184 .get_wol = rtl8169_get_wol,
1185 .set_wol = rtl8169_set_wol,
1186 .get_strings = rtl8169_get_strings,
1187 .get_sset_count = rtl8169_get_sset_count,
1188 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1191 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1192 int bitnum, int bitval)
1196 val = mdio_read(ioaddr, reg);
1197 val = (bitval == 1) ?
1198 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1199 mdio_write(ioaddr, reg, val & 0xffff);
1202 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1203 void __iomem *ioaddr)
1206 * The driver currently handles the 8168Bf and the 8168Be identically
1207 * but they can be identified more specifically through the test below
1210 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1212 * Same thing for the 8101Eb and the 8101Ec:
1214 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1222 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1223 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1224 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1225 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1226 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1229 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1230 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1231 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1232 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1235 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1236 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1237 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1238 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1239 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1240 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1241 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1242 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1243 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1244 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1245 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1246 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1247 /* FIXME: where did these entries come from ? -- FR */
1248 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1249 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1252 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1253 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1254 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1255 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1256 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1257 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1259 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1263 reg = RTL_R32(TxConfig);
1264 while ((reg & p->mask) != p->val)
1266 tp->mac_version = p->mac_version;
1268 if (p->mask == 0x00000000) {
1269 struct pci_dev *pdev = tp->pci_dev;
1271 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1275 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1277 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1285 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1288 mdio_write(ioaddr, regs->reg, regs->val);
1293 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1296 u16 regs[5]; /* Beware of bit-sign propagation */
1297 } phy_magic[5] = { {
1298 { 0x0000, //w 4 15 12 0
1299 0x00a1, //w 3 15 0 00a1
1300 0x0008, //w 2 15 0 0008
1301 0x1020, //w 1 15 0 1020
1302 0x1000 } },{ //w 0 15 0 1000
1303 { 0x7000, //w 4 15 12 7
1304 0xff41, //w 3 15 0 ff41
1305 0xde60, //w 2 15 0 de60
1306 0x0140, //w 1 15 0 0140
1307 0x0077 } },{ //w 0 15 0 0077
1308 { 0xa000, //w 4 15 12 a
1309 0xdf01, //w 3 15 0 df01
1310 0xdf20, //w 2 15 0 df20
1311 0xff95, //w 1 15 0 ff95
1312 0xfa00 } },{ //w 0 15 0 fa00
1313 { 0xb000, //w 4 15 12 b
1314 0xff41, //w 3 15 0 ff41
1315 0xde20, //w 2 15 0 de20
1316 0x0140, //w 1 15 0 0140
1317 0x00bb } },{ //w 0 15 0 00bb
1318 { 0xf000, //w 4 15 12 f
1319 0xdf01, //w 3 15 0 df01
1320 0xdf20, //w 2 15 0 df20
1321 0xff95, //w 1 15 0 ff95
1322 0xbf00 } //w 0 15 0 bf00
1327 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1328 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1329 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1330 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1332 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1335 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1336 mdio_write(ioaddr, pos, val);
1338 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1339 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1340 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1342 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1345 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1347 struct phy_reg phy_reg_init[] = {
1353 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1356 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1358 struct phy_reg phy_reg_init[] = {
1363 mdio_write(ioaddr, 0x1f, 0x0001);
1364 mdio_patch(ioaddr, 0x16, 1 << 0);
1366 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1369 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1371 struct phy_reg phy_reg_init[] = {
1377 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1380 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1382 struct phy_reg phy_reg_init[] = {
1390 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1393 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1395 struct phy_reg phy_reg_init[] = {
1415 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1417 mdio_patch(ioaddr, 0x14, 1 << 5);
1418 mdio_patch(ioaddr, 0x0d, 1 << 5);
1419 mdio_write(ioaddr, 0x1f, 0x0000);
1422 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1424 struct phy_reg phy_reg_init[] = {
1442 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1444 mdio_patch(ioaddr, 0x16, 1 << 0);
1445 mdio_patch(ioaddr, 0x14, 1 << 5);
1446 mdio_patch(ioaddr, 0x0d, 1 << 5);
1447 mdio_write(ioaddr, 0x1f, 0x0000);
1450 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1452 struct phy_reg phy_reg_init[] = {
1464 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1466 mdio_patch(ioaddr, 0x16, 1 << 0);
1467 mdio_patch(ioaddr, 0x14, 1 << 5);
1468 mdio_patch(ioaddr, 0x0d, 1 << 5);
1469 mdio_write(ioaddr, 0x1f, 0x0000);
1472 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1474 struct phy_reg phy_reg_init[] = {
1481 mdio_write(ioaddr, 0x1f, 0x0000);
1482 mdio_patch(ioaddr, 0x11, 1 << 12);
1483 mdio_patch(ioaddr, 0x19, 1 << 13);
1485 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1488 static void rtl_hw_phy_config(struct net_device *dev)
1490 struct rtl8169_private *tp = netdev_priv(dev);
1491 void __iomem *ioaddr = tp->mmio_addr;
1493 rtl8169_print_mac_version(tp);
1495 switch (tp->mac_version) {
1496 case RTL_GIGA_MAC_VER_01:
1498 case RTL_GIGA_MAC_VER_02:
1499 case RTL_GIGA_MAC_VER_03:
1500 rtl8169s_hw_phy_config(ioaddr);
1502 case RTL_GIGA_MAC_VER_04:
1503 rtl8169sb_hw_phy_config(ioaddr);
1505 case RTL_GIGA_MAC_VER_07:
1506 case RTL_GIGA_MAC_VER_08:
1507 case RTL_GIGA_MAC_VER_09:
1508 rtl8102e_hw_phy_config(ioaddr);
1510 case RTL_GIGA_MAC_VER_11:
1511 rtl8168bb_hw_phy_config(ioaddr);
1513 case RTL_GIGA_MAC_VER_12:
1514 rtl8168bef_hw_phy_config(ioaddr);
1516 case RTL_GIGA_MAC_VER_17:
1517 rtl8168bef_hw_phy_config(ioaddr);
1519 case RTL_GIGA_MAC_VER_18:
1520 rtl8168cp_hw_phy_config(ioaddr);
1522 case RTL_GIGA_MAC_VER_19:
1523 rtl8168c_1_hw_phy_config(ioaddr);
1525 case RTL_GIGA_MAC_VER_20:
1526 rtl8168c_2_hw_phy_config(ioaddr);
1528 case RTL_GIGA_MAC_VER_21:
1529 rtl8168c_3_hw_phy_config(ioaddr);
1536 static void rtl8169_phy_timer(unsigned long __opaque)
1538 struct net_device *dev = (struct net_device *)__opaque;
1539 struct rtl8169_private *tp = netdev_priv(dev);
1540 struct timer_list *timer = &tp->timer;
1541 void __iomem *ioaddr = tp->mmio_addr;
1542 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1544 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1546 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1549 spin_lock_irq(&tp->lock);
1551 if (tp->phy_reset_pending(ioaddr)) {
1553 * A busy loop could burn quite a few cycles on nowadays CPU.
1554 * Let's delay the execution of the timer for a few ticks.
1560 if (tp->link_ok(ioaddr))
1563 if (netif_msg_link(tp))
1564 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1566 tp->phy_reset_enable(ioaddr);
1569 mod_timer(timer, jiffies + timeout);
1571 spin_unlock_irq(&tp->lock);
1574 static inline void rtl8169_delete_timer(struct net_device *dev)
1576 struct rtl8169_private *tp = netdev_priv(dev);
1577 struct timer_list *timer = &tp->timer;
1579 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1582 del_timer_sync(timer);
1585 static inline void rtl8169_request_timer(struct net_device *dev)
1587 struct rtl8169_private *tp = netdev_priv(dev);
1588 struct timer_list *timer = &tp->timer;
1590 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1593 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1596 #ifdef CONFIG_NET_POLL_CONTROLLER
1598 * Polling 'interrupt' - used by things like netconsole to send skbs
1599 * without having to re-enable interrupts. It's not called while
1600 * the interrupt routine is executing.
1602 static void rtl8169_netpoll(struct net_device *dev)
1604 struct rtl8169_private *tp = netdev_priv(dev);
1605 struct pci_dev *pdev = tp->pci_dev;
1607 disable_irq(pdev->irq);
1608 rtl8169_interrupt(pdev->irq, dev);
1609 enable_irq(pdev->irq);
1613 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1614 void __iomem *ioaddr)
1617 pci_release_regions(pdev);
1618 pci_disable_device(pdev);
1622 static void rtl8169_phy_reset(struct net_device *dev,
1623 struct rtl8169_private *tp)
1625 void __iomem *ioaddr = tp->mmio_addr;
1628 tp->phy_reset_enable(ioaddr);
1629 for (i = 0; i < 100; i++) {
1630 if (!tp->phy_reset_pending(ioaddr))
1634 if (netif_msg_link(tp))
1635 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1638 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1640 void __iomem *ioaddr = tp->mmio_addr;
1642 rtl_hw_phy_config(dev);
1644 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1645 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1649 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1651 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1652 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1654 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1655 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1657 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1658 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1661 rtl8169_phy_reset(dev, tp);
1664 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1665 * only 8101. Don't panic.
1667 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1669 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1670 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1673 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1675 void __iomem *ioaddr = tp->mmio_addr;
1679 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1680 high = addr[4] | (addr[5] << 8);
1682 spin_lock_irq(&tp->lock);
1684 RTL_W8(Cfg9346, Cfg9346_Unlock);
1686 RTL_W32(MAC4, high);
1687 RTL_W8(Cfg9346, Cfg9346_Lock);
1689 spin_unlock_irq(&tp->lock);
1692 static int rtl_set_mac_address(struct net_device *dev, void *p)
1694 struct rtl8169_private *tp = netdev_priv(dev);
1695 struct sockaddr *addr = p;
1697 if (!is_valid_ether_addr(addr->sa_data))
1698 return -EADDRNOTAVAIL;
1700 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1702 rtl_rar_set(tp, dev->dev_addr);
1707 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1709 struct rtl8169_private *tp = netdev_priv(dev);
1710 struct mii_ioctl_data *data = if_mii(ifr);
1712 if (!netif_running(dev))
1717 data->phy_id = 32; /* Internal PHY */
1721 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1725 if (!capable(CAP_NET_ADMIN))
1727 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1733 static const struct rtl_cfg_info {
1734 void (*hw_start)(struct net_device *);
1735 unsigned int region;
1740 } rtl_cfg_infos [] = {
1742 .hw_start = rtl_hw_start_8169,
1745 .intr_event = SYSErr | LinkChg | RxOverflow |
1746 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1747 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1748 .features = RTL_FEATURE_GMII
1751 .hw_start = rtl_hw_start_8168,
1754 .intr_event = SYSErr | LinkChg | RxOverflow |
1755 TxErr | TxOK | RxOK | RxErr,
1756 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1757 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1760 .hw_start = rtl_hw_start_8101,
1763 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1764 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1765 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1766 .features = RTL_FEATURE_MSI
1770 /* Cfg9346_Unlock assumed. */
1771 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1772 const struct rtl_cfg_info *cfg)
1777 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1778 if (cfg->features & RTL_FEATURE_MSI) {
1779 if (pci_enable_msi(pdev)) {
1780 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1783 msi = RTL_FEATURE_MSI;
1786 RTL_W8(Config2, cfg2);
1790 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1792 if (tp->features & RTL_FEATURE_MSI) {
1793 pci_disable_msi(pdev);
1794 tp->features &= ~RTL_FEATURE_MSI;
1798 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1800 int ret, count = 100;
1804 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1810 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1813 } while (!(status & PCI_VPD_ADDR_F) && --count);
1815 if (!(status & PCI_VPD_ADDR_F))
1818 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1822 *val = cpu_to_le32(value);
1827 static void rtl_init_mac_address(struct rtl8169_private *tp,
1828 void __iomem *ioaddr)
1830 struct pci_dev *pdev = tp->pci_dev;
1834 DECLARE_MAC_BUF(buf);
1836 cfg1 = RTL_R8(Config1);
1837 if (!(cfg1 & VPD)) {
1838 dprintk("VPD access not enabled, enabling\n");
1839 RTL_W8(Cfg9346, Cfg9346_Unlock);
1840 RTL_W8(Config1, cfg1 | VPD);
1841 RTL_W8(Cfg9346, Cfg9346_Lock);
1844 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1848 /* MAC address is stored in EEPROM at offset 0x0e
1849 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1850 * address as defined in the PCI 2.2 Specifications, but the VPD data
1851 * is always consecutive 4-byte data starting from the VPD address
1854 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1855 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1856 dprintk("Reading MAC address from EEPROM failed\n");
1860 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1862 /* Write MAC address */
1863 rtl_rar_set(tp, mac);
1866 static int __devinit
1867 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1869 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1870 const unsigned int region = cfg->region;
1871 struct rtl8169_private *tp;
1872 struct mii_if_info *mii;
1873 struct net_device *dev;
1874 void __iomem *ioaddr;
1878 if (netif_msg_drv(&debug)) {
1879 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1880 MODULENAME, RTL8169_VERSION);
1883 dev = alloc_etherdev(sizeof (*tp));
1885 if (netif_msg_drv(&debug))
1886 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1891 SET_NETDEV_DEV(dev, &pdev->dev);
1892 tp = netdev_priv(dev);
1895 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1899 mii->mdio_read = rtl_mdio_read;
1900 mii->mdio_write = rtl_mdio_write;
1901 mii->phy_id_mask = 0x1f;
1902 mii->reg_num_mask = 0x1f;
1903 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1905 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1906 rc = pci_enable_device(pdev);
1908 if (netif_msg_probe(tp))
1909 dev_err(&pdev->dev, "enable failure\n");
1910 goto err_out_free_dev_1;
1913 rc = pci_set_mwi(pdev);
1915 goto err_out_disable_2;
1917 /* make sure PCI base addr 1 is MMIO */
1918 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1919 if (netif_msg_probe(tp)) {
1921 "region #%d not an MMIO resource, aborting\n",
1928 /* check for weird/broken PCI region reporting */
1929 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1930 if (netif_msg_probe(tp)) {
1932 "Invalid PCI region size(s), aborting\n");
1938 rc = pci_request_regions(pdev, MODULENAME);
1940 if (netif_msg_probe(tp))
1941 dev_err(&pdev->dev, "could not request regions.\n");
1945 tp->cp_cmd = PCIMulRW | RxChkSum;
1947 if ((sizeof(dma_addr_t) > 4) &&
1948 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1949 tp->cp_cmd |= PCIDAC;
1950 dev->features |= NETIF_F_HIGHDMA;
1952 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1954 if (netif_msg_probe(tp)) {
1956 "DMA configuration failed.\n");
1958 goto err_out_free_res_4;
1962 pci_set_master(pdev);
1964 /* ioremap MMIO region */
1965 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1967 if (netif_msg_probe(tp))
1968 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1970 goto err_out_free_res_4;
1973 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1974 if (!tp->pcie_cap && netif_msg_probe(tp))
1975 dev_info(&pdev->dev, "no PCI Express capability\n");
1977 /* Unneeded ? Don't mess with Mrs. Murphy. */
1978 rtl8169_irq_mask_and_ack(ioaddr);
1980 /* Soft reset the chip. */
1981 RTL_W8(ChipCmd, CmdReset);
1983 /* Check that the chip has finished the reset. */
1984 for (i = 0; i < 100; i++) {
1985 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1987 msleep_interruptible(1);
1990 /* Identify chip attached to board */
1991 rtl8169_get_mac_version(tp, ioaddr);
1993 rtl8169_print_mac_version(tp);
1995 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1996 if (tp->mac_version == rtl_chip_info[i].mac_version)
1999 if (i == ARRAY_SIZE(rtl_chip_info)) {
2000 /* Unknown chip: assume array element #0, original RTL-8169 */
2001 if (netif_msg_probe(tp)) {
2002 dev_printk(KERN_DEBUG, &pdev->dev,
2003 "unknown chip version, assuming %s\n",
2004 rtl_chip_info[0].name);
2010 RTL_W8(Cfg9346, Cfg9346_Unlock);
2011 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2012 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2013 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2014 tp->features |= RTL_FEATURE_WOL;
2015 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2016 tp->features |= RTL_FEATURE_WOL;
2017 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2018 RTL_W8(Cfg9346, Cfg9346_Lock);
2020 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2021 (RTL_R8(PHYstatus) & TBI_Enable)) {
2022 tp->set_speed = rtl8169_set_speed_tbi;
2023 tp->get_settings = rtl8169_gset_tbi;
2024 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2025 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2026 tp->link_ok = rtl8169_tbi_link_ok;
2028 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2030 tp->set_speed = rtl8169_set_speed_xmii;
2031 tp->get_settings = rtl8169_gset_xmii;
2032 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2033 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2034 tp->link_ok = rtl8169_xmii_link_ok;
2036 dev->do_ioctl = rtl8169_ioctl;
2039 spin_lock_init(&tp->lock);
2041 rtl_init_mac_address(tp, ioaddr);
2043 /* Get MAC address */
2044 for (i = 0; i < MAC_ADDR_LEN; i++)
2045 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2046 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2048 dev->open = rtl8169_open;
2049 dev->hard_start_xmit = rtl8169_start_xmit;
2050 dev->get_stats = rtl8169_get_stats;
2051 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2052 dev->stop = rtl8169_close;
2053 dev->tx_timeout = rtl8169_tx_timeout;
2054 dev->set_multicast_list = rtl_set_rx_mode;
2055 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2056 dev->irq = pdev->irq;
2057 dev->base_addr = (unsigned long) ioaddr;
2058 dev->change_mtu = rtl8169_change_mtu;
2059 dev->set_mac_address = rtl_set_mac_address;
2061 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2063 #ifdef CONFIG_R8169_VLAN
2064 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2065 dev->vlan_rx_register = rtl8169_vlan_rx_register;
2068 #ifdef CONFIG_NET_POLL_CONTROLLER
2069 dev->poll_controller = rtl8169_netpoll;
2072 tp->intr_mask = 0xffff;
2073 tp->mmio_addr = ioaddr;
2074 tp->align = cfg->align;
2075 tp->hw_start = cfg->hw_start;
2076 tp->intr_event = cfg->intr_event;
2077 tp->napi_event = cfg->napi_event;
2079 init_timer(&tp->timer);
2080 tp->timer.data = (unsigned long) dev;
2081 tp->timer.function = rtl8169_phy_timer;
2083 rc = register_netdev(dev);
2087 pci_set_drvdata(pdev, dev);
2089 if (netif_msg_probe(tp)) {
2090 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2092 printk(KERN_INFO "%s: %s at 0x%lx, "
2093 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2094 "XID %08x IRQ %d\n",
2096 rtl_chip_info[tp->chipset].name,
2098 dev->dev_addr[0], dev->dev_addr[1],
2099 dev->dev_addr[2], dev->dev_addr[3],
2100 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2103 rtl8169_init_phy(dev, tp);
2104 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2110 rtl_disable_msi(pdev, tp);
2113 pci_release_regions(pdev);
2115 pci_clear_mwi(pdev);
2117 pci_disable_device(pdev);
2123 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2125 struct net_device *dev = pci_get_drvdata(pdev);
2126 struct rtl8169_private *tp = netdev_priv(dev);
2128 flush_scheduled_work();
2130 unregister_netdev(dev);
2131 rtl_disable_msi(pdev, tp);
2132 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2133 pci_set_drvdata(pdev, NULL);
2136 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2137 struct net_device *dev)
2139 unsigned int mtu = dev->mtu;
2141 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2144 static int rtl8169_open(struct net_device *dev)
2146 struct rtl8169_private *tp = netdev_priv(dev);
2147 struct pci_dev *pdev = tp->pci_dev;
2148 int retval = -ENOMEM;
2151 rtl8169_set_rxbufsize(tp, dev);
2154 * Rx and Tx desscriptors needs 256 bytes alignment.
2155 * pci_alloc_consistent provides more.
2157 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2159 if (!tp->TxDescArray)
2162 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2164 if (!tp->RxDescArray)
2167 retval = rtl8169_init_ring(dev);
2171 INIT_DELAYED_WORK(&tp->task, NULL);
2175 retval = request_irq(dev->irq, rtl8169_interrupt,
2176 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2179 goto err_release_ring_2;
2181 napi_enable(&tp->napi);
2185 rtl8169_request_timer(dev);
2187 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2192 rtl8169_rx_clear(tp);
2194 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2197 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2202 static void rtl8169_hw_reset(void __iomem *ioaddr)
2204 /* Disable interrupts */
2205 rtl8169_irq_mask_and_ack(ioaddr);
2207 /* Reset the chipset */
2208 RTL_W8(ChipCmd, CmdReset);
2214 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2216 void __iomem *ioaddr = tp->mmio_addr;
2217 u32 cfg = rtl8169_rx_config;
2219 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2220 RTL_W32(RxConfig, cfg);
2222 /* Set DMA burst size and Interframe Gap Time */
2223 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2224 (InterFrameGap << TxInterFrameGapShift));
2227 static void rtl_hw_start(struct net_device *dev)
2229 struct rtl8169_private *tp = netdev_priv(dev);
2230 void __iomem *ioaddr = tp->mmio_addr;
2233 /* Soft reset the chip. */
2234 RTL_W8(ChipCmd, CmdReset);
2236 /* Check that the chip has finished the reset. */
2237 for (i = 0; i < 100; i++) {
2238 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2240 msleep_interruptible(1);
2245 netif_start_queue(dev);
2249 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2250 void __iomem *ioaddr)
2253 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2254 * register to be written before TxDescAddrLow to work.
2255 * Switching from MMIO to I/O access fixes the issue as well.
2257 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2258 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2259 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2260 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2263 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2267 cmd = RTL_R16(CPlusCmd);
2268 RTL_W16(CPlusCmd, cmd);
2272 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2274 /* Low hurts. Let's disable the filtering. */
2275 RTL_W16(RxMaxSize, 16383);
2278 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2285 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2286 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2287 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2288 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2293 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2294 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2295 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2296 RTL_W32(0x7c, p->val);
2302 static void rtl_hw_start_8169(struct net_device *dev)
2304 struct rtl8169_private *tp = netdev_priv(dev);
2305 void __iomem *ioaddr = tp->mmio_addr;
2306 struct pci_dev *pdev = tp->pci_dev;
2308 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2309 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2310 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2313 RTL_W8(Cfg9346, Cfg9346_Unlock);
2314 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2315 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2316 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2317 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2318 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2320 RTL_W8(EarlyTxThres, EarlyTxThld);
2322 rtl_set_rx_max_size(ioaddr);
2324 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2325 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2326 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2327 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2328 rtl_set_rx_tx_config_registers(tp);
2330 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2332 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2333 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2334 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2335 "Bit-3 and bit-14 MUST be 1\n");
2336 tp->cp_cmd |= (1 << 14);
2339 RTL_W16(CPlusCmd, tp->cp_cmd);
2341 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2344 * Undocumented corner. Supposedly:
2345 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2347 RTL_W16(IntrMitigate, 0x0000);
2349 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2351 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2352 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2353 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2354 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2355 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2356 rtl_set_rx_tx_config_registers(tp);
2359 RTL_W8(Cfg9346, Cfg9346_Lock);
2361 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2364 RTL_W32(RxMissed, 0);
2366 rtl_set_rx_mode(dev);
2368 /* no early-rx interrupts */
2369 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2371 /* Enable all known interrupts by setting the interrupt mask. */
2372 RTL_W16(IntrMask, tp->intr_event);
2375 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2377 struct net_device *dev = pci_get_drvdata(pdev);
2378 struct rtl8169_private *tp = netdev_priv(dev);
2379 int cap = tp->pcie_cap;
2384 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2385 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2386 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2390 static void rtl_csi_access_enable(void __iomem *ioaddr)
2394 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2395 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2399 unsigned int offset;
2404 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2409 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2410 rtl_ephy_write(ioaddr, e->offset, w);
2415 static void rtl_disable_clock_request(struct pci_dev *pdev)
2417 struct net_device *dev = pci_get_drvdata(pdev);
2418 struct rtl8169_private *tp = netdev_priv(dev);
2419 int cap = tp->pcie_cap;
2424 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2425 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2426 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2430 #define R8168_CPCMD_QUIRK_MASK (\
2441 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2443 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2445 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2447 rtl_tx_performance_tweak(pdev,
2448 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2451 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2453 rtl_hw_start_8168bb(ioaddr, pdev);
2455 RTL_W8(EarlyTxThres, EarlyTxThld);
2457 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2460 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2462 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2464 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2466 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2468 rtl_disable_clock_request(pdev);
2470 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2473 static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2475 static struct ephy_info e_info_8168cp[] = {
2476 { 0x01, 0, 0x0001 },
2477 { 0x02, 0x0800, 0x1000 },
2478 { 0x03, 0, 0x0042 },
2479 { 0x06, 0x0080, 0x0000 },
2483 rtl_csi_access_enable(ioaddr);
2485 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2487 __rtl_hw_start_8168cp(ioaddr, pdev);
2490 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2492 static struct ephy_info e_info_8168c_1[] = {
2493 { 0x02, 0x0800, 0x1000 },
2494 { 0x03, 0, 0x0002 },
2495 { 0x06, 0x0080, 0x0000 }
2498 rtl_csi_access_enable(ioaddr);
2500 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2502 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2504 __rtl_hw_start_8168cp(ioaddr, pdev);
2507 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2509 static struct ephy_info e_info_8168c_2[] = {
2510 { 0x01, 0, 0x0001 },
2511 { 0x03, 0x0400, 0x0220 }
2514 rtl_csi_access_enable(ioaddr);
2516 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2518 __rtl_hw_start_8168cp(ioaddr, pdev);
2521 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2523 rtl_hw_start_8168c_2(ioaddr, pdev);
2526 static void rtl_hw_start_8168(struct net_device *dev)
2528 struct rtl8169_private *tp = netdev_priv(dev);
2529 void __iomem *ioaddr = tp->mmio_addr;
2530 struct pci_dev *pdev = tp->pci_dev;
2532 RTL_W8(Cfg9346, Cfg9346_Unlock);
2534 RTL_W8(EarlyTxThres, EarlyTxThld);
2536 rtl_set_rx_max_size(ioaddr);
2538 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2540 RTL_W16(CPlusCmd, tp->cp_cmd);
2542 RTL_W16(IntrMitigate, 0x5151);
2544 /* Work around for RxFIFO overflow. */
2545 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2546 tp->intr_event |= RxFIFOOver | PCSTimeout;
2547 tp->intr_event &= ~RxOverflow;
2550 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2552 rtl_set_rx_mode(dev);
2554 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2555 (InterFrameGap << TxInterFrameGapShift));
2559 switch (tp->mac_version) {
2560 case RTL_GIGA_MAC_VER_11:
2561 rtl_hw_start_8168bb(ioaddr, pdev);
2564 case RTL_GIGA_MAC_VER_12:
2565 case RTL_GIGA_MAC_VER_17:
2566 rtl_hw_start_8168bef(ioaddr, pdev);
2569 case RTL_GIGA_MAC_VER_18:
2570 rtl_hw_start_8168cp(ioaddr, pdev);
2573 case RTL_GIGA_MAC_VER_19:
2574 rtl_hw_start_8168c_1(ioaddr, pdev);
2577 case RTL_GIGA_MAC_VER_20:
2578 rtl_hw_start_8168c_2(ioaddr, pdev);
2581 case RTL_GIGA_MAC_VER_21:
2582 rtl_hw_start_8168c_3(ioaddr, pdev);
2586 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2587 dev->name, tp->mac_version);
2591 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2593 RTL_W8(Cfg9346, Cfg9346_Lock);
2595 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2597 RTL_W16(IntrMask, tp->intr_event);
2600 #define R810X_CPCMD_QUIRK_MASK (\
2612 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2614 static struct ephy_info e_info_8102e_1[] = {
2615 { 0x01, 0, 0x6e65 },
2616 { 0x02, 0, 0x091f },
2617 { 0x03, 0, 0xc2f9 },
2618 { 0x06, 0, 0xafb5 },
2619 { 0x07, 0, 0x0e00 },
2620 { 0x19, 0, 0xec80 },
2621 { 0x01, 0, 0x2e65 },
2626 rtl_csi_access_enable(ioaddr);
2628 RTL_W8(DBG_REG, FIX_NAK_1);
2630 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2633 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2634 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2636 cfg1 = RTL_R8(Config1);
2637 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2638 RTL_W8(Config1, cfg1 & ~LEDS0);
2640 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2642 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2645 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2647 rtl_csi_access_enable(ioaddr);
2649 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2651 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2652 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2654 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2657 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2659 rtl_hw_start_8102e_2(ioaddr, pdev);
2661 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2664 static void rtl_hw_start_8101(struct net_device *dev)
2666 struct rtl8169_private *tp = netdev_priv(dev);
2667 void __iomem *ioaddr = tp->mmio_addr;
2668 struct pci_dev *pdev = tp->pci_dev;
2670 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2671 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2672 int cap = tp->pcie_cap;
2675 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2676 PCI_EXP_DEVCTL_NOSNOOP_EN);
2680 switch (tp->mac_version) {
2681 case RTL_GIGA_MAC_VER_07:
2682 rtl_hw_start_8102e_1(ioaddr, pdev);
2685 case RTL_GIGA_MAC_VER_08:
2686 rtl_hw_start_8102e_3(ioaddr, pdev);
2689 case RTL_GIGA_MAC_VER_09:
2690 rtl_hw_start_8102e_2(ioaddr, pdev);
2694 RTL_W8(Cfg9346, Cfg9346_Unlock);
2696 RTL_W8(EarlyTxThres, EarlyTxThld);
2698 rtl_set_rx_max_size(ioaddr);
2700 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2702 RTL_W16(CPlusCmd, tp->cp_cmd);
2704 RTL_W16(IntrMitigate, 0x0000);
2706 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2708 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2709 rtl_set_rx_tx_config_registers(tp);
2711 RTL_W8(Cfg9346, Cfg9346_Lock);
2715 rtl_set_rx_mode(dev);
2717 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2719 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2721 RTL_W16(IntrMask, tp->intr_event);
2724 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2726 struct rtl8169_private *tp = netdev_priv(dev);
2729 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2734 if (!netif_running(dev))
2739 rtl8169_set_rxbufsize(tp, dev);
2741 ret = rtl8169_init_ring(dev);
2745 napi_enable(&tp->napi);
2749 rtl8169_request_timer(dev);
2755 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2757 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2758 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2761 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2762 struct sk_buff **sk_buff, struct RxDesc *desc)
2764 struct pci_dev *pdev = tp->pci_dev;
2766 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2767 PCI_DMA_FROMDEVICE);
2768 dev_kfree_skb(*sk_buff);
2770 rtl8169_make_unusable_by_asic(desc);
2773 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2775 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2777 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2780 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2783 desc->addr = cpu_to_le64(mapping);
2785 rtl8169_mark_to_asic(desc, rx_buf_sz);
2788 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2789 struct net_device *dev,
2790 struct RxDesc *desc, int rx_buf_sz,
2793 struct sk_buff *skb;
2797 pad = align ? align : NET_IP_ALIGN;
2799 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2803 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2805 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2806 PCI_DMA_FROMDEVICE);
2808 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2813 rtl8169_make_unusable_by_asic(desc);
2817 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2821 for (i = 0; i < NUM_RX_DESC; i++) {
2822 if (tp->Rx_skbuff[i]) {
2823 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2824 tp->RxDescArray + i);
2829 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2834 for (cur = start; end - cur != 0; cur++) {
2835 struct sk_buff *skb;
2836 unsigned int i = cur % NUM_RX_DESC;
2838 WARN_ON((s32)(end - cur) < 0);
2840 if (tp->Rx_skbuff[i])
2843 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2844 tp->RxDescArray + i,
2845 tp->rx_buf_sz, tp->align);
2849 tp->Rx_skbuff[i] = skb;
2854 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2856 desc->opts1 |= cpu_to_le32(RingEnd);
2859 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2861 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2864 static int rtl8169_init_ring(struct net_device *dev)
2866 struct rtl8169_private *tp = netdev_priv(dev);
2868 rtl8169_init_ring_indexes(tp);
2870 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2871 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2873 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2876 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2881 rtl8169_rx_clear(tp);
2885 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2886 struct TxDesc *desc)
2888 unsigned int len = tx_skb->len;
2890 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2897 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2901 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2902 unsigned int entry = i % NUM_TX_DESC;
2903 struct ring_info *tx_skb = tp->tx_skb + entry;
2904 unsigned int len = tx_skb->len;
2907 struct sk_buff *skb = tx_skb->skb;
2909 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2910 tp->TxDescArray + entry);
2915 tp->dev->stats.tx_dropped++;
2918 tp->cur_tx = tp->dirty_tx = 0;
2921 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2923 struct rtl8169_private *tp = netdev_priv(dev);
2925 PREPARE_DELAYED_WORK(&tp->task, task);
2926 schedule_delayed_work(&tp->task, 4);
2929 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2931 struct rtl8169_private *tp = netdev_priv(dev);
2932 void __iomem *ioaddr = tp->mmio_addr;
2934 synchronize_irq(dev->irq);
2936 /* Wait for any pending NAPI task to complete */
2937 napi_disable(&tp->napi);
2939 rtl8169_irq_mask_and_ack(ioaddr);
2941 tp->intr_mask = 0xffff;
2942 RTL_W16(IntrMask, tp->intr_event);
2943 napi_enable(&tp->napi);
2946 static void rtl8169_reinit_task(struct work_struct *work)
2948 struct rtl8169_private *tp =
2949 container_of(work, struct rtl8169_private, task.work);
2950 struct net_device *dev = tp->dev;
2955 if (!netif_running(dev))
2958 rtl8169_wait_for_quiescence(dev);
2961 ret = rtl8169_open(dev);
2962 if (unlikely(ret < 0)) {
2963 if (net_ratelimit() && netif_msg_drv(tp)) {
2964 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2965 " Rescheduling.\n", dev->name, ret);
2967 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2974 static void rtl8169_reset_task(struct work_struct *work)
2976 struct rtl8169_private *tp =
2977 container_of(work, struct rtl8169_private, task.work);
2978 struct net_device *dev = tp->dev;
2982 if (!netif_running(dev))
2985 rtl8169_wait_for_quiescence(dev);
2987 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2988 rtl8169_tx_clear(tp);
2990 if (tp->dirty_rx == tp->cur_rx) {
2991 rtl8169_init_ring_indexes(tp);
2993 netif_wake_queue(dev);
2994 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2996 if (net_ratelimit() && netif_msg_intr(tp)) {
2997 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3000 rtl8169_schedule_work(dev, rtl8169_reset_task);
3007 static void rtl8169_tx_timeout(struct net_device *dev)
3009 struct rtl8169_private *tp = netdev_priv(dev);
3011 rtl8169_hw_reset(tp->mmio_addr);
3013 /* Let's wait a bit while any (async) irq lands on */
3014 rtl8169_schedule_work(dev, rtl8169_reset_task);
3017 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3020 struct skb_shared_info *info = skb_shinfo(skb);
3021 unsigned int cur_frag, entry;
3022 struct TxDesc * uninitialized_var(txd);
3025 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3026 skb_frag_t *frag = info->frags + cur_frag;
3031 entry = (entry + 1) % NUM_TX_DESC;
3033 txd = tp->TxDescArray + entry;
3035 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3036 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3038 /* anti gcc 2.95.3 bugware (sic) */
3039 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3041 txd->opts1 = cpu_to_le32(status);
3042 txd->addr = cpu_to_le64(mapping);
3044 tp->tx_skb[entry].len = len;
3048 tp->tx_skb[entry].skb = skb;
3049 txd->opts1 |= cpu_to_le32(LastFrag);
3055 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3057 if (dev->features & NETIF_F_TSO) {
3058 u32 mss = skb_shinfo(skb)->gso_size;
3061 return LargeSend | ((mss & MSSMask) << MSSShift);
3063 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3064 const struct iphdr *ip = ip_hdr(skb);
3066 if (ip->protocol == IPPROTO_TCP)
3067 return IPCS | TCPCS;
3068 else if (ip->protocol == IPPROTO_UDP)
3069 return IPCS | UDPCS;
3070 WARN_ON(1); /* we need a WARN() */
3075 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3077 struct rtl8169_private *tp = netdev_priv(dev);
3078 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3079 struct TxDesc *txd = tp->TxDescArray + entry;
3080 void __iomem *ioaddr = tp->mmio_addr;
3084 int ret = NETDEV_TX_OK;
3086 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3087 if (netif_msg_drv(tp)) {
3089 "%s: BUG! Tx Ring full when queue awake!\n",
3095 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3098 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3100 frags = rtl8169_xmit_frags(tp, skb, opts1);
3102 len = skb_headlen(skb);
3107 if (unlikely(len < ETH_ZLEN)) {
3108 if (skb_padto(skb, ETH_ZLEN))
3109 goto err_update_stats;
3113 opts1 |= FirstFrag | LastFrag;
3114 tp->tx_skb[entry].skb = skb;
3117 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3119 tp->tx_skb[entry].len = len;
3120 txd->addr = cpu_to_le64(mapping);
3121 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3125 /* anti gcc 2.95.3 bugware (sic) */
3126 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3127 txd->opts1 = cpu_to_le32(status);
3129 dev->trans_start = jiffies;
3131 tp->cur_tx += frags + 1;
3135 RTL_W8(TxPoll, NPQ); /* set polling bit */
3137 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3138 netif_stop_queue(dev);
3140 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3141 netif_wake_queue(dev);
3148 netif_stop_queue(dev);
3149 ret = NETDEV_TX_BUSY;
3151 dev->stats.tx_dropped++;
3155 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3157 struct rtl8169_private *tp = netdev_priv(dev);
3158 struct pci_dev *pdev = tp->pci_dev;
3159 void __iomem *ioaddr = tp->mmio_addr;
3160 u16 pci_status, pci_cmd;
3162 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3163 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3165 if (netif_msg_intr(tp)) {
3167 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3168 dev->name, pci_cmd, pci_status);
3172 * The recovery sequence below admits a very elaborated explanation:
3173 * - it seems to work;
3174 * - I did not see what else could be done;
3175 * - it makes iop3xx happy.
3177 * Feel free to adjust to your needs.
3179 if (pdev->broken_parity_status)
3180 pci_cmd &= ~PCI_COMMAND_PARITY;
3182 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3184 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3186 pci_write_config_word(pdev, PCI_STATUS,
3187 pci_status & (PCI_STATUS_DETECTED_PARITY |
3188 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3189 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3191 /* The infamous DAC f*ckup only happens at boot time */
3192 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3193 if (netif_msg_intr(tp))
3194 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3195 tp->cp_cmd &= ~PCIDAC;
3196 RTL_W16(CPlusCmd, tp->cp_cmd);
3197 dev->features &= ~NETIF_F_HIGHDMA;
3200 rtl8169_hw_reset(ioaddr);
3202 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3205 static void rtl8169_tx_interrupt(struct net_device *dev,
3206 struct rtl8169_private *tp,
3207 void __iomem *ioaddr)
3209 unsigned int dirty_tx, tx_left;
3211 dirty_tx = tp->dirty_tx;
3213 tx_left = tp->cur_tx - dirty_tx;
3215 while (tx_left > 0) {
3216 unsigned int entry = dirty_tx % NUM_TX_DESC;
3217 struct ring_info *tx_skb = tp->tx_skb + entry;
3218 u32 len = tx_skb->len;
3222 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3223 if (status & DescOwn)
3226 dev->stats.tx_bytes += len;
3227 dev->stats.tx_packets++;
3229 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3231 if (status & LastFrag) {
3232 dev_kfree_skb_irq(tx_skb->skb);
3239 if (tp->dirty_tx != dirty_tx) {
3240 tp->dirty_tx = dirty_tx;
3242 if (netif_queue_stopped(dev) &&
3243 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3244 netif_wake_queue(dev);
3247 * 8168 hack: TxPoll requests are lost when the Tx packets are
3248 * too close. Let's kick an extra TxPoll request when a burst
3249 * of start_xmit activity is detected (if it is not detected,
3250 * it is slow enough). -- FR
3253 if (tp->cur_tx != dirty_tx)
3254 RTL_W8(TxPoll, NPQ);
3258 static inline int rtl8169_fragmented_frame(u32 status)
3260 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3263 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3265 u32 opts1 = le32_to_cpu(desc->opts1);
3266 u32 status = opts1 & RxProtoMask;
3268 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3269 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3270 ((status == RxProtoIP) && !(opts1 & IPFail)))
3271 skb->ip_summed = CHECKSUM_UNNECESSARY;
3273 skb->ip_summed = CHECKSUM_NONE;
3276 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3277 struct rtl8169_private *tp, int pkt_size,
3280 struct sk_buff *skb;
3283 if (pkt_size >= rx_copybreak)
3286 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3290 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3291 PCI_DMA_FROMDEVICE);
3292 skb_reserve(skb, NET_IP_ALIGN);
3293 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3300 static int rtl8169_rx_interrupt(struct net_device *dev,
3301 struct rtl8169_private *tp,
3302 void __iomem *ioaddr, u32 budget)
3304 unsigned int cur_rx, rx_left;
3305 unsigned int delta, count;
3307 cur_rx = tp->cur_rx;
3308 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3309 rx_left = min(rx_left, budget);
3311 for (; rx_left > 0; rx_left--, cur_rx++) {
3312 unsigned int entry = cur_rx % NUM_RX_DESC;
3313 struct RxDesc *desc = tp->RxDescArray + entry;
3317 status = le32_to_cpu(desc->opts1);
3319 if (status & DescOwn)
3321 if (unlikely(status & RxRES)) {
3322 if (netif_msg_rx_err(tp)) {
3324 "%s: Rx ERROR. status = %08x\n",
3327 dev->stats.rx_errors++;
3328 if (status & (RxRWT | RxRUNT))
3329 dev->stats.rx_length_errors++;
3331 dev->stats.rx_crc_errors++;
3332 if (status & RxFOVF) {
3333 rtl8169_schedule_work(dev, rtl8169_reset_task);
3334 dev->stats.rx_fifo_errors++;
3336 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3338 struct sk_buff *skb = tp->Rx_skbuff[entry];
3339 dma_addr_t addr = le64_to_cpu(desc->addr);
3340 int pkt_size = (status & 0x00001FFF) - 4;
3341 struct pci_dev *pdev = tp->pci_dev;
3344 * The driver does not support incoming fragmented
3345 * frames. They are seen as a symptom of over-mtu
3348 if (unlikely(rtl8169_fragmented_frame(status))) {
3349 dev->stats.rx_dropped++;
3350 dev->stats.rx_length_errors++;
3351 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3355 rtl8169_rx_csum(skb, desc);
3357 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3358 pci_dma_sync_single_for_device(pdev, addr,
3359 pkt_size, PCI_DMA_FROMDEVICE);
3360 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3362 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3363 PCI_DMA_FROMDEVICE);
3364 tp->Rx_skbuff[entry] = NULL;
3367 skb_put(skb, pkt_size);
3368 skb->protocol = eth_type_trans(skb, dev);
3370 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3371 netif_receive_skb(skb);
3373 dev->last_rx = jiffies;
3374 dev->stats.rx_bytes += pkt_size;
3375 dev->stats.rx_packets++;
3378 /* Work around for AMD plateform. */
3379 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3380 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3386 count = cur_rx - tp->cur_rx;
3387 tp->cur_rx = cur_rx;
3389 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3390 if (!delta && count && netif_msg_intr(tp))
3391 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3392 tp->dirty_rx += delta;
3395 * FIXME: until there is periodic timer to try and refill the ring,
3396 * a temporary shortage may definitely kill the Rx process.
3397 * - disable the asic to try and avoid an overflow and kick it again
3399 * - how do others driver handle this condition (Uh oh...).
3401 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3402 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3407 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3409 struct net_device *dev = dev_instance;
3410 struct rtl8169_private *tp = netdev_priv(dev);
3411 void __iomem *ioaddr = tp->mmio_addr;
3415 status = RTL_R16(IntrStatus);
3417 /* hotplug/major error/no more work/shared irq */
3418 if ((status == 0xffff) || !status)
3423 if (unlikely(!netif_running(dev))) {
3424 rtl8169_asic_down(ioaddr);
3428 status &= tp->intr_mask;
3430 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3432 if (!(status & tp->intr_event))
3435 /* Work around for rx fifo overflow */
3436 if (unlikely(status & RxFIFOOver) &&
3437 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3438 netif_stop_queue(dev);
3439 rtl8169_tx_timeout(dev);
3443 if (unlikely(status & SYSErr)) {
3444 rtl8169_pcierr_interrupt(dev);
3448 if (status & LinkChg)
3449 rtl8169_check_link_status(dev, tp, ioaddr);
3451 if (status & tp->napi_event) {
3452 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3453 tp->intr_mask = ~tp->napi_event;
3455 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3456 __netif_rx_schedule(dev, &tp->napi);
3457 else if (netif_msg_intr(tp)) {
3458 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3463 return IRQ_RETVAL(handled);
3466 static int rtl8169_poll(struct napi_struct *napi, int budget)
3468 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3469 struct net_device *dev = tp->dev;
3470 void __iomem *ioaddr = tp->mmio_addr;
3473 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3474 rtl8169_tx_interrupt(dev, tp, ioaddr);
3476 if (work_done < budget) {
3477 netif_rx_complete(dev, napi);
3478 tp->intr_mask = 0xffff;
3480 * 20040426: the barrier is not strictly required but the
3481 * behavior of the irq handler could be less predictable
3482 * without it. Btw, the lack of flush for the posted pci
3483 * write is safe - FR
3486 RTL_W16(IntrMask, tp->intr_event);
3492 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3494 struct rtl8169_private *tp = netdev_priv(dev);
3496 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3499 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3500 RTL_W32(RxMissed, 0);
3503 static void rtl8169_down(struct net_device *dev)
3505 struct rtl8169_private *tp = netdev_priv(dev);
3506 void __iomem *ioaddr = tp->mmio_addr;
3507 unsigned int intrmask;
3509 rtl8169_delete_timer(dev);
3511 netif_stop_queue(dev);
3513 napi_disable(&tp->napi);
3516 spin_lock_irq(&tp->lock);
3518 rtl8169_asic_down(ioaddr);
3520 rtl8169_rx_missed(dev, ioaddr);
3522 spin_unlock_irq(&tp->lock);
3524 synchronize_irq(dev->irq);
3526 /* Give a racing hard_start_xmit a few cycles to complete. */
3527 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3530 * And now for the 50k$ question: are IRQ disabled or not ?
3532 * Two paths lead here:
3534 * -> netif_running() is available to sync the current code and the
3535 * IRQ handler. See rtl8169_interrupt for details.
3536 * 2) dev->change_mtu
3537 * -> rtl8169_poll can not be issued again and re-enable the
3538 * interruptions. Let's simply issue the IRQ down sequence again.
3540 * No loop if hotpluged or major error (0xffff).
3542 intrmask = RTL_R16(IntrMask);
3543 if (intrmask && (intrmask != 0xffff))
3546 rtl8169_tx_clear(tp);
3548 rtl8169_rx_clear(tp);
3551 static int rtl8169_close(struct net_device *dev)
3553 struct rtl8169_private *tp = netdev_priv(dev);
3554 struct pci_dev *pdev = tp->pci_dev;
3558 free_irq(dev->irq, dev);
3560 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3562 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3564 tp->TxDescArray = NULL;
3565 tp->RxDescArray = NULL;
3570 static void rtl_set_rx_mode(struct net_device *dev)
3572 struct rtl8169_private *tp = netdev_priv(dev);
3573 void __iomem *ioaddr = tp->mmio_addr;
3574 unsigned long flags;
3575 u32 mc_filter[2]; /* Multicast hash filter */
3579 if (dev->flags & IFF_PROMISC) {
3580 /* Unconditionally log net taps. */
3581 if (netif_msg_link(tp)) {
3582 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3586 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3588 mc_filter[1] = mc_filter[0] = 0xffffffff;
3589 } else if ((dev->mc_count > multicast_filter_limit)
3590 || (dev->flags & IFF_ALLMULTI)) {
3591 /* Too many to filter perfectly -- accept all multicasts. */
3592 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3593 mc_filter[1] = mc_filter[0] = 0xffffffff;
3595 struct dev_mc_list *mclist;
3598 rx_mode = AcceptBroadcast | AcceptMyPhys;
3599 mc_filter[1] = mc_filter[0] = 0;
3600 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3601 i++, mclist = mclist->next) {
3602 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3603 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3604 rx_mode |= AcceptMulticast;
3608 spin_lock_irqsave(&tp->lock, flags);
3610 tmp = rtl8169_rx_config | rx_mode |
3611 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3613 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3614 u32 data = mc_filter[0];
3616 mc_filter[0] = swab32(mc_filter[1]);
3617 mc_filter[1] = swab32(data);
3620 RTL_W32(MAR0 + 0, mc_filter[0]);
3621 RTL_W32(MAR0 + 4, mc_filter[1]);
3623 RTL_W32(RxConfig, tmp);
3625 spin_unlock_irqrestore(&tp->lock, flags);
3629 * rtl8169_get_stats - Get rtl8169 read/write statistics
3630 * @dev: The Ethernet Device to get statistics for
3632 * Get TX/RX statistics for rtl8169
3634 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3636 struct rtl8169_private *tp = netdev_priv(dev);
3637 void __iomem *ioaddr = tp->mmio_addr;
3638 unsigned long flags;
3640 if (netif_running(dev)) {
3641 spin_lock_irqsave(&tp->lock, flags);
3642 rtl8169_rx_missed(dev, ioaddr);
3643 spin_unlock_irqrestore(&tp->lock, flags);
3651 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3653 struct net_device *dev = pci_get_drvdata(pdev);
3654 struct rtl8169_private *tp = netdev_priv(dev);
3655 void __iomem *ioaddr = tp->mmio_addr;
3657 if (!netif_running(dev))
3658 goto out_pci_suspend;
3660 netif_device_detach(dev);
3661 netif_stop_queue(dev);
3663 spin_lock_irq(&tp->lock);
3665 rtl8169_asic_down(ioaddr);
3667 rtl8169_rx_missed(dev, ioaddr);
3669 spin_unlock_irq(&tp->lock);
3672 pci_save_state(pdev);
3673 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3674 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3675 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3680 static int rtl8169_resume(struct pci_dev *pdev)
3682 struct net_device *dev = pci_get_drvdata(pdev);
3684 pci_set_power_state(pdev, PCI_D0);
3685 pci_restore_state(pdev);
3686 pci_enable_wake(pdev, PCI_D0, 0);
3688 if (!netif_running(dev))
3691 netif_device_attach(dev);
3693 rtl8169_schedule_work(dev, rtl8169_reset_task);
3698 #endif /* CONFIG_PM */
3700 static struct pci_driver rtl8169_pci_driver = {
3702 .id_table = rtl8169_pci_tbl,
3703 .probe = rtl8169_init_one,
3704 .remove = __devexit_p(rtl8169_remove_one),
3706 .suspend = rtl8169_suspend,
3707 .resume = rtl8169_resume,
3711 static int __init rtl8169_init_module(void)
3713 return pci_register_driver(&rtl8169_pci_driver);
3716 static void __exit rtl8169_cleanup_module(void)
3718 pci_unregister_driver(&rtl8169_pci_driver);
3721 module_init(rtl8169_init_module);
3722 module_exit(rtl8169_cleanup_module);