1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/rockchip.c
5 * Driver for ROCKCHIP Ethernet PHYs
7 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
9 * David Wu <david.wu@rock-chips.com>
12 #include <linux/ethtool.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/mii.h>
16 #include <linux/netdevice.h>
17 #include <linux/phy.h>
19 #define INTERNAL_EPHY_ID 0x1234d400
21 #define MII_INTERNAL_CTRL_STATUS 17
22 #define SMI_ADDR_TSTCNTL 20
23 #define SMI_ADDR_TSTREAD1 21
24 #define SMI_ADDR_TSTREAD2 22
25 #define SMI_ADDR_TSTWRITE 23
26 #define MII_SPECIAL_CONTROL_STATUS 31
28 #define MII_AUTO_MDIX_EN BIT(7)
29 #define MII_MDIX_EN BIT(6)
31 #define MII_SPEED_10 BIT(2)
32 #define MII_SPEED_100 BIT(3)
34 #define TSTCNTL_RD (BIT(15) | BIT(10))
35 #define TSTCNTL_WR (BIT(14) | BIT(10))
37 #define TSTMODE_ENABLE 0x400
38 #define TSTMODE_DISABLE 0x0
40 #define WR_ADDR_A7CFG 0x18
42 static int rockchip_init_tstmode(struct phy_device *phydev)
46 /* Enable access to Analog and DSP register banks */
47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
58 static int rockchip_close_tstmode(struct phy_device *phydev)
60 /* Back to basic register bank */
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
64 static int rockchip_integrated_phy_analog_init(struct phy_device *phydev)
68 ret = rockchip_init_tstmode(phydev);
73 * Adjust tx amplitude to make sginal better,
74 * the default value is 0x8.
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB);
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG);
83 return rockchip_close_tstmode(phydev);
86 static int rockchip_integrated_phy_config_init(struct phy_device *phydev)
91 * The auto MIDX has linked problem on some board,
92 * workround to disable auto MDIX.
94 val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
97 val &= ~MII_AUTO_MDIX_EN;
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
102 return rockchip_integrated_phy_analog_init(phydev);
105 static void rockchip_link_change_notify(struct phy_device *phydev)
107 int speed = SPEED_10;
109 if (phydev->autoneg == AUTONEG_ENABLE) {
110 int reg = phy_read(phydev, MII_SPECIAL_CONTROL_STATUS);
113 phydev_err(phydev, "phy_read err: %d.\n", reg);
117 if (reg & MII_SPEED_100)
119 else if (reg & MII_SPEED_10)
122 int bmcr = phy_read(phydev, MII_BMCR);
125 phydev_err(phydev, "phy_read err: %d.\n", bmcr);
129 if (bmcr & BMCR_SPEED100)
136 * If mode switch happens from 10BT to 100BT, all DSP/AFE
137 * registers are set to default values. So any AFE/DSP
138 * registers have to be re-initialized in this case.
140 if ((phydev->speed == SPEED_10) && (speed == SPEED_100)) {
141 int ret = rockchip_integrated_phy_analog_init(phydev);
143 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n",
148 static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
152 /* get the current settings */
153 reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
157 reg &= ~MII_AUTO_MDIX_EN;
166 case ETH_TP_MDI_AUTO:
167 case ETH_TP_MDI_INVALID:
173 /* Set the new polarity value in the register */
174 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
182 static int rockchip_config_aneg(struct phy_device *phydev)
186 err = rockchip_set_polarity(phydev, phydev->mdix);
190 return genphy_config_aneg(phydev);
193 static int rockchip_phy_resume(struct phy_device *phydev)
195 genphy_resume(phydev);
197 return rockchip_integrated_phy_config_init(phydev);
200 static struct phy_driver rockchip_phy_driver[] = {
202 .phy_id = INTERNAL_EPHY_ID,
203 .phy_id_mask = 0xfffffff0,
204 .name = "Rockchip integrated EPHY",
205 .features = PHY_BASIC_FEATURES,
207 .link_change_notify = rockchip_link_change_notify,
208 .soft_reset = genphy_soft_reset,
209 .config_init = rockchip_integrated_phy_config_init,
210 .config_aneg = rockchip_config_aneg,
211 .suspend = genphy_suspend,
212 .resume = rockchip_phy_resume,
216 module_phy_driver(rockchip_phy_driver);
218 static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
219 { INTERNAL_EPHY_ID, 0xfffffff0 },
223 MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
225 MODULE_AUTHOR("David Wu <david.wu@rock-chips.com>");
226 MODULE_DESCRIPTION("Rockchip Ethernet PHY driver");
227 MODULE_LICENSE("GPL");