2 * Clause 45 PHY support
4 #include <linux/ethtool.h>
5 #include <linux/export.h>
6 #include <linux/mdio.h>
11 * genphy_c45_setup_forced - configures a forced speed
12 * @phydev: target phy_device struct
14 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
16 int ctrl1, ctrl2, ret;
18 /* Half duplex is not supported */
19 if (phydev->duplex != DUPLEX_FULL)
22 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
26 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
30 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
32 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1
33 * in 802.3-2012 and 802.3-2015.
35 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
37 switch (phydev->speed) {
39 ctrl2 |= MDIO_PMA_CTRL2_10BT;
42 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
43 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
46 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
47 /* Assume 1000base-T */
48 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
51 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
52 /* Assume 2.5Gbase-T */
53 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
56 ctrl1 |= MDIO_CTRL1_SPEED5G;
58 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
61 ctrl1 |= MDIO_CTRL1_SPEED10G;
62 /* Assume 10Gbase-T */
63 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
69 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
73 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
77 return genphy_c45_an_disable_aneg(phydev);
79 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
82 * genphy_c45_an_config_aneg - configure advertisement registers
83 * @phydev: target phy_device struct
85 * Configure advertisement registers based on modes set in phydev->advertising
87 * Returns negative errno code on failure, 0 if advertisement didn't change,
88 * or 1 if advertised modes changed.
90 int genphy_c45_an_config_aneg(struct phy_device *phydev)
95 linkmode_and(phydev->advertising, phydev->advertising,
98 changed = genphy_config_eee_advert(phydev);
100 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
102 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
103 ADVERTISE_ALL | ADVERTISE_100BASE4 |
104 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
111 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
114 MDIO_AN_10GBT_CTRL_ADV10G |
115 MDIO_AN_10GBT_CTRL_ADV5G |
116 MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
124 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
127 * genphy_c45_an_disable_aneg - disable auto-negotiation
128 * @phydev: target phy_device struct
130 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
131 * parameters are controlled through the PMA/PMD MMD registers.
133 * Returns zero on success, negative errno code on failure.
135 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
138 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
139 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
141 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
144 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
145 * @phydev: target phy_device struct
147 * This assumes that the auto-negotiation MMD is present.
149 * Enable and restart auto-negotiation.
151 int genphy_c45_restart_aneg(struct phy_device *phydev)
153 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
154 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
156 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
159 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
160 * @phydev: target phy_device struct
161 * @restart: whether aneg restart is requested
163 * This assumes that the auto-negotiation MMD is present.
165 * Check, and restart auto-negotiation if needed.
167 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
172 /* Configure and restart aneg if it wasn't set before */
173 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
177 if (!(ret & MDIO_AN_CTRL1_ENABLE))
182 ret = genphy_c45_restart_aneg(phydev);
186 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
189 * genphy_c45_aneg_done - return auto-negotiation complete status
190 * @phydev: target phy_device struct
192 * This assumes that the auto-negotiation MMD is present.
194 * Reads the status register from the auto-negotiation MMD, returning:
195 * - positive if auto-negotiation is complete
196 * - negative errno code on error
199 int genphy_c45_aneg_done(struct phy_device *phydev)
201 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
203 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
205 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
208 * genphy_c45_read_link - read the overall link status from the MMDs
209 * @phydev: target phy_device struct
211 * Read the link status from the specified MMDs, and if they all indicate
212 * that the link is up, set phydev->link to 1. If an error is encountered,
213 * a negative errno will be returned, otherwise zero.
215 int genphy_c45_read_link(struct phy_device *phydev)
217 u32 mmd_mask = MDIO_DEVS_PMAPMD;
221 while (mmd_mask && link) {
222 devad = __ffs(mmd_mask);
223 mmd_mask &= ~BIT(devad);
225 /* The link state is latched low so that momentary link
226 * drops can be detected. Do not double-read the status
227 * in polling mode to detect such short link drops.
229 if (!phy_polling_mode(phydev)) {
230 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
233 else if (val & MDIO_STAT1_LSTATUS)
237 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
241 if (!(val & MDIO_STAT1_LSTATUS))
249 EXPORT_SYMBOL_GPL(genphy_c45_read_link);
252 * genphy_c45_read_lpa - read the link partner advertisement and pause
253 * @phydev: target phy_device struct
255 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
256 * filling in the link partner advertisement, pause and asym_pause members
257 * in @phydev. This assumes that the auto-negotiation MMD is present, and
258 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
259 * to fill in the remainder of the link partner advert from vendor registers.
261 int genphy_c45_read_lpa(struct phy_device *phydev)
265 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
269 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
270 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
271 phydev->lp_advertising);
272 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
273 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
275 phydev->asym_pause = 0;
280 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
281 val & MDIO_AN_STAT1_LPABLE);
283 /* Read the link partner's base page advertisement */
284 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
288 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
289 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
290 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
292 /* Read the link partner's 10G advertisement */
293 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
297 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
301 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
304 * genphy_c45_read_pma - read link speed etc from PMA
305 * @phydev: target phy_device struct
307 int genphy_c45_read_pma(struct phy_device *phydev)
311 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
315 switch (val & MDIO_CTRL1_SPEEDSEL) {
317 phydev->speed = SPEED_10;
319 case MDIO_PMA_CTRL1_SPEED100:
320 phydev->speed = SPEED_100;
322 case MDIO_PMA_CTRL1_SPEED1000:
323 phydev->speed = SPEED_1000;
325 case MDIO_CTRL1_SPEED2_5G:
326 phydev->speed = SPEED_2500;
328 case MDIO_CTRL1_SPEED5G:
329 phydev->speed = SPEED_5000;
331 case MDIO_CTRL1_SPEED10G:
332 phydev->speed = SPEED_10000;
335 phydev->speed = SPEED_UNKNOWN;
339 phydev->duplex = DUPLEX_FULL;
343 EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
346 * genphy_c45_read_mdix - read mdix status from PMA
347 * @phydev: target phy_device struct
349 int genphy_c45_read_mdix(struct phy_device *phydev)
353 if (phydev->speed == SPEED_10000) {
354 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
355 MDIO_PMA_10GBT_SWAPPOL);
360 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
361 phydev->mdix = ETH_TP_MDI;
365 phydev->mdix = ETH_TP_MDI_X;
369 phydev->mdix = ETH_TP_MDI_INVALID;
376 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
379 * genphy_c45_pma_read_abilities - read supported link modes from PMA
380 * @phydev: target phy_device struct
382 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
383 * 1.8.9 is set, the list of supported modes is build using the values in the
384 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
385 * modes. If bit 1.11.14 is set, then the list is also extended with the modes
386 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
387 * 5GBASET are supported.
389 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
393 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
394 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
395 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
399 if (val & MDIO_AN_STAT1_ABLE)
400 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
404 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
408 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
410 val & MDIO_PMA_STAT2_10GBSR);
412 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
414 val & MDIO_PMA_STAT2_10GBLR);
416 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
418 val & MDIO_PMA_STAT2_10GBER);
420 if (val & MDIO_PMA_STAT2_EXTABLE) {
421 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
425 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
427 val & MDIO_PMA_EXTABLE_10GBLRM);
428 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
430 val & MDIO_PMA_EXTABLE_10GBT);
431 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
433 val & MDIO_PMA_EXTABLE_10GBKX4);
434 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
436 val & MDIO_PMA_EXTABLE_10GBKR);
437 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
439 val & MDIO_PMA_EXTABLE_1000BT);
440 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
442 val & MDIO_PMA_EXTABLE_1000BKX);
444 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
446 val & MDIO_PMA_EXTABLE_100BTX);
447 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
449 val & MDIO_PMA_EXTABLE_100BTX);
451 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
453 val & MDIO_PMA_EXTABLE_10BT);
454 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
456 val & MDIO_PMA_EXTABLE_10BT);
458 if (val & MDIO_PMA_EXTABLE_NBT) {
459 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
460 MDIO_PMA_NG_EXTABLE);
464 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
466 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
468 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
470 val & MDIO_PMA_NG_EXTABLE_5GBT);
476 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
479 * genphy_c45_read_status - read PHY status
480 * @phydev: target phy_device struct
482 * Reads status from PHY and sets phy_device members accordingly.
484 int genphy_c45_read_status(struct phy_device *phydev)
488 ret = genphy_c45_read_link(phydev);
492 phydev->speed = SPEED_UNKNOWN;
493 phydev->duplex = DUPLEX_UNKNOWN;
495 phydev->asym_pause = 0;
497 if (phydev->autoneg == AUTONEG_ENABLE) {
498 ret = genphy_c45_read_lpa(phydev);
502 phy_resolve_aneg_linkmode(phydev);
504 ret = genphy_c45_read_pma(phydev);
509 EXPORT_SYMBOL_GPL(genphy_c45_read_status);
511 /* The gen10g_* functions are the old Clause 45 stub */
513 int gen10g_config_aneg(struct phy_device *phydev)
517 EXPORT_SYMBOL_GPL(gen10g_config_aneg);
519 struct phy_driver genphy_c45_driver = {
520 .phy_id = 0xffffffff,
521 .phy_id_mask = 0xffffffff,
522 .name = "Generic Clause 45 PHY",
523 .soft_reset = genphy_no_soft_reset,
524 .read_status = genphy_c45_read_status,