1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
5 #include <linux/ethtool.h>
6 #include <linux/export.h>
7 #include <linux/mdio.h>
12 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
13 * @phydev: target phy_device struct
15 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
19 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
23 return !!(stat1 & MDIO_STAT1_LPOWERABLE);
27 * genphy_c45_pma_resume - wakes up the PMA module
28 * @phydev: target phy_device struct
30 int genphy_c45_pma_resume(struct phy_device *phydev)
32 if (!genphy_c45_pma_can_sleep(phydev))
35 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
38 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume);
41 * genphy_c45_pma_suspend - suspends the PMA module
42 * @phydev: target phy_device struct
44 int genphy_c45_pma_suspend(struct phy_device *phydev)
46 if (!genphy_c45_pma_can_sleep(phydev))
49 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
52 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend);
55 * genphy_c45_pma_setup_forced - configures a forced speed
56 * @phydev: target phy_device struct
58 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
60 int ctrl1, ctrl2, ret;
62 /* Half duplex is not supported */
63 if (phydev->duplex != DUPLEX_FULL)
66 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
70 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
74 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
76 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1
77 * in 802.3-2012 and 802.3-2015.
79 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
81 switch (phydev->speed) {
83 ctrl2 |= MDIO_PMA_CTRL2_10BT;
86 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
87 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
90 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
91 /* Assume 1000base-T */
92 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
95 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
96 /* Assume 2.5Gbase-T */
97 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
100 ctrl1 |= MDIO_CTRL1_SPEED5G;
101 /* Assume 5Gbase-T */
102 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
105 ctrl1 |= MDIO_CTRL1_SPEED10G;
106 /* Assume 10Gbase-T */
107 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
113 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
117 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
121 return genphy_c45_an_disable_aneg(phydev);
123 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
126 * genphy_c45_an_config_aneg - configure advertisement registers
127 * @phydev: target phy_device struct
129 * Configure advertisement registers based on modes set in phydev->advertising
131 * Returns negative errno code on failure, 0 if advertisement didn't change,
132 * or 1 if advertised modes changed.
134 int genphy_c45_an_config_aneg(struct phy_device *phydev)
139 linkmode_and(phydev->advertising, phydev->advertising,
142 changed = genphy_config_eee_advert(phydev);
144 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
146 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
147 ADVERTISE_ALL | ADVERTISE_100BASE4 |
148 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
155 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
157 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
158 MDIO_AN_10GBT_CTRL_ADV10G |
159 MDIO_AN_10GBT_CTRL_ADV5G |
160 MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
168 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
171 * genphy_c45_an_disable_aneg - disable auto-negotiation
172 * @phydev: target phy_device struct
174 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
175 * parameters are controlled through the PMA/PMD MMD registers.
177 * Returns zero on success, negative errno code on failure.
179 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
182 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
183 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
185 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
188 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
189 * @phydev: target phy_device struct
191 * This assumes that the auto-negotiation MMD is present.
193 * Enable and restart auto-negotiation.
195 int genphy_c45_restart_aneg(struct phy_device *phydev)
197 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
198 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
200 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
203 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
204 * @phydev: target phy_device struct
205 * @restart: whether aneg restart is requested
207 * This assumes that the auto-negotiation MMD is present.
209 * Check, and restart auto-negotiation if needed.
211 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
216 /* Configure and restart aneg if it wasn't set before */
217 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
221 if (!(ret & MDIO_AN_CTRL1_ENABLE))
226 return genphy_c45_restart_aneg(phydev);
230 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
233 * genphy_c45_aneg_done - return auto-negotiation complete status
234 * @phydev: target phy_device struct
236 * This assumes that the auto-negotiation MMD is present.
238 * Reads the status register from the auto-negotiation MMD, returning:
239 * - positive if auto-negotiation is complete
240 * - negative errno code on error
243 int genphy_c45_aneg_done(struct phy_device *phydev)
245 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
247 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
249 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
252 * genphy_c45_read_link - read the overall link status from the MMDs
253 * @phydev: target phy_device struct
255 * Read the link status from the specified MMDs, and if they all indicate
256 * that the link is up, set phydev->link to 1. If an error is encountered,
257 * a negative errno will be returned, otherwise zero.
259 int genphy_c45_read_link(struct phy_device *phydev)
261 u32 mmd_mask = MDIO_DEVS_PMAPMD;
265 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
266 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
270 /* Autoneg is being started, therefore disregard current
271 * link status and report link as down.
273 if (val & MDIO_AN_CTRL1_RESTART) {
279 while (mmd_mask && link) {
280 devad = __ffs(mmd_mask);
281 mmd_mask &= ~BIT(devad);
283 /* The link state is latched low so that momentary link
284 * drops can be detected. Do not double-read the status
285 * in polling mode to detect such short link drops except
286 * the link was already down.
288 if (!phy_polling_mode(phydev) || !phydev->link) {
289 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
292 else if (val & MDIO_STAT1_LSTATUS)
296 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
300 if (!(val & MDIO_STAT1_LSTATUS))
308 EXPORT_SYMBOL_GPL(genphy_c45_read_link);
311 * genphy_c45_read_lpa - read the link partner advertisement and pause
312 * @phydev: target phy_device struct
314 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
315 * filling in the link partner advertisement, pause and asym_pause members
316 * in @phydev. This assumes that the auto-negotiation MMD is present, and
317 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
318 * to fill in the remainder of the link partner advert from vendor registers.
320 int genphy_c45_read_lpa(struct phy_device *phydev)
324 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
328 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
329 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
330 phydev->lp_advertising);
331 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
332 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
334 phydev->asym_pause = 0;
339 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
340 val & MDIO_AN_STAT1_LPABLE);
342 /* Read the link partner's base page advertisement */
343 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
347 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
348 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
349 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
351 /* Read the link partner's 10G advertisement */
352 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
356 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
360 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
363 * genphy_c45_read_pma - read link speed etc from PMA
364 * @phydev: target phy_device struct
366 int genphy_c45_read_pma(struct phy_device *phydev)
370 linkmode_zero(phydev->lp_advertising);
372 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
376 switch (val & MDIO_CTRL1_SPEEDSEL) {
378 phydev->speed = SPEED_10;
380 case MDIO_PMA_CTRL1_SPEED100:
381 phydev->speed = SPEED_100;
383 case MDIO_PMA_CTRL1_SPEED1000:
384 phydev->speed = SPEED_1000;
386 case MDIO_CTRL1_SPEED2_5G:
387 phydev->speed = SPEED_2500;
389 case MDIO_CTRL1_SPEED5G:
390 phydev->speed = SPEED_5000;
392 case MDIO_CTRL1_SPEED10G:
393 phydev->speed = SPEED_10000;
396 phydev->speed = SPEED_UNKNOWN;
400 phydev->duplex = DUPLEX_FULL;
404 EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
407 * genphy_c45_read_mdix - read mdix status from PMA
408 * @phydev: target phy_device struct
410 int genphy_c45_read_mdix(struct phy_device *phydev)
414 if (phydev->speed == SPEED_10000) {
415 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
416 MDIO_PMA_10GBT_SWAPPOL);
421 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
422 phydev->mdix = ETH_TP_MDI;
426 phydev->mdix = ETH_TP_MDI_X;
430 phydev->mdix = ETH_TP_MDI_INVALID;
437 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
440 * genphy_c45_pma_read_abilities - read supported link modes from PMA
441 * @phydev: target phy_device struct
443 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
444 * 1.8.9 is set, the list of supported modes is build using the values in the
445 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
446 * modes. If bit 1.11.14 is set, then the list is also extended with the modes
447 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
448 * 5GBASET are supported.
450 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
454 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
455 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
456 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
460 if (val & MDIO_AN_STAT1_ABLE)
461 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
465 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
469 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
471 val & MDIO_PMA_STAT2_10GBSR);
473 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
475 val & MDIO_PMA_STAT2_10GBLR);
477 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
479 val & MDIO_PMA_STAT2_10GBER);
481 if (val & MDIO_PMA_STAT2_EXTABLE) {
482 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
486 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
488 val & MDIO_PMA_EXTABLE_10GBLRM);
489 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
491 val & MDIO_PMA_EXTABLE_10GBT);
492 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
494 val & MDIO_PMA_EXTABLE_10GBKX4);
495 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
497 val & MDIO_PMA_EXTABLE_10GBKR);
498 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
500 val & MDIO_PMA_EXTABLE_1000BT);
501 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
503 val & MDIO_PMA_EXTABLE_1000BKX);
505 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
507 val & MDIO_PMA_EXTABLE_100BTX);
508 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
510 val & MDIO_PMA_EXTABLE_100BTX);
512 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
514 val & MDIO_PMA_EXTABLE_10BT);
515 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
517 val & MDIO_PMA_EXTABLE_10BT);
519 if (val & MDIO_PMA_EXTABLE_NBT) {
520 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
521 MDIO_PMA_NG_EXTABLE);
525 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
527 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
529 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
531 val & MDIO_PMA_NG_EXTABLE_5GBT);
537 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
540 * genphy_c45_read_status - read PHY status
541 * @phydev: target phy_device struct
543 * Reads status from PHY and sets phy_device members accordingly.
545 int genphy_c45_read_status(struct phy_device *phydev)
549 ret = genphy_c45_read_link(phydev);
553 phydev->speed = SPEED_UNKNOWN;
554 phydev->duplex = DUPLEX_UNKNOWN;
556 phydev->asym_pause = 0;
558 if (phydev->autoneg == AUTONEG_ENABLE) {
559 ret = genphy_c45_read_lpa(phydev);
563 phy_resolve_aneg_linkmode(phydev);
565 ret = genphy_c45_read_pma(phydev);
570 EXPORT_SYMBOL_GPL(genphy_c45_read_status);
573 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
574 * @phydev: target phy_device struct
576 * Description: If auto-negotiation is enabled, we configure the
577 * advertising, and then restart auto-negotiation. If it is not
578 * enabled, then we force a configuration.
580 int genphy_c45_config_aneg(struct phy_device *phydev)
582 bool changed = false;
585 if (phydev->autoneg == AUTONEG_DISABLE)
586 return genphy_c45_pma_setup_forced(phydev);
588 ret = genphy_c45_an_config_aneg(phydev);
594 return genphy_c45_check_and_restart_aneg(phydev, changed);
596 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
598 /* The gen10g_* functions are the old Clause 45 stub */
600 int gen10g_config_aneg(struct phy_device *phydev)
604 EXPORT_SYMBOL_GPL(gen10g_config_aneg);
606 int genphy_c45_loopback(struct phy_device *phydev, bool enable)
608 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
609 MDIO_PCS_CTRL1_LOOPBACK,
610 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0);
612 EXPORT_SYMBOL_GPL(genphy_c45_loopback);
614 struct phy_driver genphy_c45_driver = {
615 .phy_id = 0xffffffff,
616 .phy_id_mask = 0xffffffff,
617 .name = "Generic Clause 45 PHY",
618 .read_status = genphy_c45_read_status,