1 // SPDX-License-Identifier: GPL-2.0
2 /* NXP TJA1100 BroadRReach PHY driver
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
6 #include <linux/delay.h>
7 #include <linux/ethtool.h>
8 #include <linux/ethtool_netlink.h>
9 #include <linux/kernel.h>
10 #include <linux/mdio.h>
11 #include <linux/mii.h>
12 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/hwmon.h>
15 #include <linux/bitfield.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_irq.h>
19 #define PHY_ID_MASK 0xfffffff0
20 #define PHY_ID_TJA1100 0x0180dc40
21 #define PHY_ID_TJA1101 0x0180dd00
22 #define PHY_ID_TJA1102 0x0180dc80
25 #define MII_ECTRL_LINK_CONTROL BIT(15)
26 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
27 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
28 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
29 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
30 #define MII_ECTRL_CABLE_TEST BIT(5)
31 #define MII_ECTRL_CONFIG_EN BIT(2)
32 #define MII_ECTRL_WAKE_REQUEST BIT(0)
35 #define MII_CFG1_MASTER_SLAVE BIT(15)
36 #define MII_CFG1_AUTO_OP BIT(14)
37 #define MII_CFG1_SLEEP_CONFIRM BIT(6)
38 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
39 #define MII_CFG1_LED_MODE_LINKUP 0
40 #define MII_CFG1_LED_ENABLE BIT(3)
43 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
44 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
47 #define MII_INTSRC_LINK_FAIL BIT(10)
48 #define MII_INTSRC_LINK_UP BIT(9)
49 #define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
50 #define MII_INTSRC_TEMP_ERR BIT(1)
51 #define MII_INTSRC_UV_ERR BIT(3)
54 #define MII_INTEN_LINK_FAIL BIT(10)
55 #define MII_INTEN_LINK_UP BIT(9)
57 #define MII_COMMSTAT 23
58 #define MII_COMMSTAT_LINK_UP BIT(15)
59 #define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
60 #define MII_COMMSTAT_SQI_MAX 7
62 #define MII_GENSTAT 24
63 #define MII_GENSTAT_PLL_LOCKED BIT(14)
65 #define MII_EXTSTAT 25
66 #define MII_EXTSTAT_SHORT_DETECT BIT(8)
67 #define MII_EXTSTAT_OPEN_DETECT BIT(7)
68 #define MII_EXTSTAT_POLARITY_DETECT BIT(6)
70 #define MII_COMMCFG 27
71 #define MII_COMMCFG_AUTO_OP BIT(15)
75 struct device *hwmon_dev;
76 struct phy_device *phydev;
77 struct work_struct phy_register_work;
80 struct tja11xx_phy_stats {
87 static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
88 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
89 { "phy_polarity_detect", 25, 6, BIT(6) },
90 { "phy_open_detect", 25, 7, BIT(7) },
91 { "phy_short_detect", 25, 8, BIT(8) },
92 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
93 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
96 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
100 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
104 static int phy_modify_check(struct phy_device *phydev, u8 reg,
109 ret = phy_modify(phydev, reg, mask, set);
113 return tja11xx_check(phydev, reg, mask, set);
116 static int tja11xx_enable_reg_write(struct phy_device *phydev)
118 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
121 static int tja11xx_enable_link_control(struct phy_device *phydev)
123 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
126 static int tja11xx_disable_link_control(struct phy_device *phydev)
128 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
131 static int tja11xx_wakeup(struct phy_device *phydev)
135 ret = phy_read(phydev, MII_ECTRL);
139 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
140 case MII_ECTRL_POWER_MODE_NO_CHANGE:
142 case MII_ECTRL_POWER_MODE_NORMAL:
143 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
147 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
151 case MII_ECTRL_POWER_MODE_STANDBY:
152 ret = phy_modify_check(phydev, MII_ECTRL,
153 MII_ECTRL_POWER_MODE_MASK,
154 MII_ECTRL_POWER_MODE_STANDBY);
158 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
159 MII_ECTRL_POWER_MODE_NORMAL);
163 ret = phy_modify_check(phydev, MII_GENSTAT,
164 MII_GENSTAT_PLL_LOCKED,
165 MII_GENSTAT_PLL_LOCKED);
169 return tja11xx_enable_link_control(phydev);
177 static int tja11xx_soft_reset(struct phy_device *phydev)
181 ret = tja11xx_enable_reg_write(phydev);
185 return genphy_soft_reset(phydev);
188 static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
190 bool finished = false;
196 if (!phydev->drv->cable_test_start ||
197 !phydev->drv->cable_test_get_status)
200 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
204 ret = phydev->drv->cable_test_start(phydev);
208 /* According to the documentation this test takes 100 usec */
209 usleep_range(100, 200);
211 ret = phydev->drv->cable_test_get_status(phydev, &finished);
216 ethnl_cable_test_finished(phydev);
221 static int tja11xx_config_aneg(struct phy_device *phydev)
223 int ret, changed = 0;
226 switch (phydev->master_slave_set) {
227 case MASTER_SLAVE_CFG_MASTER_FORCE:
228 ctl |= MII_CFG1_MASTER_SLAVE;
230 case MASTER_SLAVE_CFG_SLAVE_FORCE:
232 case MASTER_SLAVE_CFG_UNKNOWN:
233 case MASTER_SLAVE_CFG_UNSUPPORTED:
236 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
240 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
245 ret = tja11xx_config_aneg_cable_test(phydev);
249 return __genphy_config_aneg(phydev, changed);
252 static int tja11xx_config_init(struct phy_device *phydev)
256 ret = tja11xx_enable_reg_write(phydev);
260 phydev->autoneg = AUTONEG_DISABLE;
261 phydev->speed = SPEED_100;
262 phydev->duplex = DUPLEX_FULL;
264 switch (phydev->phy_id & PHY_ID_MASK) {
266 ret = phy_modify(phydev, MII_CFG1,
267 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
269 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
270 MII_CFG1_LED_ENABLE);
276 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
284 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
288 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
289 MII_CFG2_SLEEP_REQUEST_TO_16MS);
293 ret = tja11xx_wakeup(phydev);
297 /* ACK interrupts by reading the status register */
298 ret = phy_read(phydev, MII_INTSRC);
305 static int tja11xx_read_status(struct phy_device *phydev)
309 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
310 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
312 ret = genphy_update_link(phydev);
316 ret = phy_read(phydev, MII_CFG1);
320 if (ret & MII_CFG1_MASTER_SLAVE)
321 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
323 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
326 ret = phy_read(phydev, MII_COMMSTAT);
330 if (!(ret & MII_COMMSTAT_LINK_UP))
337 static int tja11xx_get_sqi(struct phy_device *phydev)
341 ret = phy_read(phydev, MII_COMMSTAT);
345 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
348 static int tja11xx_get_sqi_max(struct phy_device *phydev)
350 return MII_COMMSTAT_SQI_MAX;
353 static int tja11xx_get_sset_count(struct phy_device *phydev)
355 return ARRAY_SIZE(tja11xx_hw_stats);
358 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
362 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
363 strncpy(data + i * ETH_GSTRING_LEN,
364 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
368 static void tja11xx_get_stats(struct phy_device *phydev,
369 struct ethtool_stats *stats, u64 *data)
373 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
374 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
378 data[i] = ret & tja11xx_hw_stats[i].mask;
379 data[i] >>= tja11xx_hw_stats[i].off;
384 static int tja11xx_hwmon_read(struct device *dev,
385 enum hwmon_sensor_types type,
386 u32 attr, int channel, long *value)
388 struct phy_device *phydev = dev_get_drvdata(dev);
391 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
392 ret = phy_read(phydev, MII_INTSRC);
396 *value = !!(ret & MII_INTSRC_TEMP_ERR);
400 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
401 ret = phy_read(phydev, MII_INTSRC);
405 *value = !!(ret & MII_INTSRC_UV_ERR);
412 static umode_t tja11xx_hwmon_is_visible(const void *data,
413 enum hwmon_sensor_types type,
414 u32 attr, int channel)
416 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
419 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
425 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
426 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
427 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
431 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
432 .is_visible = tja11xx_hwmon_is_visible,
433 .read = tja11xx_hwmon_read,
436 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
437 .ops = &tja11xx_hwmon_hwmon_ops,
438 .info = tja11xx_hwmon_info,
441 static int tja11xx_hwmon_register(struct phy_device *phydev,
442 struct tja11xx_priv *priv)
444 struct device *dev = &phydev->mdio.dev;
447 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
448 if (!priv->hwmon_name)
451 for (i = 0; priv->hwmon_name[i]; i++)
452 if (hwmon_is_bad_char(priv->hwmon_name[i]))
453 priv->hwmon_name[i] = '_';
456 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
458 &tja11xx_hwmon_chip_info,
461 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
464 static int tja11xx_probe(struct phy_device *phydev)
466 struct device *dev = &phydev->mdio.dev;
467 struct tja11xx_priv *priv;
469 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
473 priv->phydev = phydev;
475 return tja11xx_hwmon_register(phydev, priv);
478 static void tja1102_p1_register(struct work_struct *work)
480 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
482 struct phy_device *phydev_phy0 = priv->phydev;
483 struct mii_bus *bus = phydev_phy0->mdio.bus;
484 struct device *dev = &phydev_phy0->mdio.dev;
485 struct device_node *np = dev->of_node;
486 struct device_node *child;
489 for_each_available_child_of_node(np, child) {
490 struct phy_device *phy;
493 addr = of_mdio_parse_addr(dev, child);
495 dev_err(dev, "Can't parse addr\n");
497 } else if (addr != phydev_phy0->mdio.addr + 1) {
498 /* Currently we care only about double PHY chip TJA1102.
499 * If some day NXP will decide to bring chips with more
500 * PHYs, this logic should be reworked.
502 dev_err(dev, "Unexpected address. Should be: %i\n",
503 phydev_phy0->mdio.addr + 1);
507 if (mdiobus_is_registered_device(bus, addr)) {
508 dev_err(dev, "device is already registered\n");
512 /* Real PHY ID of Port 1 is 0 */
513 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
515 dev_err(dev, "Can't create PHY device for Port 1: %i\n",
520 /* Overwrite parent device. phy_device_create() set parent to
521 * the mii_bus->dev, which is not correct in case.
523 phy->mdio.dev.parent = dev;
525 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
527 /* All resources needed for Port 1 should be already
528 * available for Port 0. Both ports use the same
529 * interrupt line, so -EPROBE_DEFER would make no sense
532 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
534 phy_device_free(phy);
539 static int tja1102_p0_probe(struct phy_device *phydev)
541 struct device *dev = &phydev->mdio.dev;
542 struct tja11xx_priv *priv;
545 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
549 priv->phydev = phydev;
550 INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
552 ret = tja11xx_hwmon_register(phydev, priv);
556 schedule_work(&priv->phy_register_work);
561 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
565 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
568 ret = phy_read(phydev, MII_PHYSID2);
572 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
573 * and undervoltage alarms.
581 static int tja1102_p0_match_phy_device(struct phy_device *phydev)
583 return tja1102_match_phy_device(phydev, true);
586 static int tja1102_p1_match_phy_device(struct phy_device *phydev)
588 return tja1102_match_phy_device(phydev, false);
591 static int tja11xx_ack_interrupt(struct phy_device *phydev)
595 ret = phy_read(phydev, MII_INTSRC);
597 return (ret < 0) ? ret : 0;
600 static int tja11xx_config_intr(struct phy_device *phydev)
605 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
606 err = tja11xx_ack_interrupt(phydev);
610 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP;
611 err = phy_write(phydev, MII_INTEN, value);
613 err = phy_write(phydev, MII_INTEN, value);
617 err = tja11xx_ack_interrupt(phydev);
623 static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
627 irq_status = phy_read(phydev, MII_INTSRC);
628 if (irq_status < 0) {
633 if (!(irq_status & MII_INTSRC_MASK))
636 phy_trigger_machine(phydev);
641 static int tja11xx_cable_test_start(struct phy_device *phydev)
645 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
649 ret = tja11xx_wakeup(phydev);
653 ret = tja11xx_disable_link_control(phydev);
657 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
661 * | BI_DA+ | BI_DA- | Result
662 * | open | open | open
663 * | + short to - | - short to + | short
664 * | short to Vdd | open | open
665 * | open | shot to Vdd | open
666 * | short to Vdd | short to Vdd | short
667 * | shot to GND | open | open
668 * | open | shot to GND | open
669 * | short to GND | shot to GND | short
670 * | connected to active link partner (master) | shot and open
672 static int tja11xx_cable_test_report_trans(u32 result)
674 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
676 if ((result & mask) == mask) {
677 /* connected to active link partner (master) */
678 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
679 } else if ((result & mask) == 0) {
680 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
681 } else if (result & MII_EXTSTAT_SHORT_DETECT) {
682 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
683 } else if (result & MII_EXTSTAT_OPEN_DETECT) {
684 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
686 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
690 static int tja11xx_cable_test_report(struct phy_device *phydev)
694 ret = phy_read(phydev, MII_EXTSTAT);
698 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
699 tja11xx_cable_test_report_trans(ret));
704 static int tja11xx_cable_test_get_status(struct phy_device *phydev,
711 ret = phy_read(phydev, MII_ECTRL);
715 if (!(ret & MII_ECTRL_CABLE_TEST)) {
718 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
722 return tja11xx_cable_test_report(phydev);
728 static struct phy_driver tja11xx_driver[] = {
730 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
731 .name = "NXP TJA1100",
732 .features = PHY_BASIC_T1_FEATURES,
733 .probe = tja11xx_probe,
734 .soft_reset = tja11xx_soft_reset,
735 .config_aneg = tja11xx_config_aneg,
736 .config_init = tja11xx_config_init,
737 .read_status = tja11xx_read_status,
738 .get_sqi = tja11xx_get_sqi,
739 .get_sqi_max = tja11xx_get_sqi_max,
740 .suspend = genphy_suspend,
741 .resume = genphy_resume,
742 .set_loopback = genphy_loopback,
744 .get_sset_count = tja11xx_get_sset_count,
745 .get_strings = tja11xx_get_strings,
746 .get_stats = tja11xx_get_stats,
748 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
749 .name = "NXP TJA1101",
750 .features = PHY_BASIC_T1_FEATURES,
751 .probe = tja11xx_probe,
752 .soft_reset = tja11xx_soft_reset,
753 .config_aneg = tja11xx_config_aneg,
754 .config_init = tja11xx_config_init,
755 .read_status = tja11xx_read_status,
756 .get_sqi = tja11xx_get_sqi,
757 .get_sqi_max = tja11xx_get_sqi_max,
758 .suspend = genphy_suspend,
759 .resume = genphy_resume,
760 .set_loopback = genphy_loopback,
762 .get_sset_count = tja11xx_get_sset_count,
763 .get_strings = tja11xx_get_strings,
764 .get_stats = tja11xx_get_stats,
766 .name = "NXP TJA1102 Port 0",
767 .features = PHY_BASIC_T1_FEATURES,
768 .flags = PHY_POLL_CABLE_TEST,
769 .probe = tja1102_p0_probe,
770 .soft_reset = tja11xx_soft_reset,
771 .config_aneg = tja11xx_config_aneg,
772 .config_init = tja11xx_config_init,
773 .read_status = tja11xx_read_status,
774 .get_sqi = tja11xx_get_sqi,
775 .get_sqi_max = tja11xx_get_sqi_max,
776 .match_phy_device = tja1102_p0_match_phy_device,
777 .suspend = genphy_suspend,
778 .resume = genphy_resume,
779 .set_loopback = genphy_loopback,
781 .get_sset_count = tja11xx_get_sset_count,
782 .get_strings = tja11xx_get_strings,
783 .get_stats = tja11xx_get_stats,
784 .config_intr = tja11xx_config_intr,
785 .handle_interrupt = tja11xx_handle_interrupt,
786 .cable_test_start = tja11xx_cable_test_start,
787 .cable_test_get_status = tja11xx_cable_test_get_status,
789 .name = "NXP TJA1102 Port 1",
790 .features = PHY_BASIC_T1_FEATURES,
791 .flags = PHY_POLL_CABLE_TEST,
792 /* currently no probe for Port 1 is need */
793 .soft_reset = tja11xx_soft_reset,
794 .config_aneg = tja11xx_config_aneg,
795 .config_init = tja11xx_config_init,
796 .read_status = tja11xx_read_status,
797 .get_sqi = tja11xx_get_sqi,
798 .get_sqi_max = tja11xx_get_sqi_max,
799 .match_phy_device = tja1102_p1_match_phy_device,
800 .suspend = genphy_suspend,
801 .resume = genphy_resume,
802 .set_loopback = genphy_loopback,
804 .get_sset_count = tja11xx_get_sset_count,
805 .get_strings = tja11xx_get_strings,
806 .get_stats = tja11xx_get_stats,
807 .config_intr = tja11xx_config_intr,
808 .handle_interrupt = tja11xx_handle_interrupt,
809 .cable_test_start = tja11xx_cable_test_start,
810 .cable_test_get_status = tja11xx_cable_test_get_status,
814 module_phy_driver(tja11xx_driver);
816 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
817 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
818 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
819 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
823 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
825 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
826 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
827 MODULE_LICENSE("GPL");