1 // SPDX-License-Identifier: GPL-2.0
2 /* NXP TJA1100 BroadRReach PHY driver
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
6 #include <linux/delay.h>
7 #include <linux/ethtool.h>
8 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/phy.h>
12 #include <linux/hwmon.h>
13 #include <linux/bitfield.h>
15 #define PHY_ID_MASK 0xfffffff0
16 #define PHY_ID_TJA1100 0x0180dc40
17 #define PHY_ID_TJA1101 0x0180dd00
20 #define MII_ECTRL_LINK_CONTROL BIT(15)
21 #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
22 #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
23 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
24 #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
25 #define MII_ECTRL_CONFIG_EN BIT(2)
26 #define MII_ECTRL_WAKE_REQUEST BIT(0)
29 #define MII_CFG1_AUTO_OP BIT(14)
30 #define MII_CFG1_SLEEP_CONFIRM BIT(6)
31 #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
32 #define MII_CFG1_LED_MODE_LINKUP 0
33 #define MII_CFG1_LED_ENABLE BIT(3)
36 #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
37 #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
40 #define MII_INTSRC_TEMP_ERR BIT(1)
41 #define MII_INTSRC_UV_ERR BIT(3)
43 #define MII_COMMSTAT 23
44 #define MII_COMMSTAT_LINK_UP BIT(15)
46 #define MII_GENSTAT 24
47 #define MII_GENSTAT_PLL_LOCKED BIT(14)
49 #define MII_COMMCFG 27
50 #define MII_COMMCFG_AUTO_OP BIT(15)
54 struct device *hwmon_dev;
57 struct tja11xx_phy_stats {
64 static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
65 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
66 { "phy_polarity_detect", 25, 6, BIT(6) },
67 { "phy_open_detect", 25, 7, BIT(7) },
68 { "phy_short_detect", 25, 8, BIT(8) },
69 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
70 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
73 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
77 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
81 static int phy_modify_check(struct phy_device *phydev, u8 reg,
86 ret = phy_modify(phydev, reg, mask, set);
90 return tja11xx_check(phydev, reg, mask, set);
93 static int tja11xx_enable_reg_write(struct phy_device *phydev)
95 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
98 static int tja11xx_enable_link_control(struct phy_device *phydev)
100 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
103 static int tja11xx_wakeup(struct phy_device *phydev)
107 ret = phy_read(phydev, MII_ECTRL);
111 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
112 case MII_ECTRL_POWER_MODE_NO_CHANGE:
114 case MII_ECTRL_POWER_MODE_NORMAL:
115 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
119 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
123 case MII_ECTRL_POWER_MODE_STANDBY:
124 ret = phy_modify_check(phydev, MII_ECTRL,
125 MII_ECTRL_POWER_MODE_MASK,
126 MII_ECTRL_POWER_MODE_STANDBY);
130 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
131 MII_ECTRL_POWER_MODE_NORMAL);
135 ret = phy_modify_check(phydev, MII_GENSTAT,
136 MII_GENSTAT_PLL_LOCKED,
137 MII_GENSTAT_PLL_LOCKED);
141 return tja11xx_enable_link_control(phydev);
149 static int tja11xx_soft_reset(struct phy_device *phydev)
153 ret = tja11xx_enable_reg_write(phydev);
157 return genphy_soft_reset(phydev);
160 static int tja11xx_config_init(struct phy_device *phydev)
164 ret = tja11xx_enable_reg_write(phydev);
168 phydev->autoneg = AUTONEG_DISABLE;
169 phydev->speed = SPEED_100;
170 phydev->duplex = DUPLEX_FULL;
172 switch (phydev->phy_id & PHY_ID_MASK) {
174 ret = phy_modify(phydev, MII_CFG1,
175 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
177 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
178 MII_CFG1_LED_ENABLE);
183 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
191 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
195 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
196 MII_CFG2_SLEEP_REQUEST_TO_16MS);
200 ret = tja11xx_wakeup(phydev);
204 /* ACK interrupts by reading the status register */
205 ret = phy_read(phydev, MII_INTSRC);
212 static int tja11xx_read_status(struct phy_device *phydev)
216 ret = genphy_update_link(phydev);
221 ret = phy_read(phydev, MII_COMMSTAT);
225 if (!(ret & MII_COMMSTAT_LINK_UP))
232 static int tja11xx_get_sset_count(struct phy_device *phydev)
234 return ARRAY_SIZE(tja11xx_hw_stats);
237 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
241 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
242 strncpy(data + i * ETH_GSTRING_LEN,
243 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
247 static void tja11xx_get_stats(struct phy_device *phydev,
248 struct ethtool_stats *stats, u64 *data)
252 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
253 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
257 data[i] = ret & tja11xx_hw_stats[i].mask;
258 data[i] >>= tja11xx_hw_stats[i].off;
263 static int tja11xx_hwmon_read(struct device *dev,
264 enum hwmon_sensor_types type,
265 u32 attr, int channel, long *value)
267 struct phy_device *phydev = dev_get_drvdata(dev);
270 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
271 ret = phy_read(phydev, MII_INTSRC);
275 *value = !!(ret & MII_INTSRC_TEMP_ERR);
279 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
280 ret = phy_read(phydev, MII_INTSRC);
284 *value = !!(ret & MII_INTSRC_UV_ERR);
291 static umode_t tja11xx_hwmon_is_visible(const void *data,
292 enum hwmon_sensor_types type,
293 u32 attr, int channel)
295 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
298 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
304 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
305 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
306 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
310 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
311 .is_visible = tja11xx_hwmon_is_visible,
312 .read = tja11xx_hwmon_read,
315 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
316 .ops = &tja11xx_hwmon_hwmon_ops,
317 .info = tja11xx_hwmon_info,
320 static int tja11xx_probe(struct phy_device *phydev)
322 struct device *dev = &phydev->mdio.dev;
323 struct tja11xx_priv *priv;
326 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
330 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
331 if (!priv->hwmon_name)
334 for (i = 0; priv->hwmon_name[i]; i++)
335 if (hwmon_is_bad_char(priv->hwmon_name[i]))
336 priv->hwmon_name[i] = '_';
339 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
341 &tja11xx_hwmon_chip_info,
344 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
347 static struct phy_driver tja11xx_driver[] = {
349 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
350 .name = "NXP TJA1100",
351 .features = PHY_BASIC_T1_FEATURES,
352 .probe = tja11xx_probe,
353 .soft_reset = tja11xx_soft_reset,
354 .config_init = tja11xx_config_init,
355 .read_status = tja11xx_read_status,
356 .suspend = genphy_suspend,
357 .resume = genphy_resume,
358 .set_loopback = genphy_loopback,
360 .get_sset_count = tja11xx_get_sset_count,
361 .get_strings = tja11xx_get_strings,
362 .get_stats = tja11xx_get_stats,
364 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
365 .name = "NXP TJA1101",
366 .features = PHY_BASIC_T1_FEATURES,
367 .probe = tja11xx_probe,
368 .soft_reset = tja11xx_soft_reset,
369 .config_init = tja11xx_config_init,
370 .read_status = tja11xx_read_status,
371 .suspend = genphy_suspend,
372 .resume = genphy_resume,
373 .set_loopback = genphy_loopback,
375 .get_sset_count = tja11xx_get_sset_count,
376 .get_strings = tja11xx_get_strings,
377 .get_stats = tja11xx_get_stats,
381 module_phy_driver(tja11xx_driver);
383 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
384 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
385 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
389 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
391 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
392 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
393 MODULE_LICENSE("GPL");