1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for Microsemi VSC85xx PHYs - timestamping and PHC support
5 * Authors: Quentin Schulz & Antoine Tenart
6 * License: Dual MIT/GPL
7 * Copyright (c) 2020 Microsemi Corporation
10 #include <linux/gpio/consumer.h>
12 #include <linux/net_tstamp.h>
13 #include <linux/mii.h>
14 #include <linux/phy.h>
15 #include <linux/ptp_classify.h>
16 #include <linux/ptp_clock_kernel.h>
17 #include <linux/udp.h>
18 #include <asm/unaligned.h>
23 /* Two PHYs share the same 1588 processor and it's to be entirely configured
24 * through the base PHY of this processor.
26 /* phydev->bus->mdio_lock should be locked when using this function */
27 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val)
29 struct vsc8531_private *priv = phydev->priv;
31 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock));
32 return __mdiobus_write(phydev->mdio.bus, priv->ts_base_addr, regnum,
36 /* phydev->bus->mdio_lock should be locked when using this function */
37 static int phy_ts_base_read(struct phy_device *phydev, u32 regnum)
39 struct vsc8531_private *priv = phydev->priv;
41 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock));
42 return __mdiobus_read(phydev->mdio.bus, priv->ts_base_addr, regnum);
62 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
65 struct vsc8531_private *priv = phydev->priv;
66 bool base_port = phydev->mdio.addr == priv->ts_base_addr;
68 enum ts_blk_hw blk_hw;
72 blk_hw = base_port ? INGRESS_ENGINE_0 : INGRESS_ENGINE_1;
75 blk_hw = base_port ? EGRESS_ENGINE_0 : EGRESS_ENGINE_1;
79 blk_hw = base_port ? PROCESSOR_0 : PROCESSOR_1;
83 phy_lock_mdio_bus(phydev);
85 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
87 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE |
88 BIU_ADDR_READ | BIU_BLK_ID(blk_hw) |
92 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL);
93 } while (!(val & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX);
95 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB);
97 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB);
99 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
101 phy_unlock_mdio_bus(phydev);
106 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
109 struct vsc8531_private *priv = phydev->priv;
110 bool base_port = phydev->mdio.addr == priv->ts_base_addr;
111 u32 reg, bypass, cnt = 0, lower = val & 0xffff, upper = val >> 16;
112 bool cond = (addr == MSCC_PHY_PTP_LTC_CTRL ||
113 addr == MSCC_PHY_1588_INGR_VSC85XX_INT_MASK ||
114 addr == MSCC_PHY_1588_VSC85XX_INT_MASK ||
115 addr == MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS ||
116 addr == MSCC_PHY_1588_VSC85XX_INT_STATUS) &&
118 enum ts_blk_hw blk_hw;
122 blk_hw = base_port ? INGRESS_ENGINE_0 : INGRESS_ENGINE_1;
125 blk_hw = base_port ? EGRESS_ENGINE_0 : EGRESS_ENGINE_1;
129 blk_hw = base_port ? PROCESSOR_0 : PROCESSOR_1;
133 phy_lock_mdio_bus(phydev);
135 bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
137 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
140 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_MSB, upper);
142 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_LSB, lower);
144 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE |
145 BIU_ADDR_WRITE | BIU_BLK_ID(blk_hw) |
149 reg = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL);
150 } while (!(reg & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX);
152 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
155 phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass);
157 phy_unlock_mdio_bus(phydev);
160 /* Pick bytes from PTP header */
161 #define PTP_HEADER_TRNSP_MSG 26
162 #define PTP_HEADER_DOMAIN_NUM 25
163 #define PTP_HEADER_BYTE_8_31(x) (31 - (x))
164 #define MAC_ADDRESS_BYTE(x) ((x) + (35 - ETH_ALEN + 1))
166 static int vsc85xx_ts_fsb_init(struct phy_device *phydev)
169 signed char i, pos = 0;
171 /* Seq ID is 2B long and starts at 30th byte */
172 for (i = 1; i >= 0; i--)
173 sig_sel[pos++] = PTP_HEADER_BYTE_8_31(30 + i);
176 sig_sel[pos++] = PTP_HEADER_DOMAIN_NUM;
179 sig_sel[pos++] = PTP_HEADER_TRNSP_MSG;
181 /* MAC address is 6B long */
182 for (i = ETH_ALEN - 1; i >= 0; i--)
183 sig_sel[pos++] = MAC_ADDRESS_BYTE(i);
185 /* Fill the last bytes of the signature to reach a 16B signature */
186 for (; pos < ARRAY_SIZE(sig_sel); pos++)
187 sig_sel[pos] = PTP_HEADER_TRNSP_MSG;
189 for (i = 0; i <= 2; i++) {
192 for (pos = i * 5 + 4; pos >= i * 5; pos--)
193 val = (val << 6) | sig_sel[pos];
195 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i),
199 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3),
205 static const u32 vsc85xx_egr_latency[] = {
215 static const u32 vsc85xx_egr_latency_macsec[] = {
216 /* Copper Egress ON */
220 /* Fiber Egress ON */
225 static const u32 vsc85xx_ingr_latency[] = {
235 static const u32 vsc85xx_ingr_latency_macsec[] = {
245 static void vsc85xx_ts_set_latencies(struct phy_device *phydev)
247 u32 val, ingr_latency, egr_latency;
250 /* No need to set latencies of packets if the PHY is not connected */
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY,
255 STALL_EGR_LATENCY(phydev->speed));
257 switch (phydev->speed) {
269 ingr_latency = IS_ENABLED(CONFIG_MACSEC) ?
270 vsc85xx_ingr_latency_macsec[idx] : vsc85xx_ingr_latency[idx];
271 egr_latency = IS_ENABLED(CONFIG_MACSEC) ?
272 vsc85xx_egr_latency_macsec[idx] : vsc85xx_egr_latency[idx];
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY,
275 PTP_INGR_LOCAL_LATENCY(ingr_latency));
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
278 MSCC_PHY_PTP_INGR_TSP_CTRL);
279 val |= PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS;
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL,
283 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_LOCAL_LATENCY,
284 PTP_EGR_LOCAL_LATENCY(egr_latency));
286 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL);
287 val |= PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS;
288 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val);
291 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk)
295 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0);
296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,
297 IP1_NXT_PROT_UDP_CHKSUM_WIDTH(2));
298 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0);
299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM,
300 IP2_NXT_PROT_UDP_CHKSUM_WIDTH(2));
301 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0);
302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0);
303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0);
305 for (i = 0; i < COMP_MAX_FLOWS; i++) {
306 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i),
307 IP1_FLOW_VALID_CH0 | IP1_FLOW_VALID_CH1);
308 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i),
309 IP2_FLOW_VALID_CH0 | IP2_FLOW_VALID_CH1);
310 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i),
311 ETH1_FLOW_VALID_CH0 | ETH1_FLOW_VALID_CH1);
312 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i),
313 ETH2_FLOW_VALID_CH0 | ETH2_FLOW_VALID_CH1);
314 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i),
315 MPLS_FLOW_VALID_CH0 | MPLS_FLOW_VALID_CH1);
317 if (i >= PTP_COMP_MAX_FLOWS)
320 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0);
321 vsc85xx_ts_write_csr(phydev, blk,
322 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i), 0);
323 vsc85xx_ts_write_csr(phydev, blk,
324 MSCC_ANA_PTP_FLOW_MASK_UPPER(i), 0);
325 vsc85xx_ts_write_csr(phydev, blk,
326 MSCC_ANA_PTP_FLOW_MASK_LOWER(i), 0);
327 vsc85xx_ts_write_csr(phydev, blk,
328 MSCC_ANA_PTP_FLOW_MATCH_UPPER(i), 0);
329 vsc85xx_ts_write_csr(phydev, blk,
330 MSCC_ANA_PTP_FLOW_MATCH_LOWER(i), 0);
331 vsc85xx_ts_write_csr(phydev, blk,
332 MSCC_ANA_PTP_FLOW_PTP_ACTION(i), 0);
333 vsc85xx_ts_write_csr(phydev, blk,
334 MSCC_ANA_PTP_FLOW_PTP_ACTION2(i), 0);
335 vsc85xx_ts_write_csr(phydev, blk,
336 MSCC_ANA_PTP_FLOW_PTP_0_FIELD(i), 0);
337 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i),
344 static int vsc85xx_ts_eth_cmp1_sig(struct phy_device *phydev)
348 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT);
349 val &= ~ANA_ETH1_NTX_PROT_SIG_OFF_MASK;
350 val |= ANA_ETH1_NTX_PROT_SIG_OFF(0);
351 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val);
353 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG);
354 val &= ~ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK;
355 val |= ANA_FSB_ADDR_FROM_ETH1;
356 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val);
361 static struct vsc85xx_ptphdr *get_ptp_header_l4(struct sk_buff *skb,
363 struct udphdr *udphdr)
365 if (iphdr->version != 4 || iphdr->protocol != IPPROTO_UDP)
368 return (struct vsc85xx_ptphdr *)(((unsigned char *)udphdr) + UDP_HLEN);
371 static struct vsc85xx_ptphdr *get_ptp_header_tx(struct sk_buff *skb)
373 struct ethhdr *ethhdr = eth_hdr(skb);
374 struct udphdr *udphdr;
377 if (ethhdr->h_proto == htons(ETH_P_1588))
378 return (struct vsc85xx_ptphdr *)(((unsigned char *)ethhdr) +
379 skb_mac_header_len(skb));
381 if (ethhdr->h_proto != htons(ETH_P_IP))
385 udphdr = udp_hdr(skb);
387 return get_ptp_header_l4(skb, iphdr, udphdr);
390 static struct vsc85xx_ptphdr *get_ptp_header_rx(struct sk_buff *skb,
391 enum hwtstamp_rx_filters rx_filter)
393 struct udphdr *udphdr;
396 if (rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
397 return (struct vsc85xx_ptphdr *)skb->data;
399 iphdr = (struct iphdr *)skb->data;
400 udphdr = (struct udphdr *)(skb->data + iphdr->ihl * 4);
402 return get_ptp_header_l4(skb, iphdr, udphdr);
405 static int get_sig(struct sk_buff *skb, u8 *sig)
407 struct vsc85xx_ptphdr *ptphdr = get_ptp_header_tx(skb);
408 struct ethhdr *ethhdr = eth_hdr(skb);
414 sig[0] = (__force u16)ptphdr->seq_id >> 8;
415 sig[1] = (__force u16)ptphdr->seq_id & GENMASK(7, 0);
416 sig[2] = ptphdr->domain;
417 sig[3] = ptphdr->tsmt & GENMASK(3, 0);
419 memcpy(&sig[4], ethhdr->h_dest, ETH_ALEN);
421 /* Fill the last bytes of the signature to reach a 16B signature */
422 for (i = 10; i < 16; i++)
423 sig[i] = ptphdr->tsmt & GENMASK(3, 0);
428 static void vsc85xx_dequeue_skb(struct vsc85xx_ptp *ptp)
430 struct skb_shared_hwtstamps shhwtstamps;
431 struct vsc85xx_ts_fifo fifo;
437 memset(&fifo, 0, sizeof(fifo));
440 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR,
441 MSCC_PHY_PTP_EGR_TS_FIFO(0));
442 if (reg & PTP_EGR_TS_FIFO_EMPTY)
446 *p++ = (reg >> 8) & 0xff;
448 /* Read the current FIFO item. Reading FIFO6 pops the next one. */
449 for (i = 1; i < 7; i++) {
450 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR,
451 MSCC_PHY_PTP_EGR_TS_FIFO(i));
453 *p++ = (reg >> 8) & 0xff;
454 *p++ = (reg >> 16) & 0xff;
455 *p++ = (reg >> 24) & 0xff;
458 len = skb_queue_len(&ptp->tx_queue);
463 skb = __skb_dequeue(&ptp->tx_queue);
467 /* Can't get the signature of the packet, won't ever
468 * be able to have one so let's dequeue the packet.
470 if (get_sig(skb, skb_sig) < 0) {
475 /* Check if we found the signature we were looking for. */
476 if (!memcmp(skb_sig, fifo.sig, sizeof(fifo.sig))) {
477 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
478 shhwtstamps.hwtstamp = ktime_set(fifo.secs, fifo.ns);
479 skb_complete_tx_timestamp(skb, &shhwtstamps);
484 /* Valid signature but does not match the one of the
485 * packet in the FIFO right now, reschedule it for later
488 __skb_queue_tail(&ptp->tx_queue, skb);
492 static void vsc85xx_get_tx_ts(struct vsc85xx_ptp *ptp)
497 vsc85xx_dequeue_skb(ptp);
499 /* If other timestamps are available in the FIFO, process them. */
500 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR,
501 MSCC_PHY_PTP_EGR_TS_FIFO_CTRL);
502 } while (PTP_EGR_FIFO_LEVEL_LAST_READ(reg) > 1);
505 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk)
507 struct vsc8531_private *vsc8531 = phydev->priv;
508 bool base = phydev->mdio.addr == vsc8531->ts_base_addr;
509 static const u8 msgs[] = {
511 PTP_MSGTYPE_DELAY_REQ
516 for (i = 0; i < ARRAY_SIZE(msgs); i++) {
517 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),
518 base ? PTP_FLOW_VALID_CH0 :
521 val = vsc85xx_ts_read_csr(phydev, blk,
522 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i));
523 val &= ~PTP_FLOW_DOMAIN_RANGE_ENA;
524 vsc85xx_ts_write_csr(phydev, blk,
525 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i), val);
527 vsc85xx_ts_write_csr(phydev, blk,
528 MSCC_ANA_PTP_FLOW_MATCH_UPPER(i),
531 vsc85xx_ts_write_csr(phydev, blk,
532 MSCC_ANA_PTP_FLOW_MASK_UPPER(i),
533 PTP_FLOW_MSG_TYPE_MASK);
539 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk)
541 struct vsc8531_private *vsc8531 = phydev->priv;
542 bool base = phydev->mdio.addr == vsc8531->ts_base_addr;
545 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0);
546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID,
547 ANA_ETH1_NTX_PROT_VLAN_TPID(ETH_P_8021AD));
549 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0),
550 base ? ETH1_FLOW_VALID_CH0 : ETH1_FLOW_VALID_CH1);
551 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),
552 ANA_ETH1_FLOW_MATCH_VLAN_TAG2);
553 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0);
554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0);
555 vsc85xx_ts_write_csr(phydev, blk,
556 MSCC_ANA_ETH1_FLOW_VLAN_RANGE_I_TAG(0), 0);
557 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0);
558 vsc85xx_ts_write_csr(phydev, blk,
559 MSCC_ANA_ETH1_FLOW_VLAN_TAG2_I_TAG(0), 0);
561 val = vsc85xx_ts_read_csr(phydev, blk,
562 MSCC_ANA_ETH1_FLOW_MATCH_MODE(0));
563 val &= ~ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK;
564 val |= ANA_ETH1_FLOW_MATCH_VLAN_VERIFY;
565 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),
571 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk)
573 struct vsc8531_private *vsc8531 = phydev->priv;
574 bool base = phydev->mdio.addr == vsc8531->ts_base_addr;
577 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER,
579 /* Match on dest port only, ignore src */
580 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER,
582 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER,
584 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0);
586 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));
587 val &= ~IP1_FLOW_ENA_CHANNEL_MASK_MASK;
588 val |= base ? IP1_FLOW_VALID_CH0 : IP1_FLOW_VALID_CH1;
589 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);
592 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0);
593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0);
594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0),
596 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0),
598 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0),
600 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0),
602 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0);
603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0);
605 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0);
610 static int vsc85xx_adjfine(struct ptp_clock_info *info, long scaled_ppm)
612 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps);
613 struct phy_device *phydev = ptp->phydev;
614 struct vsc8531_private *priv = phydev->priv;
618 if (abs(scaled_ppm) < 66 || abs(scaled_ppm) > 65536UL * 1000000UL)
621 adj = div64_u64(1000000ULL * 65536ULL, abs(scaled_ppm));
622 if (adj > 1000000000L)
625 val = PTP_AUTO_ADJ_NS_ROLLOVER(adj);
626 val |= scaled_ppm > 0 ? PTP_AUTO_ADJ_ADD_1NS : PTP_AUTO_ADJ_SUB_1NS;
628 mutex_lock(&priv->phc_lock);
630 /* Update the ppb val in nano seconds to the auto adjust reg. */
631 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_AUTO_ADJ,
634 /* The auto adjust update val is set to 0 after write operation. */
635 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
636 val |= PTP_LTC_CTRL_AUTO_ADJ_UPDATE;
637 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
639 mutex_unlock(&priv->phc_lock);
644 static int __vsc85xx_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
646 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps);
647 struct phy_device *phydev = ptp->phydev;
648 struct vsc85xx_shared_private *shared =
649 (struct vsc85xx_shared_private *)phydev->shared->priv;
650 struct vsc8531_private *priv = phydev->priv;
653 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
654 val |= PTP_LTC_CTRL_SAVE_ENA;
655 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
657 /* Local Time Counter (LTC) is put in SAVE* regs on rising edge of
660 mutex_lock(&shared->gpio_lock);
661 gpiod_set_value(priv->load_save, 1);
663 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
664 MSCC_PHY_PTP_LTC_SAVED_SEC_MSB);
666 ts->tv_sec = ((time64_t)val) << 32;
668 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
669 MSCC_PHY_PTP_LTC_SAVED_SEC_LSB);
672 ts->tv_nsec = vsc85xx_ts_read_csr(phydev, PROCESSOR,
673 MSCC_PHY_PTP_LTC_SAVED_NS);
675 gpiod_set_value(priv->load_save, 0);
676 mutex_unlock(&shared->gpio_lock);
681 static int vsc85xx_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
683 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps);
684 struct phy_device *phydev = ptp->phydev;
685 struct vsc8531_private *priv = phydev->priv;
687 mutex_lock(&priv->phc_lock);
688 __vsc85xx_gettime(info, ts);
689 mutex_unlock(&priv->phc_lock);
694 static int __vsc85xx_settime(struct ptp_clock_info *info,
695 const struct timespec64 *ts)
697 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps);
698 struct phy_device *phydev = ptp->phydev;
699 struct vsc85xx_shared_private *shared =
700 (struct vsc85xx_shared_private *)phydev->shared->priv;
701 struct vsc8531_private *priv = phydev->priv;
704 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_MSB,
705 PTP_LTC_LOAD_SEC_MSB(ts->tv_sec));
706 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_LSB,
707 PTP_LTC_LOAD_SEC_LSB(ts->tv_sec));
708 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_NS,
709 PTP_LTC_LOAD_NS(ts->tv_nsec));
711 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
712 val |= PTP_LTC_CTRL_LOAD_ENA;
713 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
715 /* Local Time Counter (LTC) is set from LOAD* regs on rising edge of
718 mutex_lock(&shared->gpio_lock);
719 gpiod_set_value(priv->load_save, 1);
721 val &= ~PTP_LTC_CTRL_LOAD_ENA;
722 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
724 gpiod_set_value(priv->load_save, 0);
725 mutex_unlock(&shared->gpio_lock);
730 static int vsc85xx_settime(struct ptp_clock_info *info,
731 const struct timespec64 *ts)
733 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps);
734 struct phy_device *phydev = ptp->phydev;
735 struct vsc8531_private *priv = phydev->priv;
737 mutex_lock(&priv->phc_lock);
738 __vsc85xx_settime(info, ts);
739 mutex_unlock(&priv->phc_lock);
744 static int vsc85xx_adjtime(struct ptp_clock_info *info, s64 delta)
746 struct vsc85xx_ptp *ptp = container_of(info, struct vsc85xx_ptp, caps);
747 struct phy_device *phydev = ptp->phydev;
748 struct vsc8531_private *priv = phydev->priv;
751 /* Can't recover that big of an offset. Let's set the time directly. */
752 if (abs(delta) >= NSEC_PER_SEC) {
753 struct timespec64 ts;
756 mutex_lock(&priv->phc_lock);
758 __vsc85xx_gettime(info, &ts);
759 now = ktime_to_ns(timespec64_to_ktime(ts));
760 ts = ns_to_timespec64(now + delta);
761 __vsc85xx_settime(info, &ts);
763 mutex_unlock(&priv->phc_lock);
768 mutex_lock(&priv->phc_lock);
770 val = PTP_LTC_OFFSET_VAL(abs(delta)) | PTP_LTC_OFFSET_ADJ;
772 val |= PTP_LTC_OFFSET_ADD;
773 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val);
775 mutex_unlock(&priv->phc_lock);
780 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk,
781 u32 next_comp, u32 etype)
785 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT);
786 val &= ~ANA_ETH1_NTX_PROT_COMPARATOR_MASK;
788 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val);
790 val = ANA_ETH1_NXT_PROT_ETYPE_MATCH(etype) |
791 ANA_ETH1_NXT_PROT_ETYPE_MATCH_ENA;
792 vsc85xx_ts_write_csr(phydev, blk,
793 MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH, val);
798 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk,
799 u32 next_comp, u32 header)
801 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP,
802 ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR(header) |
808 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp_cmd cmd)
812 /* Check non-zero reserved field */
813 val = PTP_FLOW_PTP_0_FIELD_PTP_FRAME | PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK;
814 vsc85xx_ts_write_csr(phydev, blk,
815 MSCC_ANA_PTP_FLOW_PTP_0_FIELD(flow), val);
817 val = PTP_FLOW_PTP_ACTION_CORR_OFFSET(8) |
818 PTP_FLOW_PTP_ACTION_TIME_OFFSET(8) |
819 PTP_FLOW_PTP_ACTION_PTP_CMD(cmd == PTP_SAVE_IN_TS_FIFO ?
821 if (cmd == PTP_SAVE_IN_TS_FIFO)
822 val |= PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME;
823 else if (cmd == PTP_WRITE_NS)
824 val |= PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE |
825 PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET(6);
826 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow),
829 if (cmd == PTP_WRITE_1588)
830 /* Rewrite timestamp directly in frame */
831 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(34) |
832 PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(10);
833 else if (cmd == PTP_SAVE_IN_TS_FIFO)
835 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(0) |
836 PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(0);
838 /* Write in reserved field */
839 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(16) |
840 PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(4);
841 vsc85xx_ts_write_csr(phydev, blk,
842 MSCC_ANA_PTP_FLOW_PTP_ACTION2(flow), val);
847 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk,
848 bool one_step, bool enable)
850 static const u8 msgs[] = {
852 PTP_MSGTYPE_DELAY_REQ
857 for (i = 0; i < ARRAY_SIZE(msgs); i++) {
859 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
861 else if (msgs[i] == PTP_MSGTYPE_SYNC && one_step)
862 /* no need to know Sync t when sending in one_step */
863 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
866 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
867 PTP_SAVE_IN_TS_FIFO);
869 val = vsc85xx_ts_read_csr(phydev, blk,
870 MSCC_ANA_PTP_FLOW_ENA(i));
871 val &= ~PTP_FLOW_ENA;
874 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),
881 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk,
884 struct vsc8531_private *vsc8531 = phydev->priv;
885 u32 val = ANA_ETH1_FLOW_ADDR_MATCH2_DEST;
887 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT) {
888 /* PTP over Ethernet multicast address for SYNC and DELAY msg */
889 u8 ptp_multicast[6] = {0x01, 0x1b, 0x19, 0x00, 0x00, 0x00};
891 val |= ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR |
892 get_unaligned_be16(&ptp_multicast[4]);
893 vsc85xx_ts_write_csr(phydev, blk,
894 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val);
895 vsc85xx_ts_write_csr(phydev, blk,
896 MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0),
897 get_unaligned_be32(ptp_multicast));
899 val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST;
900 vsc85xx_ts_write_csr(phydev, blk,
901 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val);
902 vsc85xx_ts_write_csr(phydev, blk,
903 MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0);
906 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0));
907 val &= ~ETH1_FLOW_ENA;
909 val |= ETH1_FLOW_ENA;
910 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val);
915 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk,
920 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE,
921 ANA_IP1_NXT_PROT_IPV4 |
922 ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV4);
924 /* Matching UDP protocol number */
925 val = ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK(0xff) |
926 ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH(IPPROTO_UDP) |
927 ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF(9);
928 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1,
931 /* End of IP protocol, start of next protocol (UDP) */
932 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2,
933 ANA_IP1_NXT_PROT_OFFSET2(20));
935 val = vsc85xx_ts_read_csr(phydev, blk,
936 MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM);
937 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK |
938 IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK);
939 val |= IP1_NXT_PROT_UDP_CHKSUM_WIDTH(2);
941 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_UPDATE |
942 IP1_NXT_PROT_UDP_CHKSUM_CLEAR);
943 /* UDP checksum offset in IPv4 packet
944 * according to: https://tools.ietf.org/html/rfc768
946 val |= IP1_NXT_PROT_UDP_CHKSUM_OFF(26) | IP1_NXT_PROT_UDP_CHKSUM_CLEAR;
947 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,
950 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));
951 val &= ~(IP1_FLOW_MATCH_ADDR_MASK | IP1_FLOW_ENA);
952 val |= IP1_FLOW_MATCH_DEST_SRC_ADDR;
955 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);
960 static int vsc85xx_ts_engine_init(struct phy_device *phydev, bool one_step)
962 struct vsc8531_private *vsc8531 = phydev->priv;
963 bool ptp_l4, base = phydev->mdio.addr == vsc8531->ts_base_addr;
964 u8 eng_id = base ? 0 : 1;
967 ptp_l4 = vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
969 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
970 MSCC_PHY_PTP_ANALYZER_MODE);
971 /* Disable INGRESS and EGRESS so engine eng_id can be reconfigured */
972 val &= ~(PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)) |
973 PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)));
974 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE,
977 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT) {
978 vsc85xx_eth1_next_comp(phydev, INGRESS,
979 ANA_ETH1_NTX_PROT_PTP_OAM, ETH_P_1588);
980 vsc85xx_eth1_next_comp(phydev, EGRESS,
981 ANA_ETH1_NTX_PROT_PTP_OAM, ETH_P_1588);
983 vsc85xx_eth1_next_comp(phydev, INGRESS,
984 ANA_ETH1_NTX_PROT_IP_UDP_ACH_1,
986 vsc85xx_eth1_next_comp(phydev, EGRESS,
987 ANA_ETH1_NTX_PROT_IP_UDP_ACH_1,
989 /* Header length of IPv[4/6] + UDP */
990 vsc85xx_ip1_next_comp(phydev, INGRESS,
991 ANA_ETH1_NTX_PROT_PTP_OAM, 28);
992 vsc85xx_ip1_next_comp(phydev, EGRESS,
993 ANA_ETH1_NTX_PROT_PTP_OAM, 28);
996 vsc85xx_eth1_conf(phydev, INGRESS,
997 vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE);
998 vsc85xx_ip1_conf(phydev, INGRESS,
999 ptp_l4 && vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE);
1000 vsc85xx_ptp_conf(phydev, INGRESS, one_step,
1001 vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE);
1003 vsc85xx_eth1_conf(phydev, EGRESS,
1004 vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF);
1005 vsc85xx_ip1_conf(phydev, EGRESS,
1006 ptp_l4 && vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF);
1007 vsc85xx_ptp_conf(phydev, EGRESS, one_step,
1008 vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF);
1010 val &= ~PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id));
1011 if (vsc8531->ptp->tx_type != HWTSTAMP_TX_OFF)
1012 val |= PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id));
1014 val &= ~PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id));
1015 if (vsc8531->ptp->rx_filter != HWTSTAMP_FILTER_NONE)
1016 val |= PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id));
1018 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE,
1024 void vsc85xx_link_change_notify(struct phy_device *phydev)
1026 struct vsc8531_private *priv = phydev->priv;
1028 mutex_lock(&priv->ts_lock);
1029 vsc85xx_ts_set_latencies(phydev);
1030 mutex_unlock(&priv->ts_lock);
1033 static void vsc85xx_ts_reset_fifo(struct phy_device *phydev)
1037 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1038 MSCC_PHY_PTP_EGR_TS_FIFO_CTRL);
1039 val |= PTP_EGR_TS_FIFO_RESET;
1040 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL,
1043 val &= ~PTP_EGR_TS_FIFO_RESET;
1044 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL,
1048 static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
1050 struct vsc8531_private *vsc8531 =
1051 container_of(mii_ts, struct vsc8531_private, mii_ts);
1052 struct phy_device *phydev = vsc8531->ptp->phydev;
1053 struct hwtstamp_config cfg;
1054 bool one_step = false;
1057 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1060 switch (cfg.tx_type) {
1061 case HWTSTAMP_TX_ONESTEP_SYNC:
1064 case HWTSTAMP_TX_ON:
1066 case HWTSTAMP_TX_OFF:
1072 vsc8531->ptp->tx_type = cfg.tx_type;
1074 switch (cfg.rx_filter) {
1075 case HWTSTAMP_FILTER_NONE:
1077 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1078 /* ETH->IP->UDP->PTP */
1080 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1087 vsc8531->ptp->rx_filter = cfg.rx_filter;
1089 mutex_lock(&vsc8531->ts_lock);
1091 __skb_queue_purge(&vsc8531->ptp->tx_queue);
1092 __skb_queue_head_init(&vsc8531->ptp->tx_queue);
1094 /* Disable predictor while configuring the 1588 block */
1095 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1096 MSCC_PHY_PTP_INGR_PREDICTOR);
1097 val &= ~PTP_INGR_PREDICTOR_EN;
1098 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR,
1100 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1101 MSCC_PHY_PTP_EGR_PREDICTOR);
1102 val &= ~PTP_EGR_PREDICTOR_EN;
1103 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR,
1106 /* Bypass egress or ingress blocks if timestamping isn't used */
1107 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL);
1108 val &= ~(PTP_IFACE_CTRL_EGR_BYPASS | PTP_IFACE_CTRL_INGR_BYPASS);
1109 if (vsc8531->ptp->tx_type == HWTSTAMP_TX_OFF)
1110 val |= PTP_IFACE_CTRL_EGR_BYPASS;
1111 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_NONE)
1112 val |= PTP_IFACE_CTRL_INGR_BYPASS;
1113 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val);
1115 /* Resetting FIFO so that it's empty after reconfiguration */
1116 vsc85xx_ts_reset_fifo(phydev);
1118 vsc85xx_ts_engine_init(phydev, one_step);
1120 /* Re-enable predictors now */
1121 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1122 MSCC_PHY_PTP_INGR_PREDICTOR);
1123 val |= PTP_INGR_PREDICTOR_EN;
1124 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR,
1126 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1127 MSCC_PHY_PTP_EGR_PREDICTOR);
1128 val |= PTP_EGR_PREDICTOR_EN;
1129 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR,
1132 vsc8531->ptp->configured = 1;
1133 mutex_unlock(&vsc8531->ts_lock);
1135 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1138 static int vsc85xx_ts_info(struct mii_timestamper *mii_ts,
1139 struct ethtool_ts_info *info)
1141 struct vsc8531_private *vsc8531 =
1142 container_of(mii_ts, struct vsc8531_private, mii_ts);
1144 info->phc_index = ptp_clock_index(vsc8531->ptp->ptp_clock);
1145 info->so_timestamping =
1146 SOF_TIMESTAMPING_TX_HARDWARE |
1147 SOF_TIMESTAMPING_RX_HARDWARE |
1148 SOF_TIMESTAMPING_RAW_HARDWARE;
1150 (1 << HWTSTAMP_TX_OFF) |
1151 (1 << HWTSTAMP_TX_ON) |
1152 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1154 (1 << HWTSTAMP_FILTER_NONE) |
1155 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1156 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
1161 static void vsc85xx_txtstamp(struct mii_timestamper *mii_ts,
1162 struct sk_buff *skb, int type)
1164 struct vsc8531_private *vsc8531 =
1165 container_of(mii_ts, struct vsc8531_private, mii_ts);
1167 if (!vsc8531->ptp->configured)
1170 if (vsc8531->ptp->tx_type == HWTSTAMP_TX_OFF) {
1175 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1177 mutex_lock(&vsc8531->ts_lock);
1178 __skb_queue_tail(&vsc8531->ptp->tx_queue, skb);
1179 mutex_unlock(&vsc8531->ts_lock);
1182 static bool vsc85xx_rxtstamp(struct mii_timestamper *mii_ts,
1183 struct sk_buff *skb, int type)
1185 struct vsc8531_private *vsc8531 =
1186 container_of(mii_ts, struct vsc8531_private, mii_ts);
1187 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1188 struct vsc85xx_ptphdr *ptphdr;
1189 struct timespec64 ts;
1192 if (!vsc8531->ptp->configured)
1195 if (vsc8531->ptp->rx_filter == HWTSTAMP_FILTER_NONE ||
1196 type == PTP_CLASS_NONE)
1199 vsc85xx_gettime(&vsc8531->ptp->caps, &ts);
1201 ptphdr = get_ptp_header_rx(skb, vsc8531->ptp->rx_filter);
1205 shhwtstamps = skb_hwtstamps(skb);
1206 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1208 ns = ntohl(ptphdr->rsrvd2);
1210 /* nsec is in reserved field */
1211 if (ts.tv_nsec < ns)
1214 shhwtstamps->hwtstamp = ktime_set(ts.tv_sec, ns);
1220 static const struct ptp_clock_info vsc85xx_clk_caps = {
1221 .owner = THIS_MODULE,
1222 .name = "VSC85xx timer",
1229 .adjtime = &vsc85xx_adjtime,
1230 .adjfine = &vsc85xx_adjfine,
1231 .gettime64 = &vsc85xx_gettime,
1232 .settime64 = &vsc85xx_settime,
1235 static struct vsc8531_private *vsc8584_base_priv(struct phy_device *phydev)
1237 struct vsc8531_private *vsc8531 = phydev->priv;
1239 if (vsc8531->ts_base_addr != phydev->mdio.addr) {
1240 struct mdio_device *dev;
1242 dev = phydev->mdio.bus->mdio_map[vsc8531->ts_base_addr];
1243 phydev = container_of(dev, struct phy_device, mdio);
1245 return phydev->priv;
1251 static bool vsc8584_is_1588_input_clk_configured(struct phy_device *phydev)
1253 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev);
1255 return vsc8531->input_clk_init;
1258 static void vsc8584_set_input_clk_configured(struct phy_device *phydev)
1260 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev);
1262 vsc8531->input_clk_init = true;
1265 static int __vsc8584_init_ptp(struct phy_device *phydev)
1267 struct vsc8531_private *vsc8531 = phydev->priv;
1268 static const u32 ltc_seq_e[] = { 0, 400000, 0, 0, 0 };
1269 static const u8 ltc_seq_a[] = { 8, 6, 5, 4, 2 };
1272 if (!vsc8584_is_1588_input_clk_configured(phydev)) {
1273 phy_lock_mdio_bus(phydev);
1275 /* 1588_DIFF_INPUT_CLK configuration: Use an external clock for
1276 * the LTC, as per 3.13.29 in the VSC8584 datasheet.
1278 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1279 MSCC_PHY_PAGE_1588);
1280 phy_ts_base_write(phydev, 29, 0x7ae0);
1281 phy_ts_base_write(phydev, 30, 0xb71c);
1282 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1283 MSCC_PHY_PAGE_STANDARD);
1285 phy_unlock_mdio_bus(phydev);
1287 vsc8584_set_input_clk_configured(phydev);
1290 /* Disable predictor before configuring the 1588 block */
1291 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1292 MSCC_PHY_PTP_INGR_PREDICTOR);
1293 val &= ~PTP_INGR_PREDICTOR_EN;
1294 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR,
1296 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1297 MSCC_PHY_PTP_EGR_PREDICTOR);
1298 val &= ~PTP_EGR_PREDICTOR_EN;
1299 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR,
1302 /* By default, the internal clock of fixed rate 250MHz is used */
1303 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
1304 val &= ~PTP_LTC_CTRL_CLK_SEL_MASK;
1305 val |= PTP_LTC_CTRL_CLK_SEL_INTERNAL_250;
1306 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
1308 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE);
1309 val &= ~PTP_LTC_SEQUENCE_A_MASK;
1310 val |= PTP_LTC_SEQUENCE_A(ltc_seq_a[PHC_CLK_250MHZ]);
1311 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val);
1313 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ);
1314 val &= ~(PTP_LTC_SEQ_ERR_MASK | PTP_LTC_SEQ_ADD_SUB);
1315 if (ltc_seq_e[PHC_CLK_250MHZ])
1316 val |= PTP_LTC_SEQ_ADD_SUB;
1317 val |= PTP_LTC_SEQ_ERR(ltc_seq_e[PHC_CLK_250MHZ]);
1318 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val);
1320 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ,
1323 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_DELAY_FIFO,
1324 IS_ENABLED(CONFIG_MACSEC) ?
1325 PTP_INGR_DELAY_FIFO_DEPTH_MACSEC :
1326 PTP_INGR_DELAY_FIFO_DEPTH_DEFAULT);
1328 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_DELAY_FIFO,
1329 IS_ENABLED(CONFIG_MACSEC) ?
1330 PTP_EGR_DELAY_FIFO_DEPTH_MACSEC :
1331 PTP_EGR_DELAY_FIFO_DEPTH_DEFAULT);
1333 /* Enable n-phase sampler for Viper Rev-B */
1334 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1335 MSCC_PHY_PTP_ACCUR_CFG_STATUS);
1336 val &= ~(PTP_ACCUR_PPS_OUT_BYPASS | PTP_ACCUR_PPS_IN_BYPASS |
1337 PTP_ACCUR_EGR_SOF_BYPASS | PTP_ACCUR_INGR_SOF_BYPASS |
1338 PTP_ACCUR_LOAD_SAVE_BYPASS);
1339 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE |
1340 PTP_ACCUR_PPS_IN_CALIB_ERR | PTP_ACCUR_PPS_IN_CALIB_DONE |
1341 PTP_ACCUR_EGR_SOF_CALIB_ERR | PTP_ACCUR_EGR_SOF_CALIB_DONE |
1342 PTP_ACCUR_INGR_SOF_CALIB_ERR | PTP_ACCUR_INGR_SOF_CALIB_DONE |
1343 PTP_ACCUR_LOAD_SAVE_CALIB_ERR | PTP_ACCUR_LOAD_SAVE_CALIB_DONE;
1344 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1347 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1348 MSCC_PHY_PTP_ACCUR_CFG_STATUS);
1349 val |= PTP_ACCUR_CALIB_TRIGG;
1350 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1353 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1354 MSCC_PHY_PTP_ACCUR_CFG_STATUS);
1355 val &= ~PTP_ACCUR_CALIB_TRIGG;
1356 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE |
1357 PTP_ACCUR_PPS_IN_CALIB_ERR | PTP_ACCUR_PPS_IN_CALIB_DONE |
1358 PTP_ACCUR_EGR_SOF_CALIB_ERR | PTP_ACCUR_EGR_SOF_CALIB_DONE |
1359 PTP_ACCUR_INGR_SOF_CALIB_ERR | PTP_ACCUR_INGR_SOF_CALIB_DONE |
1360 PTP_ACCUR_LOAD_SAVE_CALIB_ERR | PTP_ACCUR_LOAD_SAVE_CALIB_DONE;
1361 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1364 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1365 MSCC_PHY_PTP_ACCUR_CFG_STATUS);
1366 val |= PTP_ACCUR_CALIB_TRIGG;
1367 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1370 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1371 MSCC_PHY_PTP_ACCUR_CFG_STATUS);
1372 val &= ~PTP_ACCUR_CALIB_TRIGG;
1373 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1376 /* Do not access FIFO via SI */
1377 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1378 MSCC_PHY_PTP_TSTAMP_FIFO_SI);
1379 val &= ~PTP_TSTAMP_FIFO_SI_EN;
1380 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_TSTAMP_FIFO_SI,
1383 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1384 MSCC_PHY_PTP_INGR_REWRITER_CTRL);
1385 val &= ~PTP_INGR_REWRITER_REDUCE_PREAMBLE;
1386 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL,
1388 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1389 MSCC_PHY_PTP_EGR_REWRITER_CTRL);
1390 val &= ~PTP_EGR_REWRITER_REDUCE_PREAMBLE;
1391 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL,
1394 /* Put the flag that indicates the frame has been modified to bit 7 */
1395 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1396 MSCC_PHY_PTP_INGR_REWRITER_CTRL);
1397 val |= PTP_INGR_REWRITER_FLAG_BIT_OFF(7) | PTP_INGR_REWRITER_FLAG_VAL;
1398 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL,
1400 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1401 MSCC_PHY_PTP_EGR_REWRITER_CTRL);
1402 val |= PTP_EGR_REWRITER_FLAG_BIT_OFF(7);
1403 val &= ~PTP_EGR_REWRITER_FLAG_VAL;
1404 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL,
1407 /* 30bit mode for RX timestamp, only the nanoseconds are kept in
1410 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1411 MSCC_PHY_PTP_INGR_TSP_CTRL);
1412 val |= PHY_PTP_INGR_TSP_CTRL_FRACT_NS;
1413 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL,
1416 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL);
1417 val |= PHY_PTP_EGR_TSP_CTRL_FRACT_NS;
1418 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val);
1420 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1421 MSCC_PHY_PTP_SERIAL_TOD_IFACE);
1422 val |= PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR;
1423 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_SERIAL_TOD_IFACE,
1426 vsc85xx_ts_fsb_init(phydev);
1428 /* Set the Egress timestamp FIFO configuration and status register */
1429 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1430 MSCC_PHY_PTP_EGR_TS_FIFO_CTRL);
1431 val &= ~(PTP_EGR_TS_FIFO_SIG_BYTES_MASK | PTP_EGR_TS_FIFO_THRESH_MASK);
1432 /* 16 bytes for the signature, 10 for the timestamp in the TS FIFO */
1433 val |= PTP_EGR_TS_FIFO_SIG_BYTES(16) | PTP_EGR_TS_FIFO_THRESH(7);
1434 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL,
1437 vsc85xx_ts_reset_fifo(phydev);
1439 val = PTP_IFACE_CTRL_CLK_ENA;
1440 if (!IS_ENABLED(CONFIG_MACSEC))
1441 val |= PTP_IFACE_CTRL_GMII_PROT;
1442 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val);
1444 vsc85xx_ts_set_latencies(phydev);
1446 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE);
1448 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL);
1449 val |= PTP_IFACE_CTRL_EGR_BYPASS;
1450 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val);
1452 vsc85xx_ts_disable_flows(phydev, EGRESS);
1453 vsc85xx_ts_disable_flows(phydev, INGRESS);
1455 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1456 MSCC_PHY_PTP_ANALYZER_MODE);
1457 /* Disable INGRESS and EGRESS so engine eng_id can be reconfigured */
1458 val &= ~(PTP_ANALYZER_MODE_EGR_ENA_MASK |
1459 PTP_ANALYZER_MODE_INGR_ENA_MASK |
1460 PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK |
1461 PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK);
1462 /* Strict matching in flow (packets should match flows from the same
1463 * index in all enabled comparators (except PTP)).
1465 val |= PTP_ANA_SPLIT_ENCAP_FLOW | PTP_ANA_INGR_ENCAP_FLOW_MODE(0x7) |
1466 PTP_ANA_EGR_ENCAP_FLOW_MODE(0x7);
1467 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE,
1470 /* Initialized for ingress and egress flows:
1471 * - The Ethernet comparator.
1472 * - The IP comparator.
1473 * - The PTP comparator.
1475 vsc85xx_eth_cmp1_init(phydev, INGRESS);
1476 vsc85xx_ip_cmp1_init(phydev, INGRESS);
1477 vsc85xx_ptp_cmp_init(phydev, INGRESS);
1478 vsc85xx_eth_cmp1_init(phydev, EGRESS);
1479 vsc85xx_ip_cmp1_init(phydev, EGRESS);
1480 vsc85xx_ptp_cmp_init(phydev, EGRESS);
1482 vsc85xx_ts_eth_cmp1_sig(phydev);
1484 vsc8531->mii_ts.rxtstamp = vsc85xx_rxtstamp;
1485 vsc8531->mii_ts.txtstamp = vsc85xx_txtstamp;
1486 vsc8531->mii_ts.hwtstamp = vsc85xx_hwtstamp;
1487 vsc8531->mii_ts.ts_info = vsc85xx_ts_info;
1488 phydev->mii_ts = &vsc8531->mii_ts;
1490 memcpy(&vsc8531->ptp->caps, &vsc85xx_clk_caps, sizeof(vsc85xx_clk_caps));
1492 vsc8531->ptp->ptp_clock = ptp_clock_register(&vsc8531->ptp->caps,
1494 return PTR_ERR_OR_ZERO(vsc8531->ptp->ptp_clock);
1497 void vsc8584_config_ts_intr(struct phy_device *phydev)
1499 struct vsc8531_private *priv = phydev->priv;
1501 mutex_lock(&priv->ts_lock);
1502 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_1588_VSC85XX_INT_MASK,
1503 VSC85XX_1588_INT_MASK_MASK);
1504 mutex_unlock(&priv->ts_lock);
1507 int vsc8584_ptp_init(struct phy_device *phydev)
1509 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1510 case PHY_ID_VSC8572:
1511 case PHY_ID_VSC8574:
1512 case PHY_ID_VSC8575:
1513 case PHY_ID_VSC8582:
1514 case PHY_ID_VSC8584:
1515 return __vsc8584_init_ptp(phydev);
1521 irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
1523 struct vsc8531_private *priv = phydev->priv;
1526 mutex_lock(&priv->ts_lock);
1527 rc = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1528 MSCC_PHY_1588_VSC85XX_INT_STATUS);
1529 /* Ack the PTP interrupt */
1530 vsc85xx_ts_write_csr(phydev, PROCESSOR,
1531 MSCC_PHY_1588_VSC85XX_INT_STATUS, rc);
1533 if (!(rc & VSC85XX_1588_INT_MASK_MASK)) {
1534 mutex_unlock(&priv->ts_lock);
1538 if (rc & VSC85XX_1588_INT_FIFO_ADD) {
1539 vsc85xx_get_tx_ts(priv->ptp);
1540 } else if (rc & VSC85XX_1588_INT_FIFO_OVERFLOW) {
1541 __skb_queue_purge(&priv->ptp->tx_queue);
1542 vsc85xx_ts_reset_fifo(phydev);
1545 mutex_unlock(&priv->ts_lock);
1549 int vsc8584_ptp_probe(struct phy_device *phydev)
1551 struct vsc8531_private *vsc8531 = phydev->priv;
1553 vsc8531->ptp = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531->ptp),
1558 mutex_init(&vsc8531->phc_lock);
1559 mutex_init(&vsc8531->ts_lock);
1561 /* Retrieve the shared load/save GPIO. Request it as non exclusive as
1562 * the same GPIO can be requested by all the PHYs of the same package.
1563 * This GPIO must be used with the gpio_lock taken (the lock is shared
1564 * between all PHYs).
1566 vsc8531->load_save = devm_gpiod_get_optional(&phydev->mdio.dev, "load-save",
1567 GPIOD_FLAGS_BIT_NONEXCLUSIVE |
1569 if (IS_ERR(vsc8531->load_save)) {
1570 phydev_err(phydev, "Can't get load-save GPIO (%ld)\n",
1571 PTR_ERR(vsc8531->load_save));
1572 return PTR_ERR(vsc8531->load_save);
1575 vsc8531->ptp->phydev = phydev;
1580 int vsc8584_ptp_probe_once(struct phy_device *phydev)
1582 struct vsc85xx_shared_private *shared =
1583 (struct vsc85xx_shared_private *)phydev->shared->priv;
1585 /* Initialize shared GPIO lock */
1586 mutex_init(&shared->gpio_lock);