drivers/net/phy/mscc/mscc_main.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs
   4  *
   5  * Author: Nagaraju Lakkaraju
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2016 Microsemi Corporation
   8  */
   9
  10 #include <linux/firmware.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/mdio.h>
  15 #include <linux/mii.h>
  16 #include <linux/phy.h>
  17 #include <linux/of.h>
  18 #include <linux/netdevice.h>
  19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  20
  21 #include "mscc.h"
  22
  23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
  24         {
  25                 .string = "phy_receive_errors",
  26                 .reg    = MSCC_PHY_ERR_RX_CNT,
  27                 .page   = MSCC_PHY_PAGE_STANDARD,
  28                 .mask   = ERR_CNT_MASK,
  29         }, {
  30                 .string = "phy_false_carrier",
  31                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
  32                 .page   = MSCC_PHY_PAGE_STANDARD,
  33                 .mask   = ERR_CNT_MASK,
  34         }, {
  35                 .string = "phy_cu_media_link_disconnect",
  36                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
  37                 .page   = MSCC_PHY_PAGE_STANDARD,
  38                 .mask   = ERR_CNT_MASK,
  39         }, {
  40                 .string = "phy_cu_media_crc_good_count",
  41                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
  42                 .page   = MSCC_PHY_PAGE_EXTENDED,
  43                 .mask   = VALID_CRC_CNT_CRC_MASK,
  44         }, {
  45                 .string = "phy_cu_media_crc_error_count",
  46                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
  47                 .page   = MSCC_PHY_PAGE_EXTENDED,
  48                 .mask   = ERR_CNT_MASK,
  49         },
  50 };
  51
  52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
  53         {
  54                 .string = "phy_receive_errors",
  55                 .reg    = MSCC_PHY_ERR_RX_CNT,
  56                 .page   = MSCC_PHY_PAGE_STANDARD,
  57                 .mask   = ERR_CNT_MASK,
  58         }, {
  59                 .string = "phy_false_carrier",
  60                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
  61                 .page   = MSCC_PHY_PAGE_STANDARD,
  62                 .mask   = ERR_CNT_MASK,
  63         }, {
  64                 .string = "phy_cu_media_link_disconnect",
  65                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
  66                 .page   = MSCC_PHY_PAGE_STANDARD,
  67                 .mask   = ERR_CNT_MASK,
  68         }, {
  69                 .string = "phy_cu_media_crc_good_count",
  70                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
  71                 .page   = MSCC_PHY_PAGE_EXTENDED,
  72                 .mask   = VALID_CRC_CNT_CRC_MASK,
  73         }, {
  74                 .string = "phy_cu_media_crc_error_count",
  75                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
  76                 .page   = MSCC_PHY_PAGE_EXTENDED,
  77                 .mask   = ERR_CNT_MASK,
  78         }, {
  79                 .string = "phy_serdes_tx_good_pkt_count",
  80                 .reg    = MSCC_PHY_SERDES_TX_VALID_CNT,
  81                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  82                 .mask   = VALID_CRC_CNT_CRC_MASK,
  83         }, {
  84                 .string = "phy_serdes_tx_bad_crc_count",
  85                 .reg    = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
  86                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  87                 .mask   = ERR_CNT_MASK,
  88         }, {
  89                 .string = "phy_serdes_rx_good_pkt_count",
  90                 .reg    = MSCC_PHY_SERDES_RX_VALID_CNT,
  91                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  92                 .mask   = VALID_CRC_CNT_CRC_MASK,
  93         }, {
  94                 .string = "phy_serdes_rx_bad_crc_count",
  95                 .reg    = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
  96                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  97                 .mask   = ERR_CNT_MASK,
  98         },
  99 };
 100
 101 #if IS_ENABLED(CONFIG_OF_MDIO)
 102 static const struct vsc8531_edge_rate_table edge_table[] = {
 103         {MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
 104         {MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
 105         {MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
 106         {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
 107 };
 108 #endif
 109
 110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
 111 {
 112         return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
 113 }
 114
 115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
 116 {
 117         return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
 118 }
 119
 120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
 121 {
 122         struct vsc8531_private *priv = phydev->priv;
 123
 124         if (!priv)
 125                 return 0;
 126
 127         return priv->nstats;
 128 }
 129
 130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
 131 {
 132         struct vsc8531_private *priv = phydev->priv;
 133         int i;
 134
 135         if (!priv)
 136                 return;
 137
 138         for (i = 0; i < priv->nstats; i++)
 139                 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
 140                         ETH_GSTRING_LEN);
 141 }
 142
 143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
 144 {
 145         struct vsc8531_private *priv = phydev->priv;
 146         int val;
 147
 148         val = phy_read_paged(phydev, priv->hw_stats[i].page,
 149                              priv->hw_stats[i].reg);
 150         if (val < 0)
 151                 return U64_MAX;
 152
 153         val = val & priv->hw_stats[i].mask;
 154         priv->stats[i] += val;
 155
 156         return priv->stats[i];
 157 }
 158
 159 static void vsc85xx_get_stats(struct phy_device *phydev,
 160                               struct ethtool_stats *stats, u64 *data)
 161 {
 162         struct vsc8531_private *priv = phydev->priv;
 163         int i;
 164
 165         if (!priv)
 166                 return;
 167
 168         for (i = 0; i < priv->nstats; i++)
 169                 data[i] = vsc85xx_get_stat(phydev, i);
 170 }
 171
 172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
 173                                 u8 led_num,
 174                                 u8 mode)
 175 {
 176         int rc;
 177         u16 reg_val;
 178
 179         mutex_lock(&phydev->lock);
 180         reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
 181         reg_val &= ~LED_MODE_SEL_MASK(led_num);
 182         reg_val |= LED_MODE_SEL(led_num, (u16)mode);
 183         rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
 184         mutex_unlock(&phydev->lock);
 185
 186         return rc;
 187 }
 188
 189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 190 {
 191         u16 reg_val;
 192
 193         reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
 194         if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
 195                 *mdix = ETH_TP_MDI_X;
 196         else
 197                 *mdix = ETH_TP_MDI;
 198
 199         return 0;
 200 }
 201
 202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
 203 {
 204         int rc;
 205         u16 reg_val;
 206
 207         reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
 208         if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
 209                 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
 210                             DISABLE_POLARITY_CORR_MASK  |
 211                             DISABLE_HP_AUTO_MDIX_MASK);
 212         } else {
 213                 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
 214                              DISABLE_POLARITY_CORR_MASK  |
 215                              DISABLE_HP_AUTO_MDIX_MASK);
 216         }
 217         rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
 218         if (rc)
 219                 return rc;
 220
 221         reg_val = 0;
 222
 223         if (mdix == ETH_TP_MDI)
 224                 reg_val = FORCE_MDI_CROSSOVER_MDI;
 225         else if (mdix == ETH_TP_MDI_X)
 226                 reg_val = FORCE_MDI_CROSSOVER_MDIX;
 227
 228         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 229                               MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
 230                               reg_val);
 231         if (rc < 0)
 232                 return rc;
 233
 234         return genphy_restart_aneg(phydev);
 235 }
 236
 237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
 238 {
 239         int reg_val;
 240
 241         reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 242                                  MSCC_PHY_ACTIPHY_CNTL);
 243         if (reg_val < 0)
 244                 return reg_val;
 245
 246         reg_val &= DOWNSHIFT_CNTL_MASK;
 247         if (!(reg_val & DOWNSHIFT_EN))
 248                 *count = DOWNSHIFT_DEV_DISABLE;
 249         else
 250                 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
 251
 252         return 0;
 253 }
 254
 255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
 256 {
 257         if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
 258                 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
 259                 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 260         } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
 261                 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
 262                 return -ERANGE;
 263         } else if (count) {
 264                 /* Downshift count is either 2,3,4 or 5 */
 265                 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 266         }
 267
 268         return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 269                                 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
 270                                 count);
 271 }
 272
 273 static int vsc85xx_wol_set(struct phy_device *phydev,
 274                            struct ethtool_wolinfo *wol)
 275 {
 276         int rc;
 277         u16 reg_val;
 278         u8  i;
 279         u16 pwd[3] = {0, 0, 0};
 280         struct ethtool_wolinfo *wol_conf = wol;
 281         u8 *mac_addr = phydev->attached_dev->dev_addr;
 282
 283         mutex_lock(&phydev->lock);
 284         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 285         if (rc < 0) {
 286                 rc = phy_restore_page(phydev, rc, rc);
 287                 goto out_unlock;
 288         }
 289
 290         if (wol->wolopts & WAKE_MAGIC) {
 291                 /* Store the device address for the magic packet */
 292                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 293                         pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
 294                                  mac_addr[5 - i * 2];
 295                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
 296                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
 297                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
 298         } else {
 299                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
 300                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
 301                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
 302         }
 303
 304         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 305                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 306                         pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
 307                                  wol_conf->sopass[5 - i * 2];
 308                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
 309                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
 310                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
 311         } else {
 312                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
 313                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
 314                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
 315         }
 316
 317         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 318         if (wol_conf->wolopts & WAKE_MAGICSECURE)
 319                 reg_val |= SECURE_ON_ENABLE;
 320         else
 321                 reg_val &= ~SECURE_ON_ENABLE;
 322         __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
 323
 324         rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 325         if (rc < 0)
 326                 goto out_unlock;
 327
 328         if (wol->wolopts & WAKE_MAGIC) {
 329                 /* Enable the WOL interrupt */
 330                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 331                 reg_val |= MII_VSC85XX_INT_MASK_WOL;
 332                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 333                 if (rc)
 334                         goto out_unlock;
 335         } else {
 336                 /* Disable the WOL interrupt */
 337                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 338                 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
 339                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 340                 if (rc)
 341                         goto out_unlock;
 342         }
 343         /* Clear WOL iterrupt status */
 344         reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 345
 346 out_unlock:
 347         mutex_unlock(&phydev->lock);
 348
 349         return rc;
 350 }
 351
 352 static void vsc85xx_wol_get(struct phy_device *phydev,
 353                             struct ethtool_wolinfo *wol)
 354 {
 355         int rc;
 356         u16 reg_val;
 357         u8  i;
 358         u16 pwd[3] = {0, 0, 0};
 359         struct ethtool_wolinfo *wol_conf = wol;
 360
 361         mutex_lock(&phydev->lock);
 362         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 363         if (rc < 0)
 364                 goto out_unlock;
 365
 366         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 367         if (reg_val & SECURE_ON_ENABLE)
 368                 wol_conf->wolopts |= WAKE_MAGICSECURE;
 369         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 370                 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
 371                 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
 372                 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
 373                 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
 374                         wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
 375                         wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
 376                                                             >> 8;
 377                 }
 378         }
 379
 380 out_unlock:
 381         phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 382         mutex_unlock(&phydev->lock);
 383 }
 384
 385 #if IS_ENABLED(CONFIG_OF_MDIO)
 386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 387 {
 388         u32 vdd, sd;
 389         int i, j;
 390         struct device *dev = &phydev->mdio.dev;
 391         struct device_node *of_node = dev->of_node;
 392         u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
 393
 394         if (!of_node)
 395                 return -ENODEV;
 396
 397         if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
 398                 vdd = MSCC_VDDMAC_3300;
 399
 400         if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
 401                 sd = 0;
 402
 403         for (i = 0; i < ARRAY_SIZE(edge_table); i++)
 404                 if (edge_table[i].vddmac == vdd)
 405                         for (j = 0; j < sd_array_size; j++)
 406                                 if (edge_table[i].slowdown[j] == sd)
 407                                         return (sd_array_size - j - 1);
 408
 409         return -EINVAL;
 410 }
 411
 412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 413                                    char *led,
 414                                    u32 default_mode)
 415 {
 416         struct vsc8531_private *priv = phydev->priv;
 417         struct device *dev = &phydev->mdio.dev;
 418         struct device_node *of_node = dev->of_node;
 419         u32 led_mode;
 420         int err;
 421
 422         if (!of_node)
 423                 return -ENODEV;
 424
 425         led_mode = default_mode;
 426         err = of_property_read_u32(of_node, led, &led_mode);
 427         if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
 428                 phydev_err(phydev, "DT %s invalid\n", led);
 429                 return -EINVAL;
 430         }
 431
 432         return led_mode;
 433 }
 434
 435 #else
 436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 437 {
 438         return 0;
 439 }
 440
 441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 442                                    char *led,
 443                                    u8 default_mode)
 444 {
 445         return default_mode;
 446 }
 447 #endif /* CONFIG_OF_MDIO */
 448
 449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
 450                                     u32 *default_mode)
 451 {
 452         struct vsc8531_private *priv = phydev->priv;
 453         char led_dt_prop[28];
 454         int i, ret;
 455
 456         for (i = 0; i < priv->nleds; i++) {
 457                 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
 458                 if (ret < 0)
 459                         return ret;
 460
 461                 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
 462                                               default_mode[i]);
 463                 if (ret < 0)
 464                         return ret;
 465                 priv->leds_mode[i] = ret;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
 472 {
 473         int rc;
 474
 475         mutex_lock(&phydev->lock);
 476         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 477                               MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
 478                               edge_rate << EDGE_RATE_CNTL_POS);
 479         mutex_unlock(&phydev->lock);
 480
 481         return rc;
 482 }
 483
 484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
 485                               phy_interface_t interface)
 486 {
 487         int rc;
 488         u16 reg_val;
 489
 490         mutex_lock(&phydev->lock);
 491         reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
 492         reg_val &= ~(MAC_IF_SELECTION_MASK);
 493         switch (interface) {
 494         case PHY_INTERFACE_MODE_RGMII_TXID:
 495         case PHY_INTERFACE_MODE_RGMII_RXID:
 496         case PHY_INTERFACE_MODE_RGMII_ID:
 497         case PHY_INTERFACE_MODE_RGMII:
 498                 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
 499                 break;
 500         case PHY_INTERFACE_MODE_RMII:
 501                 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
 502                 break;
 503         case PHY_INTERFACE_MODE_MII:
 504         case PHY_INTERFACE_MODE_GMII:
 505                 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
 506                 break;
 507         default:
 508                 rc = -EINVAL;
 509                 goto out_unlock;
 510         }
 511         rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
 512         if (rc)
 513                 goto out_unlock;
 514
 515         rc = genphy_soft_reset(phydev);
 516
 517 out_unlock:
 518         mutex_unlock(&phydev->lock);
 519
 520         return rc;
 521 }
 522
 523 /* Set the RGMII RX and TX clock skews individually, according to the PHY
 524  * interface type, to:
 525  *  * 0.2 ns (their default, and lowest, hardware value) if delays should
 526  *    not be enabled
 527  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
 528  *    clock transitions at 1000 Mbps) if delays should be enabled
 529  */
 530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
 531                                    u16 rgmii_rx_delay_mask,
 532                                    u16 rgmii_tx_delay_mask)
 533 {
 534         u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
 535         u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
 536         u16 reg_val = 0;
 537         int rc;
 538
 539         mutex_lock(&phydev->lock);
 540
 541         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 542             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 543                 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
 544         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 545             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 546                 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
 547
 548         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 549                               rgmii_cntl,
 550                               rgmii_rx_delay_mask | rgmii_tx_delay_mask,
 551                               reg_val);
 552
 553         mutex_unlock(&phydev->lock);
 554
 555         return rc;
 556 }
 557
 558 static int vsc85xx_default_config(struct phy_device *phydev)
 559 {
 560         int rc;
 561
 562         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 563
 564         if (phy_interface_mode_is_rgmii(phydev->interface)) {
 565                 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL,
 566                                              VSC8502_RGMII_RX_DELAY_MASK,
 567                                              VSC8502_RGMII_TX_DELAY_MASK);
 568                 if (rc)
 569                         return rc;
 570         }
 571
 572         return 0;
 573 }
 574
 575 static int vsc85xx_get_tunable(struct phy_device *phydev,
 576                                struct ethtool_tunable *tuna, void *data)
 577 {
 578         switch (tuna->id) {
 579         case ETHTOOL_PHY_DOWNSHIFT:
 580                 return vsc85xx_downshift_get(phydev, (u8 *)data);
 581         default:
 582                 return -EINVAL;
 583         }
 584 }
 585
 586 static int vsc85xx_set_tunable(struct phy_device *phydev,
 587                                struct ethtool_tunable *tuna,
 588                                const void *data)
 589 {
 590         switch (tuna->id) {
 591         case ETHTOOL_PHY_DOWNSHIFT:
 592                 return vsc85xx_downshift_set(phydev, *(u8 *)data);
 593         default:
 594                 return -EINVAL;
 595         }
 596 }
 597
 598 /* mdiobus lock should be locked when using this function */
 599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
 600 {
 601         __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 602         __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 603         __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 604 }
 605
 606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
 607 {
 608         int rc;
 609         static const struct reg_val init_seq[] = {
 610                 {0x0f90, 0x00688980},
 611                 {0x0696, 0x00000003},
 612                 {0x07fa, 0x0050100f},
 613                 {0x1686, 0x00000004},
 614         };
 615         unsigned int i;
 616         int oldpage;
 617
 618         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
 619                               MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
 620                               SMI_BROADCAST_WR_EN);
 621         if (rc < 0)
 622                 return rc;
 623         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 624                               MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
 625         if (rc < 0)
 626                 return rc;
 627         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 628                               MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
 629         if (rc < 0)
 630                 return rc;
 631         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 632                               MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
 633         if (rc < 0)
 634                 return rc;
 635
 636         mutex_lock(&phydev->lock);
 637         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 638         if (oldpage < 0)
 639                 goto out_unlock;
 640
 641         for (i = 0; i < ARRAY_SIZE(init_seq); i++)
 642                 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
 643
 644 out_unlock:
 645         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 646         mutex_unlock(&phydev->lock);
 647
 648         return oldpage;
 649 }
 650
 651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
 652 {
 653         static const struct reg_val init_eee[] = {
 654                 {0x0f82, 0x0012b00a},
 655                 {0x1686, 0x00000004},
 656                 {0x168c, 0x00d2c46f},
 657                 {0x17a2, 0x00000620},
 658                 {0x16a0, 0x00eeffdd},
 659                 {0x16a6, 0x00071448},
 660                 {0x16a4, 0x0013132f},
 661                 {0x16a8, 0x00000000},
 662                 {0x0ffc, 0x00c0a028},
 663                 {0x0fe8, 0x0091b06c},
 664                 {0x0fea, 0x00041600},
 665                 {0x0f80, 0x00000af4},
 666                 {0x0fec, 0x00901809},
 667                 {0x0fee, 0x0000a6a1},
 668                 {0x0ffe, 0x00b01007},
 669                 {0x16b0, 0x00eeff00},
 670                 {0x16b2, 0x00007000},
 671                 {0x16b4, 0x00000814},
 672         };
 673         unsigned int i;
 674         int oldpage;
 675
 676         mutex_lock(&phydev->lock);
 677         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 678         if (oldpage < 0)
 679                 goto out_unlock;
 680
 681         for (i = 0; i < ARRAY_SIZE(init_eee); i++)
 682                 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
 683
 684 out_unlock:
 685         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 686         mutex_unlock(&phydev->lock);
 687
 688         return oldpage;
 689 }
 690
 691 /* phydev->bus->mdio_lock should be locked when using this function */
 692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
 693 {
 694         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 695                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 696                 dump_stack();
 697         }
 698
 699         return __phy_package_write(phydev, regnum, val);
 700 }
 701
 702 /* phydev->bus->mdio_lock should be locked when using this function */
 703 static int phy_base_read(struct phy_device *phydev, u32 regnum)
 704 {
 705         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 706                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 707                 dump_stack();
 708         }
 709
 710         return __phy_package_read(phydev, regnum);
 711 }
 712
 713 /* bus->mdio_lock should be locked when using this function */
 714 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
 715 {
 716         phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 717         phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 718         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 719 }
 720
 721 /* bus->mdio_lock should be locked when using this function */
 722 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
 723 {
 724         unsigned long deadline;
 725         u16 reg_val;
 726
 727         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 728                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 729
 730         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
 731
 732         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
 733         do {
 734                 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
 735         } while (time_before(jiffies, deadline) &&
 736                  (reg_val & PROC_CMD_NCOMPLETED) &&
 737                  !(reg_val & PROC_CMD_FAILED));
 738
 739         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 740
 741         if (reg_val & PROC_CMD_FAILED)
 742                 return -EIO;
 743
 744         if (reg_val & PROC_CMD_NCOMPLETED)
 745                 return -ETIMEDOUT;
 746
 747         return 0;
 748 }
 749
 750 /* bus->mdio_lock should be locked when using this function */
 751 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
 752                                         bool patch_en)
 753 {
 754         u32 enable, release;
 755
 756         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 757                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 758
 759         enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
 760         release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
 761                 MICRO_CLK_EN;
 762
 763         if (patch_en) {
 764                 enable |= MICRO_PATCH_EN;
 765                 release |= MICRO_PATCH_EN;
 766
 767                 /* Clear all patches */
 768                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 769         }
 770
 771         /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
 772          * override and addr. auto-incr; operate at 125 MHz
 773          */
 774         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
 775         /* Release 8051 Micro SW reset */
 776         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
 777
 778         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 779
 780         return 0;
 781 }
 782
 783 /* bus->mdio_lock should be locked when using this function */
 784 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
 785 {
 786         int ret;
 787         u16 reg;
 788
 789         ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
 790         if (ret)
 791                 return ret;
 792
 793         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 794                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 795
 796         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 797         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
 798         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 799
 800         phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
 801         phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
 802
 803         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 804         reg |= EN_PATCH_RAM_TRAP_ADDR(4);
 805         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 806
 807         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
 808
 809         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
 810         reg &= ~MICRO_NSOFT_RESET;
 811         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
 812
 813         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
 814                        PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
 815                        PROC_CMD_READ);
 816
 817         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 818         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
 819         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 820
 821         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 822
 823         return 0;
 824 }
 825
 826 /* bus->mdio_lock should be locked when using this function */
 827 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
 828                               u16 *crc)
 829 {
 830         int ret;
 831
 832         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 833
 834         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
 835         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
 836
 837         /* Start Micro command */
 838         ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
 839         if (ret)
 840                 goto out;
 841
 842         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 843
 844         *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
 845
 846 out:
 847         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 848
 849         return ret;
 850 }
 851
 852 /* bus->mdio_lock should be locked when using this function */
 853 static int vsc8584_patch_fw(struct phy_device *phydev,
 854                             const struct firmware *fw)
 855 {
 856         int i, ret;
 857
 858         ret = vsc8584_micro_assert_reset(phydev);
 859         if (ret) {
 860                 dev_err(&phydev->mdio.dev,
 861                         "%s: failed to assert reset of micro\n", __func__);
 862                 return ret;
 863         }
 864
 865         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 866                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 867
 868         /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
 869          * Disable the 8051 Micro clock
 870          */
 871         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
 872                        AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
 873                        MICRO_CLK_DIVIDE(2));
 874         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
 875                        INT_MEM_DATA(2));
 876         phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
 877
 878         for (i = 0; i < fw->size; i++)
 879                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
 880                                INT_MEM_WRITE_EN | fw->data[i]);
 881
 882         /* Clear internal memory access */
 883         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 884
 885         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 886
 887         return 0;
 888 }
 889
 890 /* bus->mdio_lock should be locked when using this function */
 891 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
 892 {
 893         u16 reg;
 894         bool ret;
 895
 896         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 897                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 898
 899         reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
 900         if (reg != 0x3eb7) {
 901                 ret = false;
 902                 goto out;
 903         }
 904
 905         reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
 906         if (reg != 0x4012) {
 907                 ret = false;
 908                 goto out;
 909         }
 910
 911         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 912         if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
 913                 ret = false;
 914                 goto out;
 915         }
 916
 917         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
 918         if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM |  DW8051_CLK_EN |
 919              MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
 920                 ret = false;
 921                 goto out;
 922         }
 923
 924         ret = true;
 925 out:
 926         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 927
 928         return ret;
 929 }
 930
 931 /* bus->mdio_lock should be locked when using this function */
 932 static int vsc8574_config_pre_init(struct phy_device *phydev)
 933 {
 934         static const struct reg_val pre_init1[] = {
 935                 {0x0fae, 0x000401bd},
 936                 {0x0fac, 0x000f000f},
 937                 {0x17a0, 0x00a0f147},
 938                 {0x0fe4, 0x00052f54},
 939                 {0x1792, 0x0027303d},
 940                 {0x07fe, 0x00000704},
 941                 {0x0fe0, 0x00060150},
 942                 {0x0f82, 0x0012b00a},
 943                 {0x0f80, 0x00000d74},
 944                 {0x02e0, 0x00000012},
 945                 {0x03a2, 0x00050208},
 946                 {0x03b2, 0x00009186},
 947                 {0x0fb0, 0x000e3700},
 948                 {0x1688, 0x00049f81},
 949                 {0x0fd2, 0x0000ffff},
 950                 {0x168a, 0x00039fa2},
 951                 {0x1690, 0x0020640b},
 952                 {0x0258, 0x00002220},
 953                 {0x025a, 0x00002a20},
 954                 {0x025c, 0x00003060},
 955                 {0x025e, 0x00003fa0},
 956                 {0x03a6, 0x0000e0f0},
 957                 {0x0f92, 0x00001489},
 958                 {0x16a2, 0x00007000},
 959                 {0x16a6, 0x00071448},
 960                 {0x16a0, 0x00eeffdd},
 961                 {0x0fe8, 0x0091b06c},
 962                 {0x0fea, 0x00041600},
 963                 {0x16b0, 0x00eeff00},
 964                 {0x16b2, 0x00007000},
 965                 {0x16b4, 0x00000814},
 966                 {0x0f90, 0x00688980},
 967                 {0x03a4, 0x0000d8f0},
 968                 {0x0fc0, 0x00000400},
 969                 {0x07fa, 0x0050100f},
 970                 {0x0796, 0x00000003},
 971                 {0x07f8, 0x00c3ff98},
 972                 {0x0fa4, 0x0018292a},
 973                 {0x168c, 0x00d2c46f},
 974                 {0x17a2, 0x00000620},
 975                 {0x16a4, 0x0013132f},
 976                 {0x16a8, 0x00000000},
 977                 {0x0ffc, 0x00c0a028},
 978                 {0x0fec, 0x00901c09},
 979                 {0x0fee, 0x0004a6a1},
 980                 {0x0ffe, 0x00b01807},
 981         };
 982         static const struct reg_val pre_init2[] = {
 983                 {0x0486, 0x0008a518},
 984                 {0x0488, 0x006dc696},
 985                 {0x048a, 0x00000912},
 986                 {0x048e, 0x00000db6},
 987                 {0x049c, 0x00596596},
 988                 {0x049e, 0x00000514},
 989                 {0x04a2, 0x00410280},
 990                 {0x04a4, 0x00000000},
 991                 {0x04a6, 0x00000000},
 992                 {0x04a8, 0x00000000},
 993                 {0x04aa, 0x00000000},
 994                 {0x04ae, 0x007df7dd},
 995                 {0x04b0, 0x006d95d4},
 996                 {0x04b2, 0x00492410},
 997         };
 998         struct device *dev = &phydev->mdio.dev;
 999         const struct firmware *fw;
1000         unsigned int i;
1001         u16 crc, reg;
1002         bool serdes_init;
1003         int ret;
1004
1005         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1006
1007         /* all writes below are broadcasted to all PHYs in the same package */
1008         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1009         reg |= SMI_BROADCAST_WR_EN;
1010         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1011
1012         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1013
1014         /* The below register writes are tweaking analog and electrical
1015          * configuration that were determined through characterization by PHY
1016          * engineers. These don't mean anything more than "these are the best
1017          * values".
1018          */
1019         phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1020
1021         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1022
1023         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1024         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1025         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1026         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1027
1028         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1029         reg |= TR_CLK_DISABLE;
1030         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1031
1032         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1033
1034         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1035                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1036
1037         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1038
1039         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1040
1041         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1042
1043         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1044                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1045
1046         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1047
1048         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1049         reg &= ~TR_CLK_DISABLE;
1050         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1051
1052         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1053
1054         /* end of write broadcasting */
1055         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1056         reg &= ~SMI_BROADCAST_WR_EN;
1057         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1058
1059         ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1060         if (ret) {
1061                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1062                         MSCC_VSC8574_REVB_INT8051_FW, ret);
1063                 return ret;
1064         }
1065
1066         /* Add one byte to size for the one added by the patch_fw function */
1067         ret = vsc8584_get_fw_crc(phydev,
1068                                  MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1069                                  fw->size + 1, &crc);
1070         if (ret)
1071                 goto out;
1072
1073         if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1074                 serdes_init = vsc8574_is_serdes_init(phydev);
1075
1076                 if (!serdes_init) {
1077                         ret = vsc8584_micro_assert_reset(phydev);
1078                         if (ret) {
1079                                 dev_err(dev,
1080                                         "%s: failed to assert reset of micro\n",
1081                                         __func__);
1082                                 goto out;
1083                         }
1084                 }
1085         } else {
1086                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1087
1088                 serdes_init = false;
1089
1090                 if (vsc8584_patch_fw(phydev, fw))
1091                         dev_warn(dev,
1092                                  "failed to patch FW, expect non-optimal device\n");
1093         }
1094
1095         if (!serdes_init) {
1096                 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1097                                MSCC_PHY_PAGE_EXTENDED_GPIO);
1098
1099                 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1100                 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1101                 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1102                                EN_PATCH_RAM_TRAP_ADDR(1));
1103
1104                 vsc8584_micro_deassert_reset(phydev, false);
1105
1106                 /* Add one byte to size for the one added by the patch_fw
1107                  * function
1108                  */
1109                 ret = vsc8584_get_fw_crc(phydev,
1110                                          MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1111                                          fw->size + 1, &crc);
1112                 if (ret)
1113                         goto out;
1114
1115                 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1116                         dev_warn(dev,
1117                                  "FW CRC after patching is not the expected one, expect non-optimal device\n");
1118         }
1119
1120         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1121                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1122
1123         ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1124                           PROC_CMD_PHY_INIT);
1125
1126 out:
1127         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1128
1129         release_firmware(fw);
1130
1131         return ret;
1132 }
1133
1134 /* bus->mdio_lock should be locked when using this function */
1135 static int vsc8584_config_pre_init(struct phy_device *phydev)
1136 {
1137         static const struct reg_val pre_init1[] = {
1138                 {0x07fa, 0x0050100f},
1139                 {0x1688, 0x00049f81},
1140                 {0x0f90, 0x00688980},
1141                 {0x03a4, 0x0000d8f0},
1142                 {0x0fc0, 0x00000400},
1143                 {0x0f82, 0x0012b002},
1144                 {0x1686, 0x00000004},
1145                 {0x168c, 0x00d2c46f},
1146                 {0x17a2, 0x00000620},
1147                 {0x16a0, 0x00eeffdd},
1148                 {0x16a6, 0x00071448},
1149                 {0x16a4, 0x0013132f},
1150                 {0x16a8, 0x00000000},
1151                 {0x0ffc, 0x00c0a028},
1152                 {0x0fe8, 0x0091b06c},
1153                 {0x0fea, 0x00041600},
1154                 {0x0f80, 0x00fffaff},
1155                 {0x0fec, 0x00901809},
1156                 {0x0ffe, 0x00b01007},
1157                 {0x16b0, 0x00eeff00},
1158                 {0x16b2, 0x00007000},
1159                 {0x16b4, 0x00000814},
1160         };
1161         static const struct reg_val pre_init2[] = {
1162                 {0x0486, 0x0008a518},
1163                 {0x0488, 0x006dc696},
1164                 {0x048a, 0x00000912},
1165         };
1166         const struct firmware *fw;
1167         struct device *dev = &phydev->mdio.dev;
1168         unsigned int i;
1169         u16 crc, reg;
1170         int ret;
1171
1172         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1173
1174         /* all writes below are broadcasted to all PHYs in the same package */
1175         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1176         reg |= SMI_BROADCAST_WR_EN;
1177         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1178
1179         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1180
1181         reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);
1182         reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1183         phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1184
1185         /* The below register writes are tweaking analog and electrical
1186          * configuration that were determined through characterization by PHY
1187          * engineers. These don't mean anything more than "these are the best
1188          * values".
1189          */
1190         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1191
1192         phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1193
1194         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1195
1196         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1197
1198         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1199         reg |= TR_CLK_DISABLE;
1200         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1201
1202         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1203
1204         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1205
1206         reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1207         reg &= ~0x007f;
1208         reg |= 0x0019;
1209         phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1210
1211         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1212
1213         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1214                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1215
1216         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1217
1218         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1219
1220         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1221
1222         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1223                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1224
1225         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1226
1227         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1228         reg &= ~TR_CLK_DISABLE;
1229         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1230
1231         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1232
1233         /* end of write broadcasting */
1234         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1235         reg &= ~SMI_BROADCAST_WR_EN;
1236         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1237
1238         ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1239         if (ret) {
1240                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1241                         MSCC_VSC8584_REVB_INT8051_FW, ret);
1242                 return ret;
1243         }
1244
1245         /* Add one byte to size for the one added by the patch_fw function */
1246         ret = vsc8584_get_fw_crc(phydev,
1247                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1248                                  fw->size + 1, &crc);
1249         if (ret)
1250                 goto out;
1251
1252         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1253                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1254                 if (vsc8584_patch_fw(phydev, fw))
1255                         dev_warn(dev,
1256                                  "failed to patch FW, expect non-optimal device\n");
1257         }
1258
1259         vsc8584_micro_deassert_reset(phydev, false);
1260
1261         /* Add one byte to size for the one added by the patch_fw function */
1262         ret = vsc8584_get_fw_crc(phydev,
1263                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1264                                  fw->size + 1, &crc);
1265         if (ret)
1266                 goto out;
1267
1268         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1269                 dev_warn(dev,
1270                          "FW CRC after patching is not the expected one, expect non-optimal device\n");
1271
1272         ret = vsc8584_micro_assert_reset(phydev);
1273         if (ret)
1274                 goto out;
1275
1276         vsc8584_micro_deassert_reset(phydev, true);
1277
1278 out:
1279         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1280
1281         release_firmware(fw);
1282
1283         return ret;
1284 }
1285
1286 static void vsc8584_get_base_addr(struct phy_device *phydev)
1287 {
1288         struct vsc8531_private *vsc8531 = phydev->priv;
1289         u16 val, addr;
1290
1291         phy_lock_mdio_bus(phydev);
1292         __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1293
1294         addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1295         addr >>= PHY_CNTL_4_ADDR_POS;
1296
1297         val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1298
1299         __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1300         phy_unlock_mdio_bus(phydev);
1301
1302         /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1303          * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1304          * the base PHY for timestamping operations.
1305          */
1306         vsc8531->ts_base_addr = phydev->mdio.addr;
1307         vsc8531->ts_base_phy = addr;
1308
1309         if (val & PHY_ADDR_REVERSED) {
1310                 vsc8531->base_addr = phydev->mdio.addr + addr;
1311                 if (addr > 1) {
1312                         vsc8531->ts_base_addr += 2;
1313                         vsc8531->ts_base_phy += 2;
1314                 }
1315         } else {
1316                 vsc8531->base_addr = phydev->mdio.addr - addr;
1317                 if (addr > 1) {
1318                         vsc8531->ts_base_addr -= 2;
1319                         vsc8531->ts_base_phy -= 2;
1320                 }
1321         }
1322
1323         vsc8531->addr = addr;
1324 }
1325
1326 static int vsc8584_config_init(struct phy_device *phydev)
1327 {
1328         struct vsc8531_private *vsc8531 = phydev->priv;
1329         int ret, i;
1330         u16 val;
1331
1332         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1333
1334         phy_lock_mdio_bus(phydev);
1335
1336         /* Some parts of the init sequence are identical for every PHY in the
1337          * package. Some parts are modifying the GPIO register bank which is a
1338          * set of registers that are affecting all PHYs, a few resetting the
1339          * microprocessor common to all PHYs. The CRC check responsible of the
1340          * checking the firmware within the 8051 microprocessor can only be
1341          * accessed via the PHY whose internal address in the package is 0.
1342          * All PHYs' interrupts mask register has to be zeroed before enabling
1343          * any PHY's interrupt in this register.
1344          * For all these reasons, we need to do the init sequence once and only
1345          * once whatever is the first PHY in the package that is initialized and
1346          * do the correct init sequence for all PHYs that are package-critical
1347          * in this pre-init function.
1348          */
1349         if (phy_package_init_once(phydev)) {
1350                 /* The following switch statement assumes that the lowest
1351                  * nibble of the phy_id_mask is always 0. This works because
1352                  * the lowest nibble of the PHY_ID's below are also 0.
1353                  */
1354                 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1355
1356                 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1357                 case PHY_ID_VSC8504:
1358                 case PHY_ID_VSC8552:
1359                 case PHY_ID_VSC8572:
1360                 case PHY_ID_VSC8574:
1361                         ret = vsc8574_config_pre_init(phydev);
1362                         break;
1363                 case PHY_ID_VSC856X:
1364                 case PHY_ID_VSC8575:
1365                 case PHY_ID_VSC8582:
1366                 case PHY_ID_VSC8584:
1367                         ret = vsc8584_config_pre_init(phydev);
1368                         break;
1369                 default:
1370                         ret = -EINVAL;
1371                         break;
1372                 }
1373
1374                 if (ret)
1375                         goto err;
1376         }
1377
1378         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1379                              MSCC_PHY_PAGE_EXTENDED_GPIO);
1380         if (ret)
1381                 goto err;
1382
1383         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1384         val &= ~MAC_CFG_MASK;
1385         if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1386                 val |= MAC_CFG_QSGMII;
1387         } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1388                 val |= MAC_CFG_SGMII;
1389         } else if (phy_interface_is_rgmii(phydev)) {
1390                 val |= MAC_CFG_RGMII;
1391         } else {
1392                 ret = -EINVAL;
1393                 goto err;
1394         }
1395
1396         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1397         if (ret)
1398                 goto err;
1399
1400         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1401                              MSCC_PHY_PAGE_STANDARD);
1402         if (ret)
1403                 goto err;
1404
1405         if (!phy_interface_is_rgmii(phydev)) {
1406                 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1407                         PROC_CMD_READ_MOD_WRITE_PORT;
1408                 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1409                         val |= PROC_CMD_QSGMII_MAC;
1410                 else
1411                         val |= PROC_CMD_SGMII_MAC;
1412
1413                 ret = vsc8584_cmd(phydev, val);
1414                 if (ret)
1415                         goto err;
1416
1417                 usleep_range(10000, 20000);
1418         }
1419
1420         /* Disable SerDes for 100Base-FX */
1421         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1422                           PROC_CMD_FIBER_PORT(vsc8531->addr) |
1423                           PROC_CMD_FIBER_DISABLE |
1424                           PROC_CMD_READ_MOD_WRITE_PORT |
1425                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1426         if (ret)
1427                 goto err;
1428
1429         /* Disable SerDes for 1000Base-X */
1430         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1431                           PROC_CMD_FIBER_PORT(vsc8531->addr) |
1432                           PROC_CMD_FIBER_DISABLE |
1433                           PROC_CMD_READ_MOD_WRITE_PORT |
1434                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1435         if (ret)
1436                 goto err;
1437
1438         phy_unlock_mdio_bus(phydev);
1439
1440         ret = vsc8584_macsec_init(phydev);
1441         if (ret)
1442                 return ret;
1443
1444         ret = vsc8584_ptp_init(phydev);
1445         if (ret)
1446                 return ret;
1447
1448         val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1449         val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1450         val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1451                (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1452         ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1453         if (ret)
1454                 return ret;
1455
1456         if (phy_interface_is_rgmii(phydev)) {
1457                 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL,
1458                                               VSC8572_RGMII_RX_DELAY_MASK,
1459                                               VSC8572_RGMII_TX_DELAY_MASK);
1460                 if (ret)
1461                         return ret;
1462         }
1463
1464         ret = genphy_soft_reset(phydev);
1465         if (ret)
1466                 return ret;
1467
1468         for (i = 0; i < vsc8531->nleds; i++) {
1469                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1470                 if (ret)
1471                         return ret;
1472         }
1473
1474         return 0;
1475
1476 err:
1477         phy_unlock_mdio_bus(phydev);
1478         return ret;
1479 }
1480
1481 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1482 {
1483         irqreturn_t ret;
1484         int irq_status;
1485
1486         irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1487         if (irq_status < 0)
1488                 return IRQ_NONE;
1489
1490         /* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1491          * irq_status would be 0.
1492          */
1493         ret = vsc8584_handle_ts_interrupt(phydev);
1494         if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1495                 return ret;
1496
1497         if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1498                 vsc8584_handle_macsec_interrupt(phydev);
1499
1500         if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1501                 phy_mac_interrupt(phydev);
1502
1503         return IRQ_HANDLED;
1504 }
1505
1506 static int vsc85xx_config_init(struct phy_device *phydev)
1507 {
1508         int rc, i, phy_id;
1509         struct vsc8531_private *vsc8531 = phydev->priv;
1510
1511         rc = vsc85xx_default_config(phydev);
1512         if (rc)
1513                 return rc;
1514
1515         rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1516         if (rc)
1517                 return rc;
1518
1519         rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1520         if (rc)
1521                 return rc;
1522
1523         phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1524         if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1525             PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1526                 rc = vsc8531_pre_init_seq_set(phydev);
1527                 if (rc)
1528                         return rc;
1529         }
1530
1531         rc = vsc85xx_eee_init_seq_set(phydev);
1532         if (rc)
1533                 return rc;
1534
1535         for (i = 0; i < vsc8531->nleds; i++) {
1536                 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1537                 if (rc)
1538                         return rc;
1539         }
1540
1541         return 0;
1542 }
1543
1544 static int vsc8584_did_interrupt(struct phy_device *phydev)
1545 {
1546         int rc = 0;
1547
1548         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1549                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1550
1551         return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1552 }
1553
1554 static int vsc8514_config_pre_init(struct phy_device *phydev)
1555 {
1556         /* These are the settings to override the silicon default
1557          * values to handle hardware performance of PHY. They
1558          * are set at Power-On state and remain until PHY Reset.
1559          */
1560         static const struct reg_val pre_init1[] = {
1561                 {0x0f90, 0x00688980},
1562                 {0x0786, 0x00000003},
1563                 {0x07fa, 0x0050100f},
1564                 {0x0f82, 0x0012b002},
1565                 {0x1686, 0x00000004},
1566                 {0x168c, 0x00d2c46f},
1567                 {0x17a2, 0x00000620},
1568                 {0x16a0, 0x00eeffdd},
1569                 {0x16a6, 0x00071448},
1570                 {0x16a4, 0x0013132f},
1571                 {0x16a8, 0x00000000},
1572                 {0x0ffc, 0x00c0a028},
1573                 {0x0fe8, 0x0091b06c},
1574                 {0x0fea, 0x00041600},
1575                 {0x0f80, 0x00fffaff},
1576                 {0x0fec, 0x00901809},
1577                 {0x0ffe, 0x00b01007},
1578                 {0x16b0, 0x00eeff00},
1579                 {0x16b2, 0x00007000},
1580                 {0x16b4, 0x00000814},
1581         };
1582         unsigned int i;
1583         u16 reg;
1584
1585         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1586
1587         /* all writes below are broadcasted to all PHYs in the same package */
1588         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1589         reg |= SMI_BROADCAST_WR_EN;
1590         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1591
1592         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1593
1594         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1595         reg |= BIT(15);
1596         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1597
1598         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1599
1600         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1601                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1602
1603         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1604
1605         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1606         reg &= ~BIT(15);
1607         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1608
1609         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1610
1611         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1612         reg &= ~SMI_BROADCAST_WR_EN;
1613         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1614
1615         return 0;
1616 }
1617
1618 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev,
1619                                      u32 target, u32 reg)
1620 {
1621         unsigned long deadline;
1622         u32 val, val_l, val_h;
1623
1624         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1625
1626         /* CSR registers are grouped under different Target IDs.
1627          * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1628          * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1629          * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1630          * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1631          */
1632
1633         /* Setup the Target ID */
1634         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1635                        MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1636
1637         /* Trigger CSR Action - Read into the CSR's */
1638         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1639                        MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
1640                        MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1641                        MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1642
1643         /* Wait for register access*/
1644         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1645         do {
1646                 usleep_range(500, 1000);
1647                 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1648         } while (time_before(jiffies, deadline) &&
1649                 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1650
1651         if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1652                 return 0xffffffff;
1653
1654         /* Read the Least Significant Word (LSW) (17) */
1655         val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
1656
1657         /* Read the Most Significant Word (MSW) (18) */
1658         val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
1659
1660         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1661                        MSCC_PHY_PAGE_STANDARD);
1662
1663         return (val_h << 16) | val_l;
1664 }
1665
1666 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev,
1667                                       u32 target, u32 reg, u32 val)
1668 {
1669         unsigned long deadline;
1670
1671         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1672
1673         /* CSR registers are grouped under different Target IDs.
1674          * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1675          * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1676          * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1677          * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1678          */
1679
1680         /* Setup the Target ID */
1681         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1682                        MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1683
1684         /* Write the Least Significant Word (LSW) (17) */
1685         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
1686
1687         /* Write the Most Significant Word (MSW) (18) */
1688         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
1689
1690         /* Trigger CSR Action - Write into the CSR's */
1691         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1692                        MSCC_PHY_CSR_CNTL_19_CMD |
1693                        MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1694                        MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1695
1696         /* Wait for register access */
1697         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1698         do {
1699                 usleep_range(500, 1000);
1700                 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1701         } while (time_before(jiffies, deadline) &&
1702                  !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1703
1704         if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1705                 return -ETIMEDOUT;
1706
1707         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1708                        MSCC_PHY_PAGE_STANDARD);
1709
1710         return 0;
1711 }
1712
1713 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1714                                u32 op)
1715 {
1716         unsigned long deadline;
1717         u32 val;
1718         int ret;
1719
1720         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg,
1721                                          op | (1 << mcb));
1722         if (ret)
1723                 return -EINVAL;
1724
1725         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1726         do {
1727                 usleep_range(500, 1000);
1728                 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg);
1729
1730                 if (val == 0xffffffff)
1731                         return -EIO;
1732
1733         } while (time_before(jiffies, deadline) && (val & op));
1734
1735         if (val & op)
1736                 return -ETIMEDOUT;
1737
1738         return 0;
1739 }
1740
1741 /* Trigger a read to the specified MCB */
1742 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1743 {
1744         return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1745 }
1746
1747 /* Trigger a write to the specified MCB */
1748 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1749 {
1750         return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1751 }
1752
1753 static int vsc8514_config_init(struct phy_device *phydev)
1754 {
1755         struct vsc8531_private *vsc8531 = phydev->priv;
1756         unsigned long deadline;
1757         int ret, i;
1758         u16 val;
1759         u32 reg;
1760
1761         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1762
1763         phy_lock_mdio_bus(phydev);
1764
1765         /* Some parts of the init sequence are identical for every PHY in the
1766          * package. Some parts are modifying the GPIO register bank which is a
1767          * set of registers that are affecting all PHYs, a few resetting the
1768          * microprocessor common to all PHYs.
1769          * All PHYs' interrupts mask register has to be zeroed before enabling
1770          * any PHY's interrupt in this register.
1771          * For all these reasons, we need to do the init sequence once and only
1772          * once whatever is the first PHY in the package that is initialized and
1773          * do the correct init sequence for all PHYs that are package-critical
1774          * in this pre-init function.
1775          */
1776         if (phy_package_init_once(phydev))
1777                 vsc8514_config_pre_init(phydev);
1778
1779         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1780                              MSCC_PHY_PAGE_EXTENDED_GPIO);
1781         if (ret)
1782                 goto err;
1783
1784         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1785
1786         val &= ~MAC_CFG_MASK;
1787         val |= MAC_CFG_QSGMII;
1788         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1789         if (ret)
1790                 goto err;
1791
1792         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1793                              MSCC_PHY_PAGE_STANDARD);
1794         if (ret)
1795                 goto err;
1796
1797         ret = vsc8584_cmd(phydev,
1798                           PROC_CMD_MCB_ACCESS_MAC_CONF |
1799                           PROC_CMD_RST_CONF_PORT |
1800                           PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1801         if (ret)
1802                 goto err;
1803
1804         /* 6g mcb */
1805         phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1806         /* lcpll mcb */
1807         phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1808         /* pll5gcfg0 */
1809         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1810                                          PHY_S6G_PLL5G_CFG0, 0x7036f145);
1811         if (ret)
1812                 goto err;
1813
1814         phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1815         /* pllcfg */
1816         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1817                                          PHY_S6G_PLL_CFG,
1818                                          (3 << PHY_S6G_PLL_ENA_OFFS_POS) |
1819                                          (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS)
1820                                          | (0 << PHY_S6G_PLL_FSM_ENA_POS));
1821         if (ret)
1822                 goto err;
1823
1824         /* commoncfg */
1825         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1826                                          PHY_S6G_COMMON_CFG,
1827                                          (0 << PHY_S6G_SYS_RST_POS) |
1828                                          (0 << PHY_S6G_ENA_LANE_POS) |
1829                                          (0 << PHY_S6G_ENA_LOOP_POS) |
1830                                          (0 << PHY_S6G_QRATE_POS) |
1831                                          (3 << PHY_S6G_IF_MODE_POS));
1832         if (ret)
1833                 goto err;
1834
1835         /* misccfg */
1836         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1837                                          PHY_S6G_MISC_CFG, 1);
1838         if (ret)
1839                 goto err;
1840
1841         /* gpcfg */
1842         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1843                                          PHY_S6G_GPC_CFG, 768);
1844         if (ret)
1845                 goto err;
1846
1847         phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
1848
1849         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1850         do {
1851                 usleep_range(500, 1000);
1852                 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1853                                    0); /* read 6G MCB into CSRs */
1854                 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
1855                                                 PHY_S6G_PLL_STATUS);
1856                 if (reg == 0xffffffff) {
1857                         phy_unlock_mdio_bus(phydev);
1858                         return -EIO;
1859                 }
1860
1861         } while (time_before(jiffies, deadline) && (reg & BIT(12)));
1862
1863         if (reg & BIT(12)) {
1864                 phy_unlock_mdio_bus(phydev);
1865                 return -ETIMEDOUT;
1866         }
1867
1868         /* misccfg */
1869         ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1870                                          PHY_S6G_MISC_CFG, 0);
1871         if (ret)
1872                 goto err;
1873
1874         phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1875
1876         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1877         do {
1878                 usleep_range(500, 1000);
1879                 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1880                                    0); /* read 6G MCB into CSRs */
1881                 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
1882                                                 PHY_S6G_IB_STATUS0);
1883                 if (reg == 0xffffffff) {
1884                         phy_unlock_mdio_bus(phydev);
1885                         return -EIO;
1886                 }
1887
1888         } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
1889
1890         if (!(reg & BIT(8))) {
1891                 phy_unlock_mdio_bus(phydev);
1892                 return -ETIMEDOUT;
1893         }
1894
1895         phy_unlock_mdio_bus(phydev);
1896
1897         ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
1898                          MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
1899
1900         if (ret)
1901                 return ret;
1902
1903         ret = genphy_soft_reset(phydev);
1904
1905         if (ret)
1906                 return ret;
1907
1908         for (i = 0; i < vsc8531->nleds; i++) {
1909                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1910                 if (ret)
1911                         return ret;
1912         }
1913
1914         return ret;
1915
1916 err:
1917         phy_unlock_mdio_bus(phydev);
1918         return ret;
1919 }
1920
1921 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
1922 {
1923         int rc = 0;
1924
1925         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1926                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1927
1928         return (rc < 0) ? rc : 0;
1929 }
1930
1931 static int vsc85xx_config_intr(struct phy_device *phydev)
1932 {
1933         int rc;
1934
1935         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1936                 vsc8584_config_macsec_intr(phydev);
1937                 vsc8584_config_ts_intr(phydev);
1938
1939                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
1940                                MII_VSC85XX_INT_MASK_MASK);
1941         } else {
1942                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
1943                 if (rc < 0)
1944                         return rc;
1945                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1946         }
1947
1948         return rc;
1949 }
1950
1951 static int vsc85xx_config_aneg(struct phy_device *phydev)
1952 {
1953         int rc;
1954
1955         rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
1956         if (rc < 0)
1957                 return rc;
1958
1959         return genphy_config_aneg(phydev);
1960 }
1961
1962 static int vsc85xx_read_status(struct phy_device *phydev)
1963 {
1964         int rc;
1965
1966         rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
1967         if (rc < 0)
1968                 return rc;
1969
1970         return genphy_read_status(phydev);
1971 }
1972
1973 static int vsc8514_probe(struct phy_device *phydev)
1974 {
1975         struct vsc8531_private *vsc8531;
1976         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1977            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1978            VSC8531_DUPLEX_COLLISION};
1979
1980         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1981         if (!vsc8531)
1982                 return -ENOMEM;
1983
1984         phydev->priv = vsc8531;
1985
1986         vsc8584_get_base_addr(phydev);
1987         devm_phy_package_join(&phydev->mdio.dev, phydev,
1988                               vsc8531->base_addr, 0);
1989
1990         vsc8531->nleds = 4;
1991         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
1992         vsc8531->hw_stats = vsc85xx_hw_stats;
1993         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
1994         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
1995                                       sizeof(u64), GFP_KERNEL);
1996         if (!vsc8531->stats)
1997                 return -ENOMEM;
1998
1999         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2000 }
2001
2002 static int vsc8574_probe(struct phy_device *phydev)
2003 {
2004         struct vsc8531_private *vsc8531;
2005         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2006            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2007            VSC8531_DUPLEX_COLLISION};
2008
2009         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2010         if (!vsc8531)
2011                 return -ENOMEM;
2012
2013         phydev->priv = vsc8531;
2014
2015         vsc8584_get_base_addr(phydev);
2016         devm_phy_package_join(&phydev->mdio.dev, phydev,
2017                               vsc8531->base_addr, 0);
2018
2019         vsc8531->nleds = 4;
2020         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2021         vsc8531->hw_stats = vsc8584_hw_stats;
2022         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2023         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2024                                       sizeof(u64), GFP_KERNEL);
2025         if (!vsc8531->stats)
2026                 return -ENOMEM;
2027
2028         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2029 }
2030
2031 static int vsc8584_probe(struct phy_device *phydev)
2032 {
2033         struct vsc8531_private *vsc8531;
2034         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2035            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2036            VSC8531_DUPLEX_COLLISION};
2037         int ret;
2038
2039         if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2040                 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2041                 return -ENOTSUPP;
2042         }
2043
2044         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2045         if (!vsc8531)
2046                 return -ENOMEM;
2047
2048         phydev->priv = vsc8531;
2049
2050         vsc8584_get_base_addr(phydev);
2051         devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2052                               sizeof(struct vsc85xx_shared_private));
2053
2054         vsc8531->nleds = 4;
2055         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2056         vsc8531->hw_stats = vsc8584_hw_stats;
2057         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2058         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2059                                       sizeof(u64), GFP_KERNEL);
2060         if (!vsc8531->stats)
2061                 return -ENOMEM;
2062
2063         if (phy_package_probe_once(phydev)) {
2064                 ret = vsc8584_ptp_probe_once(phydev);
2065                 if (ret)
2066                         return ret;
2067         }
2068
2069         ret = vsc8584_ptp_probe(phydev);
2070         if (ret)
2071                 return ret;
2072
2073         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2074 }
2075
2076 static int vsc85xx_probe(struct phy_device *phydev)
2077 {
2078         struct vsc8531_private *vsc8531;
2079         int rate_magic;
2080         u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2081            VSC8531_LINK_100_ACTIVITY};
2082
2083         rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2084         if (rate_magic < 0)
2085                 return rate_magic;
2086
2087         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2088         if (!vsc8531)
2089                 return -ENOMEM;
2090
2091         phydev->priv = vsc8531;
2092
2093         vsc8531->rate_magic = rate_magic;
2094         vsc8531->nleds = 2;
2095         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2096         vsc8531->hw_stats = vsc85xx_hw_stats;
2097         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2098         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2099                                       sizeof(u64), GFP_KERNEL);
2100         if (!vsc8531->stats)
2101                 return -ENOMEM;
2102
2103         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2104 }
2105
2106 /* Microsemi VSC85xx PHYs */
2107 static struct phy_driver vsc85xx_driver[] = {
2108 {
2109         .phy_id         = PHY_ID_VSC8502,
2110         .name           = "Microsemi GE VSC8502 SyncE",
2111         .phy_id_mask    = 0xfffffff0,
2112         /* PHY_BASIC_FEATURES */
2113         .soft_reset     = &genphy_soft_reset,
2114         .config_init    = &vsc85xx_config_init,
2115         .config_aneg    = &vsc85xx_config_aneg,
2116         .read_status    = &vsc85xx_read_status,
2117         .ack_interrupt  = &vsc85xx_ack_interrupt,
2118         .config_intr    = &vsc85xx_config_intr,
2119         .suspend        = &genphy_suspend,
2120         .resume         = &genphy_resume,
2121         .probe          = &vsc85xx_probe,
2122         .set_wol        = &vsc85xx_wol_set,
2123         .get_wol        = &vsc85xx_wol_get,
2124         .get_tunable    = &vsc85xx_get_tunable,
2125         .set_tunable    = &vsc85xx_set_tunable,
2126         .read_page      = &vsc85xx_phy_read_page,
2127         .write_page     = &vsc85xx_phy_write_page,
2128         .get_sset_count = &vsc85xx_get_sset_count,
2129         .get_strings    = &vsc85xx_get_strings,
2130         .get_stats      = &vsc85xx_get_stats,
2131 },
2132 {
2133         .phy_id         = PHY_ID_VSC8504,
2134         .name           = "Microsemi GE VSC8504 SyncE",
2135         .phy_id_mask    = 0xfffffff0,
2136         /* PHY_GBIT_FEATURES */
2137         .soft_reset     = &genphy_soft_reset,
2138         .config_init    = &vsc8584_config_init,
2139         .config_aneg    = &vsc85xx_config_aneg,
2140         .aneg_done      = &genphy_aneg_done,
2141         .read_status    = &vsc85xx_read_status,
2142         .ack_interrupt  = &vsc85xx_ack_interrupt,
2143         .config_intr    = &vsc85xx_config_intr,
2144         .did_interrupt  = &vsc8584_did_interrupt,
2145         .suspend        = &genphy_suspend,
2146         .resume         = &genphy_resume,
2147         .probe          = &vsc8574_probe,
2148         .set_wol        = &vsc85xx_wol_set,
2149         .get_wol        = &vsc85xx_wol_get,
2150         .get_tunable    = &vsc85xx_get_tunable,
2151         .set_tunable    = &vsc85xx_set_tunable,
2152         .read_page      = &vsc85xx_phy_read_page,
2153         .write_page     = &vsc85xx_phy_write_page,
2154         .get_sset_count = &vsc85xx_get_sset_count,
2155         .get_strings    = &vsc85xx_get_strings,
2156         .get_stats      = &vsc85xx_get_stats,
2157 },
2158 {
2159         .phy_id         = PHY_ID_VSC8514,
2160         .name           = "Microsemi GE VSC8514 SyncE",
2161         .phy_id_mask    = 0xfffffff0,
2162         .soft_reset     = &genphy_soft_reset,
2163         .config_init    = &vsc8514_config_init,
2164         .config_aneg    = &vsc85xx_config_aneg,
2165         .read_status    = &vsc85xx_read_status,
2166         .ack_interrupt  = &vsc85xx_ack_interrupt,
2167         .config_intr    = &vsc85xx_config_intr,
2168         .suspend        = &genphy_suspend,
2169         .resume         = &genphy_resume,
2170         .probe          = &vsc8514_probe,
2171         .set_wol        = &vsc85xx_wol_set,
2172         .get_wol        = &vsc85xx_wol_get,
2173         .get_tunable    = &vsc85xx_get_tunable,
2174         .set_tunable    = &vsc85xx_set_tunable,
2175         .read_page      = &vsc85xx_phy_read_page,
2176         .write_page     = &vsc85xx_phy_write_page,
2177         .get_sset_count = &vsc85xx_get_sset_count,
2178         .get_strings    = &vsc85xx_get_strings,
2179         .get_stats      = &vsc85xx_get_stats,
2180 },
2181 {
2182         .phy_id         = PHY_ID_VSC8530,
2183         .name           = "Microsemi FE VSC8530",
2184         .phy_id_mask    = 0xfffffff0,
2185         /* PHY_BASIC_FEATURES */
2186         .soft_reset     = &genphy_soft_reset,
2187         .config_init    = &vsc85xx_config_init,
2188         .config_aneg    = &vsc85xx_config_aneg,
2189         .read_status    = &vsc85xx_read_status,
2190         .ack_interrupt  = &vsc85xx_ack_interrupt,
2191         .config_intr    = &vsc85xx_config_intr,
2192         .suspend        = &genphy_suspend,
2193         .resume         = &genphy_resume,
2194         .probe          = &vsc85xx_probe,
2195         .set_wol        = &vsc85xx_wol_set,
2196         .get_wol        = &vsc85xx_wol_get,
2197         .get_tunable    = &vsc85xx_get_tunable,
2198         .set_tunable    = &vsc85xx_set_tunable,
2199         .read_page      = &vsc85xx_phy_read_page,
2200         .write_page     = &vsc85xx_phy_write_page,
2201         .get_sset_count = &vsc85xx_get_sset_count,
2202         .get_strings    = &vsc85xx_get_strings,
2203         .get_stats      = &vsc85xx_get_stats,
2204 },
2205 {
2206         .phy_id         = PHY_ID_VSC8531,
2207         .name           = "Microsemi VSC8531",
2208         .phy_id_mask    = 0xfffffff0,
2209         /* PHY_GBIT_FEATURES */
2210         .soft_reset     = &genphy_soft_reset,
2211         .config_init    = &vsc85xx_config_init,
2212         .config_aneg    = &vsc85xx_config_aneg,
2213         .read_status    = &vsc85xx_read_status,
2214         .ack_interrupt  = &vsc85xx_ack_interrupt,
2215         .config_intr    = &vsc85xx_config_intr,
2216         .suspend        = &genphy_suspend,
2217         .resume         = &genphy_resume,
2218         .probe          = &vsc85xx_probe,
2219         .set_wol        = &vsc85xx_wol_set,
2220         .get_wol        = &vsc85xx_wol_get,
2221         .get_tunable    = &vsc85xx_get_tunable,
2222         .set_tunable    = &vsc85xx_set_tunable,
2223         .read_page      = &vsc85xx_phy_read_page,
2224         .write_page     = &vsc85xx_phy_write_page,
2225         .get_sset_count = &vsc85xx_get_sset_count,
2226         .get_strings    = &vsc85xx_get_strings,
2227         .get_stats      = &vsc85xx_get_stats,
2228 },
2229 {
2230         .phy_id         = PHY_ID_VSC8540,
2231         .name           = "Microsemi FE VSC8540 SyncE",
2232         .phy_id_mask    = 0xfffffff0,
2233         /* PHY_BASIC_FEATURES */
2234         .soft_reset     = &genphy_soft_reset,
2235         .config_init    = &vsc85xx_config_init,
2236         .config_aneg    = &vsc85xx_config_aneg,
2237         .read_status    = &vsc85xx_read_status,
2238         .ack_interrupt  = &vsc85xx_ack_interrupt,
2239         .config_intr    = &vsc85xx_config_intr,
2240         .suspend        = &genphy_suspend,
2241         .resume         = &genphy_resume,
2242         .probe          = &vsc85xx_probe,
2243         .set_wol        = &vsc85xx_wol_set,
2244         .get_wol        = &vsc85xx_wol_get,
2245         .get_tunable    = &vsc85xx_get_tunable,
2246         .set_tunable    = &vsc85xx_set_tunable,
2247         .read_page      = &vsc85xx_phy_read_page,
2248         .write_page     = &vsc85xx_phy_write_page,
2249         .get_sset_count = &vsc85xx_get_sset_count,
2250         .get_strings    = &vsc85xx_get_strings,
2251         .get_stats      = &vsc85xx_get_stats,
2252 },
2253 {
2254         .phy_id         = PHY_ID_VSC8541,
2255         .name           = "Microsemi VSC8541 SyncE",
2256         .phy_id_mask    = 0xfffffff0,
2257         /* PHY_GBIT_FEATURES */
2258         .soft_reset     = &genphy_soft_reset,
2259         .config_init    = &vsc85xx_config_init,
2260         .config_aneg    = &vsc85xx_config_aneg,
2261         .read_status    = &vsc85xx_read_status,
2262         .ack_interrupt  = &vsc85xx_ack_interrupt,
2263         .config_intr    = &vsc85xx_config_intr,
2264         .suspend        = &genphy_suspend,
2265         .resume         = &genphy_resume,
2266         .probe          = &vsc85xx_probe,
2267         .set_wol        = &vsc85xx_wol_set,
2268         .get_wol        = &vsc85xx_wol_get,
2269         .get_tunable    = &vsc85xx_get_tunable,
2270         .set_tunable    = &vsc85xx_set_tunable,
2271         .read_page      = &vsc85xx_phy_read_page,
2272         .write_page     = &vsc85xx_phy_write_page,
2273         .get_sset_count = &vsc85xx_get_sset_count,
2274         .get_strings    = &vsc85xx_get_strings,
2275         .get_stats      = &vsc85xx_get_stats,
2276 },
2277 {
2278         .phy_id         = PHY_ID_VSC8552,
2279         .name           = "Microsemi GE VSC8552 SyncE",
2280         .phy_id_mask    = 0xfffffff0,
2281         /* PHY_GBIT_FEATURES */
2282         .soft_reset     = &genphy_soft_reset,
2283         .config_init    = &vsc8584_config_init,
2284         .config_aneg    = &vsc85xx_config_aneg,
2285         .read_status    = &vsc85xx_read_status,
2286         .ack_interrupt  = &vsc85xx_ack_interrupt,
2287         .config_intr    = &vsc85xx_config_intr,
2288         .did_interrupt  = &vsc8584_did_interrupt,
2289         .suspend        = &genphy_suspend,
2290         .resume         = &genphy_resume,
2291         .probe          = &vsc8574_probe,
2292         .set_wol        = &vsc85xx_wol_set,
2293         .get_wol        = &vsc85xx_wol_get,
2294         .get_tunable    = &vsc85xx_get_tunable,
2295         .set_tunable    = &vsc85xx_set_tunable,
2296         .read_page      = &vsc85xx_phy_read_page,
2297         .write_page     = &vsc85xx_phy_write_page,
2298         .get_sset_count = &vsc85xx_get_sset_count,
2299         .get_strings    = &vsc85xx_get_strings,
2300         .get_stats      = &vsc85xx_get_stats,
2301 },
2302 {
2303         .phy_id         = PHY_ID_VSC856X,
2304         .name           = "Microsemi GE VSC856X SyncE",
2305         .phy_id_mask    = 0xfffffff0,
2306         /* PHY_GBIT_FEATURES */
2307         .soft_reset     = &genphy_soft_reset,
2308         .config_init    = &vsc8584_config_init,
2309         .config_aneg    = &vsc85xx_config_aneg,
2310         .read_status    = &vsc85xx_read_status,
2311         .ack_interrupt  = &vsc85xx_ack_interrupt,
2312         .config_intr    = &vsc85xx_config_intr,
2313         .did_interrupt  = &vsc8584_did_interrupt,
2314         .suspend        = &genphy_suspend,
2315         .resume         = &genphy_resume,
2316         .probe          = &vsc8584_probe,
2317         .get_tunable    = &vsc85xx_get_tunable,
2318         .set_tunable    = &vsc85xx_set_tunable,
2319         .read_page      = &vsc85xx_phy_read_page,
2320         .write_page     = &vsc85xx_phy_write_page,
2321         .get_sset_count = &vsc85xx_get_sset_count,
2322         .get_strings    = &vsc85xx_get_strings,
2323         .get_stats      = &vsc85xx_get_stats,
2324 },
2325 {
2326         .phy_id         = PHY_ID_VSC8572,
2327         .name           = "Microsemi GE VSC8572 SyncE",
2328         .phy_id_mask    = 0xfffffff0,
2329         /* PHY_GBIT_FEATURES */
2330         .soft_reset     = &genphy_soft_reset,
2331         .config_init    = &vsc8584_config_init,
2332         .config_aneg    = &vsc85xx_config_aneg,
2333         .aneg_done      = &genphy_aneg_done,
2334         .read_status    = &vsc85xx_read_status,
2335         .handle_interrupt = &vsc8584_handle_interrupt,
2336         .ack_interrupt  = &vsc85xx_ack_interrupt,
2337         .config_intr    = &vsc85xx_config_intr,
2338         .did_interrupt  = &vsc8584_did_interrupt,
2339         .suspend        = &genphy_suspend,
2340         .resume         = &genphy_resume,
2341         .probe          = &vsc8574_probe,
2342         .set_wol        = &vsc85xx_wol_set,
2343         .get_wol        = &vsc85xx_wol_get,
2344         .get_tunable    = &vsc85xx_get_tunable,
2345         .set_tunable    = &vsc85xx_set_tunable,
2346         .read_page      = &vsc85xx_phy_read_page,
2347         .write_page     = &vsc85xx_phy_write_page,
2348         .get_sset_count = &vsc85xx_get_sset_count,
2349         .get_strings    = &vsc85xx_get_strings,
2350         .get_stats      = &vsc85xx_get_stats,
2351 },
2352 {
2353         .phy_id         = PHY_ID_VSC8574,
2354         .name           = "Microsemi GE VSC8574 SyncE",
2355         .phy_id_mask    = 0xfffffff0,
2356         /* PHY_GBIT_FEATURES */
2357         .soft_reset     = &genphy_soft_reset,
2358         .config_init    = &vsc8584_config_init,
2359         .config_aneg    = &vsc85xx_config_aneg,
2360         .aneg_done      = &genphy_aneg_done,
2361         .read_status    = &vsc85xx_read_status,
2362         .ack_interrupt  = &vsc85xx_ack_interrupt,
2363         .config_intr    = &vsc85xx_config_intr,
2364         .did_interrupt  = &vsc8584_did_interrupt,
2365         .suspend        = &genphy_suspend,
2366         .resume         = &genphy_resume,
2367         .probe          = &vsc8574_probe,
2368         .set_wol        = &vsc85xx_wol_set,
2369         .get_wol        = &vsc85xx_wol_get,
2370         .get_tunable    = &vsc85xx_get_tunable,
2371         .set_tunable    = &vsc85xx_set_tunable,
2372         .read_page      = &vsc85xx_phy_read_page,
2373         .write_page     = &vsc85xx_phy_write_page,
2374         .get_sset_count = &vsc85xx_get_sset_count,
2375         .get_strings    = &vsc85xx_get_strings,
2376         .get_stats      = &vsc85xx_get_stats,
2377 },
2378 {
2379         .phy_id         = PHY_ID_VSC8575,
2380         .name           = "Microsemi GE VSC8575 SyncE",
2381         .phy_id_mask    = 0xfffffff0,
2382         /* PHY_GBIT_FEATURES */
2383         .soft_reset     = &genphy_soft_reset,
2384         .config_init    = &vsc8584_config_init,
2385         .config_aneg    = &vsc85xx_config_aneg,
2386         .aneg_done      = &genphy_aneg_done,
2387         .read_status    = &vsc85xx_read_status,
2388         .handle_interrupt = &vsc8584_handle_interrupt,
2389         .ack_interrupt  = &vsc85xx_ack_interrupt,
2390         .config_intr    = &vsc85xx_config_intr,
2391         .did_interrupt  = &vsc8584_did_interrupt,
2392         .suspend        = &genphy_suspend,
2393         .resume         = &genphy_resume,
2394         .probe          = &vsc8584_probe,
2395         .get_tunable    = &vsc85xx_get_tunable,
2396         .set_tunable    = &vsc85xx_set_tunable,
2397         .read_page      = &vsc85xx_phy_read_page,
2398         .write_page     = &vsc85xx_phy_write_page,
2399         .get_sset_count = &vsc85xx_get_sset_count,
2400         .get_strings    = &vsc85xx_get_strings,
2401         .get_stats      = &vsc85xx_get_stats,
2402 },
2403 {
2404         .phy_id         = PHY_ID_VSC8582,
2405         .name           = "Microsemi GE VSC8582 SyncE",
2406         .phy_id_mask    = 0xfffffff0,
2407         /* PHY_GBIT_FEATURES */
2408         .soft_reset     = &genphy_soft_reset,
2409         .config_init    = &vsc8584_config_init,
2410         .config_aneg    = &vsc85xx_config_aneg,
2411         .aneg_done      = &genphy_aneg_done,
2412         .read_status    = &vsc85xx_read_status,
2413         .handle_interrupt = &vsc8584_handle_interrupt,
2414         .ack_interrupt  = &vsc85xx_ack_interrupt,
2415         .config_intr    = &vsc85xx_config_intr,
2416         .did_interrupt  = &vsc8584_did_interrupt,
2417         .suspend        = &genphy_suspend,
2418         .resume         = &genphy_resume,
2419         .probe          = &vsc8584_probe,
2420         .get_tunable    = &vsc85xx_get_tunable,
2421         .set_tunable    = &vsc85xx_set_tunable,
2422         .read_page      = &vsc85xx_phy_read_page,
2423         .write_page     = &vsc85xx_phy_write_page,
2424         .get_sset_count = &vsc85xx_get_sset_count,
2425         .get_strings    = &vsc85xx_get_strings,
2426         .get_stats      = &vsc85xx_get_stats,
2427 },
2428 {
2429         .phy_id         = PHY_ID_VSC8584,
2430         .name           = "Microsemi GE VSC8584 SyncE",
2431         .phy_id_mask    = 0xfffffff0,
2432         /* PHY_GBIT_FEATURES */
2433         .soft_reset     = &genphy_soft_reset,
2434         .config_init    = &vsc8584_config_init,
2435         .config_aneg    = &vsc85xx_config_aneg,
2436         .aneg_done      = &genphy_aneg_done,
2437         .read_status    = &vsc85xx_read_status,
2438         .handle_interrupt = &vsc8584_handle_interrupt,
2439         .ack_interrupt  = &vsc85xx_ack_interrupt,
2440         .config_intr    = &vsc85xx_config_intr,
2441         .did_interrupt  = &vsc8584_did_interrupt,
2442         .suspend        = &genphy_suspend,
2443         .resume         = &genphy_resume,
2444         .probe          = &vsc8584_probe,
2445         .get_tunable    = &vsc85xx_get_tunable,
2446         .set_tunable    = &vsc85xx_set_tunable,
2447         .read_page      = &vsc85xx_phy_read_page,
2448         .write_page     = &vsc85xx_phy_write_page,
2449         .get_sset_count = &vsc85xx_get_sset_count,
2450         .get_strings    = &vsc85xx_get_strings,
2451         .get_stats      = &vsc85xx_get_stats,
2452         .link_change_notify = &vsc85xx_link_change_notify,
2453 }
2454
2455 };
2456
2457 module_phy_driver(vsc85xx_driver);
2458
2459 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2460         { PHY_ID_VSC8504, 0xfffffff0, },
2461         { PHY_ID_VSC8514, 0xfffffff0, },
2462         { PHY_ID_VSC8530, 0xfffffff0, },
2463         { PHY_ID_VSC8531, 0xfffffff0, },
2464         { PHY_ID_VSC8540, 0xfffffff0, },
2465         { PHY_ID_VSC8541, 0xfffffff0, },
2466         { PHY_ID_VSC8552, 0xfffffff0, },
2467         { PHY_ID_VSC856X, 0xfffffff0, },
2468         { PHY_ID_VSC8572, 0xfffffff0, },
2469         { PHY_ID_VSC8574, 0xfffffff0, },
2470         { PHY_ID_VSC8575, 0xfffffff0, },
2471         { PHY_ID_VSC8582, 0xfffffff0, },
2472         { PHY_ID_VSC8584, 0xfffffff0, },
2473         { }
2474 };
2475
2476 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2477
2478 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2479 MODULE_AUTHOR("Nagaraju Lakkaraju");
2480 MODULE_LICENSE("Dual MIT/GPL");