1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for Microsemi VSC85xx PHYs
5 * Author: Nagaraju Lakkaraju
6 * License: Dual MIT/GPL
7 * Copyright (c) 2016 Microsemi Corporation
10 #include <linux/firmware.h>
11 #include <linux/jiffies.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mdio.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
18 #include <linux/netdevice.h>
19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
25 .string = "phy_receive_errors",
26 .reg = MSCC_PHY_ERR_RX_CNT,
27 .page = MSCC_PHY_PAGE_STANDARD,
30 .string = "phy_false_carrier",
31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
32 .page = MSCC_PHY_PAGE_STANDARD,
35 .string = "phy_cu_media_link_disconnect",
36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
37 .page = MSCC_PHY_PAGE_STANDARD,
40 .string = "phy_cu_media_crc_good_count",
41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
42 .page = MSCC_PHY_PAGE_EXTENDED,
43 .mask = VALID_CRC_CNT_CRC_MASK,
45 .string = "phy_cu_media_crc_error_count",
46 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
47 .page = MSCC_PHY_PAGE_EXTENDED,
52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
54 .string = "phy_receive_errors",
55 .reg = MSCC_PHY_ERR_RX_CNT,
56 .page = MSCC_PHY_PAGE_STANDARD,
59 .string = "phy_false_carrier",
60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
61 .page = MSCC_PHY_PAGE_STANDARD,
64 .string = "phy_cu_media_link_disconnect",
65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
66 .page = MSCC_PHY_PAGE_STANDARD,
69 .string = "phy_cu_media_crc_good_count",
70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
71 .page = MSCC_PHY_PAGE_EXTENDED,
72 .mask = VALID_CRC_CNT_CRC_MASK,
74 .string = "phy_cu_media_crc_error_count",
75 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
76 .page = MSCC_PHY_PAGE_EXTENDED,
79 .string = "phy_serdes_tx_good_pkt_count",
80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT,
81 .page = MSCC_PHY_PAGE_EXTENDED_3,
82 .mask = VALID_CRC_CNT_CRC_MASK,
84 .string = "phy_serdes_tx_bad_crc_count",
85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
86 .page = MSCC_PHY_PAGE_EXTENDED_3,
89 .string = "phy_serdes_rx_good_pkt_count",
90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT,
91 .page = MSCC_PHY_PAGE_EXTENDED_3,
92 .mask = VALID_CRC_CNT_CRC_MASK,
94 .string = "phy_serdes_rx_bad_crc_count",
95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
96 .page = MSCC_PHY_PAGE_EXTENDED_3,
101 #if IS_ENABLED(CONFIG_OF_MDIO)
102 static const struct vsc8531_edge_rate_table edge_table[] = {
103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
122 struct vsc8531_private *priv = phydev->priv;
130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
132 struct vsc8531_private *priv = phydev->priv;
138 for (i = 0; i < priv->nstats; i++)
139 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
145 struct vsc8531_private *priv = phydev->priv;
148 val = phy_read_paged(phydev, priv->hw_stats[i].page,
149 priv->hw_stats[i].reg);
153 val = val & priv->hw_stats[i].mask;
154 priv->stats[i] += val;
156 return priv->stats[i];
159 static void vsc85xx_get_stats(struct phy_device *phydev,
160 struct ethtool_stats *stats, u64 *data)
162 struct vsc8531_private *priv = phydev->priv;
168 for (i = 0; i < priv->nstats; i++)
169 data[i] = vsc85xx_get_stat(phydev, i);
172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
179 mutex_lock(&phydev->lock);
180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
181 reg_val &= ~LED_MODE_SEL_MASK(led_num);
182 reg_val |= LED_MODE_SEL(led_num, (u16)mode);
183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
184 mutex_unlock(&phydev->lock);
189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
194 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
195 *mdix = ETH_TP_MDI_X;
202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
208 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
209 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
210 DISABLE_POLARITY_CORR_MASK |
211 DISABLE_HP_AUTO_MDIX_MASK);
213 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
214 DISABLE_POLARITY_CORR_MASK |
215 DISABLE_HP_AUTO_MDIX_MASK);
217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
223 if (mdix == ETH_TP_MDI)
224 reg_val = FORCE_MDI_CROSSOVER_MDI;
225 else if (mdix == ETH_TP_MDI_X)
226 reg_val = FORCE_MDI_CROSSOVER_MDIX;
228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
229 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
234 return genphy_restart_aneg(phydev);
237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
242 MSCC_PHY_ACTIPHY_CNTL);
246 reg_val &= DOWNSHIFT_CNTL_MASK;
247 if (!(reg_val & DOWNSHIFT_EN))
248 *count = DOWNSHIFT_DEV_DISABLE;
250 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
257 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
258 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
259 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
260 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
264 /* Downshift count is either 2,3,4 or 5 */
265 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
269 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
273 static int vsc85xx_wol_set(struct phy_device *phydev,
274 struct ethtool_wolinfo *wol)
279 u16 pwd[3] = {0, 0, 0};
280 struct ethtool_wolinfo *wol_conf = wol;
281 u8 *mac_addr = phydev->attached_dev->dev_addr;
283 mutex_lock(&phydev->lock);
284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
286 rc = phy_restore_page(phydev, rc, rc);
290 if (wol->wolopts & WAKE_MAGIC) {
291 /* Store the device address for the magic packet */
292 for (i = 0; i < ARRAY_SIZE(pwd); i++)
293 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
304 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
305 for (i = 0; i < ARRAY_SIZE(pwd); i++)
306 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
307 wol_conf->sopass[5 - i * 2];
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
318 if (wol_conf->wolopts & WAKE_MAGICSECURE)
319 reg_val |= SECURE_ON_ENABLE;
321 reg_val &= ~SECURE_ON_ENABLE;
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
328 if (wol->wolopts & WAKE_MAGIC) {
329 /* Enable the WOL interrupt */
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
331 reg_val |= MII_VSC85XX_INT_MASK_WOL;
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
336 /* Disable the WOL interrupt */
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
338 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
343 /* Clear WOL iterrupt status */
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
347 mutex_unlock(&phydev->lock);
352 static void vsc85xx_wol_get(struct phy_device *phydev,
353 struct ethtool_wolinfo *wol)
358 u16 pwd[3] = {0, 0, 0};
359 struct ethtool_wolinfo *wol_conf = wol;
361 mutex_lock(&phydev->lock);
362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
367 if (reg_val & SECURE_ON_ENABLE)
368 wol_conf->wolopts |= WAKE_MAGICSECURE;
369 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
373 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
374 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
375 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
382 mutex_unlock(&phydev->lock);
385 #if IS_ENABLED(CONFIG_OF_MDIO)
386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
390 struct device *dev = &phydev->mdio.dev;
391 struct device_node *of_node = dev->of_node;
392 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
397 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
398 vdd = MSCC_VDDMAC_3300;
400 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
403 for (i = 0; i < ARRAY_SIZE(edge_table); i++)
404 if (edge_table[i].vddmac == vdd)
405 for (j = 0; j < sd_array_size; j++)
406 if (edge_table[i].slowdown[j] == sd)
407 return (sd_array_size - j - 1);
412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
416 struct vsc8531_private *priv = phydev->priv;
417 struct device *dev = &phydev->mdio.dev;
418 struct device_node *of_node = dev->of_node;
425 led_mode = default_mode;
426 err = of_property_read_u32(of_node, led, &led_mode);
427 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
428 phydev_err(phydev, "DT %s invalid\n", led);
436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
447 #endif /* CONFIG_OF_MDIO */
449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
452 struct vsc8531_private *priv = phydev->priv;
453 char led_dt_prop[28];
456 for (i = 0; i < priv->nleds; i++) {
457 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
465 priv->leds_mode[i] = ret;
471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
475 mutex_lock(&phydev->lock);
476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
477 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
478 edge_rate << EDGE_RATE_CNTL_POS);
479 mutex_unlock(&phydev->lock);
484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
485 phy_interface_t interface)
490 mutex_lock(&phydev->lock);
491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
492 reg_val &= ~(MAC_IF_SELECTION_MASK);
494 case PHY_INTERFACE_MODE_RGMII_TXID:
495 case PHY_INTERFACE_MODE_RGMII_RXID:
496 case PHY_INTERFACE_MODE_RGMII_ID:
497 case PHY_INTERFACE_MODE_RGMII:
498 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
500 case PHY_INTERFACE_MODE_RMII:
501 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
503 case PHY_INTERFACE_MODE_MII:
504 case PHY_INTERFACE_MODE_GMII:
505 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
515 rc = genphy_soft_reset(phydev);
518 mutex_unlock(&phydev->lock);
523 /* Set the RGMII RX and TX clock skews individually, according to the PHY
524 * interface type, to:
525 * * 0.2 ns (their default, and lowest, hardware value) if delays should
527 * * 2.0 ns (which causes the data to be sampled at exactly half way between
528 * clock transitions at 1000 Mbps) if delays should be enabled
530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
531 u16 rgmii_rx_delay_mask,
532 u16 rgmii_tx_delay_mask)
534 u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
535 u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
539 mutex_lock(&phydev->lock);
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
542 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
543 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
545 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
546 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
548 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
550 rgmii_rx_delay_mask | rgmii_tx_delay_mask,
553 mutex_unlock(&phydev->lock);
558 static int vsc85xx_default_config(struct phy_device *phydev)
562 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
564 if (phy_interface_mode_is_rgmii(phydev->interface)) {
565 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL,
566 VSC8502_RGMII_RX_DELAY_MASK,
567 VSC8502_RGMII_TX_DELAY_MASK);
575 static int vsc85xx_get_tunable(struct phy_device *phydev,
576 struct ethtool_tunable *tuna, void *data)
579 case ETHTOOL_PHY_DOWNSHIFT:
580 return vsc85xx_downshift_get(phydev, (u8 *)data);
586 static int vsc85xx_set_tunable(struct phy_device *phydev,
587 struct ethtool_tunable *tuna,
591 case ETHTOOL_PHY_DOWNSHIFT:
592 return vsc85xx_downshift_set(phydev, *(u8 *)data);
598 /* mdiobus lock should be locked when using this function */
599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
601 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
602 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
603 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
609 static const struct reg_val init_seq[] = {
610 {0x0f90, 0x00688980},
611 {0x0696, 0x00000003},
612 {0x07fa, 0x0050100f},
613 {0x1686, 0x00000004},
618 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
619 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
620 SMI_BROADCAST_WR_EN);
623 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
624 MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
628 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
632 MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
636 mutex_lock(&phydev->lock);
637 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
641 for (i = 0; i < ARRAY_SIZE(init_seq); i++)
642 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
645 oldpage = phy_restore_page(phydev, oldpage, oldpage);
646 mutex_unlock(&phydev->lock);
651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
653 static const struct reg_val init_eee[] = {
654 {0x0f82, 0x0012b00a},
655 {0x1686, 0x00000004},
656 {0x168c, 0x00d2c46f},
657 {0x17a2, 0x00000620},
658 {0x16a0, 0x00eeffdd},
659 {0x16a6, 0x00071448},
660 {0x16a4, 0x0013132f},
661 {0x16a8, 0x00000000},
662 {0x0ffc, 0x00c0a028},
663 {0x0fe8, 0x0091b06c},
664 {0x0fea, 0x00041600},
665 {0x0f80, 0x00000af4},
666 {0x0fec, 0x00901809},
667 {0x0fee, 0x0000a6a1},
668 {0x0ffe, 0x00b01007},
669 {0x16b0, 0x00eeff00},
670 {0x16b2, 0x00007000},
671 {0x16b4, 0x00000814},
676 mutex_lock(&phydev->lock);
677 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
681 for (i = 0; i < ARRAY_SIZE(init_eee); i++)
682 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
685 oldpage = phy_restore_page(phydev, oldpage, oldpage);
686 mutex_unlock(&phydev->lock);
691 /* phydev->bus->mdio_lock should be locked when using this function */
692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
694 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
695 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
699 return __phy_package_write(phydev, regnum, val);
702 /* phydev->bus->mdio_lock should be locked when using this function */
703 static int phy_base_read(struct phy_device *phydev, u32 regnum)
705 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
706 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
710 return __phy_package_read(phydev, regnum);
713 /* bus->mdio_lock should be locked when using this function */
714 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
716 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
717 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
718 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
721 /* bus->mdio_lock should be locked when using this function */
722 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
724 unsigned long deadline;
727 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
728 MSCC_PHY_PAGE_EXTENDED_GPIO);
730 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
732 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
734 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
735 } while (time_before(jiffies, deadline) &&
736 (reg_val & PROC_CMD_NCOMPLETED) &&
737 !(reg_val & PROC_CMD_FAILED));
739 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
741 if (reg_val & PROC_CMD_FAILED)
744 if (reg_val & PROC_CMD_NCOMPLETED)
750 /* bus->mdio_lock should be locked when using this function */
751 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
756 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
757 MSCC_PHY_PAGE_EXTENDED_GPIO);
759 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
760 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
764 enable |= MICRO_PATCH_EN;
765 release |= MICRO_PATCH_EN;
767 /* Clear all patches */
768 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
771 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
772 * override and addr. auto-incr; operate at 125 MHz
774 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
775 /* Release 8051 Micro SW reset */
776 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
778 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
783 /* bus->mdio_lock should be locked when using this function */
784 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
789 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
793 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
794 MSCC_PHY_PAGE_EXTENDED_GPIO);
796 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
797 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
798 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
800 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
801 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
803 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
804 reg |= EN_PATCH_RAM_TRAP_ADDR(4);
805 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
807 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
809 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
810 reg &= ~MICRO_NSOFT_RESET;
811 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
813 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
814 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
817 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
818 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
819 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
821 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
826 /* bus->mdio_lock should be locked when using this function */
827 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
832 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
834 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
835 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
837 /* Start Micro command */
838 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
842 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
844 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
847 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
852 /* bus->mdio_lock should be locked when using this function */
853 static int vsc8584_patch_fw(struct phy_device *phydev,
854 const struct firmware *fw)
858 ret = vsc8584_micro_assert_reset(phydev);
860 dev_err(&phydev->mdio.dev,
861 "%s: failed to assert reset of micro\n", __func__);
865 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
866 MSCC_PHY_PAGE_EXTENDED_GPIO);
868 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
869 * Disable the 8051 Micro clock
871 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
872 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
873 MICRO_CLK_DIVIDE(2));
874 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
876 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
878 for (i = 0; i < fw->size; i++)
879 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
880 INT_MEM_WRITE_EN | fw->data[i]);
882 /* Clear internal memory access */
883 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
885 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
890 /* bus->mdio_lock should be locked when using this function */
891 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
896 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
897 MSCC_PHY_PAGE_EXTENDED_GPIO);
899 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
905 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
911 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
912 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
917 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
918 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
919 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
926 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
931 /* bus->mdio_lock should be locked when using this function */
932 static int vsc8574_config_pre_init(struct phy_device *phydev)
934 static const struct reg_val pre_init1[] = {
935 {0x0fae, 0x000401bd},
936 {0x0fac, 0x000f000f},
937 {0x17a0, 0x00a0f147},
938 {0x0fe4, 0x00052f54},
939 {0x1792, 0x0027303d},
940 {0x07fe, 0x00000704},
941 {0x0fe0, 0x00060150},
942 {0x0f82, 0x0012b00a},
943 {0x0f80, 0x00000d74},
944 {0x02e0, 0x00000012},
945 {0x03a2, 0x00050208},
946 {0x03b2, 0x00009186},
947 {0x0fb0, 0x000e3700},
948 {0x1688, 0x00049f81},
949 {0x0fd2, 0x0000ffff},
950 {0x168a, 0x00039fa2},
951 {0x1690, 0x0020640b},
952 {0x0258, 0x00002220},
953 {0x025a, 0x00002a20},
954 {0x025c, 0x00003060},
955 {0x025e, 0x00003fa0},
956 {0x03a6, 0x0000e0f0},
957 {0x0f92, 0x00001489},
958 {0x16a2, 0x00007000},
959 {0x16a6, 0x00071448},
960 {0x16a0, 0x00eeffdd},
961 {0x0fe8, 0x0091b06c},
962 {0x0fea, 0x00041600},
963 {0x16b0, 0x00eeff00},
964 {0x16b2, 0x00007000},
965 {0x16b4, 0x00000814},
966 {0x0f90, 0x00688980},
967 {0x03a4, 0x0000d8f0},
968 {0x0fc0, 0x00000400},
969 {0x07fa, 0x0050100f},
970 {0x0796, 0x00000003},
971 {0x07f8, 0x00c3ff98},
972 {0x0fa4, 0x0018292a},
973 {0x168c, 0x00d2c46f},
974 {0x17a2, 0x00000620},
975 {0x16a4, 0x0013132f},
976 {0x16a8, 0x00000000},
977 {0x0ffc, 0x00c0a028},
978 {0x0fec, 0x00901c09},
979 {0x0fee, 0x0004a6a1},
980 {0x0ffe, 0x00b01807},
982 static const struct reg_val pre_init2[] = {
983 {0x0486, 0x0008a518},
984 {0x0488, 0x006dc696},
985 {0x048a, 0x00000912},
986 {0x048e, 0x00000db6},
987 {0x049c, 0x00596596},
988 {0x049e, 0x00000514},
989 {0x04a2, 0x00410280},
990 {0x04a4, 0x00000000},
991 {0x04a6, 0x00000000},
992 {0x04a8, 0x00000000},
993 {0x04aa, 0x00000000},
994 {0x04ae, 0x007df7dd},
995 {0x04b0, 0x006d95d4},
996 {0x04b2, 0x00492410},
998 struct device *dev = &phydev->mdio.dev;
999 const struct firmware *fw;
1005 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1007 /* all writes below are broadcasted to all PHYs in the same package */
1008 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1009 reg |= SMI_BROADCAST_WR_EN;
1010 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1012 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1014 /* The below register writes are tweaking analog and electrical
1015 * configuration that were determined through characterization by PHY
1016 * engineers. These don't mean anything more than "these are the best
1019 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1021 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1023 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1024 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1025 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1026 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1028 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1029 reg |= TR_CLK_DISABLE;
1030 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1032 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1034 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1035 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1037 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1039 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1041 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1043 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1044 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1046 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1048 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1049 reg &= ~TR_CLK_DISABLE;
1050 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1052 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1054 /* end of write broadcasting */
1055 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1056 reg &= ~SMI_BROADCAST_WR_EN;
1057 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1059 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1061 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1062 MSCC_VSC8574_REVB_INT8051_FW, ret);
1066 /* Add one byte to size for the one added by the patch_fw function */
1067 ret = vsc8584_get_fw_crc(phydev,
1068 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1069 fw->size + 1, &crc);
1073 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1074 serdes_init = vsc8574_is_serdes_init(phydev);
1077 ret = vsc8584_micro_assert_reset(phydev);
1080 "%s: failed to assert reset of micro\n",
1086 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1088 serdes_init = false;
1090 if (vsc8584_patch_fw(phydev, fw))
1092 "failed to patch FW, expect non-optimal device\n");
1096 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1097 MSCC_PHY_PAGE_EXTENDED_GPIO);
1099 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1100 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1101 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1102 EN_PATCH_RAM_TRAP_ADDR(1));
1104 vsc8584_micro_deassert_reset(phydev, false);
1106 /* Add one byte to size for the one added by the patch_fw
1109 ret = vsc8584_get_fw_crc(phydev,
1110 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1111 fw->size + 1, &crc);
1115 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1117 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1120 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1121 MSCC_PHY_PAGE_EXTENDED_GPIO);
1123 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1127 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1129 release_firmware(fw);
1134 /* bus->mdio_lock should be locked when using this function */
1135 static int vsc8584_config_pre_init(struct phy_device *phydev)
1137 static const struct reg_val pre_init1[] = {
1138 {0x07fa, 0x0050100f},
1139 {0x1688, 0x00049f81},
1140 {0x0f90, 0x00688980},
1141 {0x03a4, 0x0000d8f0},
1142 {0x0fc0, 0x00000400},
1143 {0x0f82, 0x0012b002},
1144 {0x1686, 0x00000004},
1145 {0x168c, 0x00d2c46f},
1146 {0x17a2, 0x00000620},
1147 {0x16a0, 0x00eeffdd},
1148 {0x16a6, 0x00071448},
1149 {0x16a4, 0x0013132f},
1150 {0x16a8, 0x00000000},
1151 {0x0ffc, 0x00c0a028},
1152 {0x0fe8, 0x0091b06c},
1153 {0x0fea, 0x00041600},
1154 {0x0f80, 0x00fffaff},
1155 {0x0fec, 0x00901809},
1156 {0x0ffe, 0x00b01007},
1157 {0x16b0, 0x00eeff00},
1158 {0x16b2, 0x00007000},
1159 {0x16b4, 0x00000814},
1161 static const struct reg_val pre_init2[] = {
1162 {0x0486, 0x0008a518},
1163 {0x0488, 0x006dc696},
1164 {0x048a, 0x00000912},
1166 const struct firmware *fw;
1167 struct device *dev = &phydev->mdio.dev;
1172 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1174 /* all writes below are broadcasted to all PHYs in the same package */
1175 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1176 reg |= SMI_BROADCAST_WR_EN;
1177 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1179 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1181 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1182 reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1183 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1185 /* The below register writes are tweaking analog and electrical
1186 * configuration that were determined through characterization by PHY
1187 * engineers. These don't mean anything more than "these are the best
1190 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1192 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1194 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1196 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1198 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1199 reg |= TR_CLK_DISABLE;
1200 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1202 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1204 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1206 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1209 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1211 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1213 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1214 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1216 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1218 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1220 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1222 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1223 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1225 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1227 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1228 reg &= ~TR_CLK_DISABLE;
1229 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1231 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1233 /* end of write broadcasting */
1234 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1235 reg &= ~SMI_BROADCAST_WR_EN;
1236 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1238 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1240 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1241 MSCC_VSC8584_REVB_INT8051_FW, ret);
1245 /* Add one byte to size for the one added by the patch_fw function */
1246 ret = vsc8584_get_fw_crc(phydev,
1247 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1248 fw->size + 1, &crc);
1252 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1253 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1254 if (vsc8584_patch_fw(phydev, fw))
1256 "failed to patch FW, expect non-optimal device\n");
1259 vsc8584_micro_deassert_reset(phydev, false);
1261 /* Add one byte to size for the one added by the patch_fw function */
1262 ret = vsc8584_get_fw_crc(phydev,
1263 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1264 fw->size + 1, &crc);
1268 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1270 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1272 ret = vsc8584_micro_assert_reset(phydev);
1276 vsc8584_micro_deassert_reset(phydev, true);
1279 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1281 release_firmware(fw);
1286 static void vsc8584_get_base_addr(struct phy_device *phydev)
1288 struct vsc8531_private *vsc8531 = phydev->priv;
1291 phy_lock_mdio_bus(phydev);
1292 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1294 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1295 addr >>= PHY_CNTL_4_ADDR_POS;
1297 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1299 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1300 phy_unlock_mdio_bus(phydev);
1302 /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1303 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1304 * the base PHY for timestamping operations.
1306 vsc8531->ts_base_addr = phydev->mdio.addr;
1307 vsc8531->ts_base_phy = addr;
1309 if (val & PHY_ADDR_REVERSED) {
1310 vsc8531->base_addr = phydev->mdio.addr + addr;
1312 vsc8531->ts_base_addr += 2;
1313 vsc8531->ts_base_phy += 2;
1316 vsc8531->base_addr = phydev->mdio.addr - addr;
1318 vsc8531->ts_base_addr -= 2;
1319 vsc8531->ts_base_phy -= 2;
1323 vsc8531->addr = addr;
1326 static int vsc8584_config_init(struct phy_device *phydev)
1328 struct vsc8531_private *vsc8531 = phydev->priv;
1332 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1334 phy_lock_mdio_bus(phydev);
1336 /* Some parts of the init sequence are identical for every PHY in the
1337 * package. Some parts are modifying the GPIO register bank which is a
1338 * set of registers that are affecting all PHYs, a few resetting the
1339 * microprocessor common to all PHYs. The CRC check responsible of the
1340 * checking the firmware within the 8051 microprocessor can only be
1341 * accessed via the PHY whose internal address in the package is 0.
1342 * All PHYs' interrupts mask register has to be zeroed before enabling
1343 * any PHY's interrupt in this register.
1344 * For all these reasons, we need to do the init sequence once and only
1345 * once whatever is the first PHY in the package that is initialized and
1346 * do the correct init sequence for all PHYs that are package-critical
1347 * in this pre-init function.
1349 if (phy_package_init_once(phydev)) {
1350 /* The following switch statement assumes that the lowest
1351 * nibble of the phy_id_mask is always 0. This works because
1352 * the lowest nibble of the PHY_ID's below are also 0.
1354 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1356 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1357 case PHY_ID_VSC8504:
1358 case PHY_ID_VSC8552:
1359 case PHY_ID_VSC8572:
1360 case PHY_ID_VSC8574:
1361 ret = vsc8574_config_pre_init(phydev);
1363 case PHY_ID_VSC856X:
1364 case PHY_ID_VSC8575:
1365 case PHY_ID_VSC8582:
1366 case PHY_ID_VSC8584:
1367 ret = vsc8584_config_pre_init(phydev);
1378 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1379 MSCC_PHY_PAGE_EXTENDED_GPIO);
1383 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1384 val &= ~MAC_CFG_MASK;
1385 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1386 val |= MAC_CFG_QSGMII;
1387 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1388 val |= MAC_CFG_SGMII;
1389 } else if (phy_interface_is_rgmii(phydev)) {
1390 val |= MAC_CFG_RGMII;
1396 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1400 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1401 MSCC_PHY_PAGE_STANDARD);
1405 if (!phy_interface_is_rgmii(phydev)) {
1406 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1407 PROC_CMD_READ_MOD_WRITE_PORT;
1408 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1409 val |= PROC_CMD_QSGMII_MAC;
1411 val |= PROC_CMD_SGMII_MAC;
1413 ret = vsc8584_cmd(phydev, val);
1417 usleep_range(10000, 20000);
1420 /* Disable SerDes for 100Base-FX */
1421 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1422 PROC_CMD_FIBER_PORT(vsc8531->addr) |
1423 PROC_CMD_FIBER_DISABLE |
1424 PROC_CMD_READ_MOD_WRITE_PORT |
1425 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1429 /* Disable SerDes for 1000Base-X */
1430 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1431 PROC_CMD_FIBER_PORT(vsc8531->addr) |
1432 PROC_CMD_FIBER_DISABLE |
1433 PROC_CMD_READ_MOD_WRITE_PORT |
1434 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1438 phy_unlock_mdio_bus(phydev);
1440 ret = vsc8584_macsec_init(phydev);
1444 ret = vsc8584_ptp_init(phydev);
1448 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1449 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1450 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1451 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1452 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1456 if (phy_interface_is_rgmii(phydev)) {
1457 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL,
1458 VSC8572_RGMII_RX_DELAY_MASK,
1459 VSC8572_RGMII_TX_DELAY_MASK);
1464 ret = genphy_soft_reset(phydev);
1468 for (i = 0; i < vsc8531->nleds; i++) {
1469 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1477 phy_unlock_mdio_bus(phydev);
1481 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1486 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1490 /* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1491 * irq_status would be 0.
1493 ret = vsc8584_handle_ts_interrupt(phydev);
1494 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1497 if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1498 vsc8584_handle_macsec_interrupt(phydev);
1500 if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1501 phy_mac_interrupt(phydev);
1506 static int vsc85xx_config_init(struct phy_device *phydev)
1509 struct vsc8531_private *vsc8531 = phydev->priv;
1511 rc = vsc85xx_default_config(phydev);
1515 rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1519 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1523 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1524 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1525 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1526 rc = vsc8531_pre_init_seq_set(phydev);
1531 rc = vsc85xx_eee_init_seq_set(phydev);
1535 for (i = 0; i < vsc8531->nleds; i++) {
1536 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1544 static int vsc8584_did_interrupt(struct phy_device *phydev)
1548 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1549 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1551 return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1554 static int vsc8514_config_pre_init(struct phy_device *phydev)
1556 /* These are the settings to override the silicon default
1557 * values to handle hardware performance of PHY. They
1558 * are set at Power-On state and remain until PHY Reset.
1560 static const struct reg_val pre_init1[] = {
1561 {0x0f90, 0x00688980},
1562 {0x0786, 0x00000003},
1563 {0x07fa, 0x0050100f},
1564 {0x0f82, 0x0012b002},
1565 {0x1686, 0x00000004},
1566 {0x168c, 0x00d2c46f},
1567 {0x17a2, 0x00000620},
1568 {0x16a0, 0x00eeffdd},
1569 {0x16a6, 0x00071448},
1570 {0x16a4, 0x0013132f},
1571 {0x16a8, 0x00000000},
1572 {0x0ffc, 0x00c0a028},
1573 {0x0fe8, 0x0091b06c},
1574 {0x0fea, 0x00041600},
1575 {0x0f80, 0x00fffaff},
1576 {0x0fec, 0x00901809},
1577 {0x0ffe, 0x00b01007},
1578 {0x16b0, 0x00eeff00},
1579 {0x16b2, 0x00007000},
1580 {0x16b4, 0x00000814},
1585 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1587 /* all writes below are broadcasted to all PHYs in the same package */
1588 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1589 reg |= SMI_BROADCAST_WR_EN;
1590 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1592 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1594 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1596 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1598 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1600 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1601 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1603 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1605 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1607 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1609 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1611 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1612 reg &= ~SMI_BROADCAST_WR_EN;
1613 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1618 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev,
1619 u32 target, u32 reg)
1621 unsigned long deadline;
1622 u32 val, val_l, val_h;
1624 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1626 /* CSR registers are grouped under different Target IDs.
1627 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1628 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1629 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1630 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1633 /* Setup the Target ID */
1634 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1635 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1637 /* Trigger CSR Action - Read into the CSR's */
1638 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1639 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
1640 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1641 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1643 /* Wait for register access*/
1644 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1646 usleep_range(500, 1000);
1647 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1648 } while (time_before(jiffies, deadline) &&
1649 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1651 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1654 /* Read the Least Significant Word (LSW) (17) */
1655 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
1657 /* Read the Most Significant Word (MSW) (18) */
1658 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
1660 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1661 MSCC_PHY_PAGE_STANDARD);
1663 return (val_h << 16) | val_l;
1666 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev,
1667 u32 target, u32 reg, u32 val)
1669 unsigned long deadline;
1671 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
1673 /* CSR registers are grouped under different Target IDs.
1674 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
1675 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
1676 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
1677 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
1680 /* Setup the Target ID */
1681 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
1682 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
1684 /* Write the Least Significant Word (LSW) (17) */
1685 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
1687 /* Write the Most Significant Word (MSW) (18) */
1688 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
1690 /* Trigger CSR Action - Write into the CSR's */
1691 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
1692 MSCC_PHY_CSR_CNTL_19_CMD |
1693 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
1694 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3));
1696 /* Wait for register access */
1697 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1699 usleep_range(500, 1000);
1700 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
1701 } while (time_before(jiffies, deadline) &&
1702 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
1704 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
1707 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1708 MSCC_PHY_PAGE_STANDARD);
1713 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1716 unsigned long deadline;
1720 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg,
1725 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1727 usleep_range(500, 1000);
1728 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg);
1730 if (val == 0xffffffff)
1733 } while (time_before(jiffies, deadline) && (val & op));
1741 /* Trigger a read to the specified MCB */
1742 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1744 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1747 /* Trigger a write to the specified MCB */
1748 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1750 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1753 static int vsc8514_config_init(struct phy_device *phydev)
1755 struct vsc8531_private *vsc8531 = phydev->priv;
1756 unsigned long deadline;
1761 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1763 phy_lock_mdio_bus(phydev);
1765 /* Some parts of the init sequence are identical for every PHY in the
1766 * package. Some parts are modifying the GPIO register bank which is a
1767 * set of registers that are affecting all PHYs, a few resetting the
1768 * microprocessor common to all PHYs.
1769 * All PHYs' interrupts mask register has to be zeroed before enabling
1770 * any PHY's interrupt in this register.
1771 * For all these reasons, we need to do the init sequence once and only
1772 * once whatever is the first PHY in the package that is initialized and
1773 * do the correct init sequence for all PHYs that are package-critical
1774 * in this pre-init function.
1776 if (phy_package_init_once(phydev))
1777 vsc8514_config_pre_init(phydev);
1779 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1780 MSCC_PHY_PAGE_EXTENDED_GPIO);
1784 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1786 val &= ~MAC_CFG_MASK;
1787 val |= MAC_CFG_QSGMII;
1788 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1792 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1793 MSCC_PHY_PAGE_STANDARD);
1797 ret = vsc8584_cmd(phydev,
1798 PROC_CMD_MCB_ACCESS_MAC_CONF |
1799 PROC_CMD_RST_CONF_PORT |
1800 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1805 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1807 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1809 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1810 PHY_S6G_PLL5G_CFG0, 0x7036f145);
1814 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1816 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1818 (3 << PHY_S6G_PLL_ENA_OFFS_POS) |
1819 (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS)
1820 | (0 << PHY_S6G_PLL_FSM_ENA_POS));
1825 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1827 (0 << PHY_S6G_SYS_RST_POS) |
1828 (0 << PHY_S6G_ENA_LANE_POS) |
1829 (0 << PHY_S6G_ENA_LOOP_POS) |
1830 (0 << PHY_S6G_QRATE_POS) |
1831 (3 << PHY_S6G_IF_MODE_POS));
1836 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1837 PHY_S6G_MISC_CFG, 1);
1842 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1843 PHY_S6G_GPC_CFG, 768);
1847 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
1849 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1851 usleep_range(500, 1000);
1852 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1853 0); /* read 6G MCB into CSRs */
1854 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
1855 PHY_S6G_PLL_STATUS);
1856 if (reg == 0xffffffff) {
1857 phy_unlock_mdio_bus(phydev);
1861 } while (time_before(jiffies, deadline) && (reg & BIT(12)));
1863 if (reg & BIT(12)) {
1864 phy_unlock_mdio_bus(phydev);
1869 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET,
1870 PHY_S6G_MISC_CFG, 0);
1874 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1876 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1878 usleep_range(500, 1000);
1879 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1880 0); /* read 6G MCB into CSRs */
1881 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
1882 PHY_S6G_IB_STATUS0);
1883 if (reg == 0xffffffff) {
1884 phy_unlock_mdio_bus(phydev);
1888 } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
1890 if (!(reg & BIT(8))) {
1891 phy_unlock_mdio_bus(phydev);
1895 phy_unlock_mdio_bus(phydev);
1897 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
1898 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
1903 ret = genphy_soft_reset(phydev);
1908 for (i = 0; i < vsc8531->nleds; i++) {
1909 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1917 phy_unlock_mdio_bus(phydev);
1921 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
1925 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1926 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1928 return (rc < 0) ? rc : 0;
1931 static int vsc85xx_config_intr(struct phy_device *phydev)
1935 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1936 vsc8584_config_macsec_intr(phydev);
1937 vsc8584_config_ts_intr(phydev);
1939 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
1940 MII_VSC85XX_INT_MASK_MASK);
1942 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
1945 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1951 static int vsc85xx_config_aneg(struct phy_device *phydev)
1955 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
1959 return genphy_config_aneg(phydev);
1962 static int vsc85xx_read_status(struct phy_device *phydev)
1966 rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
1970 return genphy_read_status(phydev);
1973 static int vsc8514_probe(struct phy_device *phydev)
1975 struct vsc8531_private *vsc8531;
1976 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1977 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1978 VSC8531_DUPLEX_COLLISION};
1980 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1984 phydev->priv = vsc8531;
1986 vsc8584_get_base_addr(phydev);
1987 devm_phy_package_join(&phydev->mdio.dev, phydev,
1988 vsc8531->base_addr, 0);
1991 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
1992 vsc8531->hw_stats = vsc85xx_hw_stats;
1993 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
1994 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
1995 sizeof(u64), GFP_KERNEL);
1996 if (!vsc8531->stats)
1999 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2002 static int vsc8574_probe(struct phy_device *phydev)
2004 struct vsc8531_private *vsc8531;
2005 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2006 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2007 VSC8531_DUPLEX_COLLISION};
2009 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2013 phydev->priv = vsc8531;
2015 vsc8584_get_base_addr(phydev);
2016 devm_phy_package_join(&phydev->mdio.dev, phydev,
2017 vsc8531->base_addr, 0);
2020 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2021 vsc8531->hw_stats = vsc8584_hw_stats;
2022 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2023 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2024 sizeof(u64), GFP_KERNEL);
2025 if (!vsc8531->stats)
2028 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2031 static int vsc8584_probe(struct phy_device *phydev)
2033 struct vsc8531_private *vsc8531;
2034 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2035 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2036 VSC8531_DUPLEX_COLLISION};
2039 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2040 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2044 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2048 phydev->priv = vsc8531;
2050 vsc8584_get_base_addr(phydev);
2051 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2052 sizeof(struct vsc85xx_shared_private));
2055 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2056 vsc8531->hw_stats = vsc8584_hw_stats;
2057 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2058 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2059 sizeof(u64), GFP_KERNEL);
2060 if (!vsc8531->stats)
2063 if (phy_package_probe_once(phydev)) {
2064 ret = vsc8584_ptp_probe_once(phydev);
2069 ret = vsc8584_ptp_probe(phydev);
2073 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2076 static int vsc85xx_probe(struct phy_device *phydev)
2078 struct vsc8531_private *vsc8531;
2080 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2081 VSC8531_LINK_100_ACTIVITY};
2083 rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2087 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2091 phydev->priv = vsc8531;
2093 vsc8531->rate_magic = rate_magic;
2095 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2096 vsc8531->hw_stats = vsc85xx_hw_stats;
2097 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2098 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2099 sizeof(u64), GFP_KERNEL);
2100 if (!vsc8531->stats)
2103 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2106 /* Microsemi VSC85xx PHYs */
2107 static struct phy_driver vsc85xx_driver[] = {
2109 .phy_id = PHY_ID_VSC8502,
2110 .name = "Microsemi GE VSC8502 SyncE",
2111 .phy_id_mask = 0xfffffff0,
2112 /* PHY_BASIC_FEATURES */
2113 .soft_reset = &genphy_soft_reset,
2114 .config_init = &vsc85xx_config_init,
2115 .config_aneg = &vsc85xx_config_aneg,
2116 .read_status = &vsc85xx_read_status,
2117 .ack_interrupt = &vsc85xx_ack_interrupt,
2118 .config_intr = &vsc85xx_config_intr,
2119 .suspend = &genphy_suspend,
2120 .resume = &genphy_resume,
2121 .probe = &vsc85xx_probe,
2122 .set_wol = &vsc85xx_wol_set,
2123 .get_wol = &vsc85xx_wol_get,
2124 .get_tunable = &vsc85xx_get_tunable,
2125 .set_tunable = &vsc85xx_set_tunable,
2126 .read_page = &vsc85xx_phy_read_page,
2127 .write_page = &vsc85xx_phy_write_page,
2128 .get_sset_count = &vsc85xx_get_sset_count,
2129 .get_strings = &vsc85xx_get_strings,
2130 .get_stats = &vsc85xx_get_stats,
2133 .phy_id = PHY_ID_VSC8504,
2134 .name = "Microsemi GE VSC8504 SyncE",
2135 .phy_id_mask = 0xfffffff0,
2136 /* PHY_GBIT_FEATURES */
2137 .soft_reset = &genphy_soft_reset,
2138 .config_init = &vsc8584_config_init,
2139 .config_aneg = &vsc85xx_config_aneg,
2140 .aneg_done = &genphy_aneg_done,
2141 .read_status = &vsc85xx_read_status,
2142 .ack_interrupt = &vsc85xx_ack_interrupt,
2143 .config_intr = &vsc85xx_config_intr,
2144 .did_interrupt = &vsc8584_did_interrupt,
2145 .suspend = &genphy_suspend,
2146 .resume = &genphy_resume,
2147 .probe = &vsc8574_probe,
2148 .set_wol = &vsc85xx_wol_set,
2149 .get_wol = &vsc85xx_wol_get,
2150 .get_tunable = &vsc85xx_get_tunable,
2151 .set_tunable = &vsc85xx_set_tunable,
2152 .read_page = &vsc85xx_phy_read_page,
2153 .write_page = &vsc85xx_phy_write_page,
2154 .get_sset_count = &vsc85xx_get_sset_count,
2155 .get_strings = &vsc85xx_get_strings,
2156 .get_stats = &vsc85xx_get_stats,
2159 .phy_id = PHY_ID_VSC8514,
2160 .name = "Microsemi GE VSC8514 SyncE",
2161 .phy_id_mask = 0xfffffff0,
2162 .soft_reset = &genphy_soft_reset,
2163 .config_init = &vsc8514_config_init,
2164 .config_aneg = &vsc85xx_config_aneg,
2165 .read_status = &vsc85xx_read_status,
2166 .ack_interrupt = &vsc85xx_ack_interrupt,
2167 .config_intr = &vsc85xx_config_intr,
2168 .suspend = &genphy_suspend,
2169 .resume = &genphy_resume,
2170 .probe = &vsc8514_probe,
2171 .set_wol = &vsc85xx_wol_set,
2172 .get_wol = &vsc85xx_wol_get,
2173 .get_tunable = &vsc85xx_get_tunable,
2174 .set_tunable = &vsc85xx_set_tunable,
2175 .read_page = &vsc85xx_phy_read_page,
2176 .write_page = &vsc85xx_phy_write_page,
2177 .get_sset_count = &vsc85xx_get_sset_count,
2178 .get_strings = &vsc85xx_get_strings,
2179 .get_stats = &vsc85xx_get_stats,
2182 .phy_id = PHY_ID_VSC8530,
2183 .name = "Microsemi FE VSC8530",
2184 .phy_id_mask = 0xfffffff0,
2185 /* PHY_BASIC_FEATURES */
2186 .soft_reset = &genphy_soft_reset,
2187 .config_init = &vsc85xx_config_init,
2188 .config_aneg = &vsc85xx_config_aneg,
2189 .read_status = &vsc85xx_read_status,
2190 .ack_interrupt = &vsc85xx_ack_interrupt,
2191 .config_intr = &vsc85xx_config_intr,
2192 .suspend = &genphy_suspend,
2193 .resume = &genphy_resume,
2194 .probe = &vsc85xx_probe,
2195 .set_wol = &vsc85xx_wol_set,
2196 .get_wol = &vsc85xx_wol_get,
2197 .get_tunable = &vsc85xx_get_tunable,
2198 .set_tunable = &vsc85xx_set_tunable,
2199 .read_page = &vsc85xx_phy_read_page,
2200 .write_page = &vsc85xx_phy_write_page,
2201 .get_sset_count = &vsc85xx_get_sset_count,
2202 .get_strings = &vsc85xx_get_strings,
2203 .get_stats = &vsc85xx_get_stats,
2206 .phy_id = PHY_ID_VSC8531,
2207 .name = "Microsemi VSC8531",
2208 .phy_id_mask = 0xfffffff0,
2209 /* PHY_GBIT_FEATURES */
2210 .soft_reset = &genphy_soft_reset,
2211 .config_init = &vsc85xx_config_init,
2212 .config_aneg = &vsc85xx_config_aneg,
2213 .read_status = &vsc85xx_read_status,
2214 .ack_interrupt = &vsc85xx_ack_interrupt,
2215 .config_intr = &vsc85xx_config_intr,
2216 .suspend = &genphy_suspend,
2217 .resume = &genphy_resume,
2218 .probe = &vsc85xx_probe,
2219 .set_wol = &vsc85xx_wol_set,
2220 .get_wol = &vsc85xx_wol_get,
2221 .get_tunable = &vsc85xx_get_tunable,
2222 .set_tunable = &vsc85xx_set_tunable,
2223 .read_page = &vsc85xx_phy_read_page,
2224 .write_page = &vsc85xx_phy_write_page,
2225 .get_sset_count = &vsc85xx_get_sset_count,
2226 .get_strings = &vsc85xx_get_strings,
2227 .get_stats = &vsc85xx_get_stats,
2230 .phy_id = PHY_ID_VSC8540,
2231 .name = "Microsemi FE VSC8540 SyncE",
2232 .phy_id_mask = 0xfffffff0,
2233 /* PHY_BASIC_FEATURES */
2234 .soft_reset = &genphy_soft_reset,
2235 .config_init = &vsc85xx_config_init,
2236 .config_aneg = &vsc85xx_config_aneg,
2237 .read_status = &vsc85xx_read_status,
2238 .ack_interrupt = &vsc85xx_ack_interrupt,
2239 .config_intr = &vsc85xx_config_intr,
2240 .suspend = &genphy_suspend,
2241 .resume = &genphy_resume,
2242 .probe = &vsc85xx_probe,
2243 .set_wol = &vsc85xx_wol_set,
2244 .get_wol = &vsc85xx_wol_get,
2245 .get_tunable = &vsc85xx_get_tunable,
2246 .set_tunable = &vsc85xx_set_tunable,
2247 .read_page = &vsc85xx_phy_read_page,
2248 .write_page = &vsc85xx_phy_write_page,
2249 .get_sset_count = &vsc85xx_get_sset_count,
2250 .get_strings = &vsc85xx_get_strings,
2251 .get_stats = &vsc85xx_get_stats,
2254 .phy_id = PHY_ID_VSC8541,
2255 .name = "Microsemi VSC8541 SyncE",
2256 .phy_id_mask = 0xfffffff0,
2257 /* PHY_GBIT_FEATURES */
2258 .soft_reset = &genphy_soft_reset,
2259 .config_init = &vsc85xx_config_init,
2260 .config_aneg = &vsc85xx_config_aneg,
2261 .read_status = &vsc85xx_read_status,
2262 .ack_interrupt = &vsc85xx_ack_interrupt,
2263 .config_intr = &vsc85xx_config_intr,
2264 .suspend = &genphy_suspend,
2265 .resume = &genphy_resume,
2266 .probe = &vsc85xx_probe,
2267 .set_wol = &vsc85xx_wol_set,
2268 .get_wol = &vsc85xx_wol_get,
2269 .get_tunable = &vsc85xx_get_tunable,
2270 .set_tunable = &vsc85xx_set_tunable,
2271 .read_page = &vsc85xx_phy_read_page,
2272 .write_page = &vsc85xx_phy_write_page,
2273 .get_sset_count = &vsc85xx_get_sset_count,
2274 .get_strings = &vsc85xx_get_strings,
2275 .get_stats = &vsc85xx_get_stats,
2278 .phy_id = PHY_ID_VSC8552,
2279 .name = "Microsemi GE VSC8552 SyncE",
2280 .phy_id_mask = 0xfffffff0,
2281 /* PHY_GBIT_FEATURES */
2282 .soft_reset = &genphy_soft_reset,
2283 .config_init = &vsc8584_config_init,
2284 .config_aneg = &vsc85xx_config_aneg,
2285 .read_status = &vsc85xx_read_status,
2286 .ack_interrupt = &vsc85xx_ack_interrupt,
2287 .config_intr = &vsc85xx_config_intr,
2288 .did_interrupt = &vsc8584_did_interrupt,
2289 .suspend = &genphy_suspend,
2290 .resume = &genphy_resume,
2291 .probe = &vsc8574_probe,
2292 .set_wol = &vsc85xx_wol_set,
2293 .get_wol = &vsc85xx_wol_get,
2294 .get_tunable = &vsc85xx_get_tunable,
2295 .set_tunable = &vsc85xx_set_tunable,
2296 .read_page = &vsc85xx_phy_read_page,
2297 .write_page = &vsc85xx_phy_write_page,
2298 .get_sset_count = &vsc85xx_get_sset_count,
2299 .get_strings = &vsc85xx_get_strings,
2300 .get_stats = &vsc85xx_get_stats,
2303 .phy_id = PHY_ID_VSC856X,
2304 .name = "Microsemi GE VSC856X SyncE",
2305 .phy_id_mask = 0xfffffff0,
2306 /* PHY_GBIT_FEATURES */
2307 .soft_reset = &genphy_soft_reset,
2308 .config_init = &vsc8584_config_init,
2309 .config_aneg = &vsc85xx_config_aneg,
2310 .read_status = &vsc85xx_read_status,
2311 .ack_interrupt = &vsc85xx_ack_interrupt,
2312 .config_intr = &vsc85xx_config_intr,
2313 .did_interrupt = &vsc8584_did_interrupt,
2314 .suspend = &genphy_suspend,
2315 .resume = &genphy_resume,
2316 .probe = &vsc8584_probe,
2317 .get_tunable = &vsc85xx_get_tunable,
2318 .set_tunable = &vsc85xx_set_tunable,
2319 .read_page = &vsc85xx_phy_read_page,
2320 .write_page = &vsc85xx_phy_write_page,
2321 .get_sset_count = &vsc85xx_get_sset_count,
2322 .get_strings = &vsc85xx_get_strings,
2323 .get_stats = &vsc85xx_get_stats,
2326 .phy_id = PHY_ID_VSC8572,
2327 .name = "Microsemi GE VSC8572 SyncE",
2328 .phy_id_mask = 0xfffffff0,
2329 /* PHY_GBIT_FEATURES */
2330 .soft_reset = &genphy_soft_reset,
2331 .config_init = &vsc8584_config_init,
2332 .config_aneg = &vsc85xx_config_aneg,
2333 .aneg_done = &genphy_aneg_done,
2334 .read_status = &vsc85xx_read_status,
2335 .handle_interrupt = &vsc8584_handle_interrupt,
2336 .ack_interrupt = &vsc85xx_ack_interrupt,
2337 .config_intr = &vsc85xx_config_intr,
2338 .did_interrupt = &vsc8584_did_interrupt,
2339 .suspend = &genphy_suspend,
2340 .resume = &genphy_resume,
2341 .probe = &vsc8574_probe,
2342 .set_wol = &vsc85xx_wol_set,
2343 .get_wol = &vsc85xx_wol_get,
2344 .get_tunable = &vsc85xx_get_tunable,
2345 .set_tunable = &vsc85xx_set_tunable,
2346 .read_page = &vsc85xx_phy_read_page,
2347 .write_page = &vsc85xx_phy_write_page,
2348 .get_sset_count = &vsc85xx_get_sset_count,
2349 .get_strings = &vsc85xx_get_strings,
2350 .get_stats = &vsc85xx_get_stats,
2353 .phy_id = PHY_ID_VSC8574,
2354 .name = "Microsemi GE VSC8574 SyncE",
2355 .phy_id_mask = 0xfffffff0,
2356 /* PHY_GBIT_FEATURES */
2357 .soft_reset = &genphy_soft_reset,
2358 .config_init = &vsc8584_config_init,
2359 .config_aneg = &vsc85xx_config_aneg,
2360 .aneg_done = &genphy_aneg_done,
2361 .read_status = &vsc85xx_read_status,
2362 .ack_interrupt = &vsc85xx_ack_interrupt,
2363 .config_intr = &vsc85xx_config_intr,
2364 .did_interrupt = &vsc8584_did_interrupt,
2365 .suspend = &genphy_suspend,
2366 .resume = &genphy_resume,
2367 .probe = &vsc8574_probe,
2368 .set_wol = &vsc85xx_wol_set,
2369 .get_wol = &vsc85xx_wol_get,
2370 .get_tunable = &vsc85xx_get_tunable,
2371 .set_tunable = &vsc85xx_set_tunable,
2372 .read_page = &vsc85xx_phy_read_page,
2373 .write_page = &vsc85xx_phy_write_page,
2374 .get_sset_count = &vsc85xx_get_sset_count,
2375 .get_strings = &vsc85xx_get_strings,
2376 .get_stats = &vsc85xx_get_stats,
2379 .phy_id = PHY_ID_VSC8575,
2380 .name = "Microsemi GE VSC8575 SyncE",
2381 .phy_id_mask = 0xfffffff0,
2382 /* PHY_GBIT_FEATURES */
2383 .soft_reset = &genphy_soft_reset,
2384 .config_init = &vsc8584_config_init,
2385 .config_aneg = &vsc85xx_config_aneg,
2386 .aneg_done = &genphy_aneg_done,
2387 .read_status = &vsc85xx_read_status,
2388 .handle_interrupt = &vsc8584_handle_interrupt,
2389 .ack_interrupt = &vsc85xx_ack_interrupt,
2390 .config_intr = &vsc85xx_config_intr,
2391 .did_interrupt = &vsc8584_did_interrupt,
2392 .suspend = &genphy_suspend,
2393 .resume = &genphy_resume,
2394 .probe = &vsc8584_probe,
2395 .get_tunable = &vsc85xx_get_tunable,
2396 .set_tunable = &vsc85xx_set_tunable,
2397 .read_page = &vsc85xx_phy_read_page,
2398 .write_page = &vsc85xx_phy_write_page,
2399 .get_sset_count = &vsc85xx_get_sset_count,
2400 .get_strings = &vsc85xx_get_strings,
2401 .get_stats = &vsc85xx_get_stats,
2404 .phy_id = PHY_ID_VSC8582,
2405 .name = "Microsemi GE VSC8582 SyncE",
2406 .phy_id_mask = 0xfffffff0,
2407 /* PHY_GBIT_FEATURES */
2408 .soft_reset = &genphy_soft_reset,
2409 .config_init = &vsc8584_config_init,
2410 .config_aneg = &vsc85xx_config_aneg,
2411 .aneg_done = &genphy_aneg_done,
2412 .read_status = &vsc85xx_read_status,
2413 .handle_interrupt = &vsc8584_handle_interrupt,
2414 .ack_interrupt = &vsc85xx_ack_interrupt,
2415 .config_intr = &vsc85xx_config_intr,
2416 .did_interrupt = &vsc8584_did_interrupt,
2417 .suspend = &genphy_suspend,
2418 .resume = &genphy_resume,
2419 .probe = &vsc8584_probe,
2420 .get_tunable = &vsc85xx_get_tunable,
2421 .set_tunable = &vsc85xx_set_tunable,
2422 .read_page = &vsc85xx_phy_read_page,
2423 .write_page = &vsc85xx_phy_write_page,
2424 .get_sset_count = &vsc85xx_get_sset_count,
2425 .get_strings = &vsc85xx_get_strings,
2426 .get_stats = &vsc85xx_get_stats,
2429 .phy_id = PHY_ID_VSC8584,
2430 .name = "Microsemi GE VSC8584 SyncE",
2431 .phy_id_mask = 0xfffffff0,
2432 /* PHY_GBIT_FEATURES */
2433 .soft_reset = &genphy_soft_reset,
2434 .config_init = &vsc8584_config_init,
2435 .config_aneg = &vsc85xx_config_aneg,
2436 .aneg_done = &genphy_aneg_done,
2437 .read_status = &vsc85xx_read_status,
2438 .handle_interrupt = &vsc8584_handle_interrupt,
2439 .ack_interrupt = &vsc85xx_ack_interrupt,
2440 .config_intr = &vsc85xx_config_intr,
2441 .did_interrupt = &vsc8584_did_interrupt,
2442 .suspend = &genphy_suspend,
2443 .resume = &genphy_resume,
2444 .probe = &vsc8584_probe,
2445 .get_tunable = &vsc85xx_get_tunable,
2446 .set_tunable = &vsc85xx_set_tunable,
2447 .read_page = &vsc85xx_phy_read_page,
2448 .write_page = &vsc85xx_phy_write_page,
2449 .get_sset_count = &vsc85xx_get_sset_count,
2450 .get_strings = &vsc85xx_get_strings,
2451 .get_stats = &vsc85xx_get_stats,
2452 .link_change_notify = &vsc85xx_link_change_notify,
2457 module_phy_driver(vsc85xx_driver);
2459 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2460 { PHY_ID_VSC8504, 0xfffffff0, },
2461 { PHY_ID_VSC8514, 0xfffffff0, },
2462 { PHY_ID_VSC8530, 0xfffffff0, },
2463 { PHY_ID_VSC8531, 0xfffffff0, },
2464 { PHY_ID_VSC8540, 0xfffffff0, },
2465 { PHY_ID_VSC8541, 0xfffffff0, },
2466 { PHY_ID_VSC8552, 0xfffffff0, },
2467 { PHY_ID_VSC856X, 0xfffffff0, },
2468 { PHY_ID_VSC8572, 0xfffffff0, },
2469 { PHY_ID_VSC8574, 0xfffffff0, },
2470 { PHY_ID_VSC8575, 0xfffffff0, },
2471 { PHY_ID_VSC8582, 0xfffffff0, },
2472 { PHY_ID_VSC8584, 0xfffffff0, },
2476 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2478 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2479 MODULE_AUTHOR("Nagaraju Lakkaraju");
2480 MODULE_LICENSE("Dual MIT/GPL");