drivers/net/phy/mscc/mscc_macsec.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs
   4  *
   5  * Author: Nagaraju Lakkaraju
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2016 Microsemi Corporation
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  12
  13 #include <crypto/skcipher.h>
  14
  15 #include <net/macsec.h>
  16
  17 #include "mscc.h"
  18 #include "mscc_mac.h"
  19 #include "mscc_macsec.h"
  20 #include "mscc_fc_buffer.h"
  21
  22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,
  23                                    enum macsec_bank bank, u32 reg)
  24 {
  25         u32 val, val_l = 0, val_h = 0;
  26         unsigned long deadline;
  27         int rc;
  28
  29         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  30         if (rc < 0)
  31                 goto failed;
  32
  33         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  34                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  35
  36         if (bank >> 2 == 0x1)
  37                 /* non-MACsec access */
  38                 bank &= 0x3;
  39         else
  40                 bank = 0;
  41
  42         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  43                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ |
  44                     MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  45                     MSCC_PHY_MACSEC_19_TARGET(bank));
  46
  47         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  48         do {
  49                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  50         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  51
  52         val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17);
  53         val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18);
  54
  55 failed:
  56         phy_restore_page(phydev, rc, rc);
  57
  58         return (val_h << 16) | val_l;
  59 }
  60
  61 static void vsc8584_macsec_phy_write(struct phy_device *phydev,
  62                                      enum macsec_bank bank, u32 reg, u32 val)
  63 {
  64         unsigned long deadline;
  65         int rc;
  66
  67         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  68         if (rc < 0)
  69                 goto failed;
  70
  71         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  72                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  73
  74         if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))
  75                 bank &= 0x3;
  76         else
  77                 /* MACsec access */
  78                 bank = 0;
  79
  80         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
  81         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
  82
  83         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  84                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  85                     MSCC_PHY_MACSEC_19_TARGET(bank));
  86
  87         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  88         do {
  89                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  90         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  91
  92 failed:
  93         phy_restore_page(phydev, rc, rc);
  94 }
  95
  96 static void vsc8584_macsec_classification(struct phy_device *phydev,
  97                                           enum macsec_bank bank)
  98 {
  99         /* enable VLAN tag parsing */
 100         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
 101                                  MSCC_MS_SAM_CP_TAG_PARSE_STAG |
 102                                  MSCC_MS_SAM_CP_TAG_PARSE_QTAG |
 103                                  MSCC_MS_SAM_CP_TAG_PARSE_QINQ);
 104 }
 105
 106 static void vsc8584_macsec_flow_default_action(struct phy_device *phydev,
 107                                                enum macsec_bank bank,
 108                                                bool block)
 109 {
 110         u32 port = (bank == MACSEC_INGR) ?
 111                     MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON;
 112         u32 action = MSCC_MS_FLOW_BYPASS;
 113
 114         if (block)
 115                 action = MSCC_MS_FLOW_DROP;
 116
 117         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
 118                                  /* MACsec untagged */
 119                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 120                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 121                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) |
 122                                  /* MACsec tagged */
 123                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 124                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 125                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) |
 126                                  /* Bad tag */
 127                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 128                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 129                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) |
 130                                  /* Kay tag */
 131                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 132                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 133                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port));
 134         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
 135                                  /* MACsec untagged */
 136                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 137                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 138                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) |
 139                                  /* MACsec tagged */
 140                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 141                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 142                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) |
 143                                  /* Bad tag */
 144                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 145                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 146                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) |
 147                                  /* Kay tag */
 148                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 149                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 150                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port));
 151 }
 152
 153 static void vsc8584_macsec_integrity_checks(struct phy_device *phydev,
 154                                             enum macsec_bank bank)
 155 {
 156         u32 val;
 157
 158         if (bank != MACSEC_INGR)
 159                 return;
 160
 161         /* Set default rules to pass unmatched frames */
 162         val = vsc8584_macsec_phy_read(phydev, bank,
 163                                       MSCC_MS_PARAMS2_IG_CC_CONTROL);
 164         val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT |
 165                MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT;
 166         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
 167                                  val);
 168
 169         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
 170                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG |
 171                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG |
 172                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ);
 173 }
 174
 175 static void vsc8584_macsec_block_init(struct phy_device *phydev,
 176                                       enum macsec_bank bank)
 177 {
 178         u32 val;
 179         int i;
 180
 181         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 182                                  MSCC_MS_ENA_CFG_SW_RST |
 183                                  MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA);
 184
 185         /* Set the MACsec block out of s/w reset and enable clocks */
 186         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 187                                  MSCC_MS_ENA_CFG_CLK_ENA);
 188
 189         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
 190                                  bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);
 191         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
 192                                  MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |
 193                                  MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));
 194
 195         /* Clear the counters */
 196         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 197         val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET;
 198         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 199
 200         /* Enable octet increment mode */
 201         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
 202                                  MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE);
 203
 204         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
 205
 206         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 207         val |= MSCC_MS_COUNT_CONTROL_RESET_ALL;
 208         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 209
 210         /* Set the MTU */
 211         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
 212                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) |
 213                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP);
 214
 215         for (i = 0; i < 8; i++)
 216                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
 217                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) |
 218                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP);
 219
 220         if (bank == MACSEC_EGR) {
 221                 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
 222                 val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M;
 223                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
 224
 225                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
 226                                          MSCC_MS_FC_CFG_FCBUF_ENA |
 227                                          MSCC_MS_FC_CFG_LOW_THRESH(0x1) |
 228                                          MSCC_MS_FC_CFG_HIGH_THRESH(0x4) |
 229                                          MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) |
 230                                          MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6));
 231         }
 232
 233         vsc8584_macsec_classification(phydev, bank);
 234         vsc8584_macsec_flow_default_action(phydev, bank, false);
 235         vsc8584_macsec_integrity_checks(phydev, bank);
 236
 237         /* Enable the MACsec block */
 238         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 239                                  MSCC_MS_ENA_CFG_CLK_ENA |
 240                                  MSCC_MS_ENA_CFG_MACSEC_ENA |
 241                                  MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5));
 242 }
 243
 244 static void vsc8584_macsec_mac_init(struct phy_device *phydev,
 245                                     enum macsec_bank bank)
 246 {
 247         u32 val;
 248         int i;
 249
 250         /* Clear host & line stats */
 251         for (i = 0; i < 36; i++)
 252                 vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
 253
 254         val = vsc8584_macsec_phy_read(phydev, bank,
 255                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL);
 256         val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M;
 257         val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) |
 258                MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff);
 259         vsc8584_macsec_phy_write(phydev, bank,
 260                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val);
 261
 262         val = vsc8584_macsec_phy_read(phydev, bank,
 263                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2);
 264         val |= 0xffff;
 265         vsc8584_macsec_phy_write(phydev, bank,
 266                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val);
 267
 268         val = vsc8584_macsec_phy_read(phydev, bank,
 269                                       MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL);
 270         if (bank == HOST_MAC)
 271                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA |
 272                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA;
 273         else
 274                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA |
 275                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA |
 276                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE |
 277                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA;
 278         vsc8584_macsec_phy_write(phydev, bank,
 279                                  MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val);
 280
 281         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
 282                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA |
 283                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA |
 284                                  MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA |
 285                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
 286                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
 287                                  (bank == HOST_MAC ?
 288                                   MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0));
 289
 290         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
 291         val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
 292         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
 293
 294         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
 295         val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M;
 296         val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240);
 297         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
 298
 299         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
 300                                  MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA |
 301                                  MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA |
 302                                  MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA |
 303                                  MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA);
 304
 305         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
 306         val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA;
 307         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
 308
 309         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
 310                                  MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA |
 311                                  MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA |
 312                                  MSCC_MAC_CFG_ENA_CFG_RX_ENA |
 313                                  MSCC_MAC_CFG_ENA_CFG_TX_ENA);
 314 }
 315
 316 /* Must be called with mdio_lock taken */
 317 static int __vsc8584_macsec_init(struct phy_device *phydev)
 318 {
 319         u32 val;
 320
 321         vsc8584_macsec_block_init(phydev, MACSEC_INGR);
 322         vsc8584_macsec_block_init(phydev, MACSEC_EGR);
 323         vsc8584_macsec_mac_init(phydev, HOST_MAC);
 324         vsc8584_macsec_mac_init(phydev, LINE_MAC);
 325
 326         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 327                                  MSCC_FCBUF_FC_READ_THRESH_CFG,
 328                                  MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) |
 329                                  MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5));
 330
 331         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
 332         val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA |
 333                MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA |
 334                MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA;
 335         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
 336
 337         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,
 338                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) |
 339                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9));
 340
 341         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
 342                                       MSCC_FCBUF_TX_DATA_QUEUE_CFG);
 343         val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M |
 344                  MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M);
 345         val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) |
 346                 MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119);
 347         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 348                                  MSCC_FCBUF_TX_DATA_QUEUE_CFG, val);
 349
 350         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
 351         val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
 352         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
 353
 354         val = vsc8584_macsec_phy_read(phydev, IP_1588,
 355                                       MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL);
 356         val &= ~MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
 357         val |= MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
 358         vsc8584_macsec_phy_write(phydev, IP_1588,
 359                                  MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
 360
 361         return 0;
 362 }
 363
 364 static void vsc8584_macsec_flow(struct phy_device *phydev,
 365                                 struct macsec_flow *flow)
 366 {
 367         struct vsc8531_private *priv = phydev->priv;
 368         enum macsec_bank bank = flow->bank;
 369         u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
 370
 371         if (flow->match.tagged)
 372                 match |= MSCC_MS_SAM_MISC_MATCH_TAGGED;
 373         if (flow->match.untagged)
 374                 match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED;
 375
 376         if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
 377                 match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num);
 378                 mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3);
 379         }
 380
 381         if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
 382                 match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
 383                 mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
 384                         MSCC_MS_SAM_MASK_SCI_MASK;
 385
 386                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
 387                                          lower_32_bits(flow->rx_sa->sc->sci));
 388                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
 389                                          upper_32_bits(flow->rx_sa->sc->sci));
 390         }
 391
 392         if (flow->match.etype) {
 393                 mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
 394
 395                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
 396                                          MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(htons(flow->etype)));
 397         }
 398
 399         match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
 400
 401         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
 402         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
 403
 404         /* Action for matching packets */
 405         if (flow->action.drop)
 406                 action = MSCC_MS_FLOW_DROP;
 407         else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED)
 408                 action = MSCC_MS_FLOW_BYPASS;
 409         else
 410                 action = (bank == MACSEC_INGR) ?
 411                          MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS;
 412
 413         val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
 414               MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 415               MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port);
 416
 417         if (action == MSCC_MS_FLOW_BYPASS)
 418                 goto write_ctrl;
 419
 420         if (bank == MACSEC_INGR) {
 421                 if (priv->secy->replay_protect)
 422                         val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
 423                 if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT)
 424                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
 425                 else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK)
 426                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
 427         } else if (bank == MACSEC_EGR) {
 428                 if (priv->secy->protect_frames)
 429                         val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
 430                 if (priv->secy->tx_sc.encrypt)
 431                         val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
 432                 if (priv->secy->tx_sc.send_sci)
 433                         val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
 434         }
 435
 436 write_ctrl:
 437         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 438 }
 439
 440 static struct macsec_flow *vsc8584_macsec_find_flow(struct macsec_context *ctx,
 441                                                     enum macsec_bank bank)
 442 {
 443         struct vsc8531_private *priv = ctx->phydev->priv;
 444         struct macsec_flow *pos, *tmp;
 445
 446         list_for_each_entry_safe(pos, tmp, &priv->macsec_flows, list)
 447                 if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)
 448                         return pos;
 449
 450         return ERR_PTR(-ENOENT);
 451 }
 452
 453 static void vsc8584_macsec_flow_enable(struct phy_device *phydev,
 454                                        struct macsec_flow *flow)
 455 {
 456         enum macsec_bank bank = flow->bank;
 457         u32 val, idx = flow->index;
 458
 459         if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||
 460             (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))
 461                 return;
 462
 463         /* Enable */
 464         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
 465
 466         /* Set in-use */
 467         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 468         val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 469         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 470 }
 471
 472 static void vsc8584_macsec_flow_disable(struct phy_device *phydev,
 473                                         struct macsec_flow *flow)
 474 {
 475         enum macsec_bank bank = flow->bank;
 476         u32 val, idx = flow->index;
 477
 478         /* Disable */
 479         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
 480
 481         /* Clear in-use */
 482         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 483         val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 484         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 485 }
 486
 487 static u32 vsc8584_macsec_flow_context_id(struct macsec_flow *flow)
 488 {
 489         if (flow->bank == MACSEC_INGR)
 490                 return flow->index + MSCC_MS_MAX_FLOWS;
 491
 492         return flow->index;
 493 }
 494
 495 /* Derive the AES key to get a key for the hash autentication */
 496 static int vsc8584_macsec_derive_key(const u8 key[MACSEC_KEYID_LEN],
 497                                      u16 key_len, u8 hkey[16])
 498 {
 499         struct crypto_skcipher *tfm = crypto_alloc_skcipher("ecb(aes)", 0, 0);
 500         struct skcipher_request *req = NULL;
 501         struct scatterlist src, dst;
 502         DECLARE_CRYPTO_WAIT(wait);
 503         u32 input[4] = {0};
 504         int ret;
 505
 506         if (IS_ERR(tfm))
 507                 return PTR_ERR(tfm);
 508
 509         req = skcipher_request_alloc(tfm, GFP_KERNEL);
 510         if (!req) {
 511                 ret = -ENOMEM;
 512                 goto out;
 513         }
 514
 515         skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
 516                                       CRYPTO_TFM_REQ_MAY_SLEEP, crypto_req_done,
 517                                       &wait);
 518         ret = crypto_skcipher_setkey(tfm, key, key_len);
 519         if (ret < 0)
 520                 goto out;
 521
 522         sg_init_one(&src, input, 16);
 523         sg_init_one(&dst, hkey, 16);
 524         skcipher_request_set_crypt(req, &src, &dst, 16, NULL);
 525
 526         ret = crypto_wait_req(crypto_skcipher_encrypt(req), &wait);
 527
 528 out:
 529         skcipher_request_free(req);
 530         crypto_free_skcipher(tfm);
 531         return ret;
 532 }
 533
 534 static int vsc8584_macsec_transformation(struct phy_device *phydev,
 535                                          struct macsec_flow *flow)
 536 {
 537         struct vsc8531_private *priv = phydev->priv;
 538         enum macsec_bank bank = flow->bank;
 539         int i, ret, index = flow->index;
 540         u32 rec = 0, control = 0;
 541         u8 hkey[16];
 542         sci_t sci;
 543
 544         ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey);
 545         if (ret)
 546                 return ret;
 547
 548         switch (priv->secy->key_len) {
 549         case 16:
 550                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_128);
 551                 break;
 552         case 32:
 553                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_256);
 554                 break;
 555         default:
 556                 return -EINVAL;
 557         }
 558
 559         control |= (bank == MACSEC_EGR) ?
 560                    (CONTROL_TYPE_EGRESS | CONTROL_AN(priv->secy->tx_sc.encoding_sa)) :
 561                    (CONTROL_TYPE_INGRESS | CONTROL_SEQ_MASK);
 562
 563         control |= CONTROL_UPDATE_SEQ | CONTROL_ENCRYPT_AUTH | CONTROL_KEY_IN_CTX |
 564                    CONTROL_IV0 | CONTROL_IV1 | CONTROL_IV_IN_SEQ |
 565                    CONTROL_DIGEST_TYPE(0x2) | CONTROL_SEQ_TYPE(0x1) |
 566                    CONTROL_AUTH_ALG(AUTH_ALG_AES_GHAS) | CONTROL_CONTEXT_ID;
 567
 568         /* Set the control word */
 569         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 570                                  control);
 571
 572         /* Set the context ID. Must be unique. */
 573         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 574                                  vsc8584_macsec_flow_context_id(flow));
 575
 576         /* Set the encryption/decryption key */
 577         for (i = 0; i < priv->secy->key_len / sizeof(u32); i++)
 578                 vsc8584_macsec_phy_write(phydev, bank,
 579                                          MSCC_MS_XFORM_REC(index, rec++),
 580                                          ((u32 *)flow->key)[i]);
 581
 582         /* Set the authentication key */
 583         for (i = 0; i < 4; i++)
 584                 vsc8584_macsec_phy_write(phydev, bank,
 585                                          MSCC_MS_XFORM_REC(index, rec++),
 586                                          ((u32 *)hkey)[i]);
 587
 588         /* Initial sequence number */
 589         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 590                                  bank == MACSEC_INGR ?
 591                                  flow->rx_sa->next_pn : flow->tx_sa->next_pn);
 592
 593         if (bank == MACSEC_INGR)
 594                 /* Set the mask (replay window size) */
 595                 vsc8584_macsec_phy_write(phydev, bank,
 596                                          MSCC_MS_XFORM_REC(index, rec++),
 597                                          priv->secy->replay_window);
 598
 599         /* Set the input vectors */
 600         sci = bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci;
 601         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 602                                  lower_32_bits(sci));
 603         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 604                                  upper_32_bits(sci));
 605
 606         while (rec < 20)
 607                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 608                                          0);
 609
 610         flow->has_transformation = true;
 611         return 0;
 612 }
 613
 614 static struct macsec_flow *vsc8584_macsec_alloc_flow(struct vsc8531_private *priv,
 615                                                      enum macsec_bank bank)
 616 {
 617         unsigned long *bitmap = bank == MACSEC_INGR ?
 618                                 &priv->ingr_flows : &priv->egr_flows;
 619         struct macsec_flow *flow;
 620         int index;
 621
 622         index = find_first_zero_bit(bitmap, MSCC_MS_MAX_FLOWS);
 623
 624         if (index == MSCC_MS_MAX_FLOWS)
 625                 return ERR_PTR(-ENOMEM);
 626
 627         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
 628         if (!flow)
 629                 return ERR_PTR(-ENOMEM);
 630
 631         set_bit(index, bitmap);
 632         flow->index = index;
 633         flow->bank = bank;
 634         flow->priority = 8;
 635         flow->assoc_num = -1;
 636
 637         list_add_tail(&flow->list, &priv->macsec_flows);
 638         return flow;
 639 }
 640
 641 static void vsc8584_macsec_free_flow(struct vsc8531_private *priv,
 642                                      struct macsec_flow *flow)
 643 {
 644         unsigned long *bitmap = flow->bank == MACSEC_INGR ?
 645                                 &priv->ingr_flows : &priv->egr_flows;
 646
 647         list_del(&flow->list);
 648         clear_bit(flow->index, bitmap);
 649         kfree(flow);
 650 }
 651
 652 static int vsc8584_macsec_add_flow(struct phy_device *phydev,
 653                                    struct macsec_flow *flow, bool update)
 654 {
 655         int ret;
 656
 657         flow->port = MSCC_MS_PORT_CONTROLLED;
 658         vsc8584_macsec_flow(phydev, flow);
 659
 660         if (update)
 661                 return 0;
 662
 663         ret = vsc8584_macsec_transformation(phydev, flow);
 664         if (ret) {
 665                 vsc8584_macsec_free_flow(phydev->priv, flow);
 666                 return ret;
 667         }
 668
 669         return 0;
 670 }
 671
 672 static int vsc8584_macsec_default_flows(struct phy_device *phydev)
 673 {
 674         struct macsec_flow *flow;
 675
 676         /* Add a rule to let the MKA traffic go through, ingress */
 677         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR);
 678         if (IS_ERR(flow))
 679                 return PTR_ERR(flow);
 680
 681         flow->priority = 15;
 682         flow->port = MSCC_MS_PORT_UNCONTROLLED;
 683         flow->match.tagged = 1;
 684         flow->match.untagged = 1;
 685         flow->match.etype = 1;
 686         flow->etype = ETH_P_PAE;
 687         flow->action.bypass = 1;
 688
 689         vsc8584_macsec_flow(phydev, flow);
 690         vsc8584_macsec_flow_enable(phydev, flow);
 691
 692         /* Add a rule to let the MKA traffic go through, egress */
 693         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR);
 694         if (IS_ERR(flow))
 695                 return PTR_ERR(flow);
 696
 697         flow->priority = 15;
 698         flow->port = MSCC_MS_PORT_COMMON;
 699         flow->match.untagged = 1;
 700         flow->match.etype = 1;
 701         flow->etype = ETH_P_PAE;
 702         flow->action.bypass = 1;
 703
 704         vsc8584_macsec_flow(phydev, flow);
 705         vsc8584_macsec_flow_enable(phydev, flow);
 706
 707         return 0;
 708 }
 709
 710 static void vsc8584_macsec_del_flow(struct phy_device *phydev,
 711                                     struct macsec_flow *flow)
 712 {
 713         vsc8584_macsec_flow_disable(phydev, flow);
 714         vsc8584_macsec_free_flow(phydev->priv, flow);
 715 }
 716
 717 static int __vsc8584_macsec_add_rxsa(struct macsec_context *ctx,
 718                                      struct macsec_flow *flow, bool update)
 719 {
 720         struct phy_device *phydev = ctx->phydev;
 721         struct vsc8531_private *priv = phydev->priv;
 722
 723         if (!flow) {
 724                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_INGR);
 725                 if (IS_ERR(flow))
 726                         return PTR_ERR(flow);
 727
 728                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 729         }
 730
 731         flow->assoc_num = ctx->sa.assoc_num;
 732         flow->rx_sa = ctx->sa.rx_sa;
 733
 734         /* Always match tagged packets on ingress */
 735         flow->match.tagged = 1;
 736         flow->match.sci = 1;
 737
 738         if (priv->secy->validate_frames != MACSEC_VALIDATE_DISABLED)
 739                 flow->match.untagged = 1;
 740
 741         return vsc8584_macsec_add_flow(phydev, flow, update);
 742 }
 743
 744 static int __vsc8584_macsec_add_txsa(struct macsec_context *ctx,
 745                                      struct macsec_flow *flow, bool update)
 746 {
 747         struct phy_device *phydev = ctx->phydev;
 748         struct vsc8531_private *priv = phydev->priv;
 749
 750         if (!flow) {
 751                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_EGR);
 752                 if (IS_ERR(flow))
 753                         return PTR_ERR(flow);
 754
 755                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 756         }
 757
 758         flow->assoc_num = ctx->sa.assoc_num;
 759         flow->tx_sa = ctx->sa.tx_sa;
 760
 761         /* Always match untagged packets on egress */
 762         flow->match.untagged = 1;
 763
 764         return vsc8584_macsec_add_flow(phydev, flow, update);
 765 }
 766
 767 static int vsc8584_macsec_dev_open(struct macsec_context *ctx)
 768 {
 769         struct vsc8531_private *priv = ctx->phydev->priv;
 770         struct macsec_flow *flow, *tmp;
 771
 772         /* No operation to perform before the commit step */
 773         if (ctx->prepare)
 774                 return 0;
 775
 776         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 777                 vsc8584_macsec_flow_enable(ctx->phydev, flow);
 778
 779         return 0;
 780 }
 781
 782 static int vsc8584_macsec_dev_stop(struct macsec_context *ctx)
 783 {
 784         struct vsc8531_private *priv = ctx->phydev->priv;
 785         struct macsec_flow *flow, *tmp;
 786
 787         /* No operation to perform before the commit step */
 788         if (ctx->prepare)
 789                 return 0;
 790
 791         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 792                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 793
 794         return 0;
 795 }
 796
 797 static int vsc8584_macsec_add_secy(struct macsec_context *ctx)
 798 {
 799         struct vsc8531_private *priv = ctx->phydev->priv;
 800         struct macsec_secy *secy = ctx->secy;
 801
 802         if (ctx->prepare) {
 803                 if (priv->secy)
 804                         return -EEXIST;
 805
 806                 return 0;
 807         }
 808
 809         priv->secy = secy;
 810
 811         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR,
 812                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 813         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR,
 814                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 815
 816         return vsc8584_macsec_default_flows(ctx->phydev);
 817 }
 818
 819 static int vsc8584_macsec_del_secy(struct macsec_context *ctx)
 820 {
 821         struct vsc8531_private *priv = ctx->phydev->priv;
 822         struct macsec_flow *flow, *tmp;
 823
 824         /* No operation to perform before the commit step */
 825         if (ctx->prepare)
 826                 return 0;
 827
 828         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 829                 vsc8584_macsec_del_flow(ctx->phydev, flow);
 830
 831         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false);
 832         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false);
 833
 834         priv->secy = NULL;
 835         return 0;
 836 }
 837
 838 static int vsc8584_macsec_upd_secy(struct macsec_context *ctx)
 839 {
 840         /* No operation to perform before the commit step */
 841         if (ctx->prepare)
 842                 return 0;
 843
 844         vsc8584_macsec_del_secy(ctx);
 845         return vsc8584_macsec_add_secy(ctx);
 846 }
 847
 848 static int vsc8584_macsec_add_rxsc(struct macsec_context *ctx)
 849 {
 850         /* Nothing to do */
 851         return 0;
 852 }
 853
 854 static int vsc8584_macsec_upd_rxsc(struct macsec_context *ctx)
 855 {
 856         return -EOPNOTSUPP;
 857 }
 858
 859 static int vsc8584_macsec_del_rxsc(struct macsec_context *ctx)
 860 {
 861         struct vsc8531_private *priv = ctx->phydev->priv;
 862         struct macsec_flow *flow, *tmp;
 863
 864         /* No operation to perform before the commit step */
 865         if (ctx->prepare)
 866                 return 0;
 867
 868         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
 869                 if (flow->bank == MACSEC_INGR && flow->rx_sa &&
 870                     flow->rx_sa->sc->sci == ctx->rx_sc->sci)
 871                         vsc8584_macsec_del_flow(ctx->phydev, flow);
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int vsc8584_macsec_add_rxsa(struct macsec_context *ctx)
 878 {
 879         struct macsec_flow *flow = NULL;
 880
 881         if (ctx->prepare)
 882                 return __vsc8584_macsec_add_rxsa(ctx, flow, false);
 883
 884         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 885         if (IS_ERR(flow))
 886                 return PTR_ERR(flow);
 887
 888         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 889         return 0;
 890 }
 891
 892 static int vsc8584_macsec_upd_rxsa(struct macsec_context *ctx)
 893 {
 894         struct macsec_flow *flow;
 895
 896         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 897         if (IS_ERR(flow))
 898                 return PTR_ERR(flow);
 899
 900         if (ctx->prepare) {
 901                 /* Make sure the flow is disabled before updating it */
 902                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 903
 904                 return __vsc8584_macsec_add_rxsa(ctx, flow, true);
 905         }
 906
 907         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 908         return 0;
 909 }
 910
 911 static int vsc8584_macsec_del_rxsa(struct macsec_context *ctx)
 912 {
 913         struct macsec_flow *flow;
 914
 915         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 916
 917         if (IS_ERR(flow))
 918                 return PTR_ERR(flow);
 919         if (ctx->prepare)
 920                 return 0;
 921
 922         vsc8584_macsec_del_flow(ctx->phydev, flow);
 923         return 0;
 924 }
 925
 926 static int vsc8584_macsec_add_txsa(struct macsec_context *ctx)
 927 {
 928         struct macsec_flow *flow = NULL;
 929
 930         if (ctx->prepare)
 931                 return __vsc8584_macsec_add_txsa(ctx, flow, false);
 932
 933         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 934         if (IS_ERR(flow))
 935                 return PTR_ERR(flow);
 936
 937         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 938         return 0;
 939 }
 940
 941 static int vsc8584_macsec_upd_txsa(struct macsec_context *ctx)
 942 {
 943         struct macsec_flow *flow;
 944
 945         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 946         if (IS_ERR(flow))
 947                 return PTR_ERR(flow);
 948
 949         if (ctx->prepare) {
 950                 /* Make sure the flow is disabled before updating it */
 951                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 952
 953                 return __vsc8584_macsec_add_txsa(ctx, flow, true);
 954         }
 955
 956         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 957         return 0;
 958 }
 959
 960 static int vsc8584_macsec_del_txsa(struct macsec_context *ctx)
 961 {
 962         struct macsec_flow *flow;
 963
 964         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 965
 966         if (IS_ERR(flow))
 967                 return PTR_ERR(flow);
 968         if (ctx->prepare)
 969                 return 0;
 970
 971         vsc8584_macsec_del_flow(ctx->phydev, flow);
 972         return 0;
 973 }
 974
 975 static struct macsec_ops vsc8584_macsec_ops = {
 976         .mdo_dev_open = vsc8584_macsec_dev_open,
 977         .mdo_dev_stop = vsc8584_macsec_dev_stop,
 978         .mdo_add_secy = vsc8584_macsec_add_secy,
 979         .mdo_upd_secy = vsc8584_macsec_upd_secy,
 980         .mdo_del_secy = vsc8584_macsec_del_secy,
 981         .mdo_add_rxsc = vsc8584_macsec_add_rxsc,
 982         .mdo_upd_rxsc = vsc8584_macsec_upd_rxsc,
 983         .mdo_del_rxsc = vsc8584_macsec_del_rxsc,
 984         .mdo_add_rxsa = vsc8584_macsec_add_rxsa,
 985         .mdo_upd_rxsa = vsc8584_macsec_upd_rxsa,
 986         .mdo_del_rxsa = vsc8584_macsec_del_rxsa,
 987         .mdo_add_txsa = vsc8584_macsec_add_txsa,
 988         .mdo_upd_txsa = vsc8584_macsec_upd_txsa,
 989         .mdo_del_txsa = vsc8584_macsec_del_txsa,
 990 };
 991
 992 int vsc8584_macsec_init(struct phy_device *phydev)
 993 {
 994         struct vsc8531_private *vsc8531 = phydev->priv;
 995
 996         switch (phydev->phy_id & phydev->drv->phy_id_mask) {
 997         case PHY_ID_VSC856X:
 998         case PHY_ID_VSC8575:
 999         case PHY_ID_VSC8582:
1000         case PHY_ID_VSC8584:
1001                 INIT_LIST_HEAD(&vsc8531->macsec_flows);
1002                 vsc8531->secy = NULL;
1003
1004                 phydev->macsec_ops = &vsc8584_macsec_ops;
1005
1006                 return __vsc8584_macsec_init(phydev);
1007         }
1008
1009         return 0;
1010 }
1011
1012 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
1013 {
1014         struct vsc8531_private *priv = phydev->priv;
1015         struct macsec_flow *flow, *tmp;
1016         u32 cause, rec;
1017
1018         /* Check MACsec PN rollover */
1019         cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1020                                         MSCC_MS_INTR_CTRL_STATUS);
1021         cause &= MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M;
1022         if (!(cause & MACSEC_INTR_CTRL_STATUS_ROLLOVER))
1023                 return;
1024
1025         rec = 6 + priv->secy->key_len / sizeof(u32);
1026         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
1027                 u32 val;
1028
1029                 if (flow->bank != MACSEC_EGR || !flow->has_transformation)
1030                         continue;
1031
1032                 val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1033                                               MSCC_MS_XFORM_REC(flow->index, rec));
1034                 if (val == 0xffffffff) {
1035                         vsc8584_macsec_flow_disable(phydev, flow);
1036                         macsec_pn_wrapped(priv->secy, flow->tx_sa);
1037                         return;
1038                 }
1039         }
1040 }
1041
1042 void vsc8584_config_macsec_intr(struct phy_device *phydev)
1043 {
1044         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1045         phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR);
1046         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1047
1048         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);
1049         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,
1050                                  MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(MACSEC_INTR_CTRL_STATUS_ROLLOVER));
1051 }