drivers/net/phy/mscc/mscc_macsec.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs
   4  *
   5  * Author: Nagaraju Lakkaraju
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2016 Microsemi Corporation
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  12
  13 #include <crypto/skcipher.h>
  14
  15 #include <net/macsec.h>
  16
  17 #include "mscc.h"
  18 #include "mscc_mac.h"
  19 #include "mscc_macsec.h"
  20 #include "mscc_fc_buffer.h"
  21
  22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,
  23                                    enum macsec_bank bank, u32 reg)
  24 {
  25         u32 val, val_l = 0, val_h = 0;
  26         unsigned long deadline;
  27         int rc;
  28
  29         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  30         if (rc < 0)
  31                 goto failed;
  32
  33         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  34                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  35
  36         if (bank >> 2 == 0x1)
  37                 /* non-MACsec access */
  38                 bank &= 0x3;
  39         else
  40                 bank = 0;
  41
  42         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  43                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ |
  44                     MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  45                     MSCC_PHY_MACSEC_19_TARGET(bank));
  46
  47         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  48         do {
  49                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  50         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  51
  52         val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17);
  53         val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18);
  54
  55 failed:
  56         phy_restore_page(phydev, rc, rc);
  57
  58         return (val_h << 16) | val_l;
  59 }
  60
  61 static void vsc8584_macsec_phy_write(struct phy_device *phydev,
  62                                      enum macsec_bank bank, u32 reg, u32 val)
  63 {
  64         unsigned long deadline;
  65         int rc;
  66
  67         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  68         if (rc < 0)
  69                 goto failed;
  70
  71         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  72                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  73
  74         if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))
  75                 bank &= 0x3;
  76         else
  77                 /* MACsec access */
  78                 bank = 0;
  79
  80         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
  81         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
  82
  83         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  84                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  85                     MSCC_PHY_MACSEC_19_TARGET(bank));
  86
  87         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  88         do {
  89                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  90         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  91
  92 failed:
  93         phy_restore_page(phydev, rc, rc);
  94 }
  95
  96 static void vsc8584_macsec_classification(struct phy_device *phydev,
  97                                           enum macsec_bank bank)
  98 {
  99         /* enable VLAN tag parsing */
 100         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
 101                                  MSCC_MS_SAM_CP_TAG_PARSE_STAG |
 102                                  MSCC_MS_SAM_CP_TAG_PARSE_QTAG |
 103                                  MSCC_MS_SAM_CP_TAG_PARSE_QINQ);
 104 }
 105
 106 static void vsc8584_macsec_flow_default_action(struct phy_device *phydev,
 107                                                enum macsec_bank bank,
 108                                                bool block)
 109 {
 110         u32 port = (bank == MACSEC_INGR) ?
 111                     MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON;
 112         u32 action = MSCC_MS_FLOW_BYPASS;
 113
 114         if (block)
 115                 action = MSCC_MS_FLOW_DROP;
 116
 117         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
 118                                  /* MACsec untagged */
 119                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 120                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 121                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) |
 122                                  /* MACsec tagged */
 123                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 124                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 125                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) |
 126                                  /* Bad tag */
 127                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 128                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 129                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) |
 130                                  /* Kay tag */
 131                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 132                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 133                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port));
 134         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
 135                                  /* MACsec untagged */
 136                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 137                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 138                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) |
 139                                  /* MACsec tagged */
 140                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 141                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 142                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) |
 143                                  /* Bad tag */
 144                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 145                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 146                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) |
 147                                  /* Kay tag */
 148                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 149                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 150                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port));
 151 }
 152
 153 static void vsc8584_macsec_integrity_checks(struct phy_device *phydev,
 154                                             enum macsec_bank bank)
 155 {
 156         u32 val;
 157
 158         if (bank != MACSEC_INGR)
 159                 return;
 160
 161         /* Set default rules to pass unmatched frames */
 162         val = vsc8584_macsec_phy_read(phydev, bank,
 163                                       MSCC_MS_PARAMS2_IG_CC_CONTROL);
 164         val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT |
 165                MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT;
 166         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
 167                                  val);
 168
 169         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
 170                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG |
 171                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG |
 172                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ);
 173 }
 174
 175 static void vsc8584_macsec_block_init(struct phy_device *phydev,
 176                                       enum macsec_bank bank)
 177 {
 178         u32 val;
 179         int i;
 180
 181         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 182                                  MSCC_MS_ENA_CFG_SW_RST |
 183                                  MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA);
 184
 185         /* Set the MACsec block out of s/w reset and enable clocks */
 186         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 187                                  MSCC_MS_ENA_CFG_CLK_ENA);
 188
 189         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
 190                                  bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);
 191         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
 192                                  MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |
 193                                  MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));
 194
 195         /* Clear the counters */
 196         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 197         val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET;
 198         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 199
 200         /* Enable octet increment mode */
 201         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
 202                                  MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE);
 203
 204         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
 205
 206         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 207         val |= MSCC_MS_COUNT_CONTROL_RESET_ALL;
 208         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 209
 210         /* Set the MTU */
 211         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
 212                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) |
 213                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP);
 214
 215         for (i = 0; i < 8; i++)
 216                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
 217                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) |
 218                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP);
 219
 220         if (bank == MACSEC_EGR) {
 221                 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
 222                 val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M;
 223                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
 224
 225                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
 226                                          MSCC_MS_FC_CFG_FCBUF_ENA |
 227                                          MSCC_MS_FC_CFG_LOW_THRESH(0x1) |
 228                                          MSCC_MS_FC_CFG_HIGH_THRESH(0x4) |
 229                                          MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) |
 230                                          MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6));
 231         }
 232
 233         vsc8584_macsec_classification(phydev, bank);
 234         vsc8584_macsec_flow_default_action(phydev, bank, false);
 235         vsc8584_macsec_integrity_checks(phydev, bank);
 236
 237         /* Enable the MACsec block */
 238         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 239                                  MSCC_MS_ENA_CFG_CLK_ENA |
 240                                  MSCC_MS_ENA_CFG_MACSEC_ENA |
 241                                  MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5));
 242 }
 243
 244 static void vsc8584_macsec_mac_init(struct phy_device *phydev,
 245                                     enum macsec_bank bank)
 246 {
 247         u32 val;
 248         int i;
 249
 250         /* Clear host & line stats */
 251         for (i = 0; i < 36; i++)
 252                 vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
 253
 254         val = vsc8584_macsec_phy_read(phydev, bank,
 255                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL);
 256         val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M;
 257         val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) |
 258                MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff);
 259         vsc8584_macsec_phy_write(phydev, bank,
 260                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val);
 261
 262         val = vsc8584_macsec_phy_read(phydev, bank,
 263                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2);
 264         val |= 0xffff;
 265         vsc8584_macsec_phy_write(phydev, bank,
 266                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val);
 267
 268         val = vsc8584_macsec_phy_read(phydev, bank,
 269                                       MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL);
 270         if (bank == HOST_MAC)
 271                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA |
 272                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA;
 273         else
 274                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA |
 275                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA |
 276                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE |
 277                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA;
 278         vsc8584_macsec_phy_write(phydev, bank,
 279                                  MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val);
 280
 281         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
 282                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA |
 283                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA |
 284                                  MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA |
 285                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
 286                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
 287                                  (bank == HOST_MAC ?
 288                                   MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0));
 289
 290         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
 291         val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
 292         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
 293
 294         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
 295         val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M;
 296         val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240);
 297         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
 298
 299         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
 300                                  MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA |
 301                                  MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA |
 302                                  MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA |
 303                                  MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA);
 304
 305         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
 306         val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA;
 307         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
 308
 309         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
 310                                  MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA |
 311                                  MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA |
 312                                  MSCC_MAC_CFG_ENA_CFG_RX_ENA |
 313                                  MSCC_MAC_CFG_ENA_CFG_TX_ENA);
 314 }
 315
 316 /* Must be called with mdio_lock taken */
 317 static int __vsc8584_macsec_init(struct phy_device *phydev)
 318 {
 319         struct vsc8531_private *priv = phydev->priv;
 320         enum macsec_bank proc_bank;
 321         u32 val;
 322
 323         vsc8584_macsec_block_init(phydev, MACSEC_INGR);
 324         vsc8584_macsec_block_init(phydev, MACSEC_EGR);
 325         vsc8584_macsec_mac_init(phydev, HOST_MAC);
 326         vsc8584_macsec_mac_init(phydev, LINE_MAC);
 327
 328         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 329                                  MSCC_FCBUF_FC_READ_THRESH_CFG,
 330                                  MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) |
 331                                  MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5));
 332
 333         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
 334         val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA |
 335                MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA |
 336                MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA;
 337         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
 338
 339         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,
 340                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) |
 341                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9));
 342
 343         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
 344                                       MSCC_FCBUF_TX_DATA_QUEUE_CFG);
 345         val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M |
 346                  MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M);
 347         val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) |
 348                 MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119);
 349         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 350                                  MSCC_FCBUF_TX_DATA_QUEUE_CFG, val);
 351
 352         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
 353         val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
 354         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
 355
 356         proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
 357
 358         val = vsc8584_macsec_phy_read(phydev, proc_bank,
 359                                       MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
 360         val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
 361         val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
 362         vsc8584_macsec_phy_write(phydev, proc_bank,
 363                                  MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
 364
 365         return 0;
 366 }
 367
 368 static void vsc8584_macsec_flow(struct phy_device *phydev,
 369                                 struct macsec_flow *flow)
 370 {
 371         struct vsc8531_private *priv = phydev->priv;
 372         enum macsec_bank bank = flow->bank;
 373         u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
 374
 375         if (flow->match.tagged)
 376                 match |= MSCC_MS_SAM_MISC_MATCH_TAGGED;
 377         if (flow->match.untagged)
 378                 match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED;
 379
 380         if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
 381                 match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num);
 382                 mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3);
 383         }
 384
 385         if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
 386                 match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
 387                 mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
 388                         MSCC_MS_SAM_MASK_SCI_MASK;
 389
 390                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
 391                                          lower_32_bits(flow->rx_sa->sc->sci));
 392                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
 393                                          upper_32_bits(flow->rx_sa->sc->sci));
 394         }
 395
 396         if (flow->match.etype) {
 397                 mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
 398
 399                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
 400                                          MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(htons(flow->etype)));
 401         }
 402
 403         match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
 404
 405         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
 406         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
 407
 408         /* Action for matching packets */
 409         if (flow->action.drop)
 410                 action = MSCC_MS_FLOW_DROP;
 411         else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED)
 412                 action = MSCC_MS_FLOW_BYPASS;
 413         else
 414                 action = (bank == MACSEC_INGR) ?
 415                          MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS;
 416
 417         val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
 418               MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 419               MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port);
 420
 421         if (action == MSCC_MS_FLOW_BYPASS)
 422                 goto write_ctrl;
 423
 424         if (bank == MACSEC_INGR) {
 425                 if (priv->secy->replay_protect)
 426                         val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
 427                 if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT)
 428                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
 429                 else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK)
 430                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
 431         } else if (bank == MACSEC_EGR) {
 432                 if (priv->secy->protect_frames)
 433                         val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
 434                 if (priv->secy->tx_sc.encrypt)
 435                         val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
 436                 if (priv->secy->tx_sc.send_sci)
 437                         val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
 438         }
 439
 440 write_ctrl:
 441         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 442 }
 443
 444 static struct macsec_flow *vsc8584_macsec_find_flow(struct macsec_context *ctx,
 445                                                     enum macsec_bank bank)
 446 {
 447         struct vsc8531_private *priv = ctx->phydev->priv;
 448         struct macsec_flow *pos, *tmp;
 449
 450         list_for_each_entry_safe(pos, tmp, &priv->macsec_flows, list)
 451                 if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)
 452                         return pos;
 453
 454         return ERR_PTR(-ENOENT);
 455 }
 456
 457 static void vsc8584_macsec_flow_enable(struct phy_device *phydev,
 458                                        struct macsec_flow *flow)
 459 {
 460         enum macsec_bank bank = flow->bank;
 461         u32 val, idx = flow->index;
 462
 463         if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||
 464             (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))
 465                 return;
 466
 467         /* Enable */
 468         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
 469
 470         /* Set in-use */
 471         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 472         val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 473         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 474 }
 475
 476 static void vsc8584_macsec_flow_disable(struct phy_device *phydev,
 477                                         struct macsec_flow *flow)
 478 {
 479         enum macsec_bank bank = flow->bank;
 480         u32 val, idx = flow->index;
 481
 482         /* Disable */
 483         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
 484
 485         /* Clear in-use */
 486         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 487         val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 488         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 489 }
 490
 491 static u32 vsc8584_macsec_flow_context_id(struct macsec_flow *flow)
 492 {
 493         if (flow->bank == MACSEC_INGR)
 494                 return flow->index + MSCC_MS_MAX_FLOWS;
 495
 496         return flow->index;
 497 }
 498
 499 /* Derive the AES key to get a key for the hash autentication */
 500 static int vsc8584_macsec_derive_key(const u8 key[MACSEC_KEYID_LEN],
 501                                      u16 key_len, u8 hkey[16])
 502 {
 503         struct crypto_skcipher *tfm = crypto_alloc_skcipher("ecb(aes)", 0, 0);
 504         struct skcipher_request *req = NULL;
 505         struct scatterlist src, dst;
 506         DECLARE_CRYPTO_WAIT(wait);
 507         u32 input[4] = {0};
 508         int ret;
 509
 510         if (IS_ERR(tfm))
 511                 return PTR_ERR(tfm);
 512
 513         req = skcipher_request_alloc(tfm, GFP_KERNEL);
 514         if (!req) {
 515                 ret = -ENOMEM;
 516                 goto out;
 517         }
 518
 519         skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
 520                                       CRYPTO_TFM_REQ_MAY_SLEEP, crypto_req_done,
 521                                       &wait);
 522         ret = crypto_skcipher_setkey(tfm, key, key_len);
 523         if (ret < 0)
 524                 goto out;
 525
 526         sg_init_one(&src, input, 16);
 527         sg_init_one(&dst, hkey, 16);
 528         skcipher_request_set_crypt(req, &src, &dst, 16, NULL);
 529
 530         ret = crypto_wait_req(crypto_skcipher_encrypt(req), &wait);
 531
 532 out:
 533         skcipher_request_free(req);
 534         crypto_free_skcipher(tfm);
 535         return ret;
 536 }
 537
 538 static int vsc8584_macsec_transformation(struct phy_device *phydev,
 539                                          struct macsec_flow *flow)
 540 {
 541         struct vsc8531_private *priv = phydev->priv;
 542         enum macsec_bank bank = flow->bank;
 543         int i, ret, index = flow->index;
 544         u32 rec = 0, control = 0;
 545         u8 hkey[16];
 546         sci_t sci;
 547
 548         ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey);
 549         if (ret)
 550                 return ret;
 551
 552         switch (priv->secy->key_len) {
 553         case 16:
 554                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_128);
 555                 break;
 556         case 32:
 557                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_256);
 558                 break;
 559         default:
 560                 return -EINVAL;
 561         }
 562
 563         control |= (bank == MACSEC_EGR) ?
 564                    (CONTROL_TYPE_EGRESS | CONTROL_AN(priv->secy->tx_sc.encoding_sa)) :
 565                    (CONTROL_TYPE_INGRESS | CONTROL_SEQ_MASK);
 566
 567         control |= CONTROL_UPDATE_SEQ | CONTROL_ENCRYPT_AUTH | CONTROL_KEY_IN_CTX |
 568                    CONTROL_IV0 | CONTROL_IV1 | CONTROL_IV_IN_SEQ |
 569                    CONTROL_DIGEST_TYPE(0x2) | CONTROL_SEQ_TYPE(0x1) |
 570                    CONTROL_AUTH_ALG(AUTH_ALG_AES_GHAS) | CONTROL_CONTEXT_ID;
 571
 572         /* Set the control word */
 573         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 574                                  control);
 575
 576         /* Set the context ID. Must be unique. */
 577         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 578                                  vsc8584_macsec_flow_context_id(flow));
 579
 580         /* Set the encryption/decryption key */
 581         for (i = 0; i < priv->secy->key_len / sizeof(u32); i++)
 582                 vsc8584_macsec_phy_write(phydev, bank,
 583                                          MSCC_MS_XFORM_REC(index, rec++),
 584                                          ((u32 *)flow->key)[i]);
 585
 586         /* Set the authentication key */
 587         for (i = 0; i < 4; i++)
 588                 vsc8584_macsec_phy_write(phydev, bank,
 589                                          MSCC_MS_XFORM_REC(index, rec++),
 590                                          ((u32 *)hkey)[i]);
 591
 592         /* Initial sequence number */
 593         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 594                                  bank == MACSEC_INGR ?
 595                                  flow->rx_sa->next_pn : flow->tx_sa->next_pn);
 596
 597         if (bank == MACSEC_INGR)
 598                 /* Set the mask (replay window size) */
 599                 vsc8584_macsec_phy_write(phydev, bank,
 600                                          MSCC_MS_XFORM_REC(index, rec++),
 601                                          priv->secy->replay_window);
 602
 603         /* Set the input vectors */
 604         sci = bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci;
 605         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 606                                  lower_32_bits(sci));
 607         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 608                                  upper_32_bits(sci));
 609
 610         while (rec < 20)
 611                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 612                                          0);
 613
 614         flow->has_transformation = true;
 615         return 0;
 616 }
 617
 618 static struct macsec_flow *vsc8584_macsec_alloc_flow(struct vsc8531_private *priv,
 619                                                      enum macsec_bank bank)
 620 {
 621         unsigned long *bitmap = bank == MACSEC_INGR ?
 622                                 &priv->ingr_flows : &priv->egr_flows;
 623         struct macsec_flow *flow;
 624         int index;
 625
 626         index = find_first_zero_bit(bitmap, MSCC_MS_MAX_FLOWS);
 627
 628         if (index == MSCC_MS_MAX_FLOWS)
 629                 return ERR_PTR(-ENOMEM);
 630
 631         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
 632         if (!flow)
 633                 return ERR_PTR(-ENOMEM);
 634
 635         set_bit(index, bitmap);
 636         flow->index = index;
 637         flow->bank = bank;
 638         flow->priority = 8;
 639         flow->assoc_num = -1;
 640
 641         list_add_tail(&flow->list, &priv->macsec_flows);
 642         return flow;
 643 }
 644
 645 static void vsc8584_macsec_free_flow(struct vsc8531_private *priv,
 646                                      struct macsec_flow *flow)
 647 {
 648         unsigned long *bitmap = flow->bank == MACSEC_INGR ?
 649                                 &priv->ingr_flows : &priv->egr_flows;
 650
 651         list_del(&flow->list);
 652         clear_bit(flow->index, bitmap);
 653         kfree(flow);
 654 }
 655
 656 static int vsc8584_macsec_add_flow(struct phy_device *phydev,
 657                                    struct macsec_flow *flow, bool update)
 658 {
 659         int ret;
 660
 661         flow->port = MSCC_MS_PORT_CONTROLLED;
 662         vsc8584_macsec_flow(phydev, flow);
 663
 664         if (update)
 665                 return 0;
 666
 667         ret = vsc8584_macsec_transformation(phydev, flow);
 668         if (ret) {
 669                 vsc8584_macsec_free_flow(phydev->priv, flow);
 670                 return ret;
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int vsc8584_macsec_default_flows(struct phy_device *phydev)
 677 {
 678         struct macsec_flow *flow;
 679
 680         /* Add a rule to let the MKA traffic go through, ingress */
 681         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR);
 682         if (IS_ERR(flow))
 683                 return PTR_ERR(flow);
 684
 685         flow->priority = 15;
 686         flow->port = MSCC_MS_PORT_UNCONTROLLED;
 687         flow->match.tagged = 1;
 688         flow->match.untagged = 1;
 689         flow->match.etype = 1;
 690         flow->etype = ETH_P_PAE;
 691         flow->action.bypass = 1;
 692
 693         vsc8584_macsec_flow(phydev, flow);
 694         vsc8584_macsec_flow_enable(phydev, flow);
 695
 696         /* Add a rule to let the MKA traffic go through, egress */
 697         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR);
 698         if (IS_ERR(flow))
 699                 return PTR_ERR(flow);
 700
 701         flow->priority = 15;
 702         flow->port = MSCC_MS_PORT_COMMON;
 703         flow->match.untagged = 1;
 704         flow->match.etype = 1;
 705         flow->etype = ETH_P_PAE;
 706         flow->action.bypass = 1;
 707
 708         vsc8584_macsec_flow(phydev, flow);
 709         vsc8584_macsec_flow_enable(phydev, flow);
 710
 711         return 0;
 712 }
 713
 714 static void vsc8584_macsec_del_flow(struct phy_device *phydev,
 715                                     struct macsec_flow *flow)
 716 {
 717         vsc8584_macsec_flow_disable(phydev, flow);
 718         vsc8584_macsec_free_flow(phydev->priv, flow);
 719 }
 720
 721 static int __vsc8584_macsec_add_rxsa(struct macsec_context *ctx,
 722                                      struct macsec_flow *flow, bool update)
 723 {
 724         struct phy_device *phydev = ctx->phydev;
 725         struct vsc8531_private *priv = phydev->priv;
 726
 727         if (!flow) {
 728                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_INGR);
 729                 if (IS_ERR(flow))
 730                         return PTR_ERR(flow);
 731
 732                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 733         }
 734
 735         flow->assoc_num = ctx->sa.assoc_num;
 736         flow->rx_sa = ctx->sa.rx_sa;
 737
 738         /* Always match tagged packets on ingress */
 739         flow->match.tagged = 1;
 740         flow->match.sci = 1;
 741
 742         if (priv->secy->validate_frames != MACSEC_VALIDATE_DISABLED)
 743                 flow->match.untagged = 1;
 744
 745         return vsc8584_macsec_add_flow(phydev, flow, update);
 746 }
 747
 748 static int __vsc8584_macsec_add_txsa(struct macsec_context *ctx,
 749                                      struct macsec_flow *flow, bool update)
 750 {
 751         struct phy_device *phydev = ctx->phydev;
 752         struct vsc8531_private *priv = phydev->priv;
 753
 754         if (!flow) {
 755                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_EGR);
 756                 if (IS_ERR(flow))
 757                         return PTR_ERR(flow);
 758
 759                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 760         }
 761
 762         flow->assoc_num = ctx->sa.assoc_num;
 763         flow->tx_sa = ctx->sa.tx_sa;
 764
 765         /* Always match untagged packets on egress */
 766         flow->match.untagged = 1;
 767
 768         return vsc8584_macsec_add_flow(phydev, flow, update);
 769 }
 770
 771 static int vsc8584_macsec_dev_open(struct macsec_context *ctx)
 772 {
 773         struct vsc8531_private *priv = ctx->phydev->priv;
 774         struct macsec_flow *flow, *tmp;
 775
 776         /* No operation to perform before the commit step */
 777         if (ctx->prepare)
 778                 return 0;
 779
 780         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 781                 vsc8584_macsec_flow_enable(ctx->phydev, flow);
 782
 783         return 0;
 784 }
 785
 786 static int vsc8584_macsec_dev_stop(struct macsec_context *ctx)
 787 {
 788         struct vsc8531_private *priv = ctx->phydev->priv;
 789         struct macsec_flow *flow, *tmp;
 790
 791         /* No operation to perform before the commit step */
 792         if (ctx->prepare)
 793                 return 0;
 794
 795         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 796                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 797
 798         return 0;
 799 }
 800
 801 static int vsc8584_macsec_add_secy(struct macsec_context *ctx)
 802 {
 803         struct vsc8531_private *priv = ctx->phydev->priv;
 804         struct macsec_secy *secy = ctx->secy;
 805
 806         if (ctx->prepare) {
 807                 if (priv->secy)
 808                         return -EEXIST;
 809
 810                 return 0;
 811         }
 812
 813         priv->secy = secy;
 814
 815         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR,
 816                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 817         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR,
 818                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 819
 820         return vsc8584_macsec_default_flows(ctx->phydev);
 821 }
 822
 823 static int vsc8584_macsec_del_secy(struct macsec_context *ctx)
 824 {
 825         struct vsc8531_private *priv = ctx->phydev->priv;
 826         struct macsec_flow *flow, *tmp;
 827
 828         /* No operation to perform before the commit step */
 829         if (ctx->prepare)
 830                 return 0;
 831
 832         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 833                 vsc8584_macsec_del_flow(ctx->phydev, flow);
 834
 835         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false);
 836         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false);
 837
 838         priv->secy = NULL;
 839         return 0;
 840 }
 841
 842 static int vsc8584_macsec_upd_secy(struct macsec_context *ctx)
 843 {
 844         /* No operation to perform before the commit step */
 845         if (ctx->prepare)
 846                 return 0;
 847
 848         vsc8584_macsec_del_secy(ctx);
 849         return vsc8584_macsec_add_secy(ctx);
 850 }
 851
 852 static int vsc8584_macsec_add_rxsc(struct macsec_context *ctx)
 853 {
 854         /* Nothing to do */
 855         return 0;
 856 }
 857
 858 static int vsc8584_macsec_upd_rxsc(struct macsec_context *ctx)
 859 {
 860         return -EOPNOTSUPP;
 861 }
 862
 863 static int vsc8584_macsec_del_rxsc(struct macsec_context *ctx)
 864 {
 865         struct vsc8531_private *priv = ctx->phydev->priv;
 866         struct macsec_flow *flow, *tmp;
 867
 868         /* No operation to perform before the commit step */
 869         if (ctx->prepare)
 870                 return 0;
 871
 872         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
 873                 if (flow->bank == MACSEC_INGR && flow->rx_sa &&
 874                     flow->rx_sa->sc->sci == ctx->rx_sc->sci)
 875                         vsc8584_macsec_del_flow(ctx->phydev, flow);
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int vsc8584_macsec_add_rxsa(struct macsec_context *ctx)
 882 {
 883         struct macsec_flow *flow = NULL;
 884
 885         if (ctx->prepare)
 886                 return __vsc8584_macsec_add_rxsa(ctx, flow, false);
 887
 888         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 889         if (IS_ERR(flow))
 890                 return PTR_ERR(flow);
 891
 892         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 893         return 0;
 894 }
 895
 896 static int vsc8584_macsec_upd_rxsa(struct macsec_context *ctx)
 897 {
 898         struct macsec_flow *flow;
 899
 900         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 901         if (IS_ERR(flow))
 902                 return PTR_ERR(flow);
 903
 904         if (ctx->prepare) {
 905                 /* Make sure the flow is disabled before updating it */
 906                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 907
 908                 return __vsc8584_macsec_add_rxsa(ctx, flow, true);
 909         }
 910
 911         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 912         return 0;
 913 }
 914
 915 static int vsc8584_macsec_del_rxsa(struct macsec_context *ctx)
 916 {
 917         struct macsec_flow *flow;
 918
 919         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 920
 921         if (IS_ERR(flow))
 922                 return PTR_ERR(flow);
 923         if (ctx->prepare)
 924                 return 0;
 925
 926         vsc8584_macsec_del_flow(ctx->phydev, flow);
 927         return 0;
 928 }
 929
 930 static int vsc8584_macsec_add_txsa(struct macsec_context *ctx)
 931 {
 932         struct macsec_flow *flow = NULL;
 933
 934         if (ctx->prepare)
 935                 return __vsc8584_macsec_add_txsa(ctx, flow, false);
 936
 937         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 938         if (IS_ERR(flow))
 939                 return PTR_ERR(flow);
 940
 941         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 942         return 0;
 943 }
 944
 945 static int vsc8584_macsec_upd_txsa(struct macsec_context *ctx)
 946 {
 947         struct macsec_flow *flow;
 948
 949         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 950         if (IS_ERR(flow))
 951                 return PTR_ERR(flow);
 952
 953         if (ctx->prepare) {
 954                 /* Make sure the flow is disabled before updating it */
 955                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 956
 957                 return __vsc8584_macsec_add_txsa(ctx, flow, true);
 958         }
 959
 960         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 961         return 0;
 962 }
 963
 964 static int vsc8584_macsec_del_txsa(struct macsec_context *ctx)
 965 {
 966         struct macsec_flow *flow;
 967
 968         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 969
 970         if (IS_ERR(flow))
 971                 return PTR_ERR(flow);
 972         if (ctx->prepare)
 973                 return 0;
 974
 975         vsc8584_macsec_del_flow(ctx->phydev, flow);
 976         return 0;
 977 }
 978
 979 static struct macsec_ops vsc8584_macsec_ops = {
 980         .mdo_dev_open = vsc8584_macsec_dev_open,
 981         .mdo_dev_stop = vsc8584_macsec_dev_stop,
 982         .mdo_add_secy = vsc8584_macsec_add_secy,
 983         .mdo_upd_secy = vsc8584_macsec_upd_secy,
 984         .mdo_del_secy = vsc8584_macsec_del_secy,
 985         .mdo_add_rxsc = vsc8584_macsec_add_rxsc,
 986         .mdo_upd_rxsc = vsc8584_macsec_upd_rxsc,
 987         .mdo_del_rxsc = vsc8584_macsec_del_rxsc,
 988         .mdo_add_rxsa = vsc8584_macsec_add_rxsa,
 989         .mdo_upd_rxsa = vsc8584_macsec_upd_rxsa,
 990         .mdo_del_rxsa = vsc8584_macsec_del_rxsa,
 991         .mdo_add_txsa = vsc8584_macsec_add_txsa,
 992         .mdo_upd_txsa = vsc8584_macsec_upd_txsa,
 993         .mdo_del_txsa = vsc8584_macsec_del_txsa,
 994 };
 995
 996 int vsc8584_macsec_init(struct phy_device *phydev)
 997 {
 998         struct vsc8531_private *vsc8531 = phydev->priv;
 999
1000         switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1001         case PHY_ID_VSC856X:
1002         case PHY_ID_VSC8575:
1003         case PHY_ID_VSC8582:
1004         case PHY_ID_VSC8584:
1005                 INIT_LIST_HEAD(&vsc8531->macsec_flows);
1006                 vsc8531->secy = NULL;
1007
1008                 phydev->macsec_ops = &vsc8584_macsec_ops;
1009
1010                 return __vsc8584_macsec_init(phydev);
1011         }
1012
1013         return 0;
1014 }
1015
1016 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
1017 {
1018         struct vsc8531_private *priv = phydev->priv;
1019         struct macsec_flow *flow, *tmp;
1020         u32 cause, rec;
1021
1022         /* Check MACsec PN rollover */
1023         cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1024                                         MSCC_MS_INTR_CTRL_STATUS);
1025         cause &= MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M;
1026         if (!(cause & MACSEC_INTR_CTRL_STATUS_ROLLOVER))
1027                 return;
1028
1029         rec = 6 + priv->secy->key_len / sizeof(u32);
1030         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
1031                 u32 val;
1032
1033                 if (flow->bank != MACSEC_EGR || !flow->has_transformation)
1034                         continue;
1035
1036                 val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1037                                               MSCC_MS_XFORM_REC(flow->index, rec));
1038                 if (val == 0xffffffff) {
1039                         vsc8584_macsec_flow_disable(phydev, flow);
1040                         macsec_pn_wrapped(priv->secy, flow->tx_sa);
1041                         return;
1042                 }
1043         }
1044 }
1045
1046 void vsc8584_config_macsec_intr(struct phy_device *phydev)
1047 {
1048         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1049         phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR);
1050         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1051
1052         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);
1053         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,
1054                                  MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(MACSEC_INTR_CTRL_STATUS_ROLLOVER));
1055 }