drivers/net/phy/micrel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/ethtool_netlink.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/ptp_clock.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/net_tstamp.h>
  35
  36 /* Operation Mode Strap Override */
  37 #define MII_KSZPHY_OMSO                         0x16
  38 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  39 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  40 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  41 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  42 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  43
  44 /* general Interrupt control/status reg in vendor specific block. */
  45 #define MII_KSZPHY_INTCS                        0x1B
  46 #define KSZPHY_INTCS_JABBER                     BIT(15)
  47 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  48 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  49 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  50 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  51 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  52 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  53 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  54 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  55                                                 KSZPHY_INTCS_LINK_DOWN)
  56 #define KSZPHY_INTCS_LINK_DOWN_STATUS           BIT(2)
  57 #define KSZPHY_INTCS_LINK_UP_STATUS             BIT(0)
  58 #define KSZPHY_INTCS_STATUS                     (KSZPHY_INTCS_LINK_DOWN_STATUS |\
  59                                                  KSZPHY_INTCS_LINK_UP_STATUS)
  60
  61 /* LinkMD Control/Status */
  62 #define KSZ8081_LMD                             0x1d
  63 #define KSZ8081_LMD_ENABLE_TEST                 BIT(15)
  64 #define KSZ8081_LMD_STAT_NORMAL                 0
  65 #define KSZ8081_LMD_STAT_OPEN                   1
  66 #define KSZ8081_LMD_STAT_SHORT                  2
  67 #define KSZ8081_LMD_STAT_FAIL                   3
  68 #define KSZ8081_LMD_STAT_MASK                   GENMASK(14, 13)
  69 /* Short cable (<10 meter) has been detected by LinkMD */
  70 #define KSZ8081_LMD_SHORT_INDICATOR             BIT(12)
  71 #define KSZ8081_LMD_DELTA_TIME_MASK             GENMASK(8, 0)
  72
  73 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
  74 #define LAN8814_INTC                            0x18
  75 #define LAN8814_INTS                            0x1B
  76
  77 #define LAN8814_INT_LINK_DOWN                   BIT(2)
  78 #define LAN8814_INT_LINK_UP                     BIT(0)
  79 #define LAN8814_INT_LINK                        (LAN8814_INT_LINK_UP |\
  80                                                  LAN8814_INT_LINK_DOWN)
  81
  82 #define LAN8814_INTR_CTRL_REG                   0x34
  83 #define LAN8814_INTR_CTRL_REG_POLARITY          BIT(1)
  84 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE       BIT(0)
  85
  86 /* Represents 1ppm adjustment in 2^32 format with
  87  * each nsec contains 4 clock cycles.
  88  * The value is calculated as following: (1/1000000)/((2^-32)/4)
  89  */
  90 #define LAN8814_1PPM_FORMAT                     17179
  91
  92 #define PTP_RX_MOD                              0x024F
  93 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
  94 #define PTP_RX_TIMESTAMP_EN                     0x024D
  95 #define PTP_TX_TIMESTAMP_EN                     0x028D
  96
  97 #define PTP_TIMESTAMP_EN_SYNC_                  BIT(0)
  98 #define PTP_TIMESTAMP_EN_DREQ_                  BIT(1)
  99 #define PTP_TIMESTAMP_EN_PDREQ_                 BIT(2)
 100 #define PTP_TIMESTAMP_EN_PDRES_                 BIT(3)
 101
 102 #define PTP_TX_PARSE_L2_ADDR_EN                 0x0284
 103 #define PTP_RX_PARSE_L2_ADDR_EN                 0x0244
 104
 105 #define PTP_TX_PARSE_IP_ADDR_EN                 0x0285
 106 #define PTP_RX_PARSE_IP_ADDR_EN                 0x0245
 107 #define LTC_HARD_RESET                          0x023F
 108 #define LTC_HARD_RESET_                         BIT(0)
 109
 110 #define TSU_HARD_RESET                          0x02C1
 111 #define TSU_HARD_RESET_                         BIT(0)
 112
 113 #define PTP_CMD_CTL                             0x0200
 114 #define PTP_CMD_CTL_PTP_DISABLE_                BIT(0)
 115 #define PTP_CMD_CTL_PTP_ENABLE_                 BIT(1)
 116 #define PTP_CMD_CTL_PTP_CLOCK_READ_             BIT(3)
 117 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_             BIT(4)
 118 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_           BIT(5)
 119 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_          BIT(6)
 120
 121 #define PTP_CLOCK_SET_SEC_MID                   0x0206
 122 #define PTP_CLOCK_SET_SEC_LO                    0x0207
 123 #define PTP_CLOCK_SET_NS_HI                     0x0208
 124 #define PTP_CLOCK_SET_NS_LO                     0x0209
 125
 126 #define PTP_CLOCK_READ_SEC_MID                  0x022A
 127 #define PTP_CLOCK_READ_SEC_LO                   0x022B
 128 #define PTP_CLOCK_READ_NS_HI                    0x022C
 129 #define PTP_CLOCK_READ_NS_LO                    0x022D
 130
 131 #define PTP_OPERATING_MODE                      0x0241
 132 #define PTP_OPERATING_MODE_STANDALONE_          BIT(0)
 133
 134 #define PTP_TX_MOD                              0x028F
 135 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_       BIT(12)
 136 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 137
 138 #define PTP_RX_PARSE_CONFIG                     0x0242
 139 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 140 #define PTP_RX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 141 #define PTP_RX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 142
 143 #define PTP_TX_PARSE_CONFIG                     0x0282
 144 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 145 #define PTP_TX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 146 #define PTP_TX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 147
 148 #define PTP_CLOCK_RATE_ADJ_HI                   0x020C
 149 #define PTP_CLOCK_RATE_ADJ_LO                   0x020D
 150 #define PTP_CLOCK_RATE_ADJ_DIR_                 BIT(15)
 151
 152 #define PTP_LTC_STEP_ADJ_HI                     0x0212
 153 #define PTP_LTC_STEP_ADJ_LO                     0x0213
 154 #define PTP_LTC_STEP_ADJ_DIR_                   BIT(15)
 155
 156 #define LAN8814_INTR_STS_REG                    0x0033
 157 #define LAN8814_INTR_STS_REG_1588_TSU0_         BIT(0)
 158 #define LAN8814_INTR_STS_REG_1588_TSU1_         BIT(1)
 159 #define LAN8814_INTR_STS_REG_1588_TSU2_         BIT(2)
 160 #define LAN8814_INTR_STS_REG_1588_TSU3_         BIT(3)
 161
 162 #define PTP_CAP_INFO                            0x022A
 163 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)    (((reg_val) & 0x0f00) >> 8)
 164 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)    ((reg_val) & 0x000f)
 165
 166 #define PTP_TX_EGRESS_SEC_HI                    0x0296
 167 #define PTP_TX_EGRESS_SEC_LO                    0x0297
 168 #define PTP_TX_EGRESS_NS_HI                     0x0294
 169 #define PTP_TX_EGRESS_NS_LO                     0x0295
 170 #define PTP_TX_MSG_HEADER2                      0x0299
 171
 172 #define PTP_RX_INGRESS_SEC_HI                   0x0256
 173 #define PTP_RX_INGRESS_SEC_LO                   0x0257
 174 #define PTP_RX_INGRESS_NS_HI                    0x0254
 175 #define PTP_RX_INGRESS_NS_LO                    0x0255
 176 #define PTP_RX_MSG_HEADER2                      0x0259
 177
 178 #define PTP_TSU_INT_EN                          0x0200
 179 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_      BIT(3)
 180 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_            BIT(2)
 181 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_      BIT(1)
 182 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_            BIT(0)
 183
 184 #define PTP_TSU_INT_STS                         0x0201
 185 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_    BIT(3)
 186 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_           BIT(2)
 187 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_    BIT(1)
 188 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_           BIT(0)
 189
 190 /* PHY Control 1 */
 191 #define MII_KSZPHY_CTRL_1                       0x1e
 192 #define KSZ8081_CTRL1_MDIX_STAT                 BIT(4)
 193
 194 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
 195 #define MII_KSZPHY_CTRL_2                       0x1f
 196 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
 197 /* bitmap of PHY register to set interrupt mode */
 198 #define KSZ8081_CTRL2_HP_MDIX                   BIT(15)
 199 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT          BIT(14)
 200 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX         BIT(13)
 201 #define KSZ8081_CTRL2_FORCE_LINK                BIT(11)
 202 #define KSZ8081_CTRL2_POWER_SAVING              BIT(10)
 203 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
 204 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
 205
 206 /* Write/read to/from extended registers */
 207 #define MII_KSZPHY_EXTREG                       0x0b
 208 #define KSZPHY_EXTREG_WRITE                     0x8000
 209
 210 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
 211 #define MII_KSZPHY_EXTREG_READ                  0x0d
 212
 213 /* Extended registers */
 214 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
 215 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
 216 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
 217
 218 #define PS_TO_REG                               200
 219 #define FIFO_SIZE                               8
 220
 221 struct kszphy_hw_stat {
 222         const char *string;
 223         u8 reg;
 224         u8 bits;
 225 };
 226
 227 static struct kszphy_hw_stat kszphy_hw_stats[] = {
 228         { "phy_receive_errors", 21, 16},
 229         { "phy_idle_errors", 10, 8 },
 230 };
 231
 232 struct kszphy_type {
 233         u32 led_mode_reg;
 234         u16 interrupt_level_mask;
 235         bool has_broadcast_disable;
 236         bool has_nand_tree_disable;
 237         bool has_rmii_ref_clk_sel;
 238 };
 239
 240 /* Shared structure between the PHYs of the same package. */
 241 struct lan8814_shared_priv {
 242         struct phy_device *phydev;
 243         struct ptp_clock *ptp_clock;
 244         struct ptp_clock_info ptp_clock_info;
 245
 246         /* Reference counter to how many ports in the package are enabling the
 247          * timestamping
 248          */
 249         u8 ref;
 250
 251         /* Lock for ptp_clock and ref */
 252         struct mutex shared_lock;
 253 };
 254
 255 struct lan8814_ptp_rx_ts {
 256         struct list_head list;
 257         u32 seconds;
 258         u32 nsec;
 259         u16 seq_id;
 260 };
 261
 262 struct kszphy_ptp_priv {
 263         struct mii_timestamper mii_ts;
 264         struct phy_device *phydev;
 265
 266         struct sk_buff_head tx_queue;
 267         struct sk_buff_head rx_queue;
 268
 269         struct list_head rx_ts_list;
 270         /* Lock for Rx ts fifo */
 271         spinlock_t rx_ts_lock;
 272
 273         int hwts_tx_type;
 274         enum hwtstamp_rx_filters rx_filter;
 275         int layer;
 276         int version;
 277 };
 278
 279 struct kszphy_priv {
 280         struct kszphy_ptp_priv ptp_priv;
 281         const struct kszphy_type *type;
 282         int led_mode;
 283         bool rmii_ref_clk_sel;
 284         bool rmii_ref_clk_sel_val;
 285         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 286 };
 287
 288 static const struct kszphy_type ksz8021_type = {
 289         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 290         .has_broadcast_disable  = true,
 291         .has_nand_tree_disable  = true,
 292         .has_rmii_ref_clk_sel   = true,
 293 };
 294
 295 static const struct kszphy_type ksz8041_type = {
 296         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 297 };
 298
 299 static const struct kszphy_type ksz8051_type = {
 300         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 301         .has_nand_tree_disable  = true,
 302 };
 303
 304 static const struct kszphy_type ksz8081_type = {
 305         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 306         .has_broadcast_disable  = true,
 307         .has_nand_tree_disable  = true,
 308         .has_rmii_ref_clk_sel   = true,
 309 };
 310
 311 static const struct kszphy_type ks8737_type = {
 312         .interrupt_level_mask   = BIT(14),
 313 };
 314
 315 static const struct kszphy_type ksz9021_type = {
 316         .interrupt_level_mask   = BIT(14),
 317 };
 318
 319 static int kszphy_extended_write(struct phy_device *phydev,
 320                                 u32 regnum, u16 val)
 321 {
 322         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 323         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 324 }
 325
 326 static int kszphy_extended_read(struct phy_device *phydev,
 327                                 u32 regnum)
 328 {
 329         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 330         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 331 }
 332
 333 static int kszphy_ack_interrupt(struct phy_device *phydev)
 334 {
 335         /* bit[7..0] int status, which is a read and clear register. */
 336         int rc;
 337
 338         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 339
 340         return (rc < 0) ? rc : 0;
 341 }
 342
 343 static int kszphy_config_intr(struct phy_device *phydev)
 344 {
 345         const struct kszphy_type *type = phydev->drv->driver_data;
 346         int temp, err;
 347         u16 mask;
 348
 349         if (type && type->interrupt_level_mask)
 350                 mask = type->interrupt_level_mask;
 351         else
 352                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 353
 354         /* set the interrupt pin active low */
 355         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 356         if (temp < 0)
 357                 return temp;
 358         temp &= ~mask;
 359         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 360
 361         /* enable / disable interrupts */
 362         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 363                 err = kszphy_ack_interrupt(phydev);
 364                 if (err)
 365                         return err;
 366
 367                 temp = KSZPHY_INTCS_ALL;
 368                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 369         } else {
 370                 temp = 0;
 371                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 372                 if (err)
 373                         return err;
 374
 375                 err = kszphy_ack_interrupt(phydev);
 376         }
 377
 378         return err;
 379 }
 380
 381 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
 382 {
 383         int irq_status;
 384
 385         irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
 386         if (irq_status < 0) {
 387                 phy_error(phydev);
 388                 return IRQ_NONE;
 389         }
 390
 391         if (!(irq_status & KSZPHY_INTCS_STATUS))
 392                 return IRQ_NONE;
 393
 394         phy_trigger_machine(phydev);
 395
 396         return IRQ_HANDLED;
 397 }
 398
 399 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 400 {
 401         int ctrl;
 402
 403         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 404         if (ctrl < 0)
 405                 return ctrl;
 406
 407         if (val)
 408                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 409         else
 410                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 411
 412         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 413 }
 414
 415 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 416 {
 417         int rc, temp, shift;
 418
 419         switch (reg) {
 420         case MII_KSZPHY_CTRL_1:
 421                 shift = 14;
 422                 break;
 423         case MII_KSZPHY_CTRL_2:
 424                 shift = 4;
 425                 break;
 426         default:
 427                 return -EINVAL;
 428         }
 429
 430         temp = phy_read(phydev, reg);
 431         if (temp < 0) {
 432                 rc = temp;
 433                 goto out;
 434         }
 435
 436         temp &= ~(3 << shift);
 437         temp |= val << shift;
 438         rc = phy_write(phydev, reg, temp);
 439 out:
 440         if (rc < 0)
 441                 phydev_err(phydev, "failed to set led mode\n");
 442
 443         return rc;
 444 }
 445
 446 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 447  * unique (non-broadcast) address on a shared bus.
 448  */
 449 static int kszphy_broadcast_disable(struct phy_device *phydev)
 450 {
 451         int ret;
 452
 453         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 454         if (ret < 0)
 455                 goto out;
 456
 457         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 458 out:
 459         if (ret)
 460                 phydev_err(phydev, "failed to disable broadcast address\n");
 461
 462         return ret;
 463 }
 464
 465 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 466 {
 467         int ret;
 468
 469         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 470         if (ret < 0)
 471                 goto out;
 472
 473         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 474                 return 0;
 475
 476         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 477                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 478 out:
 479         if (ret)
 480                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 481
 482         return ret;
 483 }
 484
 485 /* Some config bits need to be set again on resume, handle them here. */
 486 static int kszphy_config_reset(struct phy_device *phydev)
 487 {
 488         struct kszphy_priv *priv = phydev->priv;
 489         int ret;
 490
 491         if (priv->rmii_ref_clk_sel) {
 492                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 493                 if (ret) {
 494                         phydev_err(phydev,
 495                                    "failed to set rmii reference clock\n");
 496                         return ret;
 497                 }
 498         }
 499
 500         if (priv->led_mode >= 0)
 501                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 502
 503         return 0;
 504 }
 505
 506 static int kszphy_config_init(struct phy_device *phydev)
 507 {
 508         struct kszphy_priv *priv = phydev->priv;
 509         const struct kszphy_type *type;
 510
 511         if (!priv)
 512                 return 0;
 513
 514         type = priv->type;
 515
 516         if (type->has_broadcast_disable)
 517                 kszphy_broadcast_disable(phydev);
 518
 519         if (type->has_nand_tree_disable)
 520                 kszphy_nand_tree_disable(phydev);
 521
 522         return kszphy_config_reset(phydev);
 523 }
 524
 525 static int ksz8041_fiber_mode(struct phy_device *phydev)
 526 {
 527         struct device_node *of_node = phydev->mdio.dev.of_node;
 528
 529         return of_property_read_bool(of_node, "micrel,fiber-mode");
 530 }
 531
 532 static int ksz8041_config_init(struct phy_device *phydev)
 533 {
 534         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 535
 536         /* Limit supported and advertised modes in fiber mode */
 537         if (ksz8041_fiber_mode(phydev)) {
 538                 phydev->dev_flags |= MICREL_PHY_FXEN;
 539                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 540                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 541
 542                 linkmode_and(phydev->supported, phydev->supported, mask);
 543                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 544                                  phydev->supported);
 545                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 546                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 547                                  phydev->advertising);
 548                 phydev->autoneg = AUTONEG_DISABLE;
 549         }
 550
 551         return kszphy_config_init(phydev);
 552 }
 553
 554 static int ksz8041_config_aneg(struct phy_device *phydev)
 555 {
 556         /* Skip auto-negotiation in fiber mode */
 557         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 558                 phydev->speed = SPEED_100;
 559                 return 0;
 560         }
 561
 562         return genphy_config_aneg(phydev);
 563 }
 564
 565 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 566                                             const bool ksz_8051)
 567 {
 568         int ret;
 569
 570         if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
 571                 return 0;
 572
 573         ret = phy_read(phydev, MII_BMSR);
 574         if (ret < 0)
 575                 return ret;
 576
 577         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 578          * exact PHY ID. However, they can be told apart by the extended
 579          * capability registers presence. The KSZ8051 PHY has them while
 580          * the switch does not.
 581          */
 582         ret &= BMSR_ERCAP;
 583         if (ksz_8051)
 584                 return ret;
 585         else
 586                 return !ret;
 587 }
 588
 589 static int ksz8051_match_phy_device(struct phy_device *phydev)
 590 {
 591         return ksz8051_ksz8795_match_phy_device(phydev, true);
 592 }
 593
 594 static int ksz8081_config_init(struct phy_device *phydev)
 595 {
 596         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 597          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 598          * pull-down is missing, the factory test mode should be cleared by
 599          * manually writing a 0.
 600          */
 601         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 602
 603         return kszphy_config_init(phydev);
 604 }
 605
 606 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
 607 {
 608         u16 val;
 609
 610         switch (ctrl) {
 611         case ETH_TP_MDI:
 612                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
 613                 break;
 614         case ETH_TP_MDI_X:
 615                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
 616                         KSZ8081_CTRL2_MDI_MDI_X_SELECT;
 617                 break;
 618         case ETH_TP_MDI_AUTO:
 619                 val = 0;
 620                 break;
 621         default:
 622                 return 0;
 623         }
 624
 625         return phy_modify(phydev, MII_KSZPHY_CTRL_2,
 626                           KSZ8081_CTRL2_HP_MDIX |
 627                           KSZ8081_CTRL2_MDI_MDI_X_SELECT |
 628                           KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
 629                           KSZ8081_CTRL2_HP_MDIX | val);
 630 }
 631
 632 static int ksz8081_config_aneg(struct phy_device *phydev)
 633 {
 634         int ret;
 635
 636         ret = genphy_config_aneg(phydev);
 637         if (ret)
 638                 return ret;
 639
 640         /* The MDI-X configuration is automatically changed by the PHY after
 641          * switching from autoneg off to on. So, take MDI-X configuration under
 642          * own control and set it after autoneg configuration was done.
 643          */
 644         return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
 645 }
 646
 647 static int ksz8081_mdix_update(struct phy_device *phydev)
 648 {
 649         int ret;
 650
 651         ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
 652         if (ret < 0)
 653                 return ret;
 654
 655         if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
 656                 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
 657                         phydev->mdix_ctrl = ETH_TP_MDI_X;
 658                 else
 659                         phydev->mdix_ctrl = ETH_TP_MDI;
 660         } else {
 661                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 662         }
 663
 664         ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
 665         if (ret < 0)
 666                 return ret;
 667
 668         if (ret & KSZ8081_CTRL1_MDIX_STAT)
 669                 phydev->mdix = ETH_TP_MDI;
 670         else
 671                 phydev->mdix = ETH_TP_MDI_X;
 672
 673         return 0;
 674 }
 675
 676 static int ksz8081_read_status(struct phy_device *phydev)
 677 {
 678         int ret;
 679
 680         ret = ksz8081_mdix_update(phydev);
 681         if (ret < 0)
 682                 return ret;
 683
 684         return genphy_read_status(phydev);
 685 }
 686
 687 static int ksz8061_config_init(struct phy_device *phydev)
 688 {
 689         int ret;
 690
 691         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 692         if (ret)
 693                 return ret;
 694
 695         return kszphy_config_init(phydev);
 696 }
 697
 698 static int ksz8795_match_phy_device(struct phy_device *phydev)
 699 {
 700         return ksz8051_ksz8795_match_phy_device(phydev, false);
 701 }
 702
 703 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 704                                        const struct device_node *of_node,
 705                                        u16 reg,
 706                                        const char *field1, const char *field2,
 707                                        const char *field3, const char *field4)
 708 {
 709         int val1 = -1;
 710         int val2 = -2;
 711         int val3 = -3;
 712         int val4 = -4;
 713         int newval;
 714         int matches = 0;
 715
 716         if (!of_property_read_u32(of_node, field1, &val1))
 717                 matches++;
 718
 719         if (!of_property_read_u32(of_node, field2, &val2))
 720                 matches++;
 721
 722         if (!of_property_read_u32(of_node, field3, &val3))
 723                 matches++;
 724
 725         if (!of_property_read_u32(of_node, field4, &val4))
 726                 matches++;
 727
 728         if (!matches)
 729                 return 0;
 730
 731         if (matches < 4)
 732                 newval = kszphy_extended_read(phydev, reg);
 733         else
 734                 newval = 0;
 735
 736         if (val1 != -1)
 737                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 738
 739         if (val2 != -2)
 740                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 741
 742         if (val3 != -3)
 743                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 744
 745         if (val4 != -4)
 746                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 747
 748         return kszphy_extended_write(phydev, reg, newval);
 749 }
 750
 751 static int ksz9021_config_init(struct phy_device *phydev)
 752 {
 753         const struct device_node *of_node;
 754         const struct device *dev_walker;
 755
 756         /* The Micrel driver has a deprecated option to place phy OF
 757          * properties in the MAC node. Walk up the tree of devices to
 758          * find a device with an OF node.
 759          */
 760         dev_walker = &phydev->mdio.dev;
 761         do {
 762                 of_node = dev_walker->of_node;
 763                 dev_walker = dev_walker->parent;
 764
 765         } while (!of_node && dev_walker);
 766
 767         if (of_node) {
 768                 ksz9021_load_values_from_of(phydev, of_node,
 769                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 770                                     "txen-skew-ps", "txc-skew-ps",
 771                                     "rxdv-skew-ps", "rxc-skew-ps");
 772                 ksz9021_load_values_from_of(phydev, of_node,
 773                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 774                                     "rxd0-skew-ps", "rxd1-skew-ps",
 775                                     "rxd2-skew-ps", "rxd3-skew-ps");
 776                 ksz9021_load_values_from_of(phydev, of_node,
 777                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 778                                     "txd0-skew-ps", "txd1-skew-ps",
 779                                     "txd2-skew-ps", "txd3-skew-ps");
 780         }
 781         return 0;
 782 }
 783
 784 #define KSZ9031_PS_TO_REG               60
 785
 786 /* Extended registers */
 787 /* MMD Address 0x0 */
 788 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 789 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 790
 791 /* MMD Address 0x2 */
 792 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 793 #define MII_KSZ9031RN_RX_CTL_M          GENMASK(7, 4)
 794 #define MII_KSZ9031RN_TX_CTL_M          GENMASK(3, 0)
 795
 796 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 797 #define MII_KSZ9031RN_RXD3              GENMASK(15, 12)
 798 #define MII_KSZ9031RN_RXD2              GENMASK(11, 8)
 799 #define MII_KSZ9031RN_RXD1              GENMASK(7, 4)
 800 #define MII_KSZ9031RN_RXD0              GENMASK(3, 0)
 801
 802 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 803 #define MII_KSZ9031RN_TXD3              GENMASK(15, 12)
 804 #define MII_KSZ9031RN_TXD2              GENMASK(11, 8)
 805 #define MII_KSZ9031RN_TXD1              GENMASK(7, 4)
 806 #define MII_KSZ9031RN_TXD0              GENMASK(3, 0)
 807
 808 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 809 #define MII_KSZ9031RN_GTX_CLK           GENMASK(9, 5)
 810 #define MII_KSZ9031RN_RX_CLK            GENMASK(4, 0)
 811
 812 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
 813  * provide different RGMII options we need to configure delay offset
 814  * for each pad relative to build in delay.
 815  */
 816 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
 817  * 1.80ns
 818  */
 819 #define RX_ID                           0x7
 820 #define RX_CLK_ID                       0x19
 821
 822 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
 823  * internal 1.2ns delay.
 824  */
 825 #define RX_ND                           0xc
 826 #define RX_CLK_ND                       0x0
 827
 828 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
 829 #define TX_ID                           0x0
 830 #define TX_CLK_ID                       0x1f
 831
 832 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
 833  * dealy
 834  */
 835 #define TX_ND                           0x7
 836 #define TX_CLK_ND                       0xf
 837
 838 /* MMD Address 0x1C */
 839 #define MII_KSZ9031RN_EDPD              0x23
 840 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 841
 842 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 843                                        const struct device_node *of_node,
 844                                        u16 reg, size_t field_sz,
 845                                        const char *field[], u8 numfields,
 846                                        bool *update)
 847 {
 848         int val[4] = {-1, -2, -3, -4};
 849         int matches = 0;
 850         u16 mask;
 851         u16 maxval;
 852         u16 newval;
 853         int i;
 854
 855         for (i = 0; i < numfields; i++)
 856                 if (!of_property_read_u32(of_node, field[i], val + i))
 857                         matches++;
 858
 859         if (!matches)
 860                 return 0;
 861
 862         *update |= true;
 863
 864         if (matches < numfields)
 865                 newval = phy_read_mmd(phydev, 2, reg);
 866         else
 867                 newval = 0;
 868
 869         maxval = (field_sz == 4) ? 0xf : 0x1f;
 870         for (i = 0; i < numfields; i++)
 871                 if (val[i] != -(i + 1)) {
 872                         mask = 0xffff;
 873                         mask ^= maxval << (field_sz * i);
 874                         newval = (newval & mask) |
 875                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 876                                         << (field_sz * i));
 877                 }
 878
 879         return phy_write_mmd(phydev, 2, reg, newval);
 880 }
 881
 882 /* Center KSZ9031RNX FLP timing at 16ms. */
 883 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 884 {
 885         int result;
 886
 887         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 888                                0x0006);
 889         if (result)
 890                 return result;
 891
 892         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 893                                0x1A80);
 894         if (result)
 895                 return result;
 896
 897         return genphy_restart_aneg(phydev);
 898 }
 899
 900 /* Enable energy-detect power-down mode */
 901 static int ksz9031_enable_edpd(struct phy_device *phydev)
 902 {
 903         int reg;
 904
 905         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 906         if (reg < 0)
 907                 return reg;
 908         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 909                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 910 }
 911
 912 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
 913 {
 914         u16 rx, tx, rx_clk, tx_clk;
 915         int ret;
 916
 917         switch (phydev->interface) {
 918         case PHY_INTERFACE_MODE_RGMII:
 919                 tx = TX_ND;
 920                 tx_clk = TX_CLK_ND;
 921                 rx = RX_ND;
 922                 rx_clk = RX_CLK_ND;
 923                 break;
 924         case PHY_INTERFACE_MODE_RGMII_ID:
 925                 tx = TX_ID;
 926                 tx_clk = TX_CLK_ID;
 927                 rx = RX_ID;
 928                 rx_clk = RX_CLK_ID;
 929                 break;
 930         case PHY_INTERFACE_MODE_RGMII_RXID:
 931                 tx = TX_ND;
 932                 tx_clk = TX_CLK_ND;
 933                 rx = RX_ID;
 934                 rx_clk = RX_CLK_ID;
 935                 break;
 936         case PHY_INTERFACE_MODE_RGMII_TXID:
 937                 tx = TX_ID;
 938                 tx_clk = TX_CLK_ID;
 939                 rx = RX_ND;
 940                 rx_clk = RX_CLK_ND;
 941                 break;
 942         default:
 943                 return 0;
 944         }
 945
 946         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
 947                             FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
 948                             FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
 949         if (ret < 0)
 950                 return ret;
 951
 952         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
 953                             FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
 954                             FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
 955                             FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
 956                             FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
 957         if (ret < 0)
 958                 return ret;
 959
 960         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
 961                             FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
 962                             FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
 963                             FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
 964                             FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
 965         if (ret < 0)
 966                 return ret;
 967
 968         return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
 969                              FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
 970                              FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
 971 }
 972
 973 static int ksz9031_config_init(struct phy_device *phydev)
 974 {
 975         const struct device_node *of_node;
 976         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 977         static const char *rx_data_skews[4] = {
 978                 "rxd0-skew-ps", "rxd1-skew-ps",
 979                 "rxd2-skew-ps", "rxd3-skew-ps"
 980         };
 981         static const char *tx_data_skews[4] = {
 982                 "txd0-skew-ps", "txd1-skew-ps",
 983                 "txd2-skew-ps", "txd3-skew-ps"
 984         };
 985         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 986         const struct device *dev_walker;
 987         int result;
 988
 989         result = ksz9031_enable_edpd(phydev);
 990         if (result < 0)
 991                 return result;
 992
 993         /* The Micrel driver has a deprecated option to place phy OF
 994          * properties in the MAC node. Walk up the tree of devices to
 995          * find a device with an OF node.
 996          */
 997         dev_walker = &phydev->mdio.dev;
 998         do {
 999                 of_node = dev_walker->of_node;
1000                 dev_walker = dev_walker->parent;
1001         } while (!of_node && dev_walker);
1002
1003         if (of_node) {
1004                 bool update = false;
1005
1006                 if (phy_interface_is_rgmii(phydev)) {
1007                         result = ksz9031_config_rgmii_delay(phydev);
1008                         if (result < 0)
1009                                 return result;
1010                 }
1011
1012                 ksz9031_of_load_skew_values(phydev, of_node,
1013                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1014                                 clk_skews, 2, &update);
1015
1016                 ksz9031_of_load_skew_values(phydev, of_node,
1017                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1018                                 control_skews, 2, &update);
1019
1020                 ksz9031_of_load_skew_values(phydev, of_node,
1021                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1022                                 rx_data_skews, 4, &update);
1023
1024                 ksz9031_of_load_skew_values(phydev, of_node,
1025                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1026                                 tx_data_skews, 4, &update);
1027
1028                 if (update && !phy_interface_is_rgmii(phydev))
1029                         phydev_warn(phydev,
1030                                     "*-skew-ps values should be used only with RGMII PHY modes\n");
1031
1032                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1033                  * When the device links in the 1000BASE-T slave mode only,
1034                  * the optional 125MHz reference output clock (CLK125_NDO)
1035                  * has wide duty cycle variation.
1036                  *
1037                  * The optional CLK125_NDO clock does not meet the RGMII
1038                  * 45/55 percent (min/max) duty cycle requirement and therefore
1039                  * cannot be used directly by the MAC side for clocking
1040                  * applications that have setup/hold time requirements on
1041                  * rising and falling clock edges.
1042                  *
1043                  * Workaround:
1044                  * Force the phy to be the master to receive a stable clock
1045                  * which meets the duty cycle requirement.
1046                  */
1047                 if (of_property_read_bool(of_node, "micrel,force-master")) {
1048                         result = phy_read(phydev, MII_CTRL1000);
1049                         if (result < 0)
1050                                 goto err_force_master;
1051
1052                         /* enable master mode, config & prefer master */
1053                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1054                         result = phy_write(phydev, MII_CTRL1000, result);
1055                         if (result < 0)
1056                                 goto err_force_master;
1057                 }
1058         }
1059
1060         return ksz9031_center_flp_timing(phydev);
1061
1062 err_force_master:
1063         phydev_err(phydev, "failed to force the phy to master mode\n");
1064         return result;
1065 }
1066
1067 #define KSZ9131_SKEW_5BIT_MAX   2400
1068 #define KSZ9131_SKEW_4BIT_MAX   800
1069 #define KSZ9131_OFFSET          700
1070 #define KSZ9131_STEP            100
1071
1072 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1073                                        struct device_node *of_node,
1074                                        u16 reg, size_t field_sz,
1075                                        char *field[], u8 numfields)
1076 {
1077         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1078                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1079         int skewval, skewmax = 0;
1080         int matches = 0;
1081         u16 maxval;
1082         u16 newval;
1083         u16 mask;
1084         int i;
1085
1086         /* psec properties in dts should mean x pico seconds */
1087         if (field_sz == 5)
1088                 skewmax = KSZ9131_SKEW_5BIT_MAX;
1089         else
1090                 skewmax = KSZ9131_SKEW_4BIT_MAX;
1091
1092         for (i = 0; i < numfields; i++)
1093                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1094                         if (skewval < -KSZ9131_OFFSET)
1095                                 skewval = -KSZ9131_OFFSET;
1096                         else if (skewval > skewmax)
1097                                 skewval = skewmax;
1098
1099                         val[i] = skewval + KSZ9131_OFFSET;
1100                         matches++;
1101                 }
1102
1103         if (!matches)
1104                 return 0;
1105
1106         if (matches < numfields)
1107                 newval = phy_read_mmd(phydev, 2, reg);
1108         else
1109                 newval = 0;
1110
1111         maxval = (field_sz == 4) ? 0xf : 0x1f;
1112         for (i = 0; i < numfields; i++)
1113                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1114                         mask = 0xffff;
1115                         mask ^= maxval << (field_sz * i);
1116                         newval = (newval & mask) |
1117                                 (((val[i] / KSZ9131_STEP) & maxval)
1118                                         << (field_sz * i));
1119                 }
1120
1121         return phy_write_mmd(phydev, 2, reg, newval);
1122 }
1123
1124 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
1125 #define KSZ9131RN_RXC_DLL_CTRL          76
1126 #define KSZ9131RN_TXC_DLL_CTRL          77
1127 #define KSZ9131RN_DLL_CTRL_BYPASS       BIT_MASK(12)
1128 #define KSZ9131RN_DLL_ENABLE_DELAY      0
1129 #define KSZ9131RN_DLL_DISABLE_DELAY     BIT(12)
1130
1131 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1132 {
1133         u16 rxcdll_val, txcdll_val;
1134         int ret;
1135
1136         switch (phydev->interface) {
1137         case PHY_INTERFACE_MODE_RGMII:
1138                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1139                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1140                 break;
1141         case PHY_INTERFACE_MODE_RGMII_ID:
1142                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1143                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1144                 break;
1145         case PHY_INTERFACE_MODE_RGMII_RXID:
1146                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1147                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1148                 break;
1149         case PHY_INTERFACE_MODE_RGMII_TXID:
1150                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1151                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1152                 break;
1153         default:
1154                 return 0;
1155         }
1156
1157         ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1158                              KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1159                              rxcdll_val);
1160         if (ret < 0)
1161                 return ret;
1162
1163         return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1164                               KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1165                               txcdll_val);
1166 }
1167
1168 /* Silicon Errata DS80000693B
1169  *
1170  * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1171  * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1172  * according to the datasheet (off if there is no link).
1173  */
1174 static int ksz9131_led_errata(struct phy_device *phydev)
1175 {
1176         int reg;
1177
1178         reg = phy_read_mmd(phydev, 2, 0);
1179         if (reg < 0)
1180                 return reg;
1181
1182         if (!(reg & BIT(4)))
1183                 return 0;
1184
1185         return phy_set_bits(phydev, 0x1e, BIT(9));
1186 }
1187
1188 static int ksz9131_config_init(struct phy_device *phydev)
1189 {
1190         struct device_node *of_node;
1191         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1192         char *rx_data_skews[4] = {
1193                 "rxd0-skew-psec", "rxd1-skew-psec",
1194                 "rxd2-skew-psec", "rxd3-skew-psec"
1195         };
1196         char *tx_data_skews[4] = {
1197                 "txd0-skew-psec", "txd1-skew-psec",
1198                 "txd2-skew-psec", "txd3-skew-psec"
1199         };
1200         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1201         const struct device *dev_walker;
1202         int ret;
1203
1204         dev_walker = &phydev->mdio.dev;
1205         do {
1206                 of_node = dev_walker->of_node;
1207                 dev_walker = dev_walker->parent;
1208         } while (!of_node && dev_walker);
1209
1210         if (!of_node)
1211                 return 0;
1212
1213         if (phy_interface_is_rgmii(phydev)) {
1214                 ret = ksz9131_config_rgmii_delay(phydev);
1215                 if (ret < 0)
1216                         return ret;
1217         }
1218
1219         ret = ksz9131_of_load_skew_values(phydev, of_node,
1220                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1221                                           clk_skews, 2);
1222         if (ret < 0)
1223                 return ret;
1224
1225         ret = ksz9131_of_load_skew_values(phydev, of_node,
1226                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1227                                           control_skews, 2);
1228         if (ret < 0)
1229                 return ret;
1230
1231         ret = ksz9131_of_load_skew_values(phydev, of_node,
1232                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1233                                           rx_data_skews, 4);
1234         if (ret < 0)
1235                 return ret;
1236
1237         ret = ksz9131_of_load_skew_values(phydev, of_node,
1238                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1239                                           tx_data_skews, 4);
1240         if (ret < 0)
1241                 return ret;
1242
1243         ret = ksz9131_led_errata(phydev);
1244         if (ret < 0)
1245                 return ret;
1246
1247         return 0;
1248 }
1249
1250 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
1251 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
1252 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
1253 static int ksz8873mll_read_status(struct phy_device *phydev)
1254 {
1255         int regval;
1256
1257         /* dummy read */
1258         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1259
1260         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1261
1262         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1263                 phydev->duplex = DUPLEX_HALF;
1264         else
1265                 phydev->duplex = DUPLEX_FULL;
1266
1267         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1268                 phydev->speed = SPEED_10;
1269         else
1270                 phydev->speed = SPEED_100;
1271
1272         phydev->link = 1;
1273         phydev->pause = phydev->asym_pause = 0;
1274
1275         return 0;
1276 }
1277
1278 static int ksz9031_get_features(struct phy_device *phydev)
1279 {
1280         int ret;
1281
1282         ret = genphy_read_abilities(phydev);
1283         if (ret < 0)
1284                 return ret;
1285
1286         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1287          * Whenever the device's Asymmetric Pause capability is set to 1,
1288          * link-up may fail after a link-up to link-down transition.
1289          *
1290          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1291          *
1292          * Workaround:
1293          * Do not enable the Asymmetric Pause capability bit.
1294          */
1295         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1296
1297         /* We force setting the Pause capability as the core will force the
1298          * Asymmetric Pause capability to 1 otherwise.
1299          */
1300         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1301
1302         return 0;
1303 }
1304
1305 static int ksz9031_read_status(struct phy_device *phydev)
1306 {
1307         int err;
1308         int regval;
1309
1310         err = genphy_read_status(phydev);
1311         if (err)
1312                 return err;
1313
1314         /* Make sure the PHY is not broken. Read idle error count,
1315          * and reset the PHY if it is maxed out.
1316          */
1317         regval = phy_read(phydev, MII_STAT1000);
1318         if ((regval & 0xFF) == 0xFF) {
1319                 phy_init_hw(phydev);
1320                 phydev->link = 0;
1321                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1322                         phydev->drv->config_intr(phydev);
1323                 return genphy_config_aneg(phydev);
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1330 {
1331         return 0;
1332 }
1333
1334 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1335 {
1336         u16 val;
1337
1338         switch (ctrl) {
1339         case ETH_TP_MDI:
1340                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1341                 break;
1342         case ETH_TP_MDI_X:
1343                 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1344                  * counter intuitive, the "-X" in "1 = Force MDI" in the data
1345                  * sheet seems to be missing:
1346                  * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1347                  * 0 = Normal operation (transmit on TX+/TX- pins)
1348                  */
1349                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1350                 break;
1351         case ETH_TP_MDI_AUTO:
1352                 val = 0;
1353                 break;
1354         default:
1355                 return 0;
1356         }
1357
1358         return phy_modify(phydev, MII_BMCR,
1359                           KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1360                           KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1361                           KSZ886X_BMCR_HP_MDIX | val);
1362 }
1363
1364 static int ksz886x_config_aneg(struct phy_device *phydev)
1365 {
1366         int ret;
1367
1368         ret = genphy_config_aneg(phydev);
1369         if (ret)
1370                 return ret;
1371
1372         /* The MDI-X configuration is automatically changed by the PHY after
1373          * switching from autoneg off to on. So, take MDI-X configuration under
1374          * own control and set it after autoneg configuration was done.
1375          */
1376         return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1377 }
1378
1379 static int ksz886x_mdix_update(struct phy_device *phydev)
1380 {
1381         int ret;
1382
1383         ret = phy_read(phydev, MII_BMCR);
1384         if (ret < 0)
1385                 return ret;
1386
1387         if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1388                 if (ret & KSZ886X_BMCR_FORCE_MDI)
1389                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1390                 else
1391                         phydev->mdix_ctrl = ETH_TP_MDI;
1392         } else {
1393                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1394         }
1395
1396         ret = phy_read(phydev, MII_KSZPHY_CTRL);
1397         if (ret < 0)
1398                 return ret;
1399
1400         /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1401         if (ret & KSZ886X_CTRL_MDIX_STAT)
1402                 phydev->mdix = ETH_TP_MDI_X;
1403         else
1404                 phydev->mdix = ETH_TP_MDI;
1405
1406         return 0;
1407 }
1408
1409 static int ksz886x_read_status(struct phy_device *phydev)
1410 {
1411         int ret;
1412
1413         ret = ksz886x_mdix_update(phydev);
1414         if (ret < 0)
1415                 return ret;
1416
1417         return genphy_read_status(phydev);
1418 }
1419
1420 static int kszphy_get_sset_count(struct phy_device *phydev)
1421 {
1422         return ARRAY_SIZE(kszphy_hw_stats);
1423 }
1424
1425 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1426 {
1427         int i;
1428
1429         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1430                 strlcpy(data + i * ETH_GSTRING_LEN,
1431                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1432         }
1433 }
1434
1435 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1436 {
1437         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1438         struct kszphy_priv *priv = phydev->priv;
1439         int val;
1440         u64 ret;
1441
1442         val = phy_read(phydev, stat.reg);
1443         if (val < 0) {
1444                 ret = U64_MAX;
1445         } else {
1446                 val = val & ((1 << stat.bits) - 1);
1447                 priv->stats[i] += val;
1448                 ret = priv->stats[i];
1449         }
1450
1451         return ret;
1452 }
1453
1454 static void kszphy_get_stats(struct phy_device *phydev,
1455                              struct ethtool_stats *stats, u64 *data)
1456 {
1457         int i;
1458
1459         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1460                 data[i] = kszphy_get_stat(phydev, i);
1461 }
1462
1463 static int kszphy_suspend(struct phy_device *phydev)
1464 {
1465         /* Disable PHY Interrupts */
1466         if (phy_interrupt_is_valid(phydev)) {
1467                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1468                 if (phydev->drv->config_intr)
1469                         phydev->drv->config_intr(phydev);
1470         }
1471
1472         return genphy_suspend(phydev);
1473 }
1474
1475 static int kszphy_resume(struct phy_device *phydev)
1476 {
1477         int ret;
1478
1479         genphy_resume(phydev);
1480
1481         /* After switching from power-down to normal mode, an internal global
1482          * reset is automatically generated. Wait a minimum of 1 ms before
1483          * read/write access to the PHY registers.
1484          */
1485         usleep_range(1000, 2000);
1486
1487         ret = kszphy_config_reset(phydev);
1488         if (ret)
1489                 return ret;
1490
1491         /* Enable PHY Interrupts */
1492         if (phy_interrupt_is_valid(phydev)) {
1493                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1494                 if (phydev->drv->config_intr)
1495                         phydev->drv->config_intr(phydev);
1496         }
1497
1498         return 0;
1499 }
1500
1501 static int kszphy_probe(struct phy_device *phydev)
1502 {
1503         const struct kszphy_type *type = phydev->drv->driver_data;
1504         const struct device_node *np = phydev->mdio.dev.of_node;
1505         struct kszphy_priv *priv;
1506         struct clk *clk;
1507         int ret;
1508
1509         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1510         if (!priv)
1511                 return -ENOMEM;
1512
1513         phydev->priv = priv;
1514
1515         priv->type = type;
1516
1517         if (type->led_mode_reg) {
1518                 ret = of_property_read_u32(np, "micrel,led-mode",
1519                                 &priv->led_mode);
1520                 if (ret)
1521                         priv->led_mode = -1;
1522
1523                 if (priv->led_mode > 3) {
1524                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
1525                                    priv->led_mode);
1526                         priv->led_mode = -1;
1527                 }
1528         } else {
1529                 priv->led_mode = -1;
1530         }
1531
1532         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1533         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1534         if (!IS_ERR_OR_NULL(clk)) {
1535                 unsigned long rate = clk_get_rate(clk);
1536                 bool rmii_ref_clk_sel_25_mhz;
1537
1538                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1539                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1540                                 "micrel,rmii-reference-clock-select-25-mhz");
1541
1542                 if (rate > 24500000 && rate < 25500000) {
1543                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1544                 } else if (rate > 49500000 && rate < 50500000) {
1545                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1546                 } else {
1547                         phydev_err(phydev, "Clock rate out of range: %ld\n",
1548                                    rate);
1549                         return -EINVAL;
1550                 }
1551         }
1552
1553         if (ksz8041_fiber_mode(phydev))
1554                 phydev->port = PORT_FIBRE;
1555
1556         /* Support legacy board-file configuration */
1557         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1558                 priv->rmii_ref_clk_sel = true;
1559                 priv->rmii_ref_clk_sel_val = true;
1560         }
1561
1562         return 0;
1563 }
1564
1565 static int ksz886x_cable_test_start(struct phy_device *phydev)
1566 {
1567         if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1568                 return -EOPNOTSUPP;
1569
1570         /* If autoneg is enabled, we won't be able to test cross pair
1571          * short. In this case, the PHY will "detect" a link and
1572          * confuse the internal state machine - disable auto neg here.
1573          * If autoneg is disabled, we should set the speed to 10mbit.
1574          */
1575         return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1576 }
1577
1578 static int ksz886x_cable_test_result_trans(u16 status)
1579 {
1580         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1581         case KSZ8081_LMD_STAT_NORMAL:
1582                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1583         case KSZ8081_LMD_STAT_SHORT:
1584                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1585         case KSZ8081_LMD_STAT_OPEN:
1586                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1587         case KSZ8081_LMD_STAT_FAIL:
1588                 fallthrough;
1589         default:
1590                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1591         }
1592 }
1593
1594 static bool ksz886x_cable_test_failed(u16 status)
1595 {
1596         return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1597                 KSZ8081_LMD_STAT_FAIL;
1598 }
1599
1600 static bool ksz886x_cable_test_fault_length_valid(u16 status)
1601 {
1602         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1603         case KSZ8081_LMD_STAT_OPEN:
1604                 fallthrough;
1605         case KSZ8081_LMD_STAT_SHORT:
1606                 return true;
1607         }
1608         return false;
1609 }
1610
1611 static int ksz886x_cable_test_fault_length(u16 status)
1612 {
1613         int dt;
1614
1615         /* According to the data sheet the distance to the fault is
1616          * DELTA_TIME * 0.4 meters.
1617          */
1618         dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1619
1620         return (dt * 400) / 10;
1621 }
1622
1623 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1624 {
1625         int val, ret;
1626
1627         ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1628                                     !(val & KSZ8081_LMD_ENABLE_TEST),
1629                                     30000, 100000, true);
1630
1631         return ret < 0 ? ret : 0;
1632 }
1633
1634 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1635 {
1636         static const int ethtool_pair[] = {
1637                 ETHTOOL_A_CABLE_PAIR_A,
1638                 ETHTOOL_A_CABLE_PAIR_B,
1639         };
1640         int ret, val, mdix;
1641
1642         /* There is no way to choice the pair, like we do one ksz9031.
1643          * We can workaround this limitation by using the MDI-X functionality.
1644          */
1645         if (pair == 0)
1646                 mdix = ETH_TP_MDI;
1647         else
1648                 mdix = ETH_TP_MDI_X;
1649
1650         switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1651         case PHY_ID_KSZ8081:
1652                 ret = ksz8081_config_mdix(phydev, mdix);
1653                 break;
1654         case PHY_ID_KSZ886X:
1655                 ret = ksz886x_config_mdix(phydev, mdix);
1656                 break;
1657         default:
1658                 ret = -ENODEV;
1659         }
1660
1661         if (ret)
1662                 return ret;
1663
1664         /* Now we are ready to fire. This command will send a 100ns pulse
1665          * to the pair.
1666          */
1667         ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1668         if (ret)
1669                 return ret;
1670
1671         ret = ksz886x_cable_test_wait_for_completion(phydev);
1672         if (ret)
1673                 return ret;
1674
1675         val = phy_read(phydev, KSZ8081_LMD);
1676         if (val < 0)
1677                 return val;
1678
1679         if (ksz886x_cable_test_failed(val))
1680                 return -EAGAIN;
1681
1682         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1683                                       ksz886x_cable_test_result_trans(val));
1684         if (ret)
1685                 return ret;
1686
1687         if (!ksz886x_cable_test_fault_length_valid(val))
1688                 return 0;
1689
1690         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1691                                              ksz886x_cable_test_fault_length(val));
1692 }
1693
1694 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1695                                          bool *finished)
1696 {
1697         unsigned long pair_mask = 0x3;
1698         int retries = 20;
1699         int pair, ret;
1700
1701         *finished = false;
1702
1703         /* Try harder if link partner is active */
1704         while (pair_mask && retries--) {
1705                 for_each_set_bit(pair, &pair_mask, 4) {
1706                         ret = ksz886x_cable_test_one_pair(phydev, pair);
1707                         if (ret == -EAGAIN)
1708                                 continue;
1709                         if (ret < 0)
1710                                 return ret;
1711                         clear_bit(pair, &pair_mask);
1712                 }
1713                 /* If link partner is in autonegotiation mode it will send 2ms
1714                  * of FLPs with at least 6ms of silence.
1715                  * Add 2ms sleep to have better chances to hit this silence.
1716                  */
1717                 if (pair_mask)
1718                         msleep(2);
1719         }
1720
1721         *finished = true;
1722
1723         return ret;
1724 }
1725
1726 #define LAN_EXT_PAGE_ACCESS_CONTROL                     0x16
1727 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA                0x17
1728 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC                0x4000
1729
1730 #define LAN8814_QSGMII_SOFT_RESET                       0x43
1731 #define LAN8814_QSGMII_SOFT_RESET_BIT                   BIT(0)
1732 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG                0x13
1733 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA       BIT(3)
1734 #define LAN8814_ALIGN_SWAP                              0x4a
1735 #define LAN8814_ALIGN_TX_A_B_SWAP                       0x1
1736 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1737
1738 #define LAN8804_ALIGN_SWAP                              0x4a
1739 #define LAN8804_ALIGN_TX_A_B_SWAP                       0x1
1740 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1741 #define LAN8814_CLOCK_MANAGEMENT                        0xd
1742 #define LAN8814_LINK_QUALITY                            0x8e
1743
1744 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
1745 {
1746         u32 data;
1747
1748         phy_lock_mdio_bus(phydev);
1749         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1750         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1751         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1752                     (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1753         data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
1754         phy_unlock_mdio_bus(phydev);
1755
1756         return data;
1757 }
1758
1759 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
1760                                  u16 val)
1761 {
1762         phy_lock_mdio_bus(phydev);
1763         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1764         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1765         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1766                     page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
1767
1768         val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
1769         if (val != 0)
1770                 phydev_err(phydev, "Error: phy_write has returned error %d\n",
1771                            val);
1772         phy_unlock_mdio_bus(phydev);
1773         return val;
1774 }
1775
1776 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
1777 {
1778         u16 val = 0;
1779
1780         if (enable)
1781                 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
1782                       PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
1783                       PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
1784                       PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
1785
1786         return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
1787 }
1788
1789 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
1790                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
1791 {
1792         *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
1793         *seconds = (*seconds << 16) |
1794                    lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
1795
1796         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
1797         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
1798                         lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
1799
1800         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
1801 }
1802
1803 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
1804                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
1805 {
1806         *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
1807         *seconds = *seconds << 16 |
1808                    lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
1809
1810         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
1811         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
1812                         lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
1813
1814         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
1815 }
1816
1817 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
1818 {
1819         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
1820         struct phy_device *phydev = ptp_priv->phydev;
1821         struct lan8814_shared_priv *shared = phydev->shared->priv;
1822
1823         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1824                                 SOF_TIMESTAMPING_RX_HARDWARE |
1825                                 SOF_TIMESTAMPING_RAW_HARDWARE;
1826
1827         info->phc_index = ptp_clock_index(shared->ptp_clock);
1828
1829         info->tx_types =
1830                 (1 << HWTSTAMP_TX_OFF) |
1831                 (1 << HWTSTAMP_TX_ON) |
1832                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1833
1834         info->rx_filters =
1835                 (1 << HWTSTAMP_FILTER_NONE) |
1836                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1837                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1838                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1839                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1840
1841         return 0;
1842 }
1843
1844 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
1845 {
1846         int i;
1847
1848         for (i = 0; i < FIFO_SIZE; ++i)
1849                 lanphy_read_page_reg(phydev, 5,
1850                                      egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
1851
1852         /* Read to clear overflow status bit */
1853         lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
1854 }
1855
1856 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
1857 {
1858         struct kszphy_ptp_priv *ptp_priv =
1859                           container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
1860         struct phy_device *phydev = ptp_priv->phydev;
1861         struct lan8814_shared_priv *shared = phydev->shared->priv;
1862         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
1863         struct hwtstamp_config config;
1864         int txcfg = 0, rxcfg = 0;
1865         int pkt_ts_enable;
1866
1867         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1868                 return -EFAULT;
1869
1870         ptp_priv->hwts_tx_type = config.tx_type;
1871         ptp_priv->rx_filter = config.rx_filter;
1872
1873         switch (config.rx_filter) {
1874         case HWTSTAMP_FILTER_NONE:
1875                 ptp_priv->layer = 0;
1876                 ptp_priv->version = 0;
1877                 break;
1878         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1879         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1880         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1881                 ptp_priv->layer = PTP_CLASS_L4;
1882                 ptp_priv->version = PTP_CLASS_V2;
1883                 break;
1884         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1885         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1886         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1887                 ptp_priv->layer = PTP_CLASS_L2;
1888                 ptp_priv->version = PTP_CLASS_V2;
1889                 break;
1890         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1891         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1892         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1893                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1894                 ptp_priv->version = PTP_CLASS_V2;
1895                 break;
1896         default:
1897                 return -ERANGE;
1898         }
1899
1900         if (ptp_priv->layer & PTP_CLASS_L2) {
1901                 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
1902                 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
1903         } else if (ptp_priv->layer & PTP_CLASS_L4) {
1904                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
1905                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
1906         }
1907         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
1908         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
1909
1910         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
1911                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
1912         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
1913         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
1914
1915         if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
1916                 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
1917                                       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
1918
1919         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
1920                 lan8814_config_ts_intr(ptp_priv->phydev, true);
1921         else
1922                 lan8814_config_ts_intr(ptp_priv->phydev, false);
1923
1924         mutex_lock(&shared->shared_lock);
1925         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
1926                 shared->ref++;
1927         else
1928                 shared->ref--;
1929
1930         if (shared->ref)
1931                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
1932                                       PTP_CMD_CTL_PTP_ENABLE_);
1933         else
1934                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
1935                                       PTP_CMD_CTL_PTP_DISABLE_);
1936         mutex_unlock(&shared->shared_lock);
1937
1938         /* In case of multiple starts and stops, these needs to be cleared */
1939         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
1940                 list_del(&rx_ts->list);
1941                 kfree(rx_ts);
1942         }
1943         skb_queue_purge(&ptp_priv->rx_queue);
1944         skb_queue_purge(&ptp_priv->tx_queue);
1945
1946         lan8814_flush_fifo(ptp_priv->phydev, false);
1947         lan8814_flush_fifo(ptp_priv->phydev, true);
1948
1949         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
1950 }
1951
1952 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
1953                              struct sk_buff *skb, int type)
1954 {
1955         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
1956
1957         switch (ptp_priv->hwts_tx_type) {
1958         case HWTSTAMP_TX_ONESTEP_SYNC:
1959                 if (ptp_msg_is_sync(skb, type)) {
1960                         kfree_skb(skb);
1961                         return;
1962                 }
1963                 fallthrough;
1964         case HWTSTAMP_TX_ON:
1965                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1966                 skb_queue_tail(&ptp_priv->tx_queue, skb);
1967                 break;
1968         case HWTSTAMP_TX_OFF:
1969         default:
1970                 kfree_skb(skb);
1971                 break;
1972         }
1973 }
1974
1975 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
1976 {
1977         struct ptp_header *ptp_header;
1978         u32 type;
1979
1980         skb_push(skb, ETH_HLEN);
1981         type = ptp_classify_raw(skb);
1982         ptp_header = ptp_parse_header(skb, type);
1983         skb_pull_inline(skb, ETH_HLEN);
1984
1985         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
1986 }
1987
1988 static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
1989                                 struct sk_buff *skb)
1990 {
1991         struct skb_shared_hwtstamps *shhwtstamps;
1992         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
1993         unsigned long flags;
1994         bool ret = false;
1995         u16 skb_sig;
1996
1997         lan8814_get_sig_rx(skb, &skb_sig);
1998
1999         /* Iterate over all RX timestamps and match it with the received skbs */
2000         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2001         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2002                 /* Check if we found the signature we were looking for. */
2003                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2004                         continue;
2005
2006                 shhwtstamps = skb_hwtstamps(skb);
2007                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2008                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2009                                                   rx_ts->nsec);
2010                 list_del(&rx_ts->list);
2011                 kfree(rx_ts);
2012
2013                 ret = true;
2014                 break;
2015         }
2016         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2017
2018         if (ret)
2019                 netif_rx(skb);
2020         return ret;
2021 }
2022
2023 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2024 {
2025         struct kszphy_ptp_priv *ptp_priv =
2026                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2027
2028         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2029             type == PTP_CLASS_NONE)
2030                 return false;
2031
2032         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2033                 return false;
2034
2035         /* If we failed to match then add it to the queue for when the timestamp
2036          * will come
2037          */
2038         if (!lan8814_match_rx_ts(ptp_priv, skb))
2039                 skb_queue_tail(&ptp_priv->rx_queue, skb);
2040
2041         return true;
2042 }
2043
2044 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2045                                   u32 seconds, u32 nano_seconds)
2046 {
2047         u32 sec_low, sec_high, nsec_low, nsec_high;
2048
2049         sec_low = seconds & 0xffff;
2050         sec_high = (seconds >> 16) & 0xffff;
2051         nsec_low = nano_seconds & 0xffff;
2052         nsec_high = (nano_seconds >> 16) & 0x3fff;
2053
2054         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2055         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2056         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2057         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2058
2059         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2060 }
2061
2062 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2063                                   u32 *seconds, u32 *nano_seconds)
2064 {
2065         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2066
2067         *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2068         *seconds = (*seconds << 16) |
2069                    lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2070
2071         *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2072         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2073                         lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2074 }
2075
2076 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2077                                    struct timespec64 *ts)
2078 {
2079         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2080                                                           ptp_clock_info);
2081         struct phy_device *phydev = shared->phydev;
2082         u32 nano_seconds;
2083         u32 seconds;
2084
2085         mutex_lock(&shared->shared_lock);
2086         lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2087         mutex_unlock(&shared->shared_lock);
2088         ts->tv_sec = seconds;
2089         ts->tv_nsec = nano_seconds;
2090
2091         return 0;
2092 }
2093
2094 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2095                                    const struct timespec64 *ts)
2096 {
2097         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2098                                                           ptp_clock_info);
2099         struct phy_device *phydev = shared->phydev;
2100
2101         mutex_lock(&shared->shared_lock);
2102         lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2103         mutex_unlock(&shared->shared_lock);
2104
2105         return 0;
2106 }
2107
2108 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2109                                    s64 time_step_ns)
2110 {
2111         u32 nano_seconds_step;
2112         u64 abs_time_step_ns;
2113         u32 unsigned_seconds;
2114         u32 nano_seconds;
2115         u32 remainder;
2116         s32 seconds;
2117
2118         if (time_step_ns >  15000000000LL) {
2119                 /* convert to clock set */
2120                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2121                 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2122                                                 &remainder);
2123                 nano_seconds += remainder;
2124                 if (nano_seconds >= 1000000000) {
2125                         unsigned_seconds++;
2126                         nano_seconds -= 1000000000;
2127                 }
2128                 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2129                 return;
2130         } else if (time_step_ns < -15000000000LL) {
2131                 /* convert to clock set */
2132                 time_step_ns = -time_step_ns;
2133
2134                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2135                 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2136                                                 &remainder);
2137                 nano_seconds_step = remainder;
2138                 if (nano_seconds < nano_seconds_step) {
2139                         unsigned_seconds--;
2140                         nano_seconds += 1000000000;
2141                 }
2142                 nano_seconds -= nano_seconds_step;
2143                 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2144                                       nano_seconds);
2145                 return;
2146         }
2147
2148         /* do clock step */
2149         if (time_step_ns >= 0) {
2150                 abs_time_step_ns = (u64)time_step_ns;
2151                 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2152                                            &remainder);
2153                 nano_seconds = remainder;
2154         } else {
2155                 abs_time_step_ns = (u64)(-time_step_ns);
2156                 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2157                             &remainder));
2158                 nano_seconds = remainder;
2159                 if (nano_seconds > 0) {
2160                         /* subtracting nano seconds is not allowed
2161                          * convert to subtracting from seconds,
2162                          * and adding to nanoseconds
2163                          */
2164                         seconds--;
2165                         nano_seconds = (1000000000 - nano_seconds);
2166                 }
2167         }
2168
2169         if (nano_seconds > 0) {
2170                 /* add 8 ns to cover the likely normal increment */
2171                 nano_seconds += 8;
2172         }
2173
2174         if (nano_seconds >= 1000000000) {
2175                 /* carry into seconds */
2176                 seconds++;
2177                 nano_seconds -= 1000000000;
2178         }
2179
2180         while (seconds) {
2181                 if (seconds > 0) {
2182                         u32 adjustment_value = (u32)seconds;
2183                         u16 adjustment_value_lo, adjustment_value_hi;
2184
2185                         if (adjustment_value > 0xF)
2186                                 adjustment_value = 0xF;
2187
2188                         adjustment_value_lo = adjustment_value & 0xffff;
2189                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2190
2191                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2192                                               adjustment_value_lo);
2193                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2194                                               PTP_LTC_STEP_ADJ_DIR_ |
2195                                               adjustment_value_hi);
2196                         seconds -= ((s32)adjustment_value);
2197                 } else {
2198                         u32 adjustment_value = (u32)(-seconds);
2199                         u16 adjustment_value_lo, adjustment_value_hi;
2200
2201                         if (adjustment_value > 0xF)
2202                                 adjustment_value = 0xF;
2203
2204                         adjustment_value_lo = adjustment_value & 0xffff;
2205                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2206
2207                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2208                                               adjustment_value_lo);
2209                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2210                                               adjustment_value_hi);
2211                         seconds += ((s32)adjustment_value);
2212                 }
2213                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2214                                       PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2215         }
2216         if (nano_seconds) {
2217                 u16 nano_seconds_lo;
2218                 u16 nano_seconds_hi;
2219
2220                 nano_seconds_lo = nano_seconds & 0xffff;
2221                 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2222
2223                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2224                                       nano_seconds_lo);
2225                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2226                                       PTP_LTC_STEP_ADJ_DIR_ |
2227                                       nano_seconds_hi);
2228                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2229                                       PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2230         }
2231 }
2232
2233 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2234 {
2235         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2236                                                           ptp_clock_info);
2237         struct phy_device *phydev = shared->phydev;
2238
2239         mutex_lock(&shared->shared_lock);
2240         lan8814_ptp_clock_step(phydev, delta);
2241         mutex_unlock(&shared->shared_lock);
2242
2243         return 0;
2244 }
2245
2246 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2247 {
2248         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2249                                                           ptp_clock_info);
2250         struct phy_device *phydev = shared->phydev;
2251         u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2252         bool positive = true;
2253         u32 kszphy_rate_adj;
2254
2255         if (scaled_ppm < 0) {
2256                 scaled_ppm = -scaled_ppm;
2257                 positive = false;
2258         }
2259
2260         kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2261         kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2262
2263         kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2264         kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2265
2266         if (positive)
2267                 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2268
2269         mutex_lock(&shared->shared_lock);
2270         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2271         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2272         mutex_unlock(&shared->shared_lock);
2273
2274         return 0;
2275 }
2276
2277 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2278 {
2279         struct ptp_header *ptp_header;
2280         u32 type;
2281
2282         type = ptp_classify_raw(skb);
2283         ptp_header = ptp_parse_header(skb, type);
2284
2285         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2286 }
2287
2288 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2289 {
2290         struct phy_device *phydev = ptp_priv->phydev;
2291         struct skb_shared_hwtstamps shhwtstamps;
2292         struct sk_buff *skb, *skb_tmp;
2293         unsigned long flags;
2294         u32 seconds, nsec;
2295         bool ret = false;
2296         u16 skb_sig;
2297         u16 seq_id;
2298
2299         lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2300
2301         spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2302         skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2303                 lan8814_get_sig_tx(skb, &skb_sig);
2304
2305                 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2306                         continue;
2307
2308                 __skb_unlink(skb, &ptp_priv->tx_queue);
2309                 ret = true;
2310                 break;
2311         }
2312         spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2313
2314         if (ret) {
2315                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2316                 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2317                 skb_complete_tx_timestamp(skb, &shhwtstamps);
2318         }
2319 }
2320
2321 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2322 {
2323         struct phy_device *phydev = ptp_priv->phydev;
2324         u32 reg;
2325
2326         do {
2327                 lan8814_dequeue_tx_skb(ptp_priv);
2328
2329                 /* If other timestamps are available in the FIFO,
2330                  * process them.
2331                  */
2332                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2333         } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2334 }
2335
2336 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2337                               struct lan8814_ptp_rx_ts *rx_ts)
2338 {
2339         struct skb_shared_hwtstamps *shhwtstamps;
2340         struct sk_buff *skb, *skb_tmp;
2341         unsigned long flags;
2342         bool ret = false;
2343         u16 skb_sig;
2344
2345         spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2346         skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2347                 lan8814_get_sig_rx(skb, &skb_sig);
2348
2349                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2350                         continue;
2351
2352                 __skb_unlink(skb, &ptp_priv->rx_queue);
2353
2354                 ret = true;
2355                 break;
2356         }
2357         spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2358
2359         if (ret) {
2360                 shhwtstamps = skb_hwtstamps(skb);
2361                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2362                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2363                 netif_rx(skb);
2364         }
2365
2366         return ret;
2367 }
2368
2369 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2370 {
2371         struct phy_device *phydev = ptp_priv->phydev;
2372         struct lan8814_ptp_rx_ts *rx_ts;
2373         unsigned long flags;
2374         u32 reg;
2375
2376         do {
2377                 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2378                 if (!rx_ts)
2379                         return;
2380
2381                 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2382                                       &rx_ts->seq_id);
2383
2384                 /* If we failed to match the skb add it to the queue for when
2385                  * the frame will come
2386                  */
2387                 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2388                         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2389                         list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2390                         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2391                 } else {
2392                         kfree(rx_ts);
2393                 }
2394
2395                 /* If other timestamps are available in the FIFO,
2396                  * process them.
2397                  */
2398                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2399         } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2400 }
2401
2402 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2403 {
2404         struct kszphy_priv *priv = phydev->priv;
2405         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2406         u16 status;
2407
2408         status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2409         if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2410                 lan8814_get_tx_ts(ptp_priv);
2411
2412         if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2413                 lan8814_get_rx_ts(ptp_priv);
2414
2415         if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2416                 lan8814_flush_fifo(phydev, true);
2417                 skb_queue_purge(&ptp_priv->tx_queue);
2418         }
2419
2420         if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2421                 lan8814_flush_fifo(phydev, false);
2422                 skb_queue_purge(&ptp_priv->rx_queue);
2423         }
2424 }
2425
2426 static int lan8804_config_init(struct phy_device *phydev)
2427 {
2428         int val;
2429
2430         /* MDI-X setting for swap A,B transmit */
2431         val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2432         val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2433         val |= LAN8804_ALIGN_TX_A_B_SWAP;
2434         lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2435
2436         /* Make sure that the PHY will not stop generating the clock when the
2437          * link partner goes down
2438          */
2439         lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2440         lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2441
2442         return 0;
2443 }
2444
2445 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2446 {
2447         u16 tsu_irq_status;
2448         int irq_status;
2449
2450         irq_status = phy_read(phydev, LAN8814_INTS);
2451         if (irq_status > 0 && (irq_status & LAN8814_INT_LINK))
2452                 phy_trigger_machine(phydev);
2453
2454         if (irq_status < 0) {
2455                 phy_error(phydev);
2456                 return IRQ_NONE;
2457         }
2458
2459         while (1) {
2460                 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2461                                                       LAN8814_INTR_STS_REG);
2462
2463                 if (tsu_irq_status > 0 &&
2464                     (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2465                                        LAN8814_INTR_STS_REG_1588_TSU1_ |
2466                                        LAN8814_INTR_STS_REG_1588_TSU2_ |
2467                                        LAN8814_INTR_STS_REG_1588_TSU3_)))
2468                         lan8814_handle_ptp_interrupt(phydev);
2469                 else
2470                         break;
2471         }
2472         return IRQ_HANDLED;
2473 }
2474
2475 static int lan8814_ack_interrupt(struct phy_device *phydev)
2476 {
2477         /* bit[12..0] int status, which is a read and clear register. */
2478         int rc;
2479
2480         rc = phy_read(phydev, LAN8814_INTS);
2481
2482         return (rc < 0) ? rc : 0;
2483 }
2484
2485 static int lan8814_config_intr(struct phy_device *phydev)
2486 {
2487         int err;
2488
2489         lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
2490                               LAN8814_INTR_CTRL_REG_POLARITY |
2491                               LAN8814_INTR_CTRL_REG_INTR_ENABLE);
2492
2493         /* enable / disable interrupts */
2494         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2495                 err = lan8814_ack_interrupt(phydev);
2496                 if (err)
2497                         return err;
2498
2499                 err =  phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2500         } else {
2501                 err =  phy_write(phydev, LAN8814_INTC, 0);
2502                 if (err)
2503                         return err;
2504
2505                 err = lan8814_ack_interrupt(phydev);
2506         }
2507
2508         return err;
2509 }
2510
2511 static void lan8814_ptp_init(struct phy_device *phydev)
2512 {
2513         struct kszphy_priv *priv = phydev->priv;
2514         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2515         u32 temp;
2516
2517         lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
2518
2519         temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
2520         temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2521         lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
2522
2523         temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
2524         temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2525         lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
2526
2527         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
2528         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
2529
2530         /* Removing default registers configs related to L2 and IP */
2531         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
2532         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
2533         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
2534         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
2535
2536         skb_queue_head_init(&ptp_priv->tx_queue);
2537         skb_queue_head_init(&ptp_priv->rx_queue);
2538         INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
2539         spin_lock_init(&ptp_priv->rx_ts_lock);
2540
2541         ptp_priv->phydev = phydev;
2542
2543         ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
2544         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
2545         ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
2546         ptp_priv->mii_ts.ts_info  = lan8814_ts_info;
2547
2548         phydev->mii_ts = &ptp_priv->mii_ts;
2549 }
2550
2551 static int lan8814_ptp_probe_once(struct phy_device *phydev)
2552 {
2553         struct lan8814_shared_priv *shared = phydev->shared->priv;
2554
2555         /* Initialise shared lock for clock*/
2556         mutex_init(&shared->shared_lock);
2557
2558         shared->ptp_clock_info.owner = THIS_MODULE;
2559         snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
2560         shared->ptp_clock_info.max_adj = 31249999;
2561         shared->ptp_clock_info.n_alarm = 0;
2562         shared->ptp_clock_info.n_ext_ts = 0;
2563         shared->ptp_clock_info.n_pins = 0;
2564         shared->ptp_clock_info.pps = 0;
2565         shared->ptp_clock_info.pin_config = NULL;
2566         shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
2567         shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
2568         shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
2569         shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
2570         shared->ptp_clock_info.getcrosststamp = NULL;
2571
2572         shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
2573                                                &phydev->mdio.dev);
2574         if (IS_ERR_OR_NULL(shared->ptp_clock)) {
2575                 phydev_err(phydev, "ptp_clock_register failed %lu\n",
2576                            PTR_ERR(shared->ptp_clock));
2577                 return -EINVAL;
2578         }
2579
2580         phydev_dbg(phydev, "successfully registered ptp clock\n");
2581
2582         shared->phydev = phydev;
2583
2584         /* The EP.4 is shared between all the PHYs in the package and also it
2585          * can be accessed by any of the PHYs
2586          */
2587         lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
2588         lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
2589                               PTP_OPERATING_MODE_STANDALONE_);
2590
2591         return 0;
2592 }
2593
2594 static int lan8814_config_init(struct phy_device *phydev)
2595 {
2596         int val;
2597
2598         /* Reset the PHY */
2599         val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
2600         val |= LAN8814_QSGMII_SOFT_RESET_BIT;
2601         lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
2602
2603         /* Disable ANEG with QSGMII PCS Host side */
2604         val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
2605         val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
2606         lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
2607
2608         /* MDI-X setting for swap A,B transmit */
2609         val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
2610         val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
2611         val |= LAN8814_ALIGN_TX_A_B_SWAP;
2612         lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
2613
2614         return 0;
2615 }
2616
2617 static int lan8814_probe(struct phy_device *phydev)
2618 {
2619         struct kszphy_priv *priv;
2620         u16 addr;
2621         int err;
2622
2623         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2624         if (!priv)
2625                 return -ENOMEM;
2626
2627         priv->led_mode = -1;
2628
2629         phydev->priv = priv;
2630
2631         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2632             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2633                 return 0;
2634
2635         /* Strap-in value for PHY address, below register read gives starting
2636          * phy address value
2637          */
2638         addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
2639         devm_phy_package_join(&phydev->mdio.dev, phydev,
2640                               addr, sizeof(struct lan8814_shared_priv));
2641
2642         if (phy_package_init_once(phydev)) {
2643                 err = lan8814_ptp_probe_once(phydev);
2644                 if (err)
2645                         return err;
2646         }
2647
2648         lan8814_ptp_init(phydev);
2649
2650         return 0;
2651 }
2652
2653 static struct phy_driver ksphy_driver[] = {
2654 {
2655         .phy_id         = PHY_ID_KS8737,
2656         .phy_id_mask    = MICREL_PHY_ID_MASK,
2657         .name           = "Micrel KS8737",
2658         /* PHY_BASIC_FEATURES */
2659         .driver_data    = &ks8737_type,
2660         .config_init    = kszphy_config_init,
2661         .config_intr    = kszphy_config_intr,
2662         .handle_interrupt = kszphy_handle_interrupt,
2663         .suspend        = kszphy_suspend,
2664         .resume         = kszphy_resume,
2665 }, {
2666         .phy_id         = PHY_ID_KSZ8021,
2667         .phy_id_mask    = 0x00ffffff,
2668         .name           = "Micrel KSZ8021 or KSZ8031",
2669         /* PHY_BASIC_FEATURES */
2670         .driver_data    = &ksz8021_type,
2671         .probe          = kszphy_probe,
2672         .config_init    = kszphy_config_init,
2673         .config_intr    = kszphy_config_intr,
2674         .handle_interrupt = kszphy_handle_interrupt,
2675         .get_sset_count = kszphy_get_sset_count,
2676         .get_strings    = kszphy_get_strings,
2677         .get_stats      = kszphy_get_stats,
2678         .suspend        = kszphy_suspend,
2679         .resume         = kszphy_resume,
2680 }, {
2681         .phy_id         = PHY_ID_KSZ8031,
2682         .phy_id_mask    = 0x00ffffff,
2683         .name           = "Micrel KSZ8031",
2684         /* PHY_BASIC_FEATURES */
2685         .driver_data    = &ksz8021_type,
2686         .probe          = kszphy_probe,
2687         .config_init    = kszphy_config_init,
2688         .config_intr    = kszphy_config_intr,
2689         .handle_interrupt = kszphy_handle_interrupt,
2690         .get_sset_count = kszphy_get_sset_count,
2691         .get_strings    = kszphy_get_strings,
2692         .get_stats      = kszphy_get_stats,
2693         .suspend        = kszphy_suspend,
2694         .resume         = kszphy_resume,
2695 }, {
2696         .phy_id         = PHY_ID_KSZ8041,
2697         .phy_id_mask    = MICREL_PHY_ID_MASK,
2698         .name           = "Micrel KSZ8041",
2699         /* PHY_BASIC_FEATURES */
2700         .driver_data    = &ksz8041_type,
2701         .probe          = kszphy_probe,
2702         .config_init    = ksz8041_config_init,
2703         .config_aneg    = ksz8041_config_aneg,
2704         .config_intr    = kszphy_config_intr,
2705         .handle_interrupt = kszphy_handle_interrupt,
2706         .get_sset_count = kszphy_get_sset_count,
2707         .get_strings    = kszphy_get_strings,
2708         .get_stats      = kszphy_get_stats,
2709         /* No suspend/resume callbacks because of errata DS80000700A,
2710          * receiver error following software power down.
2711          */
2712 }, {
2713         .phy_id         = PHY_ID_KSZ8041RNLI,
2714         .phy_id_mask    = MICREL_PHY_ID_MASK,
2715         .name           = "Micrel KSZ8041RNLI",
2716         /* PHY_BASIC_FEATURES */
2717         .driver_data    = &ksz8041_type,
2718         .probe          = kszphy_probe,
2719         .config_init    = kszphy_config_init,
2720         .config_intr    = kszphy_config_intr,
2721         .handle_interrupt = kszphy_handle_interrupt,
2722         .get_sset_count = kszphy_get_sset_count,
2723         .get_strings    = kszphy_get_strings,
2724         .get_stats      = kszphy_get_stats,
2725         .suspend        = kszphy_suspend,
2726         .resume         = kszphy_resume,
2727 }, {
2728         .name           = "Micrel KSZ8051",
2729         /* PHY_BASIC_FEATURES */
2730         .driver_data    = &ksz8051_type,
2731         .probe          = kszphy_probe,
2732         .config_init    = kszphy_config_init,
2733         .config_intr    = kszphy_config_intr,
2734         .handle_interrupt = kszphy_handle_interrupt,
2735         .get_sset_count = kszphy_get_sset_count,
2736         .get_strings    = kszphy_get_strings,
2737         .get_stats      = kszphy_get_stats,
2738         .match_phy_device = ksz8051_match_phy_device,
2739         .suspend        = kszphy_suspend,
2740         .resume         = kszphy_resume,
2741 }, {
2742         .phy_id         = PHY_ID_KSZ8001,
2743         .name           = "Micrel KSZ8001 or KS8721",
2744         .phy_id_mask    = 0x00fffffc,
2745         /* PHY_BASIC_FEATURES */
2746         .driver_data    = &ksz8041_type,
2747         .probe          = kszphy_probe,
2748         .config_init    = kszphy_config_init,
2749         .config_intr    = kszphy_config_intr,
2750         .handle_interrupt = kszphy_handle_interrupt,
2751         .get_sset_count = kszphy_get_sset_count,
2752         .get_strings    = kszphy_get_strings,
2753         .get_stats      = kszphy_get_stats,
2754         .suspend        = kszphy_suspend,
2755         .resume         = kszphy_resume,
2756 }, {
2757         .phy_id         = PHY_ID_KSZ8081,
2758         .name           = "Micrel KSZ8081 or KSZ8091",
2759         .phy_id_mask    = MICREL_PHY_ID_MASK,
2760         .flags          = PHY_POLL_CABLE_TEST,
2761         /* PHY_BASIC_FEATURES */
2762         .driver_data    = &ksz8081_type,
2763         .probe          = kszphy_probe,
2764         .config_init    = ksz8081_config_init,
2765         .soft_reset     = genphy_soft_reset,
2766         .config_aneg    = ksz8081_config_aneg,
2767         .read_status    = ksz8081_read_status,
2768         .config_intr    = kszphy_config_intr,
2769         .handle_interrupt = kszphy_handle_interrupt,
2770         .get_sset_count = kszphy_get_sset_count,
2771         .get_strings    = kszphy_get_strings,
2772         .get_stats      = kszphy_get_stats,
2773         .suspend        = kszphy_suspend,
2774         .resume         = kszphy_resume,
2775         .cable_test_start       = ksz886x_cable_test_start,
2776         .cable_test_get_status  = ksz886x_cable_test_get_status,
2777 }, {
2778         .phy_id         = PHY_ID_KSZ8061,
2779         .name           = "Micrel KSZ8061",
2780         .phy_id_mask    = MICREL_PHY_ID_MASK,
2781         /* PHY_BASIC_FEATURES */
2782         .config_init    = ksz8061_config_init,
2783         .config_intr    = kszphy_config_intr,
2784         .handle_interrupt = kszphy_handle_interrupt,
2785         .suspend        = kszphy_suspend,
2786         .resume         = kszphy_resume,
2787 }, {
2788         .phy_id         = PHY_ID_KSZ9021,
2789         .phy_id_mask    = 0x000ffffe,
2790         .name           = "Micrel KSZ9021 Gigabit PHY",
2791         /* PHY_GBIT_FEATURES */
2792         .driver_data    = &ksz9021_type,
2793         .probe          = kszphy_probe,
2794         .get_features   = ksz9031_get_features,
2795         .config_init    = ksz9021_config_init,
2796         .config_intr    = kszphy_config_intr,
2797         .handle_interrupt = kszphy_handle_interrupt,
2798         .get_sset_count = kszphy_get_sset_count,
2799         .get_strings    = kszphy_get_strings,
2800         .get_stats      = kszphy_get_stats,
2801         .suspend        = kszphy_suspend,
2802         .resume         = kszphy_resume,
2803         .read_mmd       = genphy_read_mmd_unsupported,
2804         .write_mmd      = genphy_write_mmd_unsupported,
2805 }, {
2806         .phy_id         = PHY_ID_KSZ9031,
2807         .phy_id_mask    = MICREL_PHY_ID_MASK,
2808         .name           = "Micrel KSZ9031 Gigabit PHY",
2809         .driver_data    = &ksz9021_type,
2810         .probe          = kszphy_probe,
2811         .get_features   = ksz9031_get_features,
2812         .config_init    = ksz9031_config_init,
2813         .soft_reset     = genphy_soft_reset,
2814         .read_status    = ksz9031_read_status,
2815         .config_intr    = kszphy_config_intr,
2816         .handle_interrupt = kszphy_handle_interrupt,
2817         .get_sset_count = kszphy_get_sset_count,
2818         .get_strings    = kszphy_get_strings,
2819         .get_stats      = kszphy_get_stats,
2820         .suspend        = kszphy_suspend,
2821         .resume         = kszphy_resume,
2822 }, {
2823         .phy_id         = PHY_ID_LAN8814,
2824         .phy_id_mask    = MICREL_PHY_ID_MASK,
2825         .name           = "Microchip INDY Gigabit Quad PHY",
2826         .config_init    = lan8814_config_init,
2827         .probe          = lan8814_probe,
2828         .soft_reset     = genphy_soft_reset,
2829         .read_status    = ksz9031_read_status,
2830         .get_sset_count = kszphy_get_sset_count,
2831         .get_strings    = kszphy_get_strings,
2832         .get_stats      = kszphy_get_stats,
2833         .suspend        = genphy_suspend,
2834         .resume         = kszphy_resume,
2835         .config_intr    = lan8814_config_intr,
2836         .handle_interrupt = lan8814_handle_interrupt,
2837 }, {
2838         .phy_id         = PHY_ID_LAN8804,
2839         .phy_id_mask    = MICREL_PHY_ID_MASK,
2840         .name           = "Microchip LAN966X Gigabit PHY",
2841         .config_init    = lan8804_config_init,
2842         .driver_data    = &ksz9021_type,
2843         .probe          = kszphy_probe,
2844         .soft_reset     = genphy_soft_reset,
2845         .read_status    = ksz9031_read_status,
2846         .get_sset_count = kszphy_get_sset_count,
2847         .get_strings    = kszphy_get_strings,
2848         .get_stats      = kszphy_get_stats,
2849         .suspend        = genphy_suspend,
2850         .resume         = kszphy_resume,
2851 }, {
2852         .phy_id         = PHY_ID_KSZ9131,
2853         .phy_id_mask    = MICREL_PHY_ID_MASK,
2854         .name           = "Microchip KSZ9131 Gigabit PHY",
2855         /* PHY_GBIT_FEATURES */
2856         .driver_data    = &ksz9021_type,
2857         .probe          = kszphy_probe,
2858         .config_init    = ksz9131_config_init,
2859         .config_intr    = kszphy_config_intr,
2860         .handle_interrupt = kszphy_handle_interrupt,
2861         .get_sset_count = kszphy_get_sset_count,
2862         .get_strings    = kszphy_get_strings,
2863         .get_stats      = kszphy_get_stats,
2864         .suspend        = kszphy_suspend,
2865         .resume         = kszphy_resume,
2866 }, {
2867         .phy_id         = PHY_ID_KSZ8873MLL,
2868         .phy_id_mask    = MICREL_PHY_ID_MASK,
2869         .name           = "Micrel KSZ8873MLL Switch",
2870         /* PHY_BASIC_FEATURES */
2871         .config_init    = kszphy_config_init,
2872         .config_aneg    = ksz8873mll_config_aneg,
2873         .read_status    = ksz8873mll_read_status,
2874         .suspend        = genphy_suspend,
2875         .resume         = genphy_resume,
2876 }, {
2877         .phy_id         = PHY_ID_KSZ886X,
2878         .phy_id_mask    = MICREL_PHY_ID_MASK,
2879         .name           = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
2880         /* PHY_BASIC_FEATURES */
2881         .flags          = PHY_POLL_CABLE_TEST,
2882         .config_init    = kszphy_config_init,
2883         .config_aneg    = ksz886x_config_aneg,
2884         .read_status    = ksz886x_read_status,
2885         .suspend        = genphy_suspend,
2886         .resume         = genphy_resume,
2887         .cable_test_start       = ksz886x_cable_test_start,
2888         .cable_test_get_status  = ksz886x_cable_test_get_status,
2889 }, {
2890         .name           = "Micrel KSZ87XX Switch",
2891         /* PHY_BASIC_FEATURES */
2892         .config_init    = kszphy_config_init,
2893         .match_phy_device = ksz8795_match_phy_device,
2894         .suspend        = genphy_suspend,
2895         .resume         = genphy_resume,
2896 }, {
2897         .phy_id         = PHY_ID_KSZ9477,
2898         .phy_id_mask    = MICREL_PHY_ID_MASK,
2899         .name           = "Microchip KSZ9477",
2900         /* PHY_GBIT_FEATURES */
2901         .config_init    = kszphy_config_init,
2902         .suspend        = genphy_suspend,
2903         .resume         = genphy_resume,
2904 } };
2905
2906 module_phy_driver(ksphy_driver);
2907
2908 MODULE_DESCRIPTION("Micrel PHY driver");
2909 MODULE_AUTHOR("David J. Choi");
2910 MODULE_LICENSE("GPL");
2911
2912 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
2913         { PHY_ID_KSZ9021, 0x000ffffe },
2914         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
2915         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
2916         { PHY_ID_KSZ8001, 0x00fffffc },
2917         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
2918         { PHY_ID_KSZ8021, 0x00ffffff },
2919         { PHY_ID_KSZ8031, 0x00ffffff },
2920         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
2921         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
2922         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
2923         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
2924         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
2925         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
2926         { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
2927         { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
2928         { }
2929 };
2930
2931 MODULE_DEVICE_TABLE(mdio, micrel_tbl);