1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
16 * With XAUI, observation shows:
18 * XAUI PHYXS -- <appropriate PCS as above>
20 * and no switching of the host interface mode occurs.
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
25 #include <linux/ctype.h>
26 #include <linux/delay.h>
27 #include <linux/hwmon.h>
28 #include <linux/marvell_phy.h>
29 #include <linux/phy.h>
30 #include <linux/sfp.h>
32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
36 MV_PMA_FW_VER0 = 0xc011,
37 MV_PMA_FW_VER1 = 0xc012,
38 MV_PMA_21X0_PORT_CTRL = 0xc04a,
39 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
40 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
41 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
42 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
43 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
44 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
46 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
48 MV_PMA_BOOT_FATAL = BIT(0),
50 MV_PCS_BASE_T = 0x0000,
51 MV_PCS_BASE_R = 0x1000,
52 MV_PCS_1000BASEX = 0x2000,
54 MV_PCS_CSCR1 = 0x8000,
55 MV_PCS_CSCR1_ED_MASK = 0x0300,
56 MV_PCS_CSCR1_ED_OFF = 0x0000,
57 MV_PCS_CSCR1_ED_RX = 0x0200,
58 MV_PCS_CSCR1_ED_NLP = 0x0300,
59 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
60 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
61 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
62 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
64 MV_PCS_CSSR1 = 0x8008,
65 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
66 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
67 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
68 MV_PCS_CSSR1_SPD1_100 = 0x4000,
69 MV_PCS_CSSR1_SPD1_10 = 0x0000,
70 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
71 MV_PCS_CSSR1_RESOLVED = BIT(11),
72 MV_PCS_CSSR1_MDIX = BIT(6),
73 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
74 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
75 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
76 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
78 /* Temperature read register (88E2110 only) */
81 /* Number of ports on the device */
82 MV_PCS_PORT_INFO = 0xd00d,
83 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
84 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
86 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
87 * registers appear to set themselves to the 0x800X when AN is
88 * restarted, but status registers appear readable from either.
90 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
91 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
93 /* Vendor2 MMD registers */
94 MV_V2_PORT_CTRL = 0xf001,
95 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
96 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
97 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
98 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
99 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
100 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
101 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
102 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
103 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
104 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
105 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
106 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
107 /* Temperature control/read registers (88X3310 only) */
108 MV_V2_TEMP_CTRL = 0xf08a,
109 MV_V2_TEMP_CTRL_MASK = 0xc000,
110 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
111 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
113 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
117 void (*init_supported_interfaces)(unsigned long *mask);
118 int (*get_mactype)(struct phy_device *phydev);
119 int (*init_interface)(struct phy_device *phydev, int mactype);
122 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
127 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
131 phy_interface_t const_interface;
133 struct device *hwmon_dev;
137 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
139 return phydev->drv->driver_data;
143 static umode_t mv3310_hwmon_is_visible(const void *data,
144 enum hwmon_sensor_types type,
145 u32 attr, int channel)
147 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
149 if (type == hwmon_temp && attr == hwmon_temp_input)
154 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
156 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
159 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
161 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
164 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
165 u32 attr, int channel, long *value)
167 struct phy_device *phydev = dev_get_drvdata(dev);
168 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
171 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
172 *value = MSEC_PER_SEC;
176 if (type == hwmon_temp && attr == hwmon_temp_input) {
177 temp = chip->hwmon_read_temp_reg(phydev);
181 *value = ((temp & 0xff) - 75) * 1000;
189 static const struct hwmon_ops mv3310_hwmon_ops = {
190 .is_visible = mv3310_hwmon_is_visible,
191 .read = mv3310_hwmon_read,
194 static u32 mv3310_hwmon_chip_config[] = {
195 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
199 static const struct hwmon_channel_info mv3310_hwmon_chip = {
201 .config = mv3310_hwmon_chip_config,
204 static u32 mv3310_hwmon_temp_config[] = {
209 static const struct hwmon_channel_info mv3310_hwmon_temp = {
211 .config = mv3310_hwmon_temp_config,
214 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
220 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
221 .ops = &mv3310_hwmon_ops,
222 .info = mv3310_hwmon_info,
225 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
230 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
233 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
238 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
240 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
241 MV_V2_TEMP_CTRL_MASK, val);
244 static int mv3310_hwmon_probe(struct phy_device *phydev)
246 struct device *dev = &phydev->mdio.dev;
247 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
250 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
251 if (!priv->hwmon_name)
254 for (i = j = 0; priv->hwmon_name[i]; i++) {
255 if (isalnum(priv->hwmon_name[i])) {
257 priv->hwmon_name[j] = priv->hwmon_name[i];
261 priv->hwmon_name[j] = '\0';
263 ret = mv3310_hwmon_config(phydev, true);
267 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
268 priv->hwmon_name, phydev,
269 &mv3310_hwmon_chip_info, NULL);
271 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
274 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
279 static int mv3310_hwmon_probe(struct phy_device *phydev)
285 static int mv3310_power_down(struct phy_device *phydev)
287 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
288 MV_V2_PORT_CTRL_PWRDOWN);
291 static int mv3310_power_up(struct phy_device *phydev)
293 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
296 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
297 MV_V2_PORT_CTRL_PWRDOWN);
299 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
300 priv->firmware_ver < 0x00030000)
303 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
304 MV_V2_33X0_PORT_CTRL_SWRST);
307 static int mv3310_reset(struct phy_device *phydev, u32 unit)
311 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
312 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
316 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
317 unit + MDIO_CTRL1, val,
318 !(val & MDIO_CTRL1_RESET),
322 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
326 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
330 switch (val & MV_PCS_CSCR1_ED_MASK) {
331 case MV_PCS_CSCR1_ED_NLP:
334 case MV_PCS_CSCR1_ED_RX:
335 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
338 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
344 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
351 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
352 val = MV_PCS_CSCR1_ED_NLP;
355 case ETHTOOL_PHY_EDPD_NO_TX:
356 val = MV_PCS_CSCR1_ED_RX;
359 case ETHTOOL_PHY_EDPD_DISABLE:
360 val = MV_PCS_CSCR1_ED_OFF;
367 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
368 MV_PCS_CSCR1_ED_MASK, val);
370 err = mv3310_reset(phydev, MV_PCS_BASE_T);
375 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
377 struct phy_device *phydev = upstream;
378 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
379 phy_interface_t iface;
381 sfp_parse_support(phydev->sfp_bus, id, support);
382 iface = sfp_select_interface(phydev->sfp_bus, support);
384 if (iface != PHY_INTERFACE_MODE_10GBASER) {
385 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
391 static const struct sfp_upstream_ops mv3310_sfp_ops = {
392 .attach = phy_sfp_attach,
393 .detach = phy_sfp_detach,
394 .module_insert = mv3310_sfp_insert,
397 static int mv3310_probe(struct phy_device *phydev)
399 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
400 struct mv3310_priv *priv;
401 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
404 if (!phydev->is_c45 ||
405 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
408 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
412 if (ret & MV_PMA_BOOT_FATAL) {
413 dev_warn(&phydev->mdio.dev,
414 "PHY failed to boot firmware, status=%04x\n", ret);
418 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
422 dev_set_drvdata(&phydev->mdio.dev, priv);
424 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
428 priv->firmware_ver = ret << 16;
430 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
434 priv->firmware_ver |= ret;
436 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
437 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
438 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
440 /* Powering down the port when not in use saves about 600mW */
441 ret = mv3310_power_down(phydev);
445 ret = mv3310_hwmon_probe(phydev);
449 chip->init_supported_interfaces(priv->supported_interfaces);
451 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
454 static void mv3310_remove(struct phy_device *phydev)
456 mv3310_hwmon_config(phydev, false);
459 static int mv3310_suspend(struct phy_device *phydev)
461 return mv3310_power_down(phydev);
464 static int mv3310_resume(struct phy_device *phydev)
468 ret = mv3310_power_up(phydev);
472 return mv3310_hwmon_config(phydev, true);
475 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
476 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
477 * support 2.5GBASET and 5GBASET. For these models, we can still read their
478 * 2.5G/5G extended abilities register (1.21). We detect these models based on
479 * the PMA device identifier, with a mask matching models known to have this
482 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
484 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
487 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
488 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
489 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
492 static int mv2110_get_mactype(struct phy_device *phydev)
496 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
500 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
503 static int mv3310_get_mactype(struct phy_device *phydev)
507 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
511 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
514 static int mv2110_init_interface(struct phy_device *phydev, int mactype)
516 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
518 priv->rate_match = false;
520 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
521 priv->rate_match = true;
523 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
524 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
525 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
526 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
527 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
528 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
529 priv->const_interface = PHY_INTERFACE_MODE_NA;
536 static int mv3310_init_interface(struct phy_device *phydev, int mactype)
538 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
540 priv->rate_match = false;
542 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
543 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
544 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
545 priv->rate_match = true;
547 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
548 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
549 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
550 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
551 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
552 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
553 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
554 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
555 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
556 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
557 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
558 priv->const_interface = PHY_INTERFACE_MODE_XAUI;
565 static int mv3340_init_interface(struct phy_device *phydev, int mactype)
567 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
570 priv->rate_match = false;
572 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
573 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
575 err = mv3310_init_interface(phydev, mactype);
580 static int mv3310_config_init(struct phy_device *phydev)
582 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
583 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
586 /* Check that the PHY interface type is compatible */
587 if (!test_bit(phydev->interface, priv->supported_interfaces))
590 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
592 /* Power up so reset works */
593 err = mv3310_power_up(phydev);
597 mactype = chip->get_mactype(phydev);
601 err = chip->init_interface(phydev, mactype);
603 phydev_err(phydev, "MACTYPE configuration invalid\n");
607 /* Enable EDPD mode - saving 600mW */
608 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
611 static int mv3310_get_features(struct phy_device *phydev)
615 ret = genphy_c45_pma_read_abilities(phydev);
619 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
620 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
621 MDIO_PMA_NG_EXTABLE);
625 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
627 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
629 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
631 val & MDIO_PMA_NG_EXTABLE_5GBT);
637 static int mv3310_config_mdix(struct phy_device *phydev)
642 switch (phydev->mdix_ctrl) {
643 case ETH_TP_MDI_AUTO:
644 val = MV_PCS_CSCR1_MDIX_AUTO;
647 val = MV_PCS_CSCR1_MDIX_MDIX;
650 val = MV_PCS_CSCR1_MDIX_MDI;
656 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
657 MV_PCS_CSCR1_MDIX_MASK, val);
659 err = mv3310_reset(phydev, MV_PCS_BASE_T);
664 static int mv3310_config_aneg(struct phy_device *phydev)
666 bool changed = false;
670 ret = mv3310_config_mdix(phydev);
674 if (phydev->autoneg == AUTONEG_DISABLE)
675 return genphy_c45_pma_setup_forced(phydev);
677 ret = genphy_c45_an_config_aneg(phydev);
683 /* Clause 45 has no standardized support for 1000BaseT, therefore
684 * use vendor registers for this mode.
686 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
687 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
688 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
694 return genphy_c45_check_and_restart_aneg(phydev, changed);
697 static int mv3310_aneg_done(struct phy_device *phydev)
701 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
705 if (val & MDIO_STAT1_LSTATUS)
708 return genphy_c45_aneg_done(phydev);
711 static void mv3310_update_interface(struct phy_device *phydev)
713 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
718 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
719 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
720 * internal 16KB buffer.
722 * In USXGMII mode the PHY interface mode is also fixed.
724 if (priv->rate_match ||
725 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
726 phydev->interface = priv->const_interface;
730 /* The PHY automatically switches its serdes interface (and active PHYXS
731 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
732 * xaui / rxaui modes according to the speed.
733 * Florian suggests setting phydev->interface to communicate this to the
734 * MAC. Only do this if we are already in one of the above modes.
736 switch (phydev->speed) {
738 phydev->interface = priv->const_interface;
741 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
744 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
749 phydev->interface = PHY_INTERFACE_MODE_SGMII;
756 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
757 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
760 phydev->speed = SPEED_10000;
761 phydev->duplex = DUPLEX_FULL;
762 phydev->port = PORT_FIBRE;
767 static int mv3310_read_status_copper(struct phy_device *phydev)
769 int cssr1, speed, val;
771 val = genphy_c45_read_link(phydev);
775 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
779 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
783 /* If the link settings are not resolved, mark the link down */
784 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
789 /* Read the copper link settings */
790 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
791 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
792 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
795 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
796 phydev->speed = SPEED_10000;
799 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
800 phydev->speed = SPEED_5000;
803 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
804 phydev->speed = SPEED_2500;
807 case MV_PCS_CSSR1_SPD1_1000:
808 phydev->speed = SPEED_1000;
811 case MV_PCS_CSSR1_SPD1_100:
812 phydev->speed = SPEED_100;
815 case MV_PCS_CSSR1_SPD1_10:
816 phydev->speed = SPEED_10;
820 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
821 DUPLEX_FULL : DUPLEX_HALF;
822 phydev->port = PORT_TP;
823 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
824 ETH_TP_MDI_X : ETH_TP_MDI;
826 if (val & MDIO_AN_STAT1_COMPLETE) {
827 val = genphy_c45_read_lpa(phydev);
831 /* Read the link partner's 1G advertisement */
832 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
836 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
838 /* Update the pause status */
839 phy_resolve_aneg_pause(phydev);
845 static int mv3310_read_status(struct phy_device *phydev)
849 phydev->speed = SPEED_UNKNOWN;
850 phydev->duplex = DUPLEX_UNKNOWN;
851 linkmode_zero(phydev->lp_advertising);
854 phydev->asym_pause = 0;
855 phydev->mdix = ETH_TP_MDI_INVALID;
857 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
861 if (val & MDIO_STAT1_LSTATUS)
862 err = mv3310_read_status_10gbaser(phydev);
864 err = mv3310_read_status_copper(phydev);
869 mv3310_update_interface(phydev);
874 static int mv3310_get_tunable(struct phy_device *phydev,
875 struct ethtool_tunable *tuna, void *data)
878 case ETHTOOL_PHY_EDPD:
879 return mv3310_get_edpd(phydev, data);
885 static int mv3310_set_tunable(struct phy_device *phydev,
886 struct ethtool_tunable *tuna, const void *data)
889 case ETHTOOL_PHY_EDPD:
890 return mv3310_set_edpd(phydev, *(u16 *)data);
896 static void mv3310_init_supported_interfaces(unsigned long *mask)
898 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
899 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
900 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
901 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
902 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
903 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
904 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
907 static void mv3340_init_supported_interfaces(unsigned long *mask)
909 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
910 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
911 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
912 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
913 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
914 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
917 static void mv2110_init_supported_interfaces(unsigned long *mask)
919 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
920 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
921 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
922 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
923 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
926 static void mv2111_init_supported_interfaces(unsigned long *mask)
928 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
929 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
930 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
931 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
934 static const struct mv3310_chip mv3310_type = {
935 .init_supported_interfaces = mv3310_init_supported_interfaces,
936 .get_mactype = mv3310_get_mactype,
937 .init_interface = mv3310_init_interface,
940 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
944 static const struct mv3310_chip mv3340_type = {
945 .init_supported_interfaces = mv3340_init_supported_interfaces,
946 .get_mactype = mv3310_get_mactype,
947 .init_interface = mv3340_init_interface,
950 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
954 static const struct mv3310_chip mv2110_type = {
955 .init_supported_interfaces = mv2110_init_supported_interfaces,
956 .get_mactype = mv2110_get_mactype,
957 .init_interface = mv2110_init_interface,
960 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
964 static const struct mv3310_chip mv2111_type = {
965 .init_supported_interfaces = mv2111_init_supported_interfaces,
966 .get_mactype = mv2110_get_mactype,
967 .init_interface = mv2110_init_interface,
970 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
974 static int mv3310_get_number_of_ports(struct phy_device *phydev)
978 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
982 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
983 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
988 static int mv3310_match_phy_device(struct phy_device *phydev)
990 return mv3310_get_number_of_ports(phydev) == 1;
993 static int mv3340_match_phy_device(struct phy_device *phydev)
995 return mv3310_get_number_of_ports(phydev) == 4;
998 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1002 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1003 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1006 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1010 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1013 static int mv2110_match_phy_device(struct phy_device *phydev)
1015 return mv211x_match_phy_device(phydev, true);
1018 static int mv2111_match_phy_device(struct phy_device *phydev)
1020 return mv211x_match_phy_device(phydev, false);
1023 static struct phy_driver mv3310_drivers[] = {
1025 .phy_id = MARVELL_PHY_ID_88X3310,
1026 .phy_id_mask = MARVELL_PHY_ID_MASK,
1027 .match_phy_device = mv3310_match_phy_device,
1028 .name = "mv88x3310",
1029 .driver_data = &mv3310_type,
1030 .get_features = mv3310_get_features,
1031 .config_init = mv3310_config_init,
1032 .probe = mv3310_probe,
1033 .suspend = mv3310_suspend,
1034 .resume = mv3310_resume,
1035 .config_aneg = mv3310_config_aneg,
1036 .aneg_done = mv3310_aneg_done,
1037 .read_status = mv3310_read_status,
1038 .get_tunable = mv3310_get_tunable,
1039 .set_tunable = mv3310_set_tunable,
1040 .remove = mv3310_remove,
1041 .set_loopback = genphy_c45_loopback,
1044 .phy_id = MARVELL_PHY_ID_88X3310,
1045 .phy_id_mask = MARVELL_PHY_ID_MASK,
1046 .match_phy_device = mv3340_match_phy_device,
1047 .name = "mv88x3340",
1048 .driver_data = &mv3340_type,
1049 .get_features = mv3310_get_features,
1050 .config_init = mv3310_config_init,
1051 .probe = mv3310_probe,
1052 .suspend = mv3310_suspend,
1053 .resume = mv3310_resume,
1054 .config_aneg = mv3310_config_aneg,
1055 .aneg_done = mv3310_aneg_done,
1056 .read_status = mv3310_read_status,
1057 .get_tunable = mv3310_get_tunable,
1058 .set_tunable = mv3310_set_tunable,
1059 .remove = mv3310_remove,
1060 .set_loopback = genphy_c45_loopback,
1063 .phy_id = MARVELL_PHY_ID_88E2110,
1064 .phy_id_mask = MARVELL_PHY_ID_MASK,
1065 .match_phy_device = mv2110_match_phy_device,
1066 .name = "mv88e2110",
1067 .driver_data = &mv2110_type,
1068 .probe = mv3310_probe,
1069 .suspend = mv3310_suspend,
1070 .resume = mv3310_resume,
1071 .config_init = mv3310_config_init,
1072 .config_aneg = mv3310_config_aneg,
1073 .aneg_done = mv3310_aneg_done,
1074 .read_status = mv3310_read_status,
1075 .get_tunable = mv3310_get_tunable,
1076 .set_tunable = mv3310_set_tunable,
1077 .remove = mv3310_remove,
1078 .set_loopback = genphy_c45_loopback,
1081 .phy_id = MARVELL_PHY_ID_88E2110,
1082 .phy_id_mask = MARVELL_PHY_ID_MASK,
1083 .match_phy_device = mv2111_match_phy_device,
1084 .name = "mv88e2111",
1085 .driver_data = &mv2111_type,
1086 .probe = mv3310_probe,
1087 .suspend = mv3310_suspend,
1088 .resume = mv3310_resume,
1089 .config_init = mv3310_config_init,
1090 .config_aneg = mv3310_config_aneg,
1091 .aneg_done = mv3310_aneg_done,
1092 .read_status = mv3310_read_status,
1093 .get_tunable = mv3310_get_tunable,
1094 .set_tunable = mv3310_set_tunable,
1095 .remove = mv3310_remove,
1096 .set_loopback = genphy_c45_loopback,
1100 module_phy_driver(mv3310_drivers);
1102 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1103 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1104 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1107 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1108 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1109 MODULE_LICENSE("GPL");