1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/marvell.c
5 * Driver for Marvell PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
17 #include <linux/unistd.h>
18 #include <linux/hwmon.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/spinlock.h>
27 #include <linux/module.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/ethtool_netlink.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/bitfield.h>
35 #include <linux/sfp.h>
39 #include <linux/uaccess.h>
41 #define MII_MARVELL_PHY_PAGE 22
42 #define MII_MARVELL_COPPER_PAGE 0x00
43 #define MII_MARVELL_FIBER_PAGE 0x01
44 #define MII_MARVELL_MSCR_PAGE 0x02
45 #define MII_MARVELL_LED_PAGE 0x03
46 #define MII_MARVELL_VCT5_PAGE 0x05
47 #define MII_MARVELL_MISC_TEST_PAGE 0x06
48 #define MII_MARVELL_VCT7_PAGE 0x07
49 #define MII_MARVELL_WOL_PAGE 0x11
50 #define MII_MARVELL_MODE_PAGE 0x12
52 #define MII_M1011_IEVENT 0x13
53 #define MII_M1011_IEVENT_CLEAR 0x0000
55 #define MII_M1011_IMASK 0x12
56 #define MII_M1011_IMASK_INIT 0x6400
57 #define MII_M1011_IMASK_CLEAR 0x0000
59 #define MII_M1011_PHY_SCR 0x10
60 #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
61 #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
62 #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
63 #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
64 #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
65 #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
67 #define MII_M1011_PHY_SSR 0x11
68 #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
70 #define MII_M1111_PHY_LED_CONTROL 0x18
71 #define MII_M1111_PHY_LED_DIRECT 0x4100
72 #define MII_M1111_PHY_LED_COMBINE 0x411c
73 #define MII_M1111_PHY_EXT_CR 0x14
74 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
75 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
76 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
77 #define MII_M1111_RGMII_RX_DELAY BIT(7)
78 #define MII_M1111_RGMII_TX_DELAY BIT(1)
79 #define MII_M1111_PHY_EXT_SR 0x1b
81 #define MII_M1111_HWCFG_MODE_MASK 0xf
82 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
83 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
84 #define MII_M1111_HWCFG_MODE_RTBI 0x7
85 #define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
86 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
87 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
88 #define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
89 #define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
90 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
91 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
93 #define MII_88E1121_PHY_MSCR_REG 21
94 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
95 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
96 #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
98 #define MII_88E1121_MISC_TEST 0x1a
99 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
100 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
101 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
102 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
103 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
104 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
106 #define MII_88E1510_TEMP_SENSOR 0x1b
107 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
109 #define MII_88E1540_COPPER_CTRL3 0x1a
110 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
111 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
112 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
113 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
114 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
115 #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
117 #define MII_88E6390_MISC_TEST 0x1b
118 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
119 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
120 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
121 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
122 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
123 #define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
124 #define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
125 #define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
126 #define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
127 #define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
128 #define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
129 #define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
130 #define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
131 #define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
133 #define MII_88E6390_TEMP_SENSOR 0x1c
134 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
135 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
136 #define MII_88E6390_TEMP_SENSOR_MASK 0xff
137 #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
139 #define MII_88E1318S_PHY_MSCR1_REG 16
140 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
142 /* Copper Specific Interrupt Enable Register */
143 #define MII_88E1318S_PHY_CSIER 0x12
144 /* WOL Event Interrupt Enable */
145 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
147 /* LED Timer Control Register */
148 #define MII_88E1318S_PHY_LED_TCR 0x12
149 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
150 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
151 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
153 /* Magic Packet MAC address registers */
154 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
155 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
156 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
158 #define MII_88E1318S_PHY_WOL_CTRL 0x10
159 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
160 #define MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE BIT(13)
161 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
163 #define MII_PHY_LED_CTRL 16
164 #define MII_88E1121_PHY_LED_DEF 0x0030
165 #define MII_88E1510_PHY_LED_DEF 0x1177
166 #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
168 #define MII_M1011_PHY_STATUS 0x11
169 #define MII_M1011_PHY_STATUS_1000 0x8000
170 #define MII_M1011_PHY_STATUS_100 0x4000
171 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
172 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
173 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
174 #define MII_M1011_PHY_STATUS_LINK 0x0400
176 #define MII_88E3016_PHY_SPEC_CTRL 0x10
177 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
178 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
180 #define MII_88E1510_GEN_CTRL_REG_1 0x14
181 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
182 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII 0x0 /* RGMII to copper */
183 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
184 /* RGMII to 1000BASE-X */
185 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X 0x2
186 /* RGMII to 100BASE-FX */
187 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX 0x3
189 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4
190 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
192 #define MII_88E1510_MSCR_2 0x15
194 #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
195 #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
196 #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
197 #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
198 #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
199 #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
200 #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
202 #define MII_VCT5_CTRL 0x17
203 #define MII_VCT5_CTRL_ENABLE BIT(15)
204 #define MII_VCT5_CTRL_COMPLETE BIT(14)
205 #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
206 #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
207 #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
208 #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
209 #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
210 #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
211 #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
212 #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
213 #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
214 #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
215 #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
216 #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
217 #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
218 #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
219 #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
220 #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
221 #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
222 #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
223 #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
224 #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
226 #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
227 #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
228 #define MII_VCT5_TX_PULSE_CTRL 0x1c
229 #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
230 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
231 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
232 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
233 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
234 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
235 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
236 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
237 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
238 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
239 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
240 #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
241 #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
243 /* For TDR measurements less than 11 meters, a short pulse should be
246 #define TDR_SHORT_CABLE_LENGTH 11
248 #define MII_VCT7_PAIR_0_DISTANCE 0x10
249 #define MII_VCT7_PAIR_1_DISTANCE 0x11
250 #define MII_VCT7_PAIR_2_DISTANCE 0x12
251 #define MII_VCT7_PAIR_3_DISTANCE 0x13
253 #define MII_VCT7_RESULTS 0x14
254 #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
255 #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
256 #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
257 #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
258 #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
259 #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
260 #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
261 #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
262 #define MII_VCT7_RESULTS_INVALID 0
263 #define MII_VCT7_RESULTS_OK 1
264 #define MII_VCT7_RESULTS_OPEN 2
265 #define MII_VCT7_RESULTS_SAME_SHORT 3
266 #define MII_VCT7_RESULTS_CROSS_SHORT 4
267 #define MII_VCT7_RESULTS_BUSY 9
269 #define MII_VCT7_CTRL 0x15
270 #define MII_VCT7_CTRL_RUN_NOW BIT(15)
271 #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
272 #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
273 #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
274 #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
275 #define MII_VCT7_CTRL_METERS BIT(10)
276 #define MII_VCT7_CTRL_CENTIMETERS 0
278 #define LPA_PAUSE_FIBER 0x180
279 #define LPA_PAUSE_ASYM_FIBER 0x100
281 #define NB_FIBER_STATS 1
283 MODULE_DESCRIPTION("Marvell PHY driver");
284 MODULE_AUTHOR("Andy Fleming");
285 MODULE_LICENSE("GPL");
287 struct marvell_hw_stat {
294 static struct marvell_hw_stat marvell_hw_stats[] = {
295 { "phy_receive_errors_copper", 0, 21, 16},
296 { "phy_idle_errors", 0, 10, 8 },
297 { "phy_receive_errors_fiber", 1, 21, 16},
300 struct marvell_priv {
301 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
303 struct device *hwmon_dev;
311 static int marvell_read_page(struct phy_device *phydev)
313 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
316 static int marvell_write_page(struct phy_device *phydev, int page)
318 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
321 static int marvell_set_page(struct phy_device *phydev, int page)
323 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
326 static int marvell_ack_interrupt(struct phy_device *phydev)
330 /* Clear the interrupts by reading the reg */
331 err = phy_read(phydev, MII_M1011_IEVENT);
339 static int marvell_config_intr(struct phy_device *phydev)
343 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
344 err = marvell_ack_interrupt(phydev);
348 err = phy_write(phydev, MII_M1011_IMASK,
349 MII_M1011_IMASK_INIT);
351 err = phy_write(phydev, MII_M1011_IMASK,
352 MII_M1011_IMASK_CLEAR);
356 err = marvell_ack_interrupt(phydev);
362 static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
366 irq_status = phy_read(phydev, MII_M1011_IEVENT);
367 if (irq_status < 0) {
372 if (!(irq_status & MII_M1011_IMASK_INIT))
375 phy_trigger_machine(phydev);
380 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
386 val = MII_M1011_PHY_SCR_MDI;
389 val = MII_M1011_PHY_SCR_MDI_X;
391 case ETH_TP_MDI_AUTO:
392 case ETH_TP_MDI_INVALID:
394 val = MII_M1011_PHY_SCR_AUTO_CROSS;
398 return phy_modify_changed(phydev, MII_M1011_PHY_SCR,
399 MII_M1011_PHY_SCR_AUTO_CROSS, val);
402 static int marvell_config_aneg(struct phy_device *phydev)
407 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
413 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
414 MII_M1111_PHY_LED_DIRECT);
418 err = genphy_config_aneg(phydev);
422 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
423 /* A write to speed/duplex bits (that is performed by
424 * genphy_config_aneg() call above) must be followed by
425 * a software reset. Otherwise, the write has no effect.
427 err = genphy_soft_reset(phydev);
435 static int m88e1101_config_aneg(struct phy_device *phydev)
439 /* This Marvell PHY has an errata which requires
440 * that certain registers get written in order
441 * to restart autonegotiation
443 err = genphy_soft_reset(phydev);
447 err = phy_write(phydev, 0x1d, 0x1f);
451 err = phy_write(phydev, 0x1e, 0x200c);
455 err = phy_write(phydev, 0x1d, 0x5);
459 err = phy_write(phydev, 0x1e, 0);
463 err = phy_write(phydev, 0x1e, 0x100);
467 return marvell_config_aneg(phydev);
470 #if IS_ENABLED(CONFIG_OF_MDIO)
471 /* Set and/or override some configuration registers based on the
472 * marvell,reg-init property stored in the of_node for the phydev.
474 * marvell,reg-init = <reg-page reg mask value>,...;
476 * There may be one or more sets of <reg-page reg mask value>:
478 * reg-page: which register bank to use.
480 * mask: if non-zero, ANDed with existing register value.
481 * value: ORed with the masked value and written to the regiser.
484 static int marvell_of_reg_init(struct phy_device *phydev)
487 int len, i, saved_page, current_page, ret = 0;
489 if (!phydev->mdio.dev.of_node)
492 paddr = of_get_property(phydev->mdio.dev.of_node,
493 "marvell,reg-init", &len);
494 if (!paddr || len < (4 * sizeof(*paddr)))
497 saved_page = phy_save_page(phydev);
500 current_page = saved_page;
502 len /= sizeof(*paddr);
503 for (i = 0; i < len - 3; i += 4) {
504 u16 page = be32_to_cpup(paddr + i);
505 u16 reg = be32_to_cpup(paddr + i + 1);
506 u16 mask = be32_to_cpup(paddr + i + 2);
507 u16 val_bits = be32_to_cpup(paddr + i + 3);
510 if (page != current_page) {
512 ret = marvell_write_page(phydev, page);
519 val = __phy_read(phydev, reg);
528 ret = __phy_write(phydev, reg, val);
533 return phy_restore_page(phydev, saved_page, ret);
536 static int marvell_of_reg_init(struct phy_device *phydev)
540 #endif /* CONFIG_OF_MDIO */
542 static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
546 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
547 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
548 MII_88E1121_PHY_MSCR_TX_DELAY;
549 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
550 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
551 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
552 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
556 return phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
557 MII_88E1121_PHY_MSCR_REG,
558 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
561 static int m88e1121_config_aneg(struct phy_device *phydev)
566 if (phy_interface_is_rgmii(phydev)) {
567 err = m88e1121_config_aneg_rgmii_delays(phydev);
572 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
578 err = genphy_config_aneg(phydev);
582 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
583 /* A software reset is used to ensure a "commit" of the
586 err = genphy_soft_reset(phydev);
594 static int m88e1318_config_aneg(struct phy_device *phydev)
598 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
599 MII_88E1318S_PHY_MSCR1_REG,
600 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
604 return m88e1121_config_aneg(phydev);
608 * linkmode_adv_to_fiber_adv_t
609 * @advertise: the linkmode advertisement settings
611 * A small helper function that translates linkmode advertisement
612 * settings to phy autonegotiation advertisements for the MII_ADV
613 * register for fiber link.
615 static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
619 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
620 result |= ADVERTISE_1000XHALF;
621 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
622 result |= ADVERTISE_1000XFULL;
624 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
625 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
626 result |= ADVERTISE_1000XPSE_ASYM;
627 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
628 result |= ADVERTISE_1000XPAUSE;
634 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
635 * @phydev: target phy_device struct
637 * Description: If auto-negotiation is enabled, we configure the
638 * advertising, and then restart auto-negotiation. If it is not
639 * enabled, then we write the BMCR. Adapted for fiber link in
640 * some Marvell's devices.
642 static int marvell_config_aneg_fiber(struct phy_device *phydev)
648 if (phydev->autoneg != AUTONEG_ENABLE)
649 return genphy_setup_forced(phydev);
651 /* Only allow advertising what this PHY supports */
652 linkmode_and(phydev->advertising, phydev->advertising,
655 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
657 /* Setup fiber advertisement */
658 err = phy_modify_changed(phydev, MII_ADVERTISE,
659 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
660 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
667 return genphy_check_and_restart_aneg(phydev, changed);
670 static int m88e1111_config_aneg(struct phy_device *phydev)
672 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
678 /* If not using SGMII or copper 1000BaseX modes, use normal process.
679 * Steps below are only required for these modes.
681 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
682 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
683 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
684 return marvell_config_aneg(phydev);
686 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
690 /* Configure the copper link first */
691 err = marvell_config_aneg(phydev);
695 /* Then the fiber link */
696 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
700 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
701 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
702 * Just ensure that SGMII-side autonegotiation is enabled.
703 * If we switched from some other mode to SGMII it may not be.
705 err = genphy_check_and_restart_aneg(phydev, false);
707 err = marvell_config_aneg_fiber(phydev);
711 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
714 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
718 static int m88e1510_config_aneg(struct phy_device *phydev)
722 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
726 /* Configure the copper link first */
727 err = m88e1318_config_aneg(phydev);
731 /* Do not touch the fiber page if we're in copper->sgmii mode */
732 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
735 /* Then the fiber link */
736 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
740 err = marvell_config_aneg_fiber(phydev);
744 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
747 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
751 static void marvell_config_led(struct phy_device *phydev)
756 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
757 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
758 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
759 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
760 def_config = MII_88E1121_PHY_LED_DEF;
762 /* Default PHY LED config:
763 * LED[0] .. 1000Mbps Link
764 * LED[1] .. 100Mbps Link
765 * LED[2] .. Blink, Activity
767 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
768 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
769 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
771 def_config = MII_88E1510_PHY_LED_DEF;
777 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
780 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
783 static int marvell_config_init(struct phy_device *phydev)
785 /* Set default LED */
786 marvell_config_led(phydev);
788 /* Set registers from marvell,reg-init DT property */
789 return marvell_of_reg_init(phydev);
792 static int m88e3016_config_init(struct phy_device *phydev)
796 /* Enable Scrambler and Auto-Crossover */
797 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
798 MII_88E3016_DISABLE_SCRAMBLER,
799 MII_88E3016_AUTO_MDIX_CROSSOVER);
803 return marvell_config_init(phydev);
806 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
808 int fibre_copper_auto)
810 if (fibre_copper_auto)
811 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
813 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
814 MII_M1111_HWCFG_MODE_MASK |
815 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
816 MII_M1111_HWCFG_FIBER_COPPER_RES,
820 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
824 switch (phydev->interface) {
825 case PHY_INTERFACE_MODE_RGMII_ID:
826 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
828 case PHY_INTERFACE_MODE_RGMII_RXID:
829 delay = MII_M1111_RGMII_RX_DELAY;
831 case PHY_INTERFACE_MODE_RGMII_TXID:
832 delay = MII_M1111_RGMII_TX_DELAY;
839 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
840 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
844 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
849 err = m88e1111_config_init_rgmii_delays(phydev);
853 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
857 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
859 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
860 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
862 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
864 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
867 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
871 err = m88e1111_config_init_hwcfg_mode(
873 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
874 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
878 /* make sure copper is selected */
879 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
882 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
886 err = m88e1111_config_init_rgmii_delays(phydev);
890 err = m88e1111_config_init_hwcfg_mode(
892 MII_M1111_HWCFG_MODE_RTBI,
893 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
898 err = genphy_soft_reset(phydev);
902 return m88e1111_config_init_hwcfg_mode(
904 MII_M1111_HWCFG_MODE_RTBI,
905 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
908 static int m88e1111_config_init_1000basex(struct phy_device *phydev)
910 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
916 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
917 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
918 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
919 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
920 MII_M1111_HWCFG_MODE_MASK |
921 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
922 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
923 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
930 static int m88e1111_config_init(struct phy_device *phydev)
934 if (phy_interface_is_rgmii(phydev)) {
935 err = m88e1111_config_init_rgmii(phydev);
940 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
941 err = m88e1111_config_init_sgmii(phydev);
946 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
947 err = m88e1111_config_init_rtbi(phydev);
952 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
953 err = m88e1111_config_init_1000basex(phydev);
958 err = marvell_of_reg_init(phydev);
962 return genphy_soft_reset(phydev);
965 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
967 int val, cnt, enable;
969 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
973 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
974 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
976 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
981 static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
985 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
989 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
990 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
992 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
993 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
995 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
996 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
997 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1004 return genphy_soft_reset(phydev);
1007 static int m88e1111_get_tunable(struct phy_device *phydev,
1008 struct ethtool_tunable *tuna, void *data)
1011 case ETHTOOL_PHY_DOWNSHIFT:
1012 return m88e1111_get_downshift(phydev, data);
1018 static int m88e1111_set_tunable(struct phy_device *phydev,
1019 struct ethtool_tunable *tuna, const void *data)
1022 case ETHTOOL_PHY_DOWNSHIFT:
1023 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1029 static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1031 int val, cnt, enable;
1033 val = phy_read(phydev, MII_M1011_PHY_SCR);
1037 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1038 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1040 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1045 static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1049 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1053 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1054 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1056 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1057 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1059 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1060 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1061 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1068 return genphy_soft_reset(phydev);
1071 static int m88e1011_get_tunable(struct phy_device *phydev,
1072 struct ethtool_tunable *tuna, void *data)
1075 case ETHTOOL_PHY_DOWNSHIFT:
1076 return m88e1011_get_downshift(phydev, data);
1082 static int m88e1011_set_tunable(struct phy_device *phydev,
1083 struct ethtool_tunable *tuna, const void *data)
1086 case ETHTOOL_PHY_DOWNSHIFT:
1087 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1093 static int m88e1112_config_init(struct phy_device *phydev)
1097 err = m88e1011_set_downshift(phydev, 3);
1101 return m88e1111_config_init(phydev);
1104 static int m88e1111gbe_config_init(struct phy_device *phydev)
1108 err = m88e1111_set_downshift(phydev, 3);
1112 return m88e1111_config_init(phydev);
1115 static int marvell_1011gbe_config_init(struct phy_device *phydev)
1119 err = m88e1011_set_downshift(phydev, 3);
1123 return marvell_config_init(phydev);
1125 static int m88e1116r_config_init(struct phy_device *phydev)
1129 err = genphy_soft_reset(phydev);
1135 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1139 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1143 err = m88e1011_set_downshift(phydev, 8);
1147 if (phy_interface_is_rgmii(phydev)) {
1148 err = m88e1121_config_aneg_rgmii_delays(phydev);
1153 err = genphy_soft_reset(phydev);
1157 return marvell_config_init(phydev);
1160 static int m88e1318_config_init(struct phy_device *phydev)
1162 if (phy_interrupt_is_valid(phydev)) {
1163 int err = phy_modify_paged(
1164 phydev, MII_MARVELL_LED_PAGE,
1165 MII_88E1318S_PHY_LED_TCR,
1166 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1167 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1168 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1173 return marvell_config_init(phydev);
1176 static int m88e1510_config_init(struct phy_device *phydev)
1180 /* SGMII-to-Copper mode initialization */
1181 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1182 /* Select page 18 */
1183 err = marvell_set_page(phydev, 18);
1187 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1188 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1189 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1190 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1194 /* PHY reset is necessary after changing MODE[2:0] */
1195 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1196 MII_88E1510_GEN_CTRL_REG_1_RESET);
1200 /* Reset page selection */
1201 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1205 err = m88e1011_set_downshift(phydev, 3);
1209 return m88e1318_config_init(phydev);
1212 static int m88e1118_config_aneg(struct phy_device *phydev)
1216 err = genphy_soft_reset(phydev);
1220 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1224 err = genphy_config_aneg(phydev);
1228 static int m88e1118_config_init(struct phy_device *phydev)
1233 /* Enable 1000 Mbit */
1234 err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
1235 MII_88E1121_PHY_MSCR_REG, 0x1070);
1239 if (phy_interface_is_rgmii(phydev)) {
1240 err = m88e1121_config_aneg_rgmii_delays(phydev);
1245 /* Adjust LED Control */
1246 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1251 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, 0x10, leds);
1255 err = marvell_of_reg_init(phydev);
1259 /* Reset page register */
1260 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1264 return genphy_soft_reset(phydev);
1267 static int m88e1149_config_init(struct phy_device *phydev)
1271 /* Change address */
1272 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1276 /* Enable 1000 Mbit */
1277 err = phy_write(phydev, 0x15, 0x1048);
1281 err = marvell_of_reg_init(phydev);
1286 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1290 return genphy_soft_reset(phydev);
1293 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1297 err = m88e1111_config_init_rgmii_delays(phydev);
1301 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1302 err = phy_write(phydev, 0x1d, 0x0012);
1306 err = phy_modify(phydev, 0x1e, 0x0fc0,
1307 2 << 9 | /* 36 ohm */
1308 2 << 6); /* 39 ohm */
1312 err = phy_write(phydev, 0x1d, 0x3);
1316 err = phy_write(phydev, 0x1e, 0x8000);
1321 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1323 return m88e1111_config_init_hwcfg_mode(
1324 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1325 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1328 static int m88e1145_config_init(struct phy_device *phydev)
1332 /* Take care of errata E0 & E1 */
1333 err = phy_write(phydev, 0x1d, 0x001b);
1337 err = phy_write(phydev, 0x1e, 0x418f);
1341 err = phy_write(phydev, 0x1d, 0x0016);
1345 err = phy_write(phydev, 0x1e, 0xa2da);
1349 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1350 err = m88e1145_config_init_rgmii(phydev);
1355 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1356 err = m88e1145_config_init_sgmii(phydev);
1360 err = m88e1111_set_downshift(phydev, 3);
1364 err = marvell_of_reg_init(phydev);
1371 static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1375 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1379 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1380 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1384 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1387 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1390 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1393 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1396 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1406 static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1408 struct ethtool_eee eee;
1411 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1412 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1413 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1415 /* According to the Marvell data sheet EEE must be disabled for
1416 * Fast Link Down detection to work properly
1418 ret = phy_ethtool_get_eee(phydev, &eee);
1419 if (!ret && eee.eee_enabled) {
1420 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1425 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1426 else if (*msecs <= 15)
1427 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1428 else if (*msecs <= 30)
1429 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1431 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1433 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1435 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1436 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1440 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1441 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1444 static int m88e1540_get_tunable(struct phy_device *phydev,
1445 struct ethtool_tunable *tuna, void *data)
1448 case ETHTOOL_PHY_FAST_LINK_DOWN:
1449 return m88e1540_get_fld(phydev, data);
1450 case ETHTOOL_PHY_DOWNSHIFT:
1451 return m88e1011_get_downshift(phydev, data);
1457 static int m88e1540_set_tunable(struct phy_device *phydev,
1458 struct ethtool_tunable *tuna, const void *data)
1461 case ETHTOOL_PHY_FAST_LINK_DOWN:
1462 return m88e1540_set_fld(phydev, data);
1463 case ETHTOOL_PHY_DOWNSHIFT:
1464 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1470 /* The VOD can be out of specification on link up. Poke an
1471 * undocumented register, in an undocumented page, with a magic value
1474 static int m88e6390_errata(struct phy_device *phydev)
1478 err = phy_write(phydev, MII_BMCR,
1479 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1483 usleep_range(300, 400);
1485 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1489 return genphy_soft_reset(phydev);
1492 static int m88e6390_config_aneg(struct phy_device *phydev)
1496 err = m88e6390_errata(phydev);
1500 return m88e1510_config_aneg(phydev);
1504 * fiber_lpa_mod_linkmode_lpa_t
1505 * @advertising: the linkmode advertisement settings
1506 * @lpa: value of the MII_LPA register for fiber link
1508 * A small helper function that translates MII_LPA bits to linkmode LP
1509 * advertisement settings. Other bits in advertising are left
1512 static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1514 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1515 advertising, lpa & LPA_1000XHALF);
1517 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1518 advertising, lpa & LPA_1000XFULL);
1521 static int marvell_read_status_page_an(struct phy_device *phydev,
1522 int fiber, int status)
1527 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1532 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1533 phydev->duplex = DUPLEX_FULL;
1535 phydev->duplex = DUPLEX_HALF;
1537 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1538 case MII_M1011_PHY_STATUS_1000:
1539 phydev->speed = SPEED_1000;
1542 case MII_M1011_PHY_STATUS_100:
1543 phydev->speed = SPEED_100;
1547 phydev->speed = SPEED_10;
1552 err = genphy_read_lpa(phydev);
1556 phy_resolve_aneg_pause(phydev);
1558 lpa = phy_read(phydev, MII_LPA);
1562 /* The fiber link is only 1000M capable */
1563 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1565 if (phydev->duplex == DUPLEX_FULL) {
1566 if (!(lpa & LPA_PAUSE_FIBER)) {
1568 phydev->asym_pause = 0;
1569 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1571 phydev->asym_pause = 1;
1574 phydev->asym_pause = 0;
1582 /* marvell_read_status_page
1585 * Check the link, then figure out the current state
1586 * by comparing what we advertise with what the link partner
1587 * advertises. Start by checking the gigabit possibilities,
1588 * then move on to 10/100.
1590 static int marvell_read_status_page(struct phy_device *phydev, int page)
1596 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1600 /* Use the generic register for copper link status,
1601 * and the PHY status register for fiber link status.
1603 if (page == MII_MARVELL_FIBER_PAGE) {
1604 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1606 err = genphy_update_link(phydev);
1611 if (page == MII_MARVELL_FIBER_PAGE)
1616 linkmode_zero(phydev->lp_advertising);
1618 phydev->asym_pause = 0;
1619 phydev->speed = SPEED_UNKNOWN;
1620 phydev->duplex = DUPLEX_UNKNOWN;
1621 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1623 if (phydev->autoneg == AUTONEG_ENABLE)
1624 err = marvell_read_status_page_an(phydev, fiber, status);
1626 err = genphy_read_status_fixed(phydev);
1631 /* marvell_read_status
1633 * Some Marvell's phys have two modes: fiber and copper.
1634 * Both need status checked.
1636 * First, check the fiber link and status.
1637 * If the fiber link is down, check the copper link and status which
1638 * will be the default value if both link are down.
1640 static int marvell_read_status(struct phy_device *phydev)
1644 /* Check the fiber mode first */
1645 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1646 phydev->supported) &&
1647 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1648 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1652 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1656 /* If the fiber link is up, it is the selected and
1657 * used link. In this case, we need to stay in the
1658 * fiber page. Please to be careful about that, avoid
1659 * to restore Copper page in other functions which
1660 * could break the behaviour for some fiber phy like
1666 /* If fiber link is down, check and save copper mode state */
1667 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1672 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1675 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1681 * Some Marvell's phys have two modes: fiber and copper.
1682 * Both need to be suspended
1684 static int marvell_suspend(struct phy_device *phydev)
1688 /* Suspend the fiber mode first */
1689 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1690 phydev->supported)) {
1691 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1695 /* With the page set, use the generic suspend */
1696 err = genphy_suspend(phydev);
1700 /* Then, the copper link */
1701 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1706 /* With the page set, use the generic suspend */
1707 return genphy_suspend(phydev);
1710 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1716 * Some Marvell's phys have two modes: fiber and copper.
1717 * Both need to be resumed
1719 static int marvell_resume(struct phy_device *phydev)
1723 /* Resume the fiber mode first */
1724 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1725 phydev->supported)) {
1726 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1730 /* With the page set, use the generic resume */
1731 err = genphy_resume(phydev);
1735 /* Then, the copper link */
1736 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1741 /* With the page set, use the generic resume */
1742 return genphy_resume(phydev);
1745 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1749 static int marvell_aneg_done(struct phy_device *phydev)
1751 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1753 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1756 static void m88e1318_get_wol(struct phy_device *phydev,
1757 struct ethtool_wolinfo *wol)
1761 wol->supported = WAKE_MAGIC | WAKE_PHY;
1764 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1765 MII_88E1318S_PHY_WOL_CTRL);
1769 if (ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1770 wol->wolopts |= WAKE_MAGIC;
1772 if (ret & MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE)
1773 wol->wolopts |= WAKE_PHY;
1776 static int m88e1318_set_wol(struct phy_device *phydev,
1777 struct ethtool_wolinfo *wol)
1779 int err = 0, oldpage;
1781 oldpage = phy_save_page(phydev);
1785 if (wol->wolopts & (WAKE_MAGIC | WAKE_PHY)) {
1786 /* Explicitly switch to page 0x00, just to be sure */
1787 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1791 /* If WOL event happened once, the LED[2] interrupt pin
1792 * will not be cleared unless we reading the interrupt status
1793 * register. If interrupts are in use, the normal interrupt
1794 * handling will clear the WOL event. Clear the WOL event
1795 * before enabling it if !phy_interrupt_is_valid()
1797 if (!phy_interrupt_is_valid(phydev))
1798 __phy_read(phydev, MII_M1011_IEVENT);
1800 /* Enable the WOL interrupt */
1801 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1802 MII_88E1318S_PHY_CSIER_WOL_EIE);
1806 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1810 /* Setup LED[2] as interrupt pin (active low) */
1811 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1812 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1813 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1814 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1819 if (wol->wolopts & WAKE_MAGIC) {
1820 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1824 /* Store the device address for the magic packet */
1825 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1826 ((phydev->attached_dev->dev_addr[5] << 8) |
1827 phydev->attached_dev->dev_addr[4]));
1830 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1831 ((phydev->attached_dev->dev_addr[3] << 8) |
1832 phydev->attached_dev->dev_addr[2]));
1835 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1836 ((phydev->attached_dev->dev_addr[1] << 8) |
1837 phydev->attached_dev->dev_addr[0]));
1841 /* Clear WOL status and enable magic packet matching */
1842 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1843 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1844 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1848 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1852 /* Clear WOL status and disable magic packet matching */
1853 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1854 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1855 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1860 if (wol->wolopts & WAKE_PHY) {
1861 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1865 /* Clear WOL status and enable link up event */
1866 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1867 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1868 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE);
1872 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1876 /* Clear WOL status and disable link up event */
1877 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1878 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE,
1879 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1885 return phy_restore_page(phydev, oldpage, err);
1888 static int marvell_get_sset_count(struct phy_device *phydev)
1890 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1892 return ARRAY_SIZE(marvell_hw_stats);
1894 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1897 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1899 int count = marvell_get_sset_count(phydev);
1902 for (i = 0; i < count; i++) {
1903 strlcpy(data + i * ETH_GSTRING_LEN,
1904 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1908 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1910 struct marvell_hw_stat stat = marvell_hw_stats[i];
1911 struct marvell_priv *priv = phydev->priv;
1915 val = phy_read_paged(phydev, stat.page, stat.reg);
1919 val = val & ((1 << stat.bits) - 1);
1920 priv->stats[i] += val;
1921 ret = priv->stats[i];
1927 static void marvell_get_stats(struct phy_device *phydev,
1928 struct ethtool_stats *stats, u64 *data)
1930 int count = marvell_get_sset_count(phydev);
1933 for (i = 0; i < count; i++)
1934 data[i] = marvell_get_stat(phydev, i);
1937 static int m88e1510_loopback(struct phy_device *phydev, bool enable)
1942 u16 bmcr_ctl = 0, mscr2_ctl = 0;
1944 if (phydev->speed == SPEED_1000)
1945 bmcr_ctl = BMCR_SPEED1000;
1946 else if (phydev->speed == SPEED_100)
1947 bmcr_ctl = BMCR_SPEED100;
1949 if (phydev->duplex == DUPLEX_FULL)
1950 bmcr_ctl |= BMCR_FULLDPLX;
1952 err = phy_write(phydev, MII_BMCR, bmcr_ctl);
1956 if (phydev->speed == SPEED_1000)
1957 mscr2_ctl = BMCR_SPEED1000;
1958 else if (phydev->speed == SPEED_100)
1959 mscr2_ctl = BMCR_SPEED100;
1961 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
1962 MII_88E1510_MSCR_2, BMCR_SPEED1000 |
1963 BMCR_SPEED100, mscr2_ctl);
1967 /* Need soft reset to have speed configuration takes effect */
1968 err = genphy_soft_reset(phydev);
1972 /* FIXME: Based on trial and error test, it seem 1G need to have
1973 * delay between soft reset and loopback enablement.
1975 if (phydev->speed == SPEED_1000)
1978 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1981 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
1985 return phy_config_aneg(phydev);
1989 static int marvell_vct5_wait_complete(struct phy_device *phydev)
1994 for (i = 0; i < 32; i++) {
1995 val = __phy_read(phydev, MII_VCT5_CTRL);
1999 if (val & MII_VCT5_CTRL_COMPLETE)
2003 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
2007 static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
2013 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
2014 val = __phy_read(phydev, reg);
2019 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
2020 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
2022 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
2023 amplitude = -amplitude;
2025 return 1000 * amplitude / 128;
2028 static u32 marvell_vct5_distance2cm(int distance)
2030 return distance * 805 / 10;
2033 static u32 marvell_vct5_cm2distance(int cm)
2035 return cm * 10 / 805;
2038 static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
2039 int distance, int pair)
2046 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
2051 reg = MII_VCT5_CTRL_ENABLE |
2052 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2053 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2054 MII_VCT5_CTRL_SAMPLE_POINT |
2055 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
2056 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
2060 err = marvell_vct5_wait_complete(phydev);
2064 for (i = 0; i < 4; i++) {
2065 if (pair != PHY_PAIR_ALL && i != pair)
2068 mV = marvell_vct5_amplitude(phydev, i);
2069 ethnl_cable_test_amplitude(phydev, i, mV);
2075 static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
2077 struct marvell_priv *priv = phydev->priv;
2084 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
2085 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
2087 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2089 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2090 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2091 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2093 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2094 MII_VCT5_TX_PULSE_CTRL, reg);
2098 /* Reading the TDR data is very MDIO heavy. We need to optimize
2099 * access to keep the time to a minimum. So lock the bus once,
2100 * and don't release it until complete. We can then avoid having
2101 * to change the page for every access, greatly speeding things
2104 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
2108 for (distance = priv->first;
2109 distance <= priv->last;
2110 distance += priv->step) {
2111 err = marvell_vct5_amplitude_distance(phydev, distance,
2116 if (distance > TDR_SHORT_CABLE_LENGTH &&
2117 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
2118 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2119 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2120 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2121 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2122 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2129 return phy_restore_page(phydev, page, err);
2132 static int marvell_cable_test_start_common(struct phy_device *phydev)
2134 int bmcr, bmsr, ret;
2136 /* If auto-negotiation is enabled, but not complete, the cable
2137 * test never completes. So disable auto-neg.
2139 bmcr = phy_read(phydev, MII_BMCR);
2143 bmsr = phy_read(phydev, MII_BMSR);
2148 if (bmcr & BMCR_ANENABLE) {
2149 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2152 ret = genphy_soft_reset(phydev);
2157 /* If the link is up, allow it some time to go down */
2158 if (bmsr & BMSR_LSTATUS)
2164 static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2166 struct marvell_priv *priv = phydev->priv;
2169 ret = marvell_cable_test_start_common(phydev);
2173 priv->cable_test_tdr = false;
2175 /* Reset the VCT5 API control to defaults, otherwise
2176 * VCT7 does not work correctly.
2178 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2180 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2181 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2182 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2183 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2187 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2188 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2192 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2194 MII_VCT7_CTRL_RUN_NOW |
2195 MII_VCT7_CTRL_CENTIMETERS);
2198 static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2199 const struct phy_tdr_config *cfg)
2201 struct marvell_priv *priv = phydev->priv;
2204 priv->cable_test_tdr = true;
2205 priv->first = marvell_vct5_cm2distance(cfg->first);
2206 priv->last = marvell_vct5_cm2distance(cfg->last);
2207 priv->step = marvell_vct5_cm2distance(cfg->step);
2208 priv->pair = cfg->pair;
2210 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2213 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2217 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2222 ret = marvell_cable_test_start_common(phydev);
2226 ret = ethnl_cable_test_pulse(phydev, 1000);
2230 return ethnl_cable_test_step(phydev,
2231 marvell_vct5_distance2cm(priv->first),
2232 marvell_vct5_distance2cm(priv->last),
2233 marvell_vct5_distance2cm(priv->step));
2236 static int marvell_vct7_distance_to_length(int distance, bool meter)
2244 static bool marvell_vct7_distance_valid(int result)
2247 case MII_VCT7_RESULTS_OPEN:
2248 case MII_VCT7_RESULTS_SAME_SHORT:
2249 case MII_VCT7_RESULTS_CROSS_SHORT:
2255 static int marvell_vct7_report_length(struct phy_device *phydev,
2256 int pair, bool meter)
2261 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2262 MII_VCT7_PAIR_0_DISTANCE + pair);
2266 length = marvell_vct7_distance_to_length(ret, meter);
2268 ethnl_cable_test_fault_length(phydev, pair, length);
2273 static int marvell_vct7_cable_test_report_trans(int result)
2276 case MII_VCT7_RESULTS_OK:
2277 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2278 case MII_VCT7_RESULTS_OPEN:
2279 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2280 case MII_VCT7_RESULTS_SAME_SHORT:
2281 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2282 case MII_VCT7_RESULTS_CROSS_SHORT:
2283 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2285 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2289 static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2291 int pair0, pair1, pair2, pair3;
2295 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2300 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2301 MII_VCT7_RESULTS_PAIR3_SHIFT;
2302 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2303 MII_VCT7_RESULTS_PAIR2_SHIFT;
2304 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2305 MII_VCT7_RESULTS_PAIR1_SHIFT;
2306 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2307 MII_VCT7_RESULTS_PAIR0_SHIFT;
2309 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2310 marvell_vct7_cable_test_report_trans(pair0));
2311 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2312 marvell_vct7_cable_test_report_trans(pair1));
2313 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2314 marvell_vct7_cable_test_report_trans(pair2));
2315 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2316 marvell_vct7_cable_test_report_trans(pair3));
2318 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2322 meter = ret & MII_VCT7_CTRL_METERS;
2324 if (marvell_vct7_distance_valid(pair0))
2325 marvell_vct7_report_length(phydev, 0, meter);
2326 if (marvell_vct7_distance_valid(pair1))
2327 marvell_vct7_report_length(phydev, 1, meter);
2328 if (marvell_vct7_distance_valid(pair2))
2329 marvell_vct7_report_length(phydev, 2, meter);
2330 if (marvell_vct7_distance_valid(pair3))
2331 marvell_vct7_report_length(phydev, 3, meter);
2336 static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2339 struct marvell_priv *priv = phydev->priv;
2342 if (priv->cable_test_tdr) {
2343 ret = marvell_vct5_amplitude_graph(phydev);
2350 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2356 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2359 return marvell_vct7_cable_test_report(phydev);
2366 struct marvell_hwmon_ops {
2367 int (*config)(struct phy_device *phydev);
2368 int (*get_temp)(struct phy_device *phydev, long *temp);
2369 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2370 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2371 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2374 static const struct marvell_hwmon_ops *
2375 to_marvell_hwmon_ops(const struct phy_device *phydev)
2377 return phydev->drv->driver_data;
2380 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2388 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2392 /* Enable temperature sensor */
2393 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2397 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2398 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2402 /* Wait for temperature to stabilize */
2403 usleep_range(10000, 12000);
2405 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2411 /* Disable temperature sensor */
2412 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2413 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2417 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2420 return phy_restore_page(phydev, oldpage, ret);
2423 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2429 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2430 MII_88E1510_TEMP_SENSOR);
2434 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2439 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2445 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2446 MII_88E1121_MISC_TEST);
2450 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2451 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2458 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2461 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2463 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2464 MII_88E1121_MISC_TEST,
2465 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2466 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2469 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2475 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2476 MII_88E1121_MISC_TEST);
2480 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2485 static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2494 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2498 /* Enable temperature sensor */
2499 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2503 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2504 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
2506 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2510 /* Wait for temperature to stabilize */
2511 usleep_range(10000, 12000);
2513 /* Reading the temperature sense has an errata. You need to read
2514 * a number of times and take an average.
2516 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2517 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2520 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2523 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2524 *temp = (sum - 75) * 1000;
2526 /* Disable temperature sensor */
2527 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2531 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2532 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
2534 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2537 phy_restore_page(phydev, oldpage, ret);
2542 static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2546 err = m88e1510_get_temp(phydev, temp);
2548 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2549 * T + 75, so we have to subtract another 50
2556 static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2562 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2563 MII_88E6390_TEMP_SENSOR);
2567 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2568 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2573 static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2575 temp = (temp / 1000) + 75;
2577 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2578 MII_88E6390_TEMP_SENSOR,
2579 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
2580 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
2583 static int m88e6393_hwmon_config(struct phy_device *phydev)
2587 err = m88e6393_set_temp_critical(phydev, 100000);
2591 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2592 MII_88E6390_MISC_TEST,
2593 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
2594 MII_88E6393_MISC_TEST_SAMPLES_MASK |
2595 MII_88E6393_MISC_TEST_RATE_MASK,
2596 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
2597 MII_88E6393_MISC_TEST_SAMPLES_2048 |
2598 MII_88E6393_MISC_TEST_RATE_2_3MS);
2601 static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
2602 u32 attr, int channel, long *temp)
2604 struct phy_device *phydev = dev_get_drvdata(dev);
2605 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2606 int err = -EOPNOTSUPP;
2609 case hwmon_temp_input:
2611 err = ops->get_temp(phydev, temp);
2613 case hwmon_temp_crit:
2614 if (ops->get_temp_critical)
2615 err = ops->get_temp_critical(phydev, temp);
2617 case hwmon_temp_max_alarm:
2618 if (ops->get_temp_alarm)
2619 err = ops->get_temp_alarm(phydev, temp);
2626 static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
2627 u32 attr, int channel, long temp)
2629 struct phy_device *phydev = dev_get_drvdata(dev);
2630 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2631 int err = -EOPNOTSUPP;
2634 case hwmon_temp_crit:
2635 if (ops->set_temp_critical)
2636 err = ops->set_temp_critical(phydev, temp);
2643 static umode_t marvell_hwmon_is_visible(const void *data,
2644 enum hwmon_sensor_types type,
2645 u32 attr, int channel)
2647 const struct phy_device *phydev = data;
2648 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2650 if (type != hwmon_temp)
2654 case hwmon_temp_input:
2655 return ops->get_temp ? 0444 : 0;
2656 case hwmon_temp_max_alarm:
2657 return ops->get_temp_alarm ? 0444 : 0;
2658 case hwmon_temp_crit:
2659 return (ops->get_temp_critical ? 0444 : 0) |
2660 (ops->set_temp_critical ? 0200 : 0);
2666 static u32 marvell_hwmon_chip_config[] = {
2667 HWMON_C_REGISTER_TZ,
2671 static const struct hwmon_channel_info marvell_hwmon_chip = {
2673 .config = marvell_hwmon_chip_config,
2676 /* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
2677 * defined for all PHYs, because the hwmon code checks whether the attributes
2678 * exists via the .is_visible method
2680 static u32 marvell_hwmon_temp_config[] = {
2681 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2685 static const struct hwmon_channel_info marvell_hwmon_temp = {
2687 .config = marvell_hwmon_temp_config,
2690 static const struct hwmon_channel_info *marvell_hwmon_info[] = {
2691 &marvell_hwmon_chip,
2692 &marvell_hwmon_temp,
2696 static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
2697 .is_visible = marvell_hwmon_is_visible,
2698 .read = marvell_hwmon_read,
2699 .write = marvell_hwmon_write,
2702 static const struct hwmon_chip_info marvell_hwmon_chip_info = {
2703 .ops = &marvell_hwmon_hwmon_ops,
2704 .info = marvell_hwmon_info,
2707 static int marvell_hwmon_name(struct phy_device *phydev)
2709 struct marvell_priv *priv = phydev->priv;
2710 struct device *dev = &phydev->mdio.dev;
2711 const char *devname = dev_name(dev);
2712 size_t len = strlen(devname);
2715 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2716 if (!priv->hwmon_name)
2719 for (i = j = 0; i < len && devname[i]; i++) {
2720 if (isalnum(devname[i]))
2721 priv->hwmon_name[j++] = devname[i];
2727 static int marvell_hwmon_probe(struct phy_device *phydev)
2729 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2730 struct marvell_priv *priv = phydev->priv;
2731 struct device *dev = &phydev->mdio.dev;
2737 err = marvell_hwmon_name(phydev);
2741 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2742 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
2743 if (IS_ERR(priv->hwmon_dev))
2744 return PTR_ERR(priv->hwmon_dev);
2747 err = ops->config(phydev);
2752 static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
2753 .get_temp = m88e1121_get_temp,
2756 static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
2757 .get_temp = m88e1510_get_temp,
2758 .get_temp_critical = m88e1510_get_temp_critical,
2759 .set_temp_critical = m88e1510_set_temp_critical,
2760 .get_temp_alarm = m88e1510_get_temp_alarm,
2763 static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
2764 .get_temp = m88e6390_get_temp,
2767 static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
2768 .config = m88e6393_hwmon_config,
2769 .get_temp = m88e6393_get_temp,
2770 .get_temp_critical = m88e6393_get_temp_critical,
2771 .set_temp_critical = m88e6393_set_temp_critical,
2772 .get_temp_alarm = m88e1510_get_temp_alarm,
2775 #define DEF_MARVELL_HWMON_OPS(s) (&(s))
2779 #define DEF_MARVELL_HWMON_OPS(s) NULL
2781 static int marvell_hwmon_probe(struct phy_device *phydev)
2787 static int marvell_probe(struct phy_device *phydev)
2789 struct marvell_priv *priv;
2791 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2795 phydev->priv = priv;
2797 return marvell_hwmon_probe(phydev);
2800 static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
2802 struct phy_device *phydev = upstream;
2803 phy_interface_t interface;
2809 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
2811 dev = &phydev->mdio.dev;
2813 sfp_parse_support(phydev->sfp_bus, id, supported);
2814 interface = sfp_select_interface(phydev->sfp_bus, supported);
2816 dev_info(dev, "%s SFP module inserted\n", phy_modes(interface));
2818 switch (interface) {
2819 case PHY_INTERFACE_MODE_1000BASEX:
2820 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X;
2823 case PHY_INTERFACE_MODE_100BASEX:
2824 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX;
2827 case PHY_INTERFACE_MODE_SGMII:
2828 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII;
2832 dev_err(dev, "Incompatible SFP module inserted\n");
2837 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2841 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2842 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode);
2846 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2847 MII_88E1510_GEN_CTRL_REG_1_RESET);
2850 return phy_restore_page(phydev, oldpage, ret);
2853 static void m88e1510_sfp_remove(void *upstream)
2855 struct phy_device *phydev = upstream;
2859 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2863 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2864 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
2865 MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII);
2869 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2870 MII_88E1510_GEN_CTRL_REG_1_RESET);
2873 phy_restore_page(phydev, oldpage, ret);
2876 static const struct sfp_upstream_ops m88e1510_sfp_ops = {
2877 .module_insert = m88e1510_sfp_insert,
2878 .module_remove = m88e1510_sfp_remove,
2879 .attach = phy_sfp_attach,
2880 .detach = phy_sfp_detach,
2883 static int m88e1510_probe(struct phy_device *phydev)
2887 err = marvell_probe(phydev);
2891 return phy_sfp_probe(phydev, &m88e1510_sfp_ops);
2894 static struct phy_driver marvell_drivers[] = {
2896 .phy_id = MARVELL_PHY_ID_88E1101,
2897 .phy_id_mask = MARVELL_PHY_ID_MASK,
2898 .name = "Marvell 88E1101",
2899 /* PHY_GBIT_FEATURES */
2900 .probe = marvell_probe,
2901 .config_init = marvell_config_init,
2902 .config_aneg = m88e1101_config_aneg,
2903 .config_intr = marvell_config_intr,
2904 .handle_interrupt = marvell_handle_interrupt,
2905 .resume = genphy_resume,
2906 .suspend = genphy_suspend,
2907 .read_page = marvell_read_page,
2908 .write_page = marvell_write_page,
2909 .get_sset_count = marvell_get_sset_count,
2910 .get_strings = marvell_get_strings,
2911 .get_stats = marvell_get_stats,
2914 .phy_id = MARVELL_PHY_ID_88E1112,
2915 .phy_id_mask = MARVELL_PHY_ID_MASK,
2916 .name = "Marvell 88E1112",
2917 /* PHY_GBIT_FEATURES */
2918 .probe = marvell_probe,
2919 .config_init = m88e1112_config_init,
2920 .config_aneg = marvell_config_aneg,
2921 .config_intr = marvell_config_intr,
2922 .handle_interrupt = marvell_handle_interrupt,
2923 .resume = genphy_resume,
2924 .suspend = genphy_suspend,
2925 .read_page = marvell_read_page,
2926 .write_page = marvell_write_page,
2927 .get_sset_count = marvell_get_sset_count,
2928 .get_strings = marvell_get_strings,
2929 .get_stats = marvell_get_stats,
2930 .get_tunable = m88e1011_get_tunable,
2931 .set_tunable = m88e1011_set_tunable,
2934 .phy_id = MARVELL_PHY_ID_88E1111,
2935 .phy_id_mask = MARVELL_PHY_ID_MASK,
2936 .name = "Marvell 88E1111",
2937 /* PHY_GBIT_FEATURES */
2938 .probe = marvell_probe,
2939 .config_init = m88e1111gbe_config_init,
2940 .config_aneg = m88e1111_config_aneg,
2941 .read_status = marvell_read_status,
2942 .config_intr = marvell_config_intr,
2943 .handle_interrupt = marvell_handle_interrupt,
2944 .resume = genphy_resume,
2945 .suspend = genphy_suspend,
2946 .read_page = marvell_read_page,
2947 .write_page = marvell_write_page,
2948 .get_sset_count = marvell_get_sset_count,
2949 .get_strings = marvell_get_strings,
2950 .get_stats = marvell_get_stats,
2951 .get_tunable = m88e1111_get_tunable,
2952 .set_tunable = m88e1111_set_tunable,
2955 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
2956 .phy_id_mask = MARVELL_PHY_ID_MASK,
2957 .name = "Marvell 88E1111 (Finisar)",
2958 /* PHY_GBIT_FEATURES */
2959 .probe = marvell_probe,
2960 .config_init = m88e1111gbe_config_init,
2961 .config_aneg = m88e1111_config_aneg,
2962 .read_status = marvell_read_status,
2963 .config_intr = marvell_config_intr,
2964 .handle_interrupt = marvell_handle_interrupt,
2965 .resume = genphy_resume,
2966 .suspend = genphy_suspend,
2967 .read_page = marvell_read_page,
2968 .write_page = marvell_write_page,
2969 .get_sset_count = marvell_get_sset_count,
2970 .get_strings = marvell_get_strings,
2971 .get_stats = marvell_get_stats,
2972 .get_tunable = m88e1111_get_tunable,
2973 .set_tunable = m88e1111_set_tunable,
2976 .phy_id = MARVELL_PHY_ID_88E1118,
2977 .phy_id_mask = MARVELL_PHY_ID_MASK,
2978 .name = "Marvell 88E1118",
2979 /* PHY_GBIT_FEATURES */
2980 .probe = marvell_probe,
2981 .config_init = m88e1118_config_init,
2982 .config_aneg = m88e1118_config_aneg,
2983 .config_intr = marvell_config_intr,
2984 .handle_interrupt = marvell_handle_interrupt,
2985 .resume = genphy_resume,
2986 .suspend = genphy_suspend,
2987 .read_page = marvell_read_page,
2988 .write_page = marvell_write_page,
2989 .get_sset_count = marvell_get_sset_count,
2990 .get_strings = marvell_get_strings,
2991 .get_stats = marvell_get_stats,
2994 .phy_id = MARVELL_PHY_ID_88E1121R,
2995 .phy_id_mask = MARVELL_PHY_ID_MASK,
2996 .name = "Marvell 88E1121R",
2997 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
2998 /* PHY_GBIT_FEATURES */
2999 .probe = marvell_probe,
3000 .config_init = marvell_1011gbe_config_init,
3001 .config_aneg = m88e1121_config_aneg,
3002 .read_status = marvell_read_status,
3003 .config_intr = marvell_config_intr,
3004 .handle_interrupt = marvell_handle_interrupt,
3005 .resume = genphy_resume,
3006 .suspend = genphy_suspend,
3007 .read_page = marvell_read_page,
3008 .write_page = marvell_write_page,
3009 .get_sset_count = marvell_get_sset_count,
3010 .get_strings = marvell_get_strings,
3011 .get_stats = marvell_get_stats,
3012 .get_tunable = m88e1011_get_tunable,
3013 .set_tunable = m88e1011_set_tunable,
3016 .phy_id = MARVELL_PHY_ID_88E1318S,
3017 .phy_id_mask = MARVELL_PHY_ID_MASK,
3018 .name = "Marvell 88E1318S",
3019 /* PHY_GBIT_FEATURES */
3020 .probe = marvell_probe,
3021 .config_init = m88e1318_config_init,
3022 .config_aneg = m88e1318_config_aneg,
3023 .read_status = marvell_read_status,
3024 .config_intr = marvell_config_intr,
3025 .handle_interrupt = marvell_handle_interrupt,
3026 .get_wol = m88e1318_get_wol,
3027 .set_wol = m88e1318_set_wol,
3028 .resume = genphy_resume,
3029 .suspend = genphy_suspend,
3030 .read_page = marvell_read_page,
3031 .write_page = marvell_write_page,
3032 .get_sset_count = marvell_get_sset_count,
3033 .get_strings = marvell_get_strings,
3034 .get_stats = marvell_get_stats,
3037 .phy_id = MARVELL_PHY_ID_88E1145,
3038 .phy_id_mask = MARVELL_PHY_ID_MASK,
3039 .name = "Marvell 88E1145",
3040 /* PHY_GBIT_FEATURES */
3041 .probe = marvell_probe,
3042 .config_init = m88e1145_config_init,
3043 .config_aneg = m88e1101_config_aneg,
3044 .config_intr = marvell_config_intr,
3045 .handle_interrupt = marvell_handle_interrupt,
3046 .resume = genphy_resume,
3047 .suspend = genphy_suspend,
3048 .read_page = marvell_read_page,
3049 .write_page = marvell_write_page,
3050 .get_sset_count = marvell_get_sset_count,
3051 .get_strings = marvell_get_strings,
3052 .get_stats = marvell_get_stats,
3053 .get_tunable = m88e1111_get_tunable,
3054 .set_tunable = m88e1111_set_tunable,
3057 .phy_id = MARVELL_PHY_ID_88E1149R,
3058 .phy_id_mask = MARVELL_PHY_ID_MASK,
3059 .name = "Marvell 88E1149R",
3060 /* PHY_GBIT_FEATURES */
3061 .probe = marvell_probe,
3062 .config_init = m88e1149_config_init,
3063 .config_aneg = m88e1118_config_aneg,
3064 .config_intr = marvell_config_intr,
3065 .handle_interrupt = marvell_handle_interrupt,
3066 .resume = genphy_resume,
3067 .suspend = genphy_suspend,
3068 .read_page = marvell_read_page,
3069 .write_page = marvell_write_page,
3070 .get_sset_count = marvell_get_sset_count,
3071 .get_strings = marvell_get_strings,
3072 .get_stats = marvell_get_stats,
3075 .phy_id = MARVELL_PHY_ID_88E1240,
3076 .phy_id_mask = MARVELL_PHY_ID_MASK,
3077 .name = "Marvell 88E1240",
3078 /* PHY_GBIT_FEATURES */
3079 .probe = marvell_probe,
3080 .config_init = m88e1112_config_init,
3081 .config_aneg = marvell_config_aneg,
3082 .config_intr = marvell_config_intr,
3083 .handle_interrupt = marvell_handle_interrupt,
3084 .resume = genphy_resume,
3085 .suspend = genphy_suspend,
3086 .read_page = marvell_read_page,
3087 .write_page = marvell_write_page,
3088 .get_sset_count = marvell_get_sset_count,
3089 .get_strings = marvell_get_strings,
3090 .get_stats = marvell_get_stats,
3091 .get_tunable = m88e1011_get_tunable,
3092 .set_tunable = m88e1011_set_tunable,
3095 .phy_id = MARVELL_PHY_ID_88E1116R,
3096 .phy_id_mask = MARVELL_PHY_ID_MASK,
3097 .name = "Marvell 88E1116R",
3098 /* PHY_GBIT_FEATURES */
3099 .probe = marvell_probe,
3100 .config_init = m88e1116r_config_init,
3101 .config_intr = marvell_config_intr,
3102 .handle_interrupt = marvell_handle_interrupt,
3103 .resume = genphy_resume,
3104 .suspend = genphy_suspend,
3105 .read_page = marvell_read_page,
3106 .write_page = marvell_write_page,
3107 .get_sset_count = marvell_get_sset_count,
3108 .get_strings = marvell_get_strings,
3109 .get_stats = marvell_get_stats,
3110 .get_tunable = m88e1011_get_tunable,
3111 .set_tunable = m88e1011_set_tunable,
3114 .phy_id = MARVELL_PHY_ID_88E1510,
3115 .phy_id_mask = MARVELL_PHY_ID_MASK,
3116 .name = "Marvell 88E1510",
3117 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3118 .features = PHY_GBIT_FIBRE_FEATURES,
3119 .flags = PHY_POLL_CABLE_TEST,
3120 .probe = m88e1510_probe,
3121 .config_init = m88e1510_config_init,
3122 .config_aneg = m88e1510_config_aneg,
3123 .read_status = marvell_read_status,
3124 .config_intr = marvell_config_intr,
3125 .handle_interrupt = marvell_handle_interrupt,
3126 .get_wol = m88e1318_get_wol,
3127 .set_wol = m88e1318_set_wol,
3128 .resume = marvell_resume,
3129 .suspend = marvell_suspend,
3130 .read_page = marvell_read_page,
3131 .write_page = marvell_write_page,
3132 .get_sset_count = marvell_get_sset_count,
3133 .get_strings = marvell_get_strings,
3134 .get_stats = marvell_get_stats,
3135 .set_loopback = m88e1510_loopback,
3136 .get_tunable = m88e1011_get_tunable,
3137 .set_tunable = m88e1011_set_tunable,
3138 .cable_test_start = marvell_vct7_cable_test_start,
3139 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3140 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3143 .phy_id = MARVELL_PHY_ID_88E1540,
3144 .phy_id_mask = MARVELL_PHY_ID_MASK,
3145 .name = "Marvell 88E1540",
3146 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3147 /* PHY_GBIT_FEATURES */
3148 .flags = PHY_POLL_CABLE_TEST,
3149 .probe = marvell_probe,
3150 .config_init = marvell_1011gbe_config_init,
3151 .config_aneg = m88e1510_config_aneg,
3152 .read_status = marvell_read_status,
3153 .config_intr = marvell_config_intr,
3154 .handle_interrupt = marvell_handle_interrupt,
3155 .resume = genphy_resume,
3156 .suspend = genphy_suspend,
3157 .read_page = marvell_read_page,
3158 .write_page = marvell_write_page,
3159 .get_sset_count = marvell_get_sset_count,
3160 .get_strings = marvell_get_strings,
3161 .get_stats = marvell_get_stats,
3162 .get_tunable = m88e1540_get_tunable,
3163 .set_tunable = m88e1540_set_tunable,
3164 .cable_test_start = marvell_vct7_cable_test_start,
3165 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3166 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3169 .phy_id = MARVELL_PHY_ID_88E1545,
3170 .phy_id_mask = MARVELL_PHY_ID_MASK,
3171 .name = "Marvell 88E1545",
3172 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3173 .probe = marvell_probe,
3174 /* PHY_GBIT_FEATURES */
3175 .flags = PHY_POLL_CABLE_TEST,
3176 .config_init = marvell_1011gbe_config_init,
3177 .config_aneg = m88e1510_config_aneg,
3178 .read_status = marvell_read_status,
3179 .config_intr = marvell_config_intr,
3180 .handle_interrupt = marvell_handle_interrupt,
3181 .resume = genphy_resume,
3182 .suspend = genphy_suspend,
3183 .read_page = marvell_read_page,
3184 .write_page = marvell_write_page,
3185 .get_sset_count = marvell_get_sset_count,
3186 .get_strings = marvell_get_strings,
3187 .get_stats = marvell_get_stats,
3188 .get_tunable = m88e1540_get_tunable,
3189 .set_tunable = m88e1540_set_tunable,
3190 .cable_test_start = marvell_vct7_cable_test_start,
3191 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3192 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3195 .phy_id = MARVELL_PHY_ID_88E3016,
3196 .phy_id_mask = MARVELL_PHY_ID_MASK,
3197 .name = "Marvell 88E3016",
3198 /* PHY_BASIC_FEATURES */
3199 .probe = marvell_probe,
3200 .config_init = m88e3016_config_init,
3201 .aneg_done = marvell_aneg_done,
3202 .read_status = marvell_read_status,
3203 .config_intr = marvell_config_intr,
3204 .handle_interrupt = marvell_handle_interrupt,
3205 .resume = genphy_resume,
3206 .suspend = genphy_suspend,
3207 .read_page = marvell_read_page,
3208 .write_page = marvell_write_page,
3209 .get_sset_count = marvell_get_sset_count,
3210 .get_strings = marvell_get_strings,
3211 .get_stats = marvell_get_stats,
3214 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
3215 .phy_id_mask = MARVELL_PHY_ID_MASK,
3216 .name = "Marvell 88E6341 Family",
3217 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3218 /* PHY_GBIT_FEATURES */
3219 .flags = PHY_POLL_CABLE_TEST,
3220 .probe = marvell_probe,
3221 .config_init = marvell_1011gbe_config_init,
3222 .config_aneg = m88e6390_config_aneg,
3223 .read_status = marvell_read_status,
3224 .config_intr = marvell_config_intr,
3225 .handle_interrupt = marvell_handle_interrupt,
3226 .resume = genphy_resume,
3227 .suspend = genphy_suspend,
3228 .read_page = marvell_read_page,
3229 .write_page = marvell_write_page,
3230 .get_sset_count = marvell_get_sset_count,
3231 .get_strings = marvell_get_strings,
3232 .get_stats = marvell_get_stats,
3233 .get_tunable = m88e1540_get_tunable,
3234 .set_tunable = m88e1540_set_tunable,
3235 .cable_test_start = marvell_vct7_cable_test_start,
3236 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3237 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3240 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
3241 .phy_id_mask = MARVELL_PHY_ID_MASK,
3242 .name = "Marvell 88E6390 Family",
3243 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
3244 /* PHY_GBIT_FEATURES */
3245 .flags = PHY_POLL_CABLE_TEST,
3246 .probe = marvell_probe,
3247 .config_init = marvell_1011gbe_config_init,
3248 .config_aneg = m88e6390_config_aneg,
3249 .read_status = marvell_read_status,
3250 .config_intr = marvell_config_intr,
3251 .handle_interrupt = marvell_handle_interrupt,
3252 .resume = genphy_resume,
3253 .suspend = genphy_suspend,
3254 .read_page = marvell_read_page,
3255 .write_page = marvell_write_page,
3256 .get_sset_count = marvell_get_sset_count,
3257 .get_strings = marvell_get_strings,
3258 .get_stats = marvell_get_stats,
3259 .get_tunable = m88e1540_get_tunable,
3260 .set_tunable = m88e1540_set_tunable,
3261 .cable_test_start = marvell_vct7_cable_test_start,
3262 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3263 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3266 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
3267 .phy_id_mask = MARVELL_PHY_ID_MASK,
3268 .name = "Marvell 88E6393 Family",
3269 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
3270 /* PHY_GBIT_FEATURES */
3271 .flags = PHY_POLL_CABLE_TEST,
3272 .probe = marvell_probe,
3273 .config_init = marvell_1011gbe_config_init,
3274 .config_aneg = m88e1510_config_aneg,
3275 .read_status = marvell_read_status,
3276 .config_intr = marvell_config_intr,
3277 .handle_interrupt = marvell_handle_interrupt,
3278 .resume = genphy_resume,
3279 .suspend = genphy_suspend,
3280 .read_page = marvell_read_page,
3281 .write_page = marvell_write_page,
3282 .get_sset_count = marvell_get_sset_count,
3283 .get_strings = marvell_get_strings,
3284 .get_stats = marvell_get_stats,
3285 .get_tunable = m88e1540_get_tunable,
3286 .set_tunable = m88e1540_set_tunable,
3287 .cable_test_start = marvell_vct7_cable_test_start,
3288 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3289 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3292 .phy_id = MARVELL_PHY_ID_88E1340S,
3293 .phy_id_mask = MARVELL_PHY_ID_MASK,
3294 .name = "Marvell 88E1340S",
3295 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3296 .probe = marvell_probe,
3297 /* PHY_GBIT_FEATURES */
3298 .config_init = marvell_1011gbe_config_init,
3299 .config_aneg = m88e1510_config_aneg,
3300 .read_status = marvell_read_status,
3301 .config_intr = marvell_config_intr,
3302 .handle_interrupt = marvell_handle_interrupt,
3303 .resume = genphy_resume,
3304 .suspend = genphy_suspend,
3305 .read_page = marvell_read_page,
3306 .write_page = marvell_write_page,
3307 .get_sset_count = marvell_get_sset_count,
3308 .get_strings = marvell_get_strings,
3309 .get_stats = marvell_get_stats,
3310 .get_tunable = m88e1540_get_tunable,
3311 .set_tunable = m88e1540_set_tunable,
3314 .phy_id = MARVELL_PHY_ID_88E1548P,
3315 .phy_id_mask = MARVELL_PHY_ID_MASK,
3316 .name = "Marvell 88E1548P",
3317 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3318 .probe = marvell_probe,
3319 .features = PHY_GBIT_FIBRE_FEATURES,
3320 .config_init = marvell_1011gbe_config_init,
3321 .config_aneg = m88e1510_config_aneg,
3322 .read_status = marvell_read_status,
3323 .config_intr = marvell_config_intr,
3324 .handle_interrupt = marvell_handle_interrupt,
3325 .resume = genphy_resume,
3326 .suspend = genphy_suspend,
3327 .read_page = marvell_read_page,
3328 .write_page = marvell_write_page,
3329 .get_sset_count = marvell_get_sset_count,
3330 .get_strings = marvell_get_strings,
3331 .get_stats = marvell_get_stats,
3332 .get_tunable = m88e1540_get_tunable,
3333 .set_tunable = m88e1540_set_tunable,
3337 module_phy_driver(marvell_drivers);
3339 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3340 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3341 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3342 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3343 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
3344 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3345 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3346 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3347 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3348 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3349 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3350 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3351 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3352 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3353 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3354 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3355 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3356 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3357 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
3358 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3359 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3363 MODULE_DEVICE_TABLE(mdio, marvell_tbl);