1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/lxt.c
5 * Driver for Intel LXT PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/errno.h>
14 #include <linux/unistd.h>
15 #include <linux/interrupt.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/netdevice.h>
19 #include <linux/etherdevice.h>
20 #include <linux/skbuff.h>
21 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/mii.h>
25 #include <linux/ethtool.h>
26 #include <linux/phy.h>
30 #include <linux/uaccess.h>
32 /* The Level one LXT970 is used by many boards */
34 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
36 #define MII_LXT970_IER_IEN 0x0002
38 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
40 #define MII_LXT970_CONFIG 19 /* Configuration Register */
42 /* ------------------------------------------------------------------------- */
43 /* The Level one LXT971 is used on some of my custom boards */
45 /* register definitions for the 971 */
46 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
47 #define MII_LXT971_IER_IEN 0x00f2
49 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
51 /* register definitions for the 973 */
52 #define MII_LXT973_PCR 16 /* Port Configuration Register */
53 #define PCR_FIBER_SELECT 1
55 MODULE_DESCRIPTION("Intel LXT PHY driver");
56 MODULE_AUTHOR("Andy Fleming");
57 MODULE_LICENSE("GPL");
59 static int lxt970_ack_interrupt(struct phy_device *phydev)
63 err = phy_read(phydev, MII_BMSR);
68 err = phy_read(phydev, MII_LXT970_ISR);
76 static int lxt970_config_intr(struct phy_device *phydev)
78 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
79 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
81 return phy_write(phydev, MII_LXT970_IER, 0);
84 static int lxt970_config_init(struct phy_device *phydev)
86 return phy_write(phydev, MII_LXT970_CONFIG, 0);
90 static int lxt971_ack_interrupt(struct phy_device *phydev)
92 int err = phy_read(phydev, MII_LXT971_ISR);
100 static int lxt971_config_intr(struct phy_device *phydev)
102 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
103 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
105 return phy_write(phydev, MII_LXT971_IER, 0);
109 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
110 * of the previous even register when you read a odd register regularly
113 static int lxt973a2_update_link(struct phy_device *phydev)
117 int retry = 8; /* we try 8 times */
120 status = phy_read(phydev, MII_BMSR);
125 control = phy_read(phydev, MII_BMCR);
130 /* Read link and autonegotiation status */
131 status = phy_read(phydev, MII_BMSR);
132 } while (status >= 0 && retry-- && status == control);
137 if ((status & BMSR_LSTATUS) == 0)
145 static int lxt973a2_read_status(struct phy_device *phydev)
151 /* Update the link, but return if there was an error */
152 err = lxt973a2_update_link(phydev);
156 if (AUTONEG_ENABLE == phydev->autoneg) {
159 adv = phy_read(phydev, MII_ADVERTISE);
165 lpa = phy_read(phydev, MII_LPA);
170 /* If both registers are equal, it is suspect but not
171 * impossible, hence a new try
173 } while (lpa == adv && retry--);
175 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa);
179 phydev->speed = SPEED_10;
180 phydev->duplex = DUPLEX_HALF;
181 phydev->pause = phydev->asym_pause = 0;
183 if (lpa & (LPA_100FULL | LPA_100HALF)) {
184 phydev->speed = SPEED_100;
186 if (lpa & LPA_100FULL)
187 phydev->duplex = DUPLEX_FULL;
189 if (lpa & LPA_10FULL)
190 phydev->duplex = DUPLEX_FULL;
193 if (phydev->duplex == DUPLEX_FULL) {
194 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
195 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
198 int bmcr = phy_read(phydev, MII_BMCR);
203 if (bmcr & BMCR_FULLDPLX)
204 phydev->duplex = DUPLEX_FULL;
206 phydev->duplex = DUPLEX_HALF;
208 if (bmcr & BMCR_SPEED1000)
209 phydev->speed = SPEED_1000;
210 else if (bmcr & BMCR_SPEED100)
211 phydev->speed = SPEED_100;
213 phydev->speed = SPEED_10;
215 phydev->pause = phydev->asym_pause = 0;
216 linkmode_zero(phydev->lp_advertising);
222 static int lxt973_probe(struct phy_device *phydev)
224 int val = phy_read(phydev, MII_LXT973_PCR);
226 if (val & PCR_FIBER_SELECT) {
228 * If fiber is selected, then the only correct setting
229 * is 100Mbps, full duplex, and auto negotiation off.
231 val = phy_read(phydev, MII_BMCR);
232 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
233 val &= ~BMCR_ANENABLE;
234 phy_write(phydev, MII_BMCR, val);
235 /* Remember that the port is in fiber mode. */
236 phydev->priv = lxt973_probe;
243 static int lxt973_config_aneg(struct phy_device *phydev)
245 /* Do nothing if port is in fiber mode. */
246 return phydev->priv ? 0 : genphy_config_aneg(phydev);
249 static struct phy_driver lxt97x_driver[] = {
251 .phy_id = 0x78100000,
253 .phy_id_mask = 0xfffffff0,
254 /* PHY_BASIC_FEATURES */
255 .config_init = lxt970_config_init,
256 .ack_interrupt = lxt970_ack_interrupt,
257 .config_intr = lxt970_config_intr,
259 .phy_id = 0x001378e0,
261 .phy_id_mask = 0xfffffff0,
262 /* PHY_BASIC_FEATURES */
263 .ack_interrupt = lxt971_ack_interrupt,
264 .config_intr = lxt971_config_intr,
265 .suspend = genphy_suspend,
266 .resume = genphy_resume,
268 .phy_id = 0x00137a10,
270 .phy_id_mask = 0xffffffff,
271 /* PHY_BASIC_FEATURES */
273 .probe = lxt973_probe,
274 .config_aneg = lxt973_config_aneg,
275 .read_status = lxt973a2_read_status,
276 .suspend = genphy_suspend,
277 .resume = genphy_resume,
279 .phy_id = 0x00137a10,
281 .phy_id_mask = 0xfffffff0,
282 /* PHY_BASIC_FEATURES */
284 .probe = lxt973_probe,
285 .config_aneg = lxt973_config_aneg,
286 .suspend = genphy_suspend,
287 .resume = genphy_resume,
290 module_phy_driver(lxt97x_driver);
292 static struct mdio_device_id __maybe_unused lxt_tbl[] = {
293 { 0x78100000, 0xfffffff0 },
294 { 0x001378e0, 0xfffffff0 },
295 { 0x00137a10, 0xfffffff0 },
299 MODULE_DEVICE_TABLE(mdio, lxt_tbl);