Merge tag 'for-5.13-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave...
[linux-2.6-microblaze.git] / drivers / net / phy / dp83869.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83869 PHY
3  * Copyright (C) 2019 Texas Instruments Inc.
4  */
5
6 #include <linux/ethtool.h>
7 #include <linux/etherdevice.h>
8 #include <linux/kernel.h>
9 #include <linux/mii.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/delay.h>
14 #include <linux/bitfield.h>
15
16 #include <dt-bindings/net/ti-dp83869.h>
17
18 #define DP83869_PHY_ID          0x2000a0f1
19 #define DP83869_DEVADDR         0x1f
20
21 #define MII_DP83869_PHYCTRL     0x10
22 #define MII_DP83869_MICR        0x12
23 #define MII_DP83869_ISR         0x13
24 #define DP83869_CFG2            0x14
25 #define DP83869_CTRL            0x1f
26 #define DP83869_CFG4            0x1e
27
28 /* Extended Registers */
29 #define DP83869_GEN_CFG3        0x0031
30 #define DP83869_RGMIICTL        0x0032
31 #define DP83869_STRAP_STS1      0x006e
32 #define DP83869_RGMIIDCTL       0x0086
33 #define DP83869_RXFCFG          0x0134
34 #define DP83869_RXFPMD1         0x0136
35 #define DP83869_RXFPMD2         0x0137
36 #define DP83869_RXFPMD3         0x0138
37 #define DP83869_RXFSOP1         0x0139
38 #define DP83869_RXFSOP2         0x013A
39 #define DP83869_RXFSOP3         0x013B
40 #define DP83869_IO_MUX_CFG      0x0170
41 #define DP83869_OP_MODE         0x01df
42 #define DP83869_FX_CTRL         0x0c00
43
44 #define DP83869_SW_RESET        BIT(15)
45 #define DP83869_SW_RESTART      BIT(14)
46
47 /* MICR Interrupt bits */
48 #define MII_DP83869_MICR_AN_ERR_INT_EN          BIT(15)
49 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN      BIT(14)
50 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
51 #define MII_DP83869_MICR_PAGE_RXD_INT_EN        BIT(12)
52 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN    BIT(11)
53 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
54 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN   BIT(8)
55 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
56 #define MII_DP83869_MICR_WOL_INT_EN             BIT(3)
57 #define MII_DP83869_MICR_XGMII_ERR_INT_EN       BIT(2)
58 #define MII_DP83869_MICR_POL_CHNG_INT_EN        BIT(1)
59 #define MII_DP83869_MICR_JABBER_INT_EN          BIT(0)
60
61 #define MII_DP83869_BMCR_DEFAULT        (BMCR_ANENABLE | \
62                                          BMCR_FULLDPLX | \
63                                          BMCR_SPEED1000)
64
65 #define MII_DP83869_FIBER_ADVERTISE    (ADVERTISED_FIBRE | \
66                                         ADVERTISED_Pause | \
67                                         ADVERTISED_Asym_Pause)
68
69 /* This is the same bit mask as the BMCR so re-use the BMCR default */
70 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
71
72 /* CFG1 bits */
73 #define DP83869_CFG1_DEFAULT    (ADVERTISE_1000HALF | \
74                                  ADVERTISE_1000FULL | \
75                                  CTL1000_AS_MASTER)
76
77 /* RGMIICTL bits */
78 #define DP83869_RGMII_TX_CLK_DELAY_EN           BIT(1)
79 #define DP83869_RGMII_RX_CLK_DELAY_EN           BIT(0)
80
81 /* RGMIIDCTL */
82 #define DP83869_RGMII_CLK_DELAY_SHIFT           4
83 #define DP83869_CLK_DELAY_DEF                   7
84
85 /* STRAP_STS1 bits */
86 #define DP83869_STRAP_OP_MODE_MASK              GENMASK(2, 0)
87 #define DP83869_STRAP_STS1_RESERVED             BIT(11)
88 #define DP83869_STRAP_MIRROR_ENABLED           BIT(12)
89
90 /* PHYCTRL bits */
91 #define DP83869_RX_FIFO_SHIFT   12
92 #define DP83869_TX_FIFO_SHIFT   14
93
94 /* PHY_CTRL lower bytes 0x48 are declared as reserved */
95 #define DP83869_PHY_CTRL_DEFAULT        0x48
96 #define DP83869_PHYCR_FIFO_DEPTH_MASK   GENMASK(15, 12)
97 #define DP83869_PHYCR_RESERVED_MASK     BIT(11)
98
99 /* IO_MUX_CFG bits */
100 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
101
102 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
103 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
104 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
105 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
106
107 /* CFG3 bits */
108 #define DP83869_CFG3_PORT_MIRROR_EN              BIT(0)
109
110 /* CFG4 bits */
111 #define DP83869_INT_OE  BIT(7)
112
113 /* OP MODE */
114 #define DP83869_OP_MODE_MII                     BIT(5)
115 #define DP83869_SGMII_RGMII_BRIDGE              BIT(6)
116
117 /* RXFCFG bits*/
118 #define DP83869_WOL_MAGIC_EN            BIT(0)
119 #define DP83869_WOL_PATTERN_EN          BIT(1)
120 #define DP83869_WOL_BCAST_EN            BIT(2)
121 #define DP83869_WOL_UCAST_EN            BIT(4)
122 #define DP83869_WOL_SEC_EN              BIT(5)
123 #define DP83869_WOL_ENH_MAC             BIT(7)
124
125 /* CFG2 bits */
126 #define DP83869_DOWNSHIFT_EN            (BIT(8) | BIT(9))
127 #define DP83869_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
128 #define DP83869_DOWNSHIFT_1_COUNT_VAL   0
129 #define DP83869_DOWNSHIFT_2_COUNT_VAL   1
130 #define DP83869_DOWNSHIFT_4_COUNT_VAL   2
131 #define DP83869_DOWNSHIFT_8_COUNT_VAL   3
132 #define DP83869_DOWNSHIFT_1_COUNT       1
133 #define DP83869_DOWNSHIFT_2_COUNT       2
134 #define DP83869_DOWNSHIFT_4_COUNT       4
135 #define DP83869_DOWNSHIFT_8_COUNT       8
136
137 enum {
138         DP83869_PORT_MIRRORING_KEEP,
139         DP83869_PORT_MIRRORING_EN,
140         DP83869_PORT_MIRRORING_DIS,
141 };
142
143 struct dp83869_private {
144         int tx_fifo_depth;
145         int rx_fifo_depth;
146         s32 rx_int_delay;
147         s32 tx_int_delay;
148         int io_impedance;
149         int port_mirroring;
150         bool rxctrl_strap_quirk;
151         int clk_output_sel;
152         int mode;
153 };
154
155 static int dp83869_read_status(struct phy_device *phydev)
156 {
157         struct dp83869_private *dp83869 = phydev->priv;
158         int ret;
159
160         ret = genphy_read_status(phydev);
161         if (ret)
162                 return ret;
163
164         if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
165                 if (phydev->link) {
166                         if (dp83869->mode == DP83869_RGMII_100_BASE)
167                                 phydev->speed = SPEED_100;
168                 } else {
169                         phydev->speed = SPEED_UNKNOWN;
170                         phydev->duplex = DUPLEX_UNKNOWN;
171                 }
172         }
173
174         return 0;
175 }
176
177 static int dp83869_ack_interrupt(struct phy_device *phydev)
178 {
179         int err = phy_read(phydev, MII_DP83869_ISR);
180
181         if (err < 0)
182                 return err;
183
184         return 0;
185 }
186
187 static int dp83869_config_intr(struct phy_device *phydev)
188 {
189         int micr_status = 0, err;
190
191         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
192                 err = dp83869_ack_interrupt(phydev);
193                 if (err)
194                         return err;
195
196                 micr_status = phy_read(phydev, MII_DP83869_MICR);
197                 if (micr_status < 0)
198                         return micr_status;
199
200                 micr_status |=
201                         (MII_DP83869_MICR_AN_ERR_INT_EN |
202                         MII_DP83869_MICR_SPEED_CHNG_INT_EN |
203                         MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
204                         MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
205                         MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
206                         MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
207
208                 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
209         } else {
210                 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
211                 if (err)
212                         return err;
213
214                 err = dp83869_ack_interrupt(phydev);
215         }
216
217         return err;
218 }
219
220 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev)
221 {
222         int irq_status, irq_enabled;
223
224         irq_status = phy_read(phydev, MII_DP83869_ISR);
225         if (irq_status < 0) {
226                 phy_error(phydev);
227                 return IRQ_NONE;
228         }
229
230         irq_enabled = phy_read(phydev, MII_DP83869_MICR);
231         if (irq_enabled < 0) {
232                 phy_error(phydev);
233                 return IRQ_NONE;
234         }
235
236         if (!(irq_status & irq_enabled))
237                 return IRQ_NONE;
238
239         phy_trigger_machine(phydev);
240
241         return IRQ_HANDLED;
242 }
243
244 static int dp83869_set_wol(struct phy_device *phydev,
245                            struct ethtool_wolinfo *wol)
246 {
247         struct net_device *ndev = phydev->attached_dev;
248         int val_rxcfg, val_micr;
249         u8 *mac;
250         int ret;
251
252         val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
253         if (val_rxcfg < 0)
254                 return val_rxcfg;
255
256         val_micr = phy_read(phydev, MII_DP83869_MICR);
257         if (val_micr < 0)
258                 return val_micr;
259
260         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
261                             WAKE_BCAST)) {
262                 val_rxcfg |= DP83869_WOL_ENH_MAC;
263                 val_micr |= MII_DP83869_MICR_WOL_INT_EN;
264
265                 if (wol->wolopts & WAKE_MAGIC ||
266                     wol->wolopts & WAKE_MAGICSECURE) {
267                         mac = (u8 *)ndev->dev_addr;
268
269                         if (!is_valid_ether_addr(mac))
270                                 return -EINVAL;
271
272                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
273                                             DP83869_RXFPMD1,
274                                             mac[1] << 8 | mac[0]);
275                         if (ret)
276                                 return ret;
277
278                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
279                                             DP83869_RXFPMD2,
280                                             mac[3] << 8 | mac[2]);
281                         if (ret)
282                                 return ret;
283
284                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
285                                             DP83869_RXFPMD3,
286                                             mac[5] << 8 | mac[4]);
287                         if (ret)
288                                 return ret;
289
290                         val_rxcfg |= DP83869_WOL_MAGIC_EN;
291                 } else {
292                         val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
293                 }
294
295                 if (wol->wolopts & WAKE_MAGICSECURE) {
296                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
297                                             DP83869_RXFSOP1,
298                                             (wol->sopass[1] << 8) | wol->sopass[0]);
299                         if (ret)
300                                 return ret;
301
302                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
303                                             DP83869_RXFSOP2,
304                                             (wol->sopass[3] << 8) | wol->sopass[2]);
305                         if (ret)
306                                 return ret;
307                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
308                                             DP83869_RXFSOP3,
309                                             (wol->sopass[5] << 8) | wol->sopass[4]);
310                         if (ret)
311                                 return ret;
312
313                         val_rxcfg |= DP83869_WOL_SEC_EN;
314                 } else {
315                         val_rxcfg &= ~DP83869_WOL_SEC_EN;
316                 }
317
318                 if (wol->wolopts & WAKE_UCAST)
319                         val_rxcfg |= DP83869_WOL_UCAST_EN;
320                 else
321                         val_rxcfg &= ~DP83869_WOL_UCAST_EN;
322
323                 if (wol->wolopts & WAKE_BCAST)
324                         val_rxcfg |= DP83869_WOL_BCAST_EN;
325                 else
326                         val_rxcfg &= ~DP83869_WOL_BCAST_EN;
327         } else {
328                 val_rxcfg &= ~DP83869_WOL_ENH_MAC;
329                 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
330         }
331
332         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
333         if (ret)
334                 return ret;
335
336         return phy_write(phydev, MII_DP83869_MICR, val_micr);
337 }
338
339 static void dp83869_get_wol(struct phy_device *phydev,
340                             struct ethtool_wolinfo *wol)
341 {
342         int value, sopass_val;
343
344         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
345                         WAKE_MAGICSECURE);
346         wol->wolopts = 0;
347
348         value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
349         if (value < 0) {
350                 phydev_err(phydev, "Failed to read RX CFG\n");
351                 return;
352         }
353
354         if (value & DP83869_WOL_UCAST_EN)
355                 wol->wolopts |= WAKE_UCAST;
356
357         if (value & DP83869_WOL_BCAST_EN)
358                 wol->wolopts |= WAKE_BCAST;
359
360         if (value & DP83869_WOL_MAGIC_EN)
361                 wol->wolopts |= WAKE_MAGIC;
362
363         if (value & DP83869_WOL_SEC_EN) {
364                 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
365                                           DP83869_RXFSOP1);
366                 if (sopass_val < 0) {
367                         phydev_err(phydev, "Failed to read RX SOP 1\n");
368                         return;
369                 }
370
371                 wol->sopass[0] = (sopass_val & 0xff);
372                 wol->sopass[1] = (sopass_val >> 8);
373
374                 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
375                                           DP83869_RXFSOP2);
376                 if (sopass_val < 0) {
377                         phydev_err(phydev, "Failed to read RX SOP 2\n");
378                         return;
379                 }
380
381                 wol->sopass[2] = (sopass_val & 0xff);
382                 wol->sopass[3] = (sopass_val >> 8);
383
384                 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
385                                           DP83869_RXFSOP3);
386                 if (sopass_val < 0) {
387                         phydev_err(phydev, "Failed to read RX SOP 3\n");
388                         return;
389                 }
390
391                 wol->sopass[4] = (sopass_val & 0xff);
392                 wol->sopass[5] = (sopass_val >> 8);
393
394                 wol->wolopts |= WAKE_MAGICSECURE;
395         }
396
397         if (!(value & DP83869_WOL_ENH_MAC))
398                 wol->wolopts = 0;
399 }
400
401 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
402 {
403         int val, cnt, enable, count;
404
405         val = phy_read(phydev, DP83869_CFG2);
406         if (val < 0)
407                 return val;
408
409         enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
410         cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
411
412         switch (cnt) {
413         case DP83869_DOWNSHIFT_1_COUNT_VAL:
414                 count = DP83869_DOWNSHIFT_1_COUNT;
415                 break;
416         case DP83869_DOWNSHIFT_2_COUNT_VAL:
417                 count = DP83869_DOWNSHIFT_2_COUNT;
418                 break;
419         case DP83869_DOWNSHIFT_4_COUNT_VAL:
420                 count = DP83869_DOWNSHIFT_4_COUNT;
421                 break;
422         case DP83869_DOWNSHIFT_8_COUNT_VAL:
423                 count = DP83869_DOWNSHIFT_8_COUNT;
424                 break;
425         default:
426                 return -EINVAL;
427         }
428
429         *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
430
431         return 0;
432 }
433
434 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
435 {
436         int val, count;
437
438         if (cnt > DP83869_DOWNSHIFT_8_COUNT)
439                 return -EINVAL;
440
441         if (!cnt)
442                 return phy_clear_bits(phydev, DP83869_CFG2,
443                                       DP83869_DOWNSHIFT_EN);
444
445         switch (cnt) {
446         case DP83869_DOWNSHIFT_1_COUNT:
447                 count = DP83869_DOWNSHIFT_1_COUNT_VAL;
448                 break;
449         case DP83869_DOWNSHIFT_2_COUNT:
450                 count = DP83869_DOWNSHIFT_2_COUNT_VAL;
451                 break;
452         case DP83869_DOWNSHIFT_4_COUNT:
453                 count = DP83869_DOWNSHIFT_4_COUNT_VAL;
454                 break;
455         case DP83869_DOWNSHIFT_8_COUNT:
456                 count = DP83869_DOWNSHIFT_8_COUNT_VAL;
457                 break;
458         default:
459                 phydev_err(phydev,
460                            "Downshift count must be 1, 2, 4 or 8\n");
461                 return -EINVAL;
462         }
463
464         val = DP83869_DOWNSHIFT_EN;
465         val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
466
467         return phy_modify(phydev, DP83869_CFG2,
468                           DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
469                           val);
470 }
471
472 static int dp83869_get_tunable(struct phy_device *phydev,
473                                struct ethtool_tunable *tuna, void *data)
474 {
475         switch (tuna->id) {
476         case ETHTOOL_PHY_DOWNSHIFT:
477                 return dp83869_get_downshift(phydev, data);
478         default:
479                 return -EOPNOTSUPP;
480         }
481 }
482
483 static int dp83869_set_tunable(struct phy_device *phydev,
484                                struct ethtool_tunable *tuna, const void *data)
485 {
486         switch (tuna->id) {
487         case ETHTOOL_PHY_DOWNSHIFT:
488                 return dp83869_set_downshift(phydev, *(const u8 *)data);
489         default:
490                 return -EOPNOTSUPP;
491         }
492 }
493
494 static int dp83869_config_port_mirroring(struct phy_device *phydev)
495 {
496         struct dp83869_private *dp83869 = phydev->priv;
497
498         if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
499                 return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
500                                         DP83869_GEN_CFG3,
501                                         DP83869_CFG3_PORT_MIRROR_EN);
502         else
503                 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
504                                           DP83869_GEN_CFG3,
505                                           DP83869_CFG3_PORT_MIRROR_EN);
506 }
507
508 static int dp83869_set_strapped_mode(struct phy_device *phydev)
509 {
510         struct dp83869_private *dp83869 = phydev->priv;
511         int val;
512
513         val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
514         if (val < 0)
515                 return val;
516
517         dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
518
519         return 0;
520 }
521
522 #if IS_ENABLED(CONFIG_OF_MDIO)
523 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
524                                              1750, 2000, 2250, 2500, 2750, 3000,
525                                              3250, 3500, 3750, 4000};
526
527 static int dp83869_of_init(struct phy_device *phydev)
528 {
529         struct dp83869_private *dp83869 = phydev->priv;
530         struct device *dev = &phydev->mdio.dev;
531         struct device_node *of_node = dev->of_node;
532         int delay_size = ARRAY_SIZE(dp83869_internal_delay);
533         int ret;
534
535         if (!of_node)
536                 return -ENODEV;
537
538         dp83869->io_impedance = -EINVAL;
539
540         /* Optional configuration */
541         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
542                                    &dp83869->clk_output_sel);
543         if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
544                 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
545
546         ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
547         if (ret == 0) {
548                 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
549                     dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
550                         return -EINVAL;
551         } else {
552                 ret = dp83869_set_strapped_mode(phydev);
553                 if (ret)
554                         return ret;
555         }
556
557         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
558                 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
559         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
560                 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
561
562         if (of_property_read_bool(of_node, "enet-phy-lane-swap")) {
563                 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
564         } else {
565                 /* If the lane swap is not in the DT then check the straps */
566                 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
567                 if (ret < 0)
568                         return ret;
569
570                 if (ret & DP83869_STRAP_MIRROR_ENABLED)
571                         dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
572                 else
573                         dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
574
575                 ret = 0;
576         }
577
578         if (of_property_read_u32(of_node, "rx-fifo-depth",
579                                  &dp83869->rx_fifo_depth))
580                 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
581
582         if (of_property_read_u32(of_node, "tx-fifo-depth",
583                                  &dp83869->tx_fifo_depth))
584                 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
585
586         dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
587                                                        &dp83869_internal_delay[0],
588                                                        delay_size, true);
589         if (dp83869->rx_int_delay < 0)
590                 dp83869->rx_int_delay =
591                                 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
592
593         dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
594                                                        &dp83869_internal_delay[0],
595                                                        delay_size, false);
596         if (dp83869->tx_int_delay < 0)
597                 dp83869->tx_int_delay =
598                                 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
599
600         return ret;
601 }
602 #else
603 static int dp83869_of_init(struct phy_device *phydev)
604 {
605         return dp83869_set_strapped_mode(phydev);
606 }
607 #endif /* CONFIG_OF_MDIO */
608
609 static int dp83869_configure_rgmii(struct phy_device *phydev,
610                                    struct dp83869_private *dp83869)
611 {
612         int ret = 0, val;
613
614         if (phy_interface_is_rgmii(phydev)) {
615                 val = phy_read(phydev, MII_DP83869_PHYCTRL);
616                 if (val < 0)
617                         return val;
618
619                 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
620                 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
621                 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
622
623                 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
624                 if (ret)
625                         return ret;
626         }
627
628         if (dp83869->io_impedance >= 0)
629                 ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
630                                      DP83869_IO_MUX_CFG,
631                                      DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
632                                      dp83869->io_impedance &
633                                      DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
634
635         return ret;
636 }
637
638 static int dp83869_configure_fiber(struct phy_device *phydev,
639                                    struct dp83869_private *dp83869)
640 {
641         int bmcr;
642         int ret;
643
644         /* Only allow advertising what this PHY supports */
645         linkmode_and(phydev->advertising, phydev->advertising,
646                      phydev->supported);
647
648         linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
649         linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
650
651         if (dp83869->mode == DP83869_RGMII_1000_BASE) {
652                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
653                                  phydev->supported);
654         } else {
655                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
656                                  phydev->supported);
657                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
658                                  phydev->supported);
659
660                 /* Auto neg is not supported in 100base FX mode */
661                 bmcr = phy_read(phydev, MII_BMCR);
662                 if (bmcr < 0)
663                         return bmcr;
664
665                 phydev->autoneg = AUTONEG_DISABLE;
666                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
667                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
668
669                 if (bmcr & BMCR_ANENABLE) {
670                         ret =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
671                         if (ret < 0)
672                                 return ret;
673                 }
674         }
675
676         /* Update advertising from supported */
677         linkmode_or(phydev->advertising, phydev->advertising,
678                     phydev->supported);
679
680         return 0;
681 }
682
683 static int dp83869_configure_mode(struct phy_device *phydev,
684                                   struct dp83869_private *dp83869)
685 {
686         int phy_ctrl_val;
687         int ret;
688
689         if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
690             dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
691                 return -EINVAL;
692
693         /* Below init sequence for each operational mode is defined in
694          * section 9.4.8 of the datasheet.
695          */
696         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
697                             dp83869->mode);
698         if (ret)
699                 return ret;
700
701         ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
702         if (ret)
703                 return ret;
704
705         phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
706                         dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
707                         DP83869_PHY_CTRL_DEFAULT);
708
709         switch (dp83869->mode) {
710         case DP83869_RGMII_COPPER_ETHERNET:
711                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
712                                 phy_ctrl_val);
713                 if (ret)
714                         return ret;
715
716                 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
717                 if (ret)
718                         return ret;
719
720                 ret = dp83869_configure_rgmii(phydev, dp83869);
721                 if (ret)
722                         return ret;
723                 break;
724         case DP83869_RGMII_SGMII_BRIDGE:
725                 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
726                                      DP83869_SGMII_RGMII_BRIDGE,
727                                      DP83869_SGMII_RGMII_BRIDGE);
728                 if (ret)
729                         return ret;
730
731                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
732                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
733                 if (ret)
734                         return ret;
735
736                 break;
737         case DP83869_1000M_MEDIA_CONVERT:
738                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
739                                 phy_ctrl_val);
740                 if (ret)
741                         return ret;
742
743                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
744                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
745                 if (ret)
746                         return ret;
747                 break;
748         case DP83869_100M_MEDIA_CONVERT:
749                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
750                                 phy_ctrl_val);
751                 if (ret)
752                         return ret;
753                 break;
754         case DP83869_SGMII_COPPER_ETHERNET:
755                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
756                                 phy_ctrl_val);
757                 if (ret)
758                         return ret;
759
760                 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
761                 if (ret)
762                         return ret;
763
764                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
765                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
766                 if (ret)
767                         return ret;
768
769                 break;
770         case DP83869_RGMII_1000_BASE:
771         case DP83869_RGMII_100_BASE:
772                 ret = dp83869_configure_fiber(phydev, dp83869);
773                 break;
774         default:
775                 return -EINVAL;
776         }
777
778         return ret;
779 }
780
781 static int dp83869_config_init(struct phy_device *phydev)
782 {
783         struct dp83869_private *dp83869 = phydev->priv;
784         int ret, val;
785
786         /* Force speed optimization for the PHY even if it strapped */
787         ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
788                          DP83869_DOWNSHIFT_EN);
789         if (ret)
790                 return ret;
791
792         ret = dp83869_configure_mode(phydev, dp83869);
793         if (ret)
794                 return ret;
795
796         /* Enable Interrupt output INT_OE in CFG4 register */
797         if (phy_interrupt_is_valid(phydev)) {
798                 val = phy_read(phydev, DP83869_CFG4);
799                 val |= DP83869_INT_OE;
800                 phy_write(phydev, DP83869_CFG4, val);
801         }
802
803         if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
804                 dp83869_config_port_mirroring(phydev);
805
806         /* Clock output selection if muxing property is set */
807         if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
808                 ret = phy_modify_mmd(phydev,
809                                      DP83869_DEVADDR, DP83869_IO_MUX_CFG,
810                                      DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
811                                      dp83869->clk_output_sel <<
812                                      DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
813
814         if (phy_interface_is_rgmii(phydev)) {
815                 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
816                                     dp83869->rx_int_delay |
817                         dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT);
818                 if (ret)
819                         return ret;
820
821                 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
822                 val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
823                         DP83869_RGMII_RX_CLK_DELAY_EN);
824
825                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
826                         val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
827                                  DP83869_RGMII_RX_CLK_DELAY_EN);
828
829                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
830                         val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
831
832                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
833                         val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
834
835                 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
836                                     val);
837         }
838
839         return ret;
840 }
841
842 static int dp83869_probe(struct phy_device *phydev)
843 {
844         struct dp83869_private *dp83869;
845         int ret;
846
847         dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
848                                GFP_KERNEL);
849         if (!dp83869)
850                 return -ENOMEM;
851
852         phydev->priv = dp83869;
853
854         ret = dp83869_of_init(phydev);
855         if (ret)
856                 return ret;
857
858         if (dp83869->mode == DP83869_RGMII_100_BASE ||
859             dp83869->mode == DP83869_RGMII_1000_BASE)
860                 phydev->port = PORT_FIBRE;
861
862         return dp83869_config_init(phydev);
863 }
864
865 static int dp83869_phy_reset(struct phy_device *phydev)
866 {
867         int ret;
868
869         ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
870         if (ret < 0)
871                 return ret;
872
873         usleep_range(10, 20);
874
875         /* Global sw reset sets all registers to default.
876          * Need to set the registers in the PHY to the right config.
877          */
878         return dp83869_config_init(phydev);
879 }
880
881 static struct phy_driver dp83869_driver[] = {
882         {
883                 PHY_ID_MATCH_MODEL(DP83869_PHY_ID),
884                 .name           = "TI DP83869",
885
886                 .probe          = dp83869_probe,
887                 .config_init    = dp83869_config_init,
888                 .soft_reset     = dp83869_phy_reset,
889
890                 /* IRQ related */
891                 .config_intr    = dp83869_config_intr,
892                 .handle_interrupt = dp83869_handle_interrupt,
893                 .read_status    = dp83869_read_status,
894
895                 .get_tunable    = dp83869_get_tunable,
896                 .set_tunable    = dp83869_set_tunable,
897
898                 .get_wol        = dp83869_get_wol,
899                 .set_wol        = dp83869_set_wol,
900
901                 .suspend        = genphy_suspend,
902                 .resume         = genphy_resume,
903         },
904 };
905 module_phy_driver(dp83869_driver);
906
907 static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
908         { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
909         { }
910 };
911 MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
912
913 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
914 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
915 MODULE_LICENSE("GPL v2");