drivers/net/phy/dp83869.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83869 PHY
   3  * Copyright (C) 2019 Texas Instruments Inc.
   4  */
   5
   6 #include <linux/ethtool.h>
   7 #include <linux/etherdevice.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mii.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/delay.h>
  14 #include <linux/bitfield.h>
  15
  16 #include <dt-bindings/net/ti-dp83869.h>
  17
  18 #define DP83869_PHY_ID          0x2000a0f1
  19 #define DP83869_DEVADDR         0x1f
  20
  21 #define MII_DP83869_PHYCTRL     0x10
  22 #define MII_DP83869_MICR        0x12
  23 #define MII_DP83869_ISR         0x13
  24 #define DP83869_CFG2            0x14
  25 #define DP83869_CTRL            0x1f
  26 #define DP83869_CFG4            0x1e
  27
  28 /* Extended Registers */
  29 #define DP83869_GEN_CFG3        0x0031
  30 #define DP83869_RGMIICTL        0x0032
  31 #define DP83869_STRAP_STS1      0x006e
  32 #define DP83869_RGMIIDCTL       0x0086
  33 #define DP83869_RXFCFG          0x0134
  34 #define DP83869_RXFPMD1         0x0136
  35 #define DP83869_RXFPMD2         0x0137
  36 #define DP83869_RXFPMD3         0x0138
  37 #define DP83869_RXFSOP1         0x0139
  38 #define DP83869_RXFSOP2         0x013A
  39 #define DP83869_RXFSOP3         0x013B
  40 #define DP83869_IO_MUX_CFG      0x0170
  41 #define DP83869_OP_MODE         0x01df
  42 #define DP83869_FX_CTRL         0x0c00
  43
  44 #define DP83869_SW_RESET        BIT(15)
  45 #define DP83869_SW_RESTART      BIT(14)
  46
  47 /* MICR Interrupt bits */
  48 #define MII_DP83869_MICR_AN_ERR_INT_EN          BIT(15)
  49 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN      BIT(14)
  50 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  51 #define MII_DP83869_MICR_PAGE_RXD_INT_EN        BIT(12)
  52 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  53 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  54 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  55 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  56 #define MII_DP83869_MICR_WOL_INT_EN             BIT(3)
  57 #define MII_DP83869_MICR_XGMII_ERR_INT_EN       BIT(2)
  58 #define MII_DP83869_MICR_POL_CHNG_INT_EN        BIT(1)
  59 #define MII_DP83869_MICR_JABBER_INT_EN          BIT(0)
  60
  61 #define MII_DP83869_BMCR_DEFAULT        (BMCR_ANENABLE | \
  62                                          BMCR_FULLDPLX | \
  63                                          BMCR_SPEED1000)
  64
  65 #define MII_DP83869_FIBER_ADVERTISE    (ADVERTISED_FIBRE | \
  66                                         ADVERTISED_Pause | \
  67                                         ADVERTISED_Asym_Pause)
  68
  69 /* This is the same bit mask as the BMCR so re-use the BMCR default */
  70 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
  71
  72 /* CFG1 bits */
  73 #define DP83869_CFG1_DEFAULT    (ADVERTISE_1000HALF | \
  74                                  ADVERTISE_1000FULL | \
  75                                  CTL1000_AS_MASTER)
  76
  77 /* RGMIICTL bits */
  78 #define DP83869_RGMII_TX_CLK_DELAY_EN           BIT(1)
  79 #define DP83869_RGMII_RX_CLK_DELAY_EN           BIT(0)
  80
  81 /* RGMIIDCTL */
  82 #define DP83869_RGMII_CLK_DELAY_SHIFT           4
  83 #define DP83869_CLK_DELAY_DEF                   7
  84
  85 /* STRAP_STS1 bits */
  86 #define DP83869_STRAP_OP_MODE_MASK              GENMASK(2, 0)
  87 #define DP83869_STRAP_STS1_RESERVED             BIT(11)
  88 #define DP83869_STRAP_MIRROR_ENABLED           BIT(12)
  89
  90 /* PHYCTRL bits */
  91 #define DP83869_RX_FIFO_SHIFT   12
  92 #define DP83869_TX_FIFO_SHIFT   14
  93
  94 /* PHY_CTRL lower bytes 0x48 are declared as reserved */
  95 #define DP83869_PHY_CTRL_DEFAULT        0x48
  96 #define DP83869_PHYCR_FIFO_DEPTH_MASK   GENMASK(15, 12)
  97 #define DP83869_PHYCR_RESERVED_MASK     BIT(11)
  98
  99 /* IO_MUX_CFG bits */
 100 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
 101
 102 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 103 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 104 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 105 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 106
 107 /* CFG3 bits */
 108 #define DP83869_CFG3_PORT_MIRROR_EN              BIT(0)
 109
 110 /* CFG4 bits */
 111 #define DP83869_INT_OE  BIT(7)
 112
 113 /* OP MODE */
 114 #define DP83869_OP_MODE_MII                     BIT(5)
 115 #define DP83869_SGMII_RGMII_BRIDGE              BIT(6)
 116
 117 /* RXFCFG bits*/
 118 #define DP83869_WOL_MAGIC_EN            BIT(0)
 119 #define DP83869_WOL_PATTERN_EN          BIT(1)
 120 #define DP83869_WOL_BCAST_EN            BIT(2)
 121 #define DP83869_WOL_UCAST_EN            BIT(4)
 122 #define DP83869_WOL_SEC_EN              BIT(5)
 123 #define DP83869_WOL_ENH_MAC             BIT(7)
 124
 125 /* CFG2 bits */
 126 #define DP83869_DOWNSHIFT_EN            (BIT(8) | BIT(9))
 127 #define DP83869_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
 128 #define DP83869_DOWNSHIFT_1_COUNT_VAL   0
 129 #define DP83869_DOWNSHIFT_2_COUNT_VAL   1
 130 #define DP83869_DOWNSHIFT_4_COUNT_VAL   2
 131 #define DP83869_DOWNSHIFT_8_COUNT_VAL   3
 132 #define DP83869_DOWNSHIFT_1_COUNT       1
 133 #define DP83869_DOWNSHIFT_2_COUNT       2
 134 #define DP83869_DOWNSHIFT_4_COUNT       4
 135 #define DP83869_DOWNSHIFT_8_COUNT       8
 136
 137 enum {
 138         DP83869_PORT_MIRRORING_KEEP,
 139         DP83869_PORT_MIRRORING_EN,
 140         DP83869_PORT_MIRRORING_DIS,
 141 };
 142
 143 struct dp83869_private {
 144         int tx_fifo_depth;
 145         int rx_fifo_depth;
 146         s32 rx_int_delay;
 147         s32 tx_int_delay;
 148         int io_impedance;
 149         int port_mirroring;
 150         bool rxctrl_strap_quirk;
 151         int clk_output_sel;
 152         int mode;
 153 };
 154
 155 static int dp83869_read_status(struct phy_device *phydev)
 156 {
 157         struct dp83869_private *dp83869 = phydev->priv;
 158         int ret;
 159
 160         ret = genphy_read_status(phydev);
 161         if (ret)
 162                 return ret;
 163
 164         if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
 165                 if (phydev->link) {
 166                         if (dp83869->mode == DP83869_RGMII_100_BASE)
 167                                 phydev->speed = SPEED_100;
 168                 } else {
 169                         phydev->speed = SPEED_UNKNOWN;
 170                         phydev->duplex = DUPLEX_UNKNOWN;
 171                 }
 172         }
 173
 174         return 0;
 175 }
 176
 177 static int dp83869_ack_interrupt(struct phy_device *phydev)
 178 {
 179         int err = phy_read(phydev, MII_DP83869_ISR);
 180
 181         if (err < 0)
 182                 return err;
 183
 184         return 0;
 185 }
 186
 187 static int dp83869_config_intr(struct phy_device *phydev)
 188 {
 189         int micr_status = 0;
 190
 191         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 192                 micr_status = phy_read(phydev, MII_DP83869_MICR);
 193                 if (micr_status < 0)
 194                         return micr_status;
 195
 196                 micr_status |=
 197                         (MII_DP83869_MICR_AN_ERR_INT_EN |
 198                         MII_DP83869_MICR_SPEED_CHNG_INT_EN |
 199                         MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
 200                         MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
 201                         MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
 202                         MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
 203
 204                 return phy_write(phydev, MII_DP83869_MICR, micr_status);
 205         }
 206
 207         return phy_write(phydev, MII_DP83869_MICR, micr_status);
 208 }
 209
 210 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev)
 211 {
 212         int irq_status, irq_enabled;
 213
 214         irq_status = phy_read(phydev, MII_DP83869_ISR);
 215         if (irq_status < 0) {
 216                 phy_error(phydev);
 217                 return IRQ_NONE;
 218         }
 219
 220         irq_enabled = phy_read(phydev, MII_DP83869_MICR);
 221         if (irq_enabled < 0) {
 222                 phy_error(phydev);
 223                 return IRQ_NONE;
 224         }
 225
 226         if (!(irq_status & irq_enabled))
 227                 return IRQ_NONE;
 228
 229         phy_trigger_machine(phydev);
 230
 231         return IRQ_HANDLED;
 232 }
 233
 234 static int dp83869_set_wol(struct phy_device *phydev,
 235                            struct ethtool_wolinfo *wol)
 236 {
 237         struct net_device *ndev = phydev->attached_dev;
 238         int val_rxcfg, val_micr;
 239         u8 *mac;
 240         int ret;
 241
 242         val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
 243         if (val_rxcfg < 0)
 244                 return val_rxcfg;
 245
 246         val_micr = phy_read(phydev, MII_DP83869_MICR);
 247         if (val_micr < 0)
 248                 return val_micr;
 249
 250         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 251                             WAKE_BCAST)) {
 252                 val_rxcfg |= DP83869_WOL_ENH_MAC;
 253                 val_micr |= MII_DP83869_MICR_WOL_INT_EN;
 254
 255                 if (wol->wolopts & WAKE_MAGIC ||
 256                     wol->wolopts & WAKE_MAGICSECURE) {
 257                         mac = (u8 *)ndev->dev_addr;
 258
 259                         if (!is_valid_ether_addr(mac))
 260                                 return -EINVAL;
 261
 262                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 263                                             DP83869_RXFPMD1,
 264                                             mac[1] << 8 | mac[0]);
 265                         if (ret)
 266                                 return ret;
 267
 268                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 269                                             DP83869_RXFPMD2,
 270                                             mac[3] << 8 | mac[2]);
 271                         if (ret)
 272                                 return ret;
 273
 274                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 275                                             DP83869_RXFPMD3,
 276                                             mac[5] << 8 | mac[4]);
 277                         if (ret)
 278                                 return ret;
 279
 280                         val_rxcfg |= DP83869_WOL_MAGIC_EN;
 281                 } else {
 282                         val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
 283                 }
 284
 285                 if (wol->wolopts & WAKE_MAGICSECURE) {
 286                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 287                                             DP83869_RXFSOP1,
 288                                             (wol->sopass[1] << 8) | wol->sopass[0]);
 289                         if (ret)
 290                                 return ret;
 291
 292                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 293                                             DP83869_RXFSOP2,
 294                                             (wol->sopass[3] << 8) | wol->sopass[2]);
 295                         if (ret)
 296                                 return ret;
 297                         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 298                                             DP83869_RXFSOP3,
 299                                             (wol->sopass[5] << 8) | wol->sopass[4]);
 300                         if (ret)
 301                                 return ret;
 302
 303                         val_rxcfg |= DP83869_WOL_SEC_EN;
 304                 } else {
 305                         val_rxcfg &= ~DP83869_WOL_SEC_EN;
 306                 }
 307
 308                 if (wol->wolopts & WAKE_UCAST)
 309                         val_rxcfg |= DP83869_WOL_UCAST_EN;
 310                 else
 311                         val_rxcfg &= ~DP83869_WOL_UCAST_EN;
 312
 313                 if (wol->wolopts & WAKE_BCAST)
 314                         val_rxcfg |= DP83869_WOL_BCAST_EN;
 315                 else
 316                         val_rxcfg &= ~DP83869_WOL_BCAST_EN;
 317         } else {
 318                 val_rxcfg &= ~DP83869_WOL_ENH_MAC;
 319                 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
 320         }
 321
 322         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
 323         if (ret)
 324                 return ret;
 325
 326         return phy_write(phydev, MII_DP83869_MICR, val_micr);
 327 }
 328
 329 static void dp83869_get_wol(struct phy_device *phydev,
 330                             struct ethtool_wolinfo *wol)
 331 {
 332         int value, sopass_val;
 333
 334         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 335                         WAKE_MAGICSECURE);
 336         wol->wolopts = 0;
 337
 338         value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
 339         if (value < 0) {
 340                 phydev_err(phydev, "Failed to read RX CFG\n");
 341                 return;
 342         }
 343
 344         if (value & DP83869_WOL_UCAST_EN)
 345                 wol->wolopts |= WAKE_UCAST;
 346
 347         if (value & DP83869_WOL_BCAST_EN)
 348                 wol->wolopts |= WAKE_BCAST;
 349
 350         if (value & DP83869_WOL_MAGIC_EN)
 351                 wol->wolopts |= WAKE_MAGIC;
 352
 353         if (value & DP83869_WOL_SEC_EN) {
 354                 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
 355                                           DP83869_RXFSOP1);
 356                 if (sopass_val < 0) {
 357                         phydev_err(phydev, "Failed to read RX SOP 1\n");
 358                         return;
 359                 }
 360
 361                 wol->sopass[0] = (sopass_val & 0xff);
 362                 wol->sopass[1] = (sopass_val >> 8);
 363
 364                 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
 365                                           DP83869_RXFSOP2);
 366                 if (sopass_val < 0) {
 367                         phydev_err(phydev, "Failed to read RX SOP 2\n");
 368                         return;
 369                 }
 370
 371                 wol->sopass[2] = (sopass_val & 0xff);
 372                 wol->sopass[3] = (sopass_val >> 8);
 373
 374                 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
 375                                           DP83869_RXFSOP3);
 376                 if (sopass_val < 0) {
 377                         phydev_err(phydev, "Failed to read RX SOP 3\n");
 378                         return;
 379                 }
 380
 381                 wol->sopass[4] = (sopass_val & 0xff);
 382                 wol->sopass[5] = (sopass_val >> 8);
 383
 384                 wol->wolopts |= WAKE_MAGICSECURE;
 385         }
 386
 387         if (!(value & DP83869_WOL_ENH_MAC))
 388                 wol->wolopts = 0;
 389 }
 390
 391 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
 392 {
 393         int val, cnt, enable, count;
 394
 395         val = phy_read(phydev, DP83869_CFG2);
 396         if (val < 0)
 397                 return val;
 398
 399         enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
 400         cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
 401
 402         switch (cnt) {
 403         case DP83869_DOWNSHIFT_1_COUNT_VAL:
 404                 count = DP83869_DOWNSHIFT_1_COUNT;
 405                 break;
 406         case DP83869_DOWNSHIFT_2_COUNT_VAL:
 407                 count = DP83869_DOWNSHIFT_2_COUNT;
 408                 break;
 409         case DP83869_DOWNSHIFT_4_COUNT_VAL:
 410                 count = DP83869_DOWNSHIFT_4_COUNT;
 411                 break;
 412         case DP83869_DOWNSHIFT_8_COUNT_VAL:
 413                 count = DP83869_DOWNSHIFT_8_COUNT;
 414                 break;
 415         default:
 416                 return -EINVAL;
 417         }
 418
 419         *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
 420
 421         return 0;
 422 }
 423
 424 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
 425 {
 426         int val, count;
 427
 428         if (cnt > DP83869_DOWNSHIFT_8_COUNT)
 429                 return -EINVAL;
 430
 431         if (!cnt)
 432                 return phy_clear_bits(phydev, DP83869_CFG2,
 433                                       DP83869_DOWNSHIFT_EN);
 434
 435         switch (cnt) {
 436         case DP83869_DOWNSHIFT_1_COUNT:
 437                 count = DP83869_DOWNSHIFT_1_COUNT_VAL;
 438                 break;
 439         case DP83869_DOWNSHIFT_2_COUNT:
 440                 count = DP83869_DOWNSHIFT_2_COUNT_VAL;
 441                 break;
 442         case DP83869_DOWNSHIFT_4_COUNT:
 443                 count = DP83869_DOWNSHIFT_4_COUNT_VAL;
 444                 break;
 445         case DP83869_DOWNSHIFT_8_COUNT:
 446                 count = DP83869_DOWNSHIFT_8_COUNT_VAL;
 447                 break;
 448         default:
 449                 phydev_err(phydev,
 450                            "Downshift count must be 1, 2, 4 or 8\n");
 451                 return -EINVAL;
 452         }
 453
 454         val = DP83869_DOWNSHIFT_EN;
 455         val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
 456
 457         return phy_modify(phydev, DP83869_CFG2,
 458                           DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
 459                           val);
 460 }
 461
 462 static int dp83869_get_tunable(struct phy_device *phydev,
 463                                struct ethtool_tunable *tuna, void *data)
 464 {
 465         switch (tuna->id) {
 466         case ETHTOOL_PHY_DOWNSHIFT:
 467                 return dp83869_get_downshift(phydev, data);
 468         default:
 469                 return -EOPNOTSUPP;
 470         }
 471 }
 472
 473 static int dp83869_set_tunable(struct phy_device *phydev,
 474                                struct ethtool_tunable *tuna, const void *data)
 475 {
 476         switch (tuna->id) {
 477         case ETHTOOL_PHY_DOWNSHIFT:
 478                 return dp83869_set_downshift(phydev, *(const u8 *)data);
 479         default:
 480                 return -EOPNOTSUPP;
 481         }
 482 }
 483
 484 static int dp83869_config_port_mirroring(struct phy_device *phydev)
 485 {
 486         struct dp83869_private *dp83869 = phydev->priv;
 487
 488         if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
 489                 return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
 490                                         DP83869_GEN_CFG3,
 491                                         DP83869_CFG3_PORT_MIRROR_EN);
 492         else
 493                 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
 494                                           DP83869_GEN_CFG3,
 495                                           DP83869_CFG3_PORT_MIRROR_EN);
 496 }
 497
 498 static int dp83869_set_strapped_mode(struct phy_device *phydev)
 499 {
 500         struct dp83869_private *dp83869 = phydev->priv;
 501         int val;
 502
 503         val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
 504         if (val < 0)
 505                 return val;
 506
 507         dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
 508
 509         return 0;
 510 }
 511
 512 #if IS_ENABLED(CONFIG_OF_MDIO)
 513 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
 514                                              1750, 2000, 2250, 2500, 2750, 3000,
 515                                              3250, 3500, 3750, 4000};
 516
 517 static int dp83869_of_init(struct phy_device *phydev)
 518 {
 519         struct dp83869_private *dp83869 = phydev->priv;
 520         struct device *dev = &phydev->mdio.dev;
 521         struct device_node *of_node = dev->of_node;
 522         int delay_size = ARRAY_SIZE(dp83869_internal_delay);
 523         int ret;
 524
 525         if (!of_node)
 526                 return -ENODEV;
 527
 528         dp83869->io_impedance = -EINVAL;
 529
 530         /* Optional configuration */
 531         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 532                                    &dp83869->clk_output_sel);
 533         if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
 534                 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
 535
 536         ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
 537         if (ret == 0) {
 538                 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
 539                     dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
 540                         return -EINVAL;
 541         } else {
 542                 ret = dp83869_set_strapped_mode(phydev);
 543                 if (ret)
 544                         return ret;
 545         }
 546
 547         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 548                 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 549         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 550                 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 551
 552         if (of_property_read_bool(of_node, "enet-phy-lane-swap")) {
 553                 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
 554         } else {
 555                 /* If the lane swap is not in the DT then check the straps */
 556                 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
 557                 if (ret < 0)
 558                         return ret;
 559
 560                 if (ret & DP83869_STRAP_MIRROR_ENABLED)
 561                         dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
 562                 else
 563                         dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
 564
 565                 ret = 0;
 566         }
 567
 568         if (of_property_read_u32(of_node, "rx-fifo-depth",
 569                                  &dp83869->rx_fifo_depth))
 570                 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
 571
 572         if (of_property_read_u32(of_node, "tx-fifo-depth",
 573                                  &dp83869->tx_fifo_depth))
 574                 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
 575
 576         dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
 577                                                        &dp83869_internal_delay[0],
 578                                                        delay_size, true);
 579         if (dp83869->rx_int_delay < 0)
 580                 dp83869->rx_int_delay =
 581                                 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
 582
 583         dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
 584                                                        &dp83869_internal_delay[0],
 585                                                        delay_size, false);
 586         if (dp83869->tx_int_delay < 0)
 587                 dp83869->tx_int_delay =
 588                                 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
 589
 590         return ret;
 591 }
 592 #else
 593 static int dp83869_of_init(struct phy_device *phydev)
 594 {
 595         return dp83869_set_strapped_mode(phydev);
 596 }
 597 #endif /* CONFIG_OF_MDIO */
 598
 599 static int dp83869_configure_rgmii(struct phy_device *phydev,
 600                                    struct dp83869_private *dp83869)
 601 {
 602         int ret = 0, val;
 603
 604         if (phy_interface_is_rgmii(phydev)) {
 605                 val = phy_read(phydev, MII_DP83869_PHYCTRL);
 606                 if (val < 0)
 607                         return val;
 608
 609                 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
 610                 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
 611                 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
 612
 613                 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
 614                 if (ret)
 615                         return ret;
 616         }
 617
 618         if (dp83869->io_impedance >= 0)
 619                 ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
 620                                      DP83869_IO_MUX_CFG,
 621                                      DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
 622                                      dp83869->io_impedance &
 623                                      DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
 624
 625         return ret;
 626 }
 627
 628 static int dp83869_configure_fiber(struct phy_device *phydev,
 629                                    struct dp83869_private *dp83869)
 630 {
 631         int bmcr;
 632         int ret;
 633
 634         /* Only allow advertising what this PHY supports */
 635         linkmode_and(phydev->advertising, phydev->advertising,
 636                      phydev->supported);
 637
 638         linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
 639         linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
 640
 641         if (dp83869->mode == DP83869_RGMII_1000_BASE) {
 642                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 643                                  phydev->supported);
 644         } else {
 645                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 646                                  phydev->supported);
 647                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 648                                  phydev->supported);
 649
 650                 /* Auto neg is not supported in 100base FX mode */
 651                 bmcr = phy_read(phydev, MII_BMCR);
 652                 if (bmcr < 0)
 653                         return bmcr;
 654
 655                 phydev->autoneg = AUTONEG_DISABLE;
 656                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
 657                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
 658
 659                 if (bmcr & BMCR_ANENABLE) {
 660                         ret =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
 661                         if (ret < 0)
 662                                 return ret;
 663                 }
 664         }
 665
 666         /* Update advertising from supported */
 667         linkmode_or(phydev->advertising, phydev->advertising,
 668                     phydev->supported);
 669
 670         return 0;
 671 }
 672
 673 static int dp83869_configure_mode(struct phy_device *phydev,
 674                                   struct dp83869_private *dp83869)
 675 {
 676         int phy_ctrl_val;
 677         int ret;
 678
 679         if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
 680             dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
 681                 return -EINVAL;
 682
 683         /* Below init sequence for each operational mode is defined in
 684          * section 9.4.8 of the datasheet.
 685          */
 686         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
 687                             dp83869->mode);
 688         if (ret)
 689                 return ret;
 690
 691         ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
 692         if (ret)
 693                 return ret;
 694
 695         phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
 696                         dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
 697                         DP83869_PHY_CTRL_DEFAULT);
 698
 699         switch (dp83869->mode) {
 700         case DP83869_RGMII_COPPER_ETHERNET:
 701                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 702                                 phy_ctrl_val);
 703                 if (ret)
 704                         return ret;
 705
 706                 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
 707                 if (ret)
 708                         return ret;
 709
 710                 ret = dp83869_configure_rgmii(phydev, dp83869);
 711                 if (ret)
 712                         return ret;
 713                 break;
 714         case DP83869_RGMII_SGMII_BRIDGE:
 715                 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
 716                                      DP83869_SGMII_RGMII_BRIDGE,
 717                                      DP83869_SGMII_RGMII_BRIDGE);
 718                 if (ret)
 719                         return ret;
 720
 721                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 722                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 723                 if (ret)
 724                         return ret;
 725
 726                 break;
 727         case DP83869_1000M_MEDIA_CONVERT:
 728                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 729                                 phy_ctrl_val);
 730                 if (ret)
 731                         return ret;
 732
 733                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 734                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 735                 if (ret)
 736                         return ret;
 737                 break;
 738         case DP83869_100M_MEDIA_CONVERT:
 739                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 740                                 phy_ctrl_val);
 741                 if (ret)
 742                         return ret;
 743                 break;
 744         case DP83869_SGMII_COPPER_ETHERNET:
 745                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 746                                 phy_ctrl_val);
 747                 if (ret)
 748                         return ret;
 749
 750                 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
 751                 if (ret)
 752                         return ret;
 753
 754                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 755                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 756                 if (ret)
 757                         return ret;
 758
 759                 break;
 760         case DP83869_RGMII_1000_BASE:
 761         case DP83869_RGMII_100_BASE:
 762                 ret = dp83869_configure_fiber(phydev, dp83869);
 763                 break;
 764         default:
 765                 return -EINVAL;
 766         }
 767
 768         return ret;
 769 }
 770
 771 static int dp83869_config_init(struct phy_device *phydev)
 772 {
 773         struct dp83869_private *dp83869 = phydev->priv;
 774         int ret, val;
 775
 776         /* Force speed optimization for the PHY even if it strapped */
 777         ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
 778                          DP83869_DOWNSHIFT_EN);
 779         if (ret)
 780                 return ret;
 781
 782         ret = dp83869_configure_mode(phydev, dp83869);
 783         if (ret)
 784                 return ret;
 785
 786         /* Enable Interrupt output INT_OE in CFG4 register */
 787         if (phy_interrupt_is_valid(phydev)) {
 788                 val = phy_read(phydev, DP83869_CFG4);
 789                 val |= DP83869_INT_OE;
 790                 phy_write(phydev, DP83869_CFG4, val);
 791         }
 792
 793         if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
 794                 dp83869_config_port_mirroring(phydev);
 795
 796         /* Clock output selection if muxing property is set */
 797         if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
 798                 ret = phy_modify_mmd(phydev,
 799                                      DP83869_DEVADDR, DP83869_IO_MUX_CFG,
 800                                      DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
 801                                      dp83869->clk_output_sel <<
 802                                      DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 803
 804         if (phy_interface_is_rgmii(phydev)) {
 805                 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
 806                                     dp83869->rx_int_delay |
 807                         dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT);
 808                 if (ret)
 809                         return ret;
 810
 811                 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
 812                 val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
 813                         DP83869_RGMII_RX_CLK_DELAY_EN);
 814
 815                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 816                         val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
 817                                  DP83869_RGMII_RX_CLK_DELAY_EN);
 818
 819                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 820                         val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
 821
 822                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 823                         val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
 824
 825                 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
 826                                     val);
 827         }
 828
 829         return ret;
 830 }
 831
 832 static int dp83869_probe(struct phy_device *phydev)
 833 {
 834         struct dp83869_private *dp83869;
 835         int ret;
 836
 837         dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
 838                                GFP_KERNEL);
 839         if (!dp83869)
 840                 return -ENOMEM;
 841
 842         phydev->priv = dp83869;
 843
 844         ret = dp83869_of_init(phydev);
 845         if (ret)
 846                 return ret;
 847
 848         return dp83869_config_init(phydev);
 849 }
 850
 851 static int dp83869_phy_reset(struct phy_device *phydev)
 852 {
 853         int ret;
 854
 855         ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
 856         if (ret < 0)
 857                 return ret;
 858
 859         usleep_range(10, 20);
 860
 861         /* Global sw reset sets all registers to default.
 862          * Need to set the registers in the PHY to the right config.
 863          */
 864         return dp83869_config_init(phydev);
 865 }
 866
 867 static struct phy_driver dp83869_driver[] = {
 868         {
 869                 PHY_ID_MATCH_MODEL(DP83869_PHY_ID),
 870                 .name           = "TI DP83869",
 871
 872                 .probe          = dp83869_probe,
 873                 .config_init    = dp83869_config_init,
 874                 .soft_reset     = dp83869_phy_reset,
 875
 876                 /* IRQ related */
 877                 .ack_interrupt  = dp83869_ack_interrupt,
 878                 .config_intr    = dp83869_config_intr,
 879                 .handle_interrupt = dp83869_handle_interrupt,
 880                 .read_status    = dp83869_read_status,
 881
 882                 .get_tunable    = dp83869_get_tunable,
 883                 .set_tunable    = dp83869_set_tunable,
 884
 885                 .get_wol        = dp83869_get_wol,
 886                 .set_wol        = dp83869_set_wol,
 887
 888                 .suspend        = genphy_suspend,
 889                 .resume         = genphy_resume,
 890         },
 891 };
 892 module_phy_driver(dp83869_driver);
 893
 894 static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
 895         { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
 896         { }
 897 };
 898 MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
 899
 900 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
 901 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 902 MODULE_LICENSE("GPL v2");