1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Texas Instruments DP83867 PHY
5 * Copyright (C) 2015 Texas Instruments Inc.
8 #include <linux/ethtool.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/bitfield.h>
19 #include <dt-bindings/net/ti-dp83867.h>
21 #define DP83867_PHY_ID 0x2000a231
22 #define DP83867_DEVADDR 0x1f
24 #define MII_DP83867_PHYCTRL 0x10
25 #define MII_DP83867_PHYSTS 0x11
26 #define MII_DP83867_MICR 0x12
27 #define MII_DP83867_ISR 0x13
28 #define DP83867_CFG2 0x14
29 #define DP83867_CFG3 0x1e
30 #define DP83867_CTRL 0x1f
32 /* Extended Registers */
33 #define DP83867_FLD_THR_CFG 0x002e
34 #define DP83867_CFG4 0x0031
35 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
36 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
37 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
38 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
39 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
41 #define DP83867_RGMIICTL 0x0032
42 #define DP83867_STRAP_STS1 0x006E
43 #define DP83867_STRAP_STS2 0x006f
44 #define DP83867_RGMIIDCTL 0x0086
45 #define DP83867_RXFCFG 0x0134
46 #define DP83867_RXFPMD1 0x0136
47 #define DP83867_RXFPMD2 0x0137
48 #define DP83867_RXFPMD3 0x0138
49 #define DP83867_RXFSOP1 0x0139
50 #define DP83867_RXFSOP2 0x013A
51 #define DP83867_RXFSOP3 0x013B
52 #define DP83867_IO_MUX_CFG 0x0170
53 #define DP83867_SGMIICTL 0x00D3
54 #define DP83867_10M_SGMII_CFG 0x016F
55 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
57 #define DP83867_SW_RESET BIT(15)
58 #define DP83867_SW_RESTART BIT(14)
60 /* MICR Interrupt bits */
61 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
62 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
63 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
64 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
65 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
66 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
67 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
68 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
69 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
70 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
71 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
72 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
75 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
76 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
79 #define DP83867_SGMII_TYPE BIT(14)
82 #define DP83867_WOL_MAGIC_EN BIT(0)
83 #define DP83867_WOL_BCAST_EN BIT(2)
84 #define DP83867_WOL_UCAST_EN BIT(4)
85 #define DP83867_WOL_SEC_EN BIT(5)
86 #define DP83867_WOL_ENH_MAC BIT(7)
89 #define DP83867_STRAP_STS1_RESERVED BIT(11)
92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
93 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
95 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
96 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
97 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
100 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
101 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
102 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
103 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
104 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
105 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
106 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
109 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
110 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
111 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
112 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
113 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
114 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
117 /* IO_MUX_CFG bits */
118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
119 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
120 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
121 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
122 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
123 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
126 #define DP83867_PHYSTS_1000 BIT(15)
127 #define DP83867_PHYSTS_100 BIT(14)
128 #define DP83867_PHYSTS_DUPLEX BIT(13)
129 #define DP83867_PHYSTS_LINK BIT(10)
132 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
133 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
134 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0
135 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1
136 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2
137 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3
138 #define DP83867_DOWNSHIFT_1_COUNT 1
139 #define DP83867_DOWNSHIFT_2_COUNT 2
140 #define DP83867_DOWNSHIFT_4_COUNT 4
141 #define DP83867_DOWNSHIFT_8_COUNT 8
144 #define DP83867_CFG3_INT_OE BIT(7)
145 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
148 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
151 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
154 DP83867_PORT_MIRROING_KEEP,
155 DP83867_PORT_MIRROING_EN,
156 DP83867_PORT_MIRROING_DIS,
159 struct dp83867_private {
166 bool rxctrl_strap_quirk;
169 bool sgmii_ref_clk_en;
172 static int dp83867_ack_interrupt(struct phy_device *phydev)
174 int err = phy_read(phydev, MII_DP83867_ISR);
182 static int dp83867_set_wol(struct phy_device *phydev,
183 struct ethtool_wolinfo *wol)
185 struct net_device *ndev = phydev->attached_dev;
186 u16 val_rxcfg, val_micr;
189 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
190 val_micr = phy_read(phydev, MII_DP83867_MICR);
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
194 val_rxcfg |= DP83867_WOL_ENH_MAC;
195 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
197 if (wol->wolopts & WAKE_MAGIC) {
198 mac = (u8 *)ndev->dev_addr;
200 if (!is_valid_ether_addr(mac))
203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
204 (mac[1] << 8 | mac[0]));
205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
206 (mac[3] << 8 | mac[2]));
207 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
208 (mac[5] << 8 | mac[4]));
210 val_rxcfg |= DP83867_WOL_MAGIC_EN;
212 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
215 if (wol->wolopts & WAKE_MAGICSECURE) {
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
217 (wol->sopass[1] << 8) | wol->sopass[0]);
218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
219 (wol->sopass[3] << 8) | wol->sopass[2]);
220 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
221 (wol->sopass[5] << 8) | wol->sopass[4]);
223 val_rxcfg |= DP83867_WOL_SEC_EN;
225 val_rxcfg &= ~DP83867_WOL_SEC_EN;
228 if (wol->wolopts & WAKE_UCAST)
229 val_rxcfg |= DP83867_WOL_UCAST_EN;
231 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
233 if (wol->wolopts & WAKE_BCAST)
234 val_rxcfg |= DP83867_WOL_BCAST_EN;
236 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
238 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
239 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
243 phy_write(phydev, MII_DP83867_MICR, val_micr);
248 static void dp83867_get_wol(struct phy_device *phydev,
249 struct ethtool_wolinfo *wol)
251 u16 value, sopass_val;
253 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
257 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
259 if (value & DP83867_WOL_UCAST_EN)
260 wol->wolopts |= WAKE_UCAST;
262 if (value & DP83867_WOL_BCAST_EN)
263 wol->wolopts |= WAKE_BCAST;
265 if (value & DP83867_WOL_MAGIC_EN)
266 wol->wolopts |= WAKE_MAGIC;
268 if (value & DP83867_WOL_SEC_EN) {
269 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
271 wol->sopass[0] = (sopass_val & 0xff);
272 wol->sopass[1] = (sopass_val >> 8);
274 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
276 wol->sopass[2] = (sopass_val & 0xff);
277 wol->sopass[3] = (sopass_val >> 8);
279 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
281 wol->sopass[4] = (sopass_val & 0xff);
282 wol->sopass[5] = (sopass_val >> 8);
284 wol->wolopts |= WAKE_MAGICSECURE;
287 if (!(value & DP83867_WOL_ENH_MAC))
291 static int dp83867_config_intr(struct phy_device *phydev)
295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
296 micr_status = phy_read(phydev, MII_DP83867_MICR);
301 (MII_DP83867_MICR_AN_ERR_INT_EN |
302 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
303 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
304 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
305 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
306 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
308 return phy_write(phydev, MII_DP83867_MICR, micr_status);
312 return phy_write(phydev, MII_DP83867_MICR, micr_status);
315 static int dp83867_read_status(struct phy_device *phydev)
317 int status = phy_read(phydev, MII_DP83867_PHYSTS);
320 ret = genphy_read_status(phydev);
327 if (status & DP83867_PHYSTS_DUPLEX)
328 phydev->duplex = DUPLEX_FULL;
330 phydev->duplex = DUPLEX_HALF;
332 if (status & DP83867_PHYSTS_1000)
333 phydev->speed = SPEED_1000;
334 else if (status & DP83867_PHYSTS_100)
335 phydev->speed = SPEED_100;
337 phydev->speed = SPEED_10;
342 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
344 int val, cnt, enable, count;
346 val = phy_read(phydev, DP83867_CFG2);
350 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
351 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
354 case DP83867_DOWNSHIFT_1_COUNT_VAL:
355 count = DP83867_DOWNSHIFT_1_COUNT;
357 case DP83867_DOWNSHIFT_2_COUNT_VAL:
358 count = DP83867_DOWNSHIFT_2_COUNT;
360 case DP83867_DOWNSHIFT_4_COUNT_VAL:
361 count = DP83867_DOWNSHIFT_4_COUNT;
363 case DP83867_DOWNSHIFT_8_COUNT_VAL:
364 count = DP83867_DOWNSHIFT_8_COUNT;
370 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
375 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
379 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
383 return phy_clear_bits(phydev, DP83867_CFG2,
384 DP83867_DOWNSHIFT_EN);
387 case DP83867_DOWNSHIFT_1_COUNT:
388 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
390 case DP83867_DOWNSHIFT_2_COUNT:
391 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
393 case DP83867_DOWNSHIFT_4_COUNT:
394 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
396 case DP83867_DOWNSHIFT_8_COUNT:
397 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
401 "Downshift count must be 1, 2, 4 or 8\n");
405 val = DP83867_DOWNSHIFT_EN;
406 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
408 return phy_modify(phydev, DP83867_CFG2,
409 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
413 static int dp83867_get_tunable(struct phy_device *phydev,
414 struct ethtool_tunable *tuna, void *data)
417 case ETHTOOL_PHY_DOWNSHIFT:
418 return dp83867_get_downshift(phydev, data);
424 static int dp83867_set_tunable(struct phy_device *phydev,
425 struct ethtool_tunable *tuna, const void *data)
428 case ETHTOOL_PHY_DOWNSHIFT:
429 return dp83867_set_downshift(phydev, *(const u8 *)data);
435 static int dp83867_config_port_mirroring(struct phy_device *phydev)
437 struct dp83867_private *dp83867 =
438 (struct dp83867_private *)phydev->priv;
440 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
441 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
442 DP83867_CFG4_PORT_MIRROR_EN);
444 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
445 DP83867_CFG4_PORT_MIRROR_EN);
449 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
451 struct dp83867_private *dp83867 = phydev->priv;
453 /* Existing behavior was to use default pin strapping delay in rgmii
454 * mode, but rgmii should have meant no delay. Warn existing users.
456 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
457 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
459 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
460 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
461 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
462 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
464 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
465 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
467 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
468 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
472 /* RX delay *must* be specified if internal delay of RX is used. */
473 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
474 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
475 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
476 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
480 /* TX delay *must* be specified if internal delay of TX is used. */
481 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
482 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
483 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
484 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
491 #if IS_ENABLED(CONFIG_OF_MDIO)
492 static int dp83867_of_init(struct phy_device *phydev)
494 struct dp83867_private *dp83867 = phydev->priv;
495 struct device *dev = &phydev->mdio.dev;
496 struct device_node *of_node = dev->of_node;
502 /* Optional configuration */
503 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
504 &dp83867->clk_output_sel);
505 /* If not set, keep default */
507 dp83867->set_clk_output = true;
508 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
509 * DP83867_CLK_O_SEL_OFF.
511 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
512 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
513 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
514 dp83867->clk_output_sel);
519 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
520 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
521 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
522 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
524 dp83867->io_impedance = -1; /* leave at default */
526 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
527 "ti,dp83867-rxctrl-strap-quirk");
529 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
530 "ti,sgmii-ref-clock-output-enable");
533 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
534 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
535 &dp83867->rx_id_delay);
536 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
538 "ti,rx-internal-delay value of %u out of range\n",
539 dp83867->rx_id_delay);
543 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
544 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
545 &dp83867->tx_id_delay);
546 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
548 "ti,tx-internal-delay value of %u out of range\n",
549 dp83867->tx_id_delay);
553 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
554 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
556 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
557 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
559 ret = of_property_read_u32(of_node, "ti,fifo-depth",
560 &dp83867->tx_fifo_depth);
562 ret = of_property_read_u32(of_node, "tx-fifo-depth",
563 &dp83867->tx_fifo_depth);
565 dp83867->tx_fifo_depth =
566 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
569 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
570 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
571 dp83867->tx_fifo_depth);
575 ret = of_property_read_u32(of_node, "rx-fifo-depth",
576 &dp83867->rx_fifo_depth);
578 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
580 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
581 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
582 dp83867->rx_fifo_depth);
589 static int dp83867_of_init(struct phy_device *phydev)
593 #endif /* CONFIG_OF_MDIO */
595 static int dp83867_probe(struct phy_device *phydev)
597 struct dp83867_private *dp83867;
599 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
604 phydev->priv = dp83867;
606 return dp83867_of_init(phydev);
609 static int dp83867_config_init(struct phy_device *phydev)
611 struct dp83867_private *dp83867 = phydev->priv;
615 /* Force speed optimization for the PHY even if it strapped */
616 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
617 DP83867_DOWNSHIFT_EN);
621 ret = dp83867_verify_rgmii_cfg(phydev);
625 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
626 if (dp83867->rxctrl_strap_quirk)
627 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
630 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
631 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
632 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
633 * be set to 0x2. This may causes the PHY link to be unstable -
634 * the default value 0x1 need to be restored.
636 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
638 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
644 if (phy_interface_is_rgmii(phydev) ||
645 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
646 val = phy_read(phydev, MII_DP83867_PHYCTRL);
650 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
651 val |= (dp83867->tx_fifo_depth <<
652 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
654 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
655 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
656 val |= (dp83867->rx_fifo_depth <<
657 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
660 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
665 if (phy_interface_is_rgmii(phydev)) {
666 val = phy_read(phydev, MII_DP83867_PHYCTRL);
670 /* The code below checks if "port mirroring" N/A MODE4 has been
671 * enabled during power on bootstrap.
673 * Such N/A mode enabled by mistake can put PHY IC in some
674 * internal testing mode and disable RGMII transmission.
676 * In this particular case one needs to check STRAP_STS1
677 * register's bit 11 (marked as RESERVED).
680 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
681 if (bs & DP83867_STRAP_STS1_RESERVED)
682 val &= ~DP83867_PHYCR_RESERVED_MASK;
684 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
688 /* If rgmii mode with no internal delay is selected, we do NOT use
689 * aligned mode as one might expect. Instead we use the PHY's default
690 * based on pin strapping. And the "mode 0" default is to *use*
691 * internal delay with a value of 7 (2.00 ns).
693 * Set up RGMII delays
695 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
697 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
698 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
699 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
701 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
702 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
704 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
705 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
707 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
710 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
711 delay |= dp83867->rx_id_delay;
712 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
713 delay |= dp83867->tx_id_delay <<
714 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
716 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
720 /* If specified, set io impedance */
721 if (dp83867->io_impedance >= 0)
722 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
723 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
724 dp83867->io_impedance);
726 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
727 /* For support SPEED_10 in SGMII mode
728 * DP83867_10M_SGMII_RATE_ADAPT bit
729 * has to be cleared by software. That
730 * does not affect SPEED_100 and
733 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
734 DP83867_10M_SGMII_CFG,
735 DP83867_10M_SGMII_RATE_ADAPT_MASK,
740 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
741 * are 01). That is not enough to finalize autoneg on some
742 * devices. Increase this timer duration to maximum 16ms.
744 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
746 DP83867_CFG4_SGMII_ANEG_MASK,
747 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
752 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
753 /* SGMII type is set to 4-wire mode by default.
754 * If we place appropriate property in dts (see above)
755 * switch on 6-wire mode.
757 if (dp83867->sgmii_ref_clk_en)
758 val |= DP83867_SGMII_TYPE;
760 val &= ~DP83867_SGMII_TYPE;
761 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
764 val = phy_read(phydev, DP83867_CFG3);
765 /* Enable Interrupt output INT_OE in CFG3 register */
766 if (phy_interrupt_is_valid(phydev))
767 val |= DP83867_CFG3_INT_OE;
769 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
770 phy_write(phydev, DP83867_CFG3, val);
772 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
773 dp83867_config_port_mirroring(phydev);
775 /* Clock output selection if muxing property is set */
776 if (dp83867->set_clk_output) {
777 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
779 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
780 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
782 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
783 val = dp83867->clk_output_sel <<
784 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
787 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
794 static int dp83867_phy_reset(struct phy_device *phydev)
798 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
802 usleep_range(10, 20);
804 /* After reset FORCE_LINK_GOOD bit is set. Although the
805 * default value should be unset. Disable FORCE_LINK_GOOD
806 * for the phy to work properly.
808 return phy_modify(phydev, MII_DP83867_PHYCTRL,
809 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
812 static struct phy_driver dp83867_driver[] = {
814 .phy_id = DP83867_PHY_ID,
815 .phy_id_mask = 0xfffffff0,
816 .name = "TI DP83867",
817 /* PHY_GBIT_FEATURES */
819 .probe = dp83867_probe,
820 .config_init = dp83867_config_init,
821 .soft_reset = dp83867_phy_reset,
823 .read_status = dp83867_read_status,
824 .get_tunable = dp83867_get_tunable,
825 .set_tunable = dp83867_set_tunable,
827 .get_wol = dp83867_get_wol,
828 .set_wol = dp83867_set_wol,
831 .ack_interrupt = dp83867_ack_interrupt,
832 .config_intr = dp83867_config_intr,
834 .suspend = genphy_suspend,
835 .resume = genphy_resume,
838 module_phy_driver(dp83867_driver);
840 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
841 { DP83867_PHY_ID, 0xfffffff0 },
845 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
847 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
848 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
849 MODULE_LICENSE("GPL v2");