drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  */
   6
   7 #include <linux/ethtool.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mii.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/delay.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/bitfield.h>
  17
  18 #include <dt-bindings/net/ti-dp83867.h>
  19
  20 #define DP83867_PHY_ID          0x2000a231
  21 #define DP83867_DEVADDR         0x1f
  22
  23 #define MII_DP83867_PHYCTRL     0x10
  24 #define MII_DP83867_PHYSTS      0x11
  25 #define MII_DP83867_MICR        0x12
  26 #define MII_DP83867_ISR         0x13
  27 #define DP83867_CFG2            0x14
  28 #define DP83867_CFG3            0x1e
  29 #define DP83867_CTRL            0x1f
  30
  31 /* Extended Registers */
  32 #define DP83867_FLD_THR_CFG     0x002e
  33 #define DP83867_CFG4            0x0031
  34 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  35 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  36 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  37 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  38 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  39
  40 #define DP83867_RGMIICTL        0x0032
  41 #define DP83867_STRAP_STS1      0x006E
  42 #define DP83867_STRAP_STS2      0x006f
  43 #define DP83867_RGMIIDCTL       0x0086
  44 #define DP83867_RXFCFG          0x0134
  45 #define DP83867_RXFPMD1 0x0136
  46 #define DP83867_RXFPMD2 0x0137
  47 #define DP83867_RXFPMD3 0x0138
  48 #define DP83867_RXFSOP1 0x0139
  49 #define DP83867_RXFSOP2 0x013A
  50 #define DP83867_RXFSOP3 0x013B
  51 #define DP83867_IO_MUX_CFG      0x0170
  52 #define DP83867_SGMIICTL        0x00D3
  53 #define DP83867_10M_SGMII_CFG   0x016F
  54 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  55
  56 #define DP83867_SW_RESET        BIT(15)
  57 #define DP83867_SW_RESTART      BIT(14)
  58
  59 /* MICR Interrupt bits */
  60 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  61 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  62 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  63 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  64 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  65 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  66 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  67 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  68 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  69 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  70 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  71 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  72
  73 /* RGMIICTL bits */
  74 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  75 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  76
  77 /* SGMIICTL bits */
  78 #define DP83867_SGMII_TYPE              BIT(14)
  79
  80 /* RXFCFG bits*/
  81 #define DP83867_WOL_MAGIC_EN            BIT(0)
  82 #define DP83867_WOL_BCAST_EN            BIT(2)
  83 #define DP83867_WOL_UCAST_EN            BIT(4)
  84 #define DP83867_WOL_SEC_EN              BIT(5)
  85 #define DP83867_WOL_ENH_MAC             BIT(7)
  86
  87 /* STRAP_STS1 bits */
  88 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  89
  90 /* STRAP_STS2 bits */
  91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  95 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  96 #define DP83867_STRAP_STS2_STRAP_FLD            BIT(10)
  97
  98 /* PHY CTRL bits */
  99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT       14
 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT       12
 101 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
 102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK        GENMASK(15, 14)
 103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK        GENMASK(13, 12)
 104 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
 105 #define DP83867_PHYCR_FORCE_LINK_GOOD           BIT(10)
 106
 107 /* RGMIIDCTL bits */
 108 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
 109 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
 110 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
 111 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
 112 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
 113 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
 114
 115 /* IO_MUX_CFG bits */
 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
 117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 122
 123 /* PHY STS bits */
 124 #define DP83867_PHYSTS_1000                     BIT(15)
 125 #define DP83867_PHYSTS_100                      BIT(14)
 126 #define DP83867_PHYSTS_DUPLEX                   BIT(13)
 127 #define DP83867_PHYSTS_LINK                     BIT(10)
 128
 129 /* CFG2 bits */
 130 #define DP83867_DOWNSHIFT_EN            (BIT(8) | BIT(9))
 131 #define DP83867_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
 132 #define DP83867_DOWNSHIFT_1_COUNT_VAL   0
 133 #define DP83867_DOWNSHIFT_2_COUNT_VAL   1
 134 #define DP83867_DOWNSHIFT_4_COUNT_VAL   2
 135 #define DP83867_DOWNSHIFT_8_COUNT_VAL   3
 136 #define DP83867_DOWNSHIFT_1_COUNT       1
 137 #define DP83867_DOWNSHIFT_2_COUNT       2
 138 #define DP83867_DOWNSHIFT_4_COUNT       4
 139 #define DP83867_DOWNSHIFT_8_COUNT       8
 140
 141 /* CFG3 bits */
 142 #define DP83867_CFG3_INT_OE                     BIT(7)
 143 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
 144
 145 /* CFG4 bits */
 146 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
 147
 148 /* FLD_THR_CFG */
 149 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK        0x7
 150
 151 enum {
 152         DP83867_PORT_MIRROING_KEEP,
 153         DP83867_PORT_MIRROING_EN,
 154         DP83867_PORT_MIRROING_DIS,
 155 };
 156
 157 struct dp83867_private {
 158         u32 rx_id_delay;
 159         u32 tx_id_delay;
 160         u32 tx_fifo_depth;
 161         u32 rx_fifo_depth;
 162         int io_impedance;
 163         int port_mirroring;
 164         bool rxctrl_strap_quirk;
 165         bool set_clk_output;
 166         u32 clk_output_sel;
 167         bool sgmii_ref_clk_en;
 168 };
 169
 170 static int dp83867_ack_interrupt(struct phy_device *phydev)
 171 {
 172         int err = phy_read(phydev, MII_DP83867_ISR);
 173
 174         if (err < 0)
 175                 return err;
 176
 177         return 0;
 178 }
 179
 180 static int dp83867_set_wol(struct phy_device *phydev,
 181                            struct ethtool_wolinfo *wol)
 182 {
 183         struct net_device *ndev = phydev->attached_dev;
 184         u16 val_rxcfg, val_micr;
 185         u8 *mac;
 186
 187         val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 188         val_micr = phy_read(phydev, MII_DP83867_MICR);
 189
 190         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 191                             WAKE_BCAST)) {
 192                 val_rxcfg |= DP83867_WOL_ENH_MAC;
 193                 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
 194
 195                 if (wol->wolopts & WAKE_MAGIC) {
 196                         mac = (u8 *)ndev->dev_addr;
 197
 198                         if (!is_valid_ether_addr(mac))
 199                                 return -EINVAL;
 200
 201                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
 202                                       (mac[1] << 8 | mac[0]));
 203                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
 204                                       (mac[3] << 8 | mac[2]));
 205                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
 206                                       (mac[5] << 8 | mac[4]));
 207
 208                         val_rxcfg |= DP83867_WOL_MAGIC_EN;
 209                 } else {
 210                         val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
 211                 }
 212
 213                 if (wol->wolopts & WAKE_MAGICSECURE) {
 214                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 215                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 216                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
 217                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 218                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
 219                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 220
 221                         val_rxcfg |= DP83867_WOL_SEC_EN;
 222                 } else {
 223                         val_rxcfg &= ~DP83867_WOL_SEC_EN;
 224                 }
 225
 226                 if (wol->wolopts & WAKE_UCAST)
 227                         val_rxcfg |= DP83867_WOL_UCAST_EN;
 228                 else
 229                         val_rxcfg &= ~DP83867_WOL_UCAST_EN;
 230
 231                 if (wol->wolopts & WAKE_BCAST)
 232                         val_rxcfg |= DP83867_WOL_BCAST_EN;
 233                 else
 234                         val_rxcfg &= ~DP83867_WOL_BCAST_EN;
 235         } else {
 236                 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
 237                 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
 238         }
 239
 240         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
 241         phy_write(phydev, MII_DP83867_MICR, val_micr);
 242
 243         return 0;
 244 }
 245
 246 static void dp83867_get_wol(struct phy_device *phydev,
 247                             struct ethtool_wolinfo *wol)
 248 {
 249         u16 value, sopass_val;
 250
 251         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 252                         WAKE_MAGICSECURE);
 253         wol->wolopts = 0;
 254
 255         value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 256
 257         if (value & DP83867_WOL_UCAST_EN)
 258                 wol->wolopts |= WAKE_UCAST;
 259
 260         if (value & DP83867_WOL_BCAST_EN)
 261                 wol->wolopts |= WAKE_BCAST;
 262
 263         if (value & DP83867_WOL_MAGIC_EN)
 264                 wol->wolopts |= WAKE_MAGIC;
 265
 266         if (value & DP83867_WOL_SEC_EN) {
 267                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 268                                           DP83867_RXFSOP1);
 269                 wol->sopass[0] = (sopass_val & 0xff);
 270                 wol->sopass[1] = (sopass_val >> 8);
 271
 272                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 273                                           DP83867_RXFSOP2);
 274                 wol->sopass[2] = (sopass_val & 0xff);
 275                 wol->sopass[3] = (sopass_val >> 8);
 276
 277                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 278                                           DP83867_RXFSOP3);
 279                 wol->sopass[4] = (sopass_val & 0xff);
 280                 wol->sopass[5] = (sopass_val >> 8);
 281
 282                 wol->wolopts |= WAKE_MAGICSECURE;
 283         }
 284
 285         if (!(value & DP83867_WOL_ENH_MAC))
 286                 wol->wolopts = 0;
 287 }
 288
 289 static int dp83867_config_intr(struct phy_device *phydev)
 290 {
 291         int micr_status;
 292
 293         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 294                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 295                 if (micr_status < 0)
 296                         return micr_status;
 297
 298                 micr_status |=
 299                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 300                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 301                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 302                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 303                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 304                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 305
 306                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 307         }
 308
 309         micr_status = 0x0;
 310         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 311 }
 312
 313 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
 314 {
 315         int irq_status, irq_enabled;
 316
 317         irq_status = phy_read(phydev, MII_DP83867_ISR);
 318         if (irq_status < 0) {
 319                 phy_error(phydev);
 320                 return IRQ_NONE;
 321         }
 322
 323         irq_enabled = phy_read(phydev, MII_DP83867_MICR);
 324         if (irq_enabled < 0) {
 325                 phy_error(phydev);
 326                 return IRQ_NONE;
 327         }
 328
 329         if (!(irq_status & irq_enabled))
 330                 return IRQ_NONE;
 331
 332         phy_trigger_machine(phydev);
 333
 334         return IRQ_HANDLED;
 335 }
 336
 337 static int dp83867_read_status(struct phy_device *phydev)
 338 {
 339         int status = phy_read(phydev, MII_DP83867_PHYSTS);
 340         int ret;
 341
 342         ret = genphy_read_status(phydev);
 343         if (ret)
 344                 return ret;
 345
 346         if (status < 0)
 347                 return status;
 348
 349         if (status & DP83867_PHYSTS_DUPLEX)
 350                 phydev->duplex = DUPLEX_FULL;
 351         else
 352                 phydev->duplex = DUPLEX_HALF;
 353
 354         if (status & DP83867_PHYSTS_1000)
 355                 phydev->speed = SPEED_1000;
 356         else if (status & DP83867_PHYSTS_100)
 357                 phydev->speed = SPEED_100;
 358         else
 359                 phydev->speed = SPEED_10;
 360
 361         return 0;
 362 }
 363
 364 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
 365 {
 366         int val, cnt, enable, count;
 367
 368         val = phy_read(phydev, DP83867_CFG2);
 369         if (val < 0)
 370                 return val;
 371
 372         enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
 373         cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
 374
 375         switch (cnt) {
 376         case DP83867_DOWNSHIFT_1_COUNT_VAL:
 377                 count = DP83867_DOWNSHIFT_1_COUNT;
 378                 break;
 379         case DP83867_DOWNSHIFT_2_COUNT_VAL:
 380                 count = DP83867_DOWNSHIFT_2_COUNT;
 381                 break;
 382         case DP83867_DOWNSHIFT_4_COUNT_VAL:
 383                 count = DP83867_DOWNSHIFT_4_COUNT;
 384                 break;
 385         case DP83867_DOWNSHIFT_8_COUNT_VAL:
 386                 count = DP83867_DOWNSHIFT_8_COUNT;
 387                 break;
 388         default:
 389                 return -EINVAL;
 390         }
 391
 392         *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
 393
 394         return 0;
 395 }
 396
 397 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
 398 {
 399         int val, count;
 400
 401         if (cnt > DP83867_DOWNSHIFT_8_COUNT)
 402                 return -E2BIG;
 403
 404         if (!cnt)
 405                 return phy_clear_bits(phydev, DP83867_CFG2,
 406                                       DP83867_DOWNSHIFT_EN);
 407
 408         switch (cnt) {
 409         case DP83867_DOWNSHIFT_1_COUNT:
 410                 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
 411                 break;
 412         case DP83867_DOWNSHIFT_2_COUNT:
 413                 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
 414                 break;
 415         case DP83867_DOWNSHIFT_4_COUNT:
 416                 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
 417                 break;
 418         case DP83867_DOWNSHIFT_8_COUNT:
 419                 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
 420                 break;
 421         default:
 422                 phydev_err(phydev,
 423                            "Downshift count must be 1, 2, 4 or 8\n");
 424                 return -EINVAL;
 425         }
 426
 427         val = DP83867_DOWNSHIFT_EN;
 428         val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
 429
 430         return phy_modify(phydev, DP83867_CFG2,
 431                           DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
 432                           val);
 433 }
 434
 435 static int dp83867_get_tunable(struct phy_device *phydev,
 436                                struct ethtool_tunable *tuna, void *data)
 437 {
 438         switch (tuna->id) {
 439         case ETHTOOL_PHY_DOWNSHIFT:
 440                 return dp83867_get_downshift(phydev, data);
 441         default:
 442                 return -EOPNOTSUPP;
 443         }
 444 }
 445
 446 static int dp83867_set_tunable(struct phy_device *phydev,
 447                                struct ethtool_tunable *tuna, const void *data)
 448 {
 449         switch (tuna->id) {
 450         case ETHTOOL_PHY_DOWNSHIFT:
 451                 return dp83867_set_downshift(phydev, *(const u8 *)data);
 452         default:
 453                 return -EOPNOTSUPP;
 454         }
 455 }
 456
 457 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 458 {
 459         struct dp83867_private *dp83867 =
 460                 (struct dp83867_private *)phydev->priv;
 461
 462         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 463                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 464                                  DP83867_CFG4_PORT_MIRROR_EN);
 465         else
 466                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 467                                    DP83867_CFG4_PORT_MIRROR_EN);
 468         return 0;
 469 }
 470
 471 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
 472 {
 473         struct dp83867_private *dp83867 = phydev->priv;
 474
 475         /* Existing behavior was to use default pin strapping delay in rgmii
 476          * mode, but rgmii should have meant no delay.  Warn existing users.
 477          */
 478         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 479                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 480                                              DP83867_STRAP_STS2);
 481                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 482                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 483                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 484                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 485
 486                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 487                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 488                         phydev_warn(phydev,
 489                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 490                                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
 491                                     txskew, rxskew);
 492         }
 493
 494         /* RX delay *must* be specified if internal delay of RX is used. */
 495         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 496              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
 497              dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
 498                 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 499                 return -EINVAL;
 500         }
 501
 502         /* TX delay *must* be specified if internal delay of TX is used. */
 503         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 504              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
 505              dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
 506                 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 507                 return -EINVAL;
 508         }
 509
 510         return 0;
 511 }
 512
 513 #if IS_ENABLED(CONFIG_OF_MDIO)
 514 static int dp83867_of_init(struct phy_device *phydev)
 515 {
 516         struct dp83867_private *dp83867 = phydev->priv;
 517         struct device *dev = &phydev->mdio.dev;
 518         struct device_node *of_node = dev->of_node;
 519         int ret;
 520
 521         if (!of_node)
 522                 return -ENODEV;
 523
 524         /* Optional configuration */
 525         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 526                                    &dp83867->clk_output_sel);
 527         /* If not set, keep default */
 528         if (!ret) {
 529                 dp83867->set_clk_output = true;
 530                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 531                  * DP83867_CLK_O_SEL_OFF.
 532                  */
 533                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 534                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 535                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 536                                    dp83867->clk_output_sel);
 537                         return -EINVAL;
 538                 }
 539         }
 540
 541         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 542                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 543         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 544                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 545         else
 546                 dp83867->io_impedance = -1; /* leave at default */
 547
 548         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 549                                                             "ti,dp83867-rxctrl-strap-quirk");
 550
 551         dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
 552                                                           "ti,sgmii-ref-clock-output-enable");
 553
 554         dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
 555         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 556                                    &dp83867->rx_id_delay);
 557         if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 558                 phydev_err(phydev,
 559                            "ti,rx-internal-delay value of %u out of range\n",
 560                            dp83867->rx_id_delay);
 561                 return -EINVAL;
 562         }
 563
 564         dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
 565         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 566                                    &dp83867->tx_id_delay);
 567         if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 568                 phydev_err(phydev,
 569                            "ti,tx-internal-delay value of %u out of range\n",
 570                            dp83867->tx_id_delay);
 571                 return -EINVAL;
 572         }
 573
 574         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 575                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 576
 577         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 578                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 579
 580         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 581                                    &dp83867->tx_fifo_depth);
 582         if (ret) {
 583                 ret = of_property_read_u32(of_node, "tx-fifo-depth",
 584                                            &dp83867->tx_fifo_depth);
 585                 if (ret)
 586                         dp83867->tx_fifo_depth =
 587                                         DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 588         }
 589
 590         if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 591                 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
 592                            dp83867->tx_fifo_depth);
 593                 return -EINVAL;
 594         }
 595
 596         ret = of_property_read_u32(of_node, "rx-fifo-depth",
 597                                    &dp83867->rx_fifo_depth);
 598         if (ret)
 599                 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 600
 601         if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 602                 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
 603                            dp83867->rx_fifo_depth);
 604                 return -EINVAL;
 605         }
 606
 607         return 0;
 608 }
 609 #else
 610 static int dp83867_of_init(struct phy_device *phydev)
 611 {
 612         return 0;
 613 }
 614 #endif /* CONFIG_OF_MDIO */
 615
 616 static int dp83867_probe(struct phy_device *phydev)
 617 {
 618         struct dp83867_private *dp83867;
 619
 620         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 621                                GFP_KERNEL);
 622         if (!dp83867)
 623                 return -ENOMEM;
 624
 625         phydev->priv = dp83867;
 626
 627         return dp83867_of_init(phydev);
 628 }
 629
 630 static int dp83867_config_init(struct phy_device *phydev)
 631 {
 632         struct dp83867_private *dp83867 = phydev->priv;
 633         int ret, val, bs;
 634         u16 delay;
 635
 636         /* Force speed optimization for the PHY even if it strapped */
 637         ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
 638                          DP83867_DOWNSHIFT_EN);
 639         if (ret)
 640                 return ret;
 641
 642         ret = dp83867_verify_rgmii_cfg(phydev);
 643         if (ret)
 644                 return ret;
 645
 646         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 647         if (dp83867->rxctrl_strap_quirk)
 648                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 649                                    BIT(7));
 650
 651         bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
 652         if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
 653                 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
 654                  * be set to 0x2. This may causes the PHY link to be unstable -
 655                  * the default value 0x1 need to be restored.
 656                  */
 657                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 658                                      DP83867_FLD_THR_CFG,
 659                                      DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
 660                                      0x1);
 661                 if (ret)
 662                         return ret;
 663         }
 664
 665         if (phy_interface_is_rgmii(phydev) ||
 666             phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 667                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 668                 if (val < 0)
 669                         return val;
 670
 671                 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
 672                 val |= (dp83867->tx_fifo_depth <<
 673                         DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 674
 675                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 676                         val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
 677                         val |= (dp83867->rx_fifo_depth <<
 678                                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
 679                 }
 680
 681                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 682                 if (ret)
 683                         return ret;
 684         }
 685
 686         if (phy_interface_is_rgmii(phydev)) {
 687                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 688                 if (val < 0)
 689                         return val;
 690
 691                 /* The code below checks if "port mirroring" N/A MODE4 has been
 692                  * enabled during power on bootstrap.
 693                  *
 694                  * Such N/A mode enabled by mistake can put PHY IC in some
 695                  * internal testing mode and disable RGMII transmission.
 696                  *
 697                  * In this particular case one needs to check STRAP_STS1
 698                  * register's bit 11 (marked as RESERVED).
 699                  */
 700
 701                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 702                 if (bs & DP83867_STRAP_STS1_RESERVED)
 703                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 704
 705                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 706                 if (ret)
 707                         return ret;
 708
 709                 /* If rgmii mode with no internal delay is selected, we do NOT use
 710                  * aligned mode as one might expect.  Instead we use the PHY's default
 711                  * based on pin strapping.  And the "mode 0" default is to *use*
 712                  * internal delay with a value of 7 (2.00 ns).
 713                  *
 714                  * Set up RGMII delays
 715                  */
 716                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 717
 718                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 719                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 720                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 721
 722                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 723                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 724
 725                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 726                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 727
 728                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 729
 730                 delay = 0;
 731                 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
 732                         delay |= dp83867->rx_id_delay;
 733                 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
 734                         delay |= dp83867->tx_id_delay <<
 735                                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
 736
 737                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 738                               delay);
 739         }
 740
 741         /* If specified, set io impedance */
 742         if (dp83867->io_impedance >= 0)
 743                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 744                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 745                                dp83867->io_impedance);
 746
 747         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 748                 /* For support SPEED_10 in SGMII mode
 749                  * DP83867_10M_SGMII_RATE_ADAPT bit
 750                  * has to be cleared by software. That
 751                  * does not affect SPEED_100 and
 752                  * SPEED_1000.
 753                  */
 754                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 755                                      DP83867_10M_SGMII_CFG,
 756                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 757                                      0);
 758                 if (ret)
 759                         return ret;
 760
 761                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 762                  * are 01). That is not enough to finalize autoneg on some
 763                  * devices. Increase this timer duration to maximum 16ms.
 764                  */
 765                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 766                                      DP83867_CFG4,
 767                                      DP83867_CFG4_SGMII_ANEG_MASK,
 768                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 769
 770                 if (ret)
 771                         return ret;
 772
 773                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
 774                 /* SGMII type is set to 4-wire mode by default.
 775                  * If we place appropriate property in dts (see above)
 776                  * switch on 6-wire mode.
 777                  */
 778                 if (dp83867->sgmii_ref_clk_en)
 779                         val |= DP83867_SGMII_TYPE;
 780                 else
 781                         val &= ~DP83867_SGMII_TYPE;
 782                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
 783         }
 784
 785         val = phy_read(phydev, DP83867_CFG3);
 786         /* Enable Interrupt output INT_OE in CFG3 register */
 787         if (phy_interrupt_is_valid(phydev))
 788                 val |= DP83867_CFG3_INT_OE;
 789
 790         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 791         phy_write(phydev, DP83867_CFG3, val);
 792
 793         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 794                 dp83867_config_port_mirroring(phydev);
 795
 796         /* Clock output selection if muxing property is set */
 797         if (dp83867->set_clk_output) {
 798                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 799
 800                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 801                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 802                 } else {
 803                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 804                         val = dp83867->clk_output_sel <<
 805                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 806                 }
 807
 808                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 809                                mask, val);
 810         }
 811
 812         return 0;
 813 }
 814
 815 static int dp83867_phy_reset(struct phy_device *phydev)
 816 {
 817         int err;
 818
 819         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 820         if (err < 0)
 821                 return err;
 822
 823         usleep_range(10, 20);
 824
 825         /* After reset FORCE_LINK_GOOD bit is set. Although the
 826          * default value should be unset. Disable FORCE_LINK_GOOD
 827          * for the phy to work properly.
 828          */
 829         return phy_modify(phydev, MII_DP83867_PHYCTRL,
 830                          DP83867_PHYCR_FORCE_LINK_GOOD, 0);
 831 }
 832
 833 static struct phy_driver dp83867_driver[] = {
 834         {
 835                 .phy_id         = DP83867_PHY_ID,
 836                 .phy_id_mask    = 0xfffffff0,
 837                 .name           = "TI DP83867",
 838                 /* PHY_GBIT_FEATURES */
 839
 840                 .probe          = dp83867_probe,
 841                 .config_init    = dp83867_config_init,
 842                 .soft_reset     = dp83867_phy_reset,
 843
 844                 .read_status    = dp83867_read_status,
 845                 .get_tunable    = dp83867_get_tunable,
 846                 .set_tunable    = dp83867_set_tunable,
 847
 848                 .get_wol        = dp83867_get_wol,
 849                 .set_wol        = dp83867_set_wol,
 850
 851                 /* IRQ related */
 852                 .ack_interrupt  = dp83867_ack_interrupt,
 853                 .config_intr    = dp83867_config_intr,
 854                 .handle_interrupt = dp83867_handle_interrupt,
 855
 856                 .suspend        = genphy_suspend,
 857                 .resume         = genphy_resume,
 858         },
 859 };
 860 module_phy_driver(dp83867_driver);
 861
 862 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 863         { DP83867_PHY_ID, 0xfffffff0 },
 864         { }
 865 };
 866
 867 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 868
 869 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 870 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 871 MODULE_LICENSE("GPL v2");